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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
568d7c76 | 27 | #include <linux/pagemap.h> |
d38ceaf9 AD |
28 | #include <drm/drmP.h> |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
d38ceaf9 AD |
33 | int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, |
34 | u32 ip_instance, u32 ring, | |
35 | struct amdgpu_ring **out_ring) | |
36 | { | |
37 | /* Right now all IPs have only one instance - multiple rings. */ | |
38 | if (ip_instance != 0) { | |
39 | DRM_ERROR("invalid ip instance: %d\n", ip_instance); | |
40 | return -EINVAL; | |
41 | } | |
42 | ||
43 | switch (ip_type) { | |
44 | default: | |
45 | DRM_ERROR("unknown ip type: %d\n", ip_type); | |
46 | return -EINVAL; | |
47 | case AMDGPU_HW_IP_GFX: | |
48 | if (ring < adev->gfx.num_gfx_rings) { | |
49 | *out_ring = &adev->gfx.gfx_ring[ring]; | |
50 | } else { | |
51 | DRM_ERROR("only %d gfx rings are supported now\n", | |
52 | adev->gfx.num_gfx_rings); | |
53 | return -EINVAL; | |
54 | } | |
55 | break; | |
56 | case AMDGPU_HW_IP_COMPUTE: | |
57 | if (ring < adev->gfx.num_compute_rings) { | |
58 | *out_ring = &adev->gfx.compute_ring[ring]; | |
59 | } else { | |
60 | DRM_ERROR("only %d compute rings are supported now\n", | |
61 | adev->gfx.num_compute_rings); | |
62 | return -EINVAL; | |
63 | } | |
64 | break; | |
65 | case AMDGPU_HW_IP_DMA: | |
c113ea1c AD |
66 | if (ring < adev->sdma.num_instances) { |
67 | *out_ring = &adev->sdma.instance[ring].ring; | |
d38ceaf9 | 68 | } else { |
c113ea1c AD |
69 | DRM_ERROR("only %d SDMA rings are supported\n", |
70 | adev->sdma.num_instances); | |
d38ceaf9 AD |
71 | return -EINVAL; |
72 | } | |
73 | break; | |
74 | case AMDGPU_HW_IP_UVD: | |
75 | *out_ring = &adev->uvd.ring; | |
76 | break; | |
77 | case AMDGPU_HW_IP_VCE: | |
78 | if (ring < 2){ | |
79 | *out_ring = &adev->vce.ring[ring]; | |
80 | } else { | |
81 | DRM_ERROR("only two VCE rings are supported\n"); | |
82 | return -EINVAL; | |
83 | } | |
84 | break; | |
85 | } | |
86 | return 0; | |
87 | } | |
88 | ||
91acbeb6 | 89 | static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, |
758ac17f CK |
90 | struct drm_amdgpu_cs_chunk_fence *data, |
91 | uint32_t *offset) | |
91acbeb6 CK |
92 | { |
93 | struct drm_gem_object *gobj; | |
91acbeb6 | 94 | |
a8ad0bd8 | 95 | gobj = drm_gem_object_lookup(p->filp, data->handle); |
91acbeb6 CK |
96 | if (gobj == NULL) |
97 | return -EINVAL; | |
98 | ||
758ac17f | 99 | p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); |
91acbeb6 CK |
100 | p->uf_entry.priority = 0; |
101 | p->uf_entry.tv.bo = &p->uf_entry.robj->tbo; | |
102 | p->uf_entry.tv.shared = true; | |
2f568dbd | 103 | p->uf_entry.user_pages = NULL; |
758ac17f | 104 | *offset = data->offset; |
91acbeb6 CK |
105 | |
106 | drm_gem_object_unreference_unlocked(gobj); | |
758ac17f CK |
107 | |
108 | if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) { | |
109 | amdgpu_bo_unref(&p->uf_entry.robj); | |
110 | return -EINVAL; | |
111 | } | |
112 | ||
91acbeb6 CK |
113 | return 0; |
114 | } | |
115 | ||
d38ceaf9 AD |
116 | int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) |
117 | { | |
4c0b242c | 118 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
c5637837 | 119 | struct amdgpu_vm *vm = &fpriv->vm; |
d38ceaf9 AD |
120 | union drm_amdgpu_cs *cs = data; |
121 | uint64_t *chunk_array_user; | |
1d263474 | 122 | uint64_t *chunk_array; |
50838c8c | 123 | unsigned size, num_ibs = 0; |
758ac17f | 124 | uint32_t uf_offset = 0; |
54313503 | 125 | int i; |
1d263474 | 126 | int ret; |
d38ceaf9 | 127 | |
1d263474 DC |
128 | if (cs->in.num_chunks == 0) |
129 | return 0; | |
130 | ||
131 | chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); | |
132 | if (!chunk_array) | |
133 | return -ENOMEM; | |
d38ceaf9 | 134 | |
3cb485f3 CK |
135 | p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); |
136 | if (!p->ctx) { | |
1d263474 DC |
137 | ret = -EINVAL; |
138 | goto free_chunk; | |
3cb485f3 | 139 | } |
1d263474 | 140 | |
d38ceaf9 | 141 | /* get chunks */ |
028423b0 | 142 | chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks); |
d38ceaf9 AD |
143 | if (copy_from_user(chunk_array, chunk_array_user, |
144 | sizeof(uint64_t)*cs->in.num_chunks)) { | |
1d263474 | 145 | ret = -EFAULT; |
2a7d9bda | 146 | goto put_ctx; |
d38ceaf9 AD |
147 | } |
148 | ||
149 | p->nchunks = cs->in.num_chunks; | |
e60b344f | 150 | p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), |
d38ceaf9 | 151 | GFP_KERNEL); |
1d263474 DC |
152 | if (!p->chunks) { |
153 | ret = -ENOMEM; | |
2a7d9bda | 154 | goto put_ctx; |
d38ceaf9 AD |
155 | } |
156 | ||
157 | for (i = 0; i < p->nchunks; i++) { | |
158 | struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; | |
159 | struct drm_amdgpu_cs_chunk user_chunk; | |
160 | uint32_t __user *cdata; | |
161 | ||
028423b0 | 162 | chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; |
d38ceaf9 AD |
163 | if (copy_from_user(&user_chunk, chunk_ptr, |
164 | sizeof(struct drm_amdgpu_cs_chunk))) { | |
1d263474 DC |
165 | ret = -EFAULT; |
166 | i--; | |
167 | goto free_partial_kdata; | |
d38ceaf9 AD |
168 | } |
169 | p->chunks[i].chunk_id = user_chunk.chunk_id; | |
170 | p->chunks[i].length_dw = user_chunk.length_dw; | |
d38ceaf9 AD |
171 | |
172 | size = p->chunks[i].length_dw; | |
028423b0 | 173 | cdata = (void __user *)(unsigned long)user_chunk.chunk_data; |
d38ceaf9 AD |
174 | |
175 | p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); | |
176 | if (p->chunks[i].kdata == NULL) { | |
1d263474 DC |
177 | ret = -ENOMEM; |
178 | i--; | |
179 | goto free_partial_kdata; | |
d38ceaf9 AD |
180 | } |
181 | size *= sizeof(uint32_t); | |
182 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { | |
1d263474 DC |
183 | ret = -EFAULT; |
184 | goto free_partial_kdata; | |
d38ceaf9 AD |
185 | } |
186 | ||
9a5e8fb1 CK |
187 | switch (p->chunks[i].chunk_id) { |
188 | case AMDGPU_CHUNK_ID_IB: | |
50838c8c | 189 | ++num_ibs; |
9a5e8fb1 CK |
190 | break; |
191 | ||
192 | case AMDGPU_CHUNK_ID_FENCE: | |
d38ceaf9 | 193 | size = sizeof(struct drm_amdgpu_cs_chunk_fence); |
91acbeb6 | 194 | if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { |
1d263474 DC |
195 | ret = -EINVAL; |
196 | goto free_partial_kdata; | |
d38ceaf9 | 197 | } |
91acbeb6 | 198 | |
758ac17f CK |
199 | ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata, |
200 | &uf_offset); | |
91acbeb6 CK |
201 | if (ret) |
202 | goto free_partial_kdata; | |
203 | ||
9a5e8fb1 CK |
204 | break; |
205 | ||
2b48d323 CK |
206 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
207 | break; | |
208 | ||
9a5e8fb1 | 209 | default: |
1d263474 DC |
210 | ret = -EINVAL; |
211 | goto free_partial_kdata; | |
d38ceaf9 AD |
212 | } |
213 | } | |
214 | ||
c5637837 | 215 | ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm); |
50838c8c | 216 | if (ret) |
4acabfe3 | 217 | goto free_all_kdata; |
d38ceaf9 | 218 | |
758ac17f CK |
219 | if (p->uf_entry.robj) { |
220 | p->job->uf_bo = amdgpu_bo_ref(p->uf_entry.robj); | |
221 | p->job->uf_offset = uf_offset; | |
222 | } | |
4c0b242c | 223 | |
d38ceaf9 | 224 | kfree(chunk_array); |
1d263474 DC |
225 | return 0; |
226 | ||
227 | free_all_kdata: | |
228 | i = p->nchunks - 1; | |
229 | free_partial_kdata: | |
230 | for (; i >= 0; i--) | |
231 | drm_free_large(p->chunks[i].kdata); | |
232 | kfree(p->chunks); | |
2a7d9bda | 233 | put_ctx: |
1d263474 DC |
234 | amdgpu_ctx_put(p->ctx); |
235 | free_chunk: | |
236 | kfree(chunk_array); | |
237 | ||
238 | return ret; | |
d38ceaf9 AD |
239 | } |
240 | ||
241 | /* Returns how many bytes TTM can move per IB. | |
242 | */ | |
243 | static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev) | |
244 | { | |
245 | u64 real_vram_size = adev->mc.real_vram_size; | |
246 | u64 vram_usage = atomic64_read(&adev->vram_usage); | |
247 | ||
248 | /* This function is based on the current VRAM usage. | |
249 | * | |
250 | * - If all of VRAM is free, allow relocating the number of bytes that | |
251 | * is equal to 1/4 of the size of VRAM for this IB. | |
252 | ||
253 | * - If more than one half of VRAM is occupied, only allow relocating | |
254 | * 1 MB of data for this IB. | |
255 | * | |
256 | * - From 0 to one half of used VRAM, the threshold decreases | |
257 | * linearly. | |
258 | * __________________ | |
259 | * 1/4 of -|\ | | |
260 | * VRAM | \ | | |
261 | * | \ | | |
262 | * | \ | | |
263 | * | \ | | |
264 | * | \ | | |
265 | * | \ | | |
266 | * | \________|1 MB | |
267 | * |----------------| | |
268 | * VRAM 0 % 100 % | |
269 | * used used | |
270 | * | |
271 | * Note: It's a threshold, not a limit. The threshold must be crossed | |
272 | * for buffer relocations to stop, so any buffer of an arbitrary size | |
273 | * can be moved as long as the threshold isn't crossed before | |
274 | * the relocation takes place. We don't want to disable buffer | |
275 | * relocations completely. | |
276 | * | |
277 | * The idea is that buffers should be placed in VRAM at creation time | |
278 | * and TTM should only do a minimum number of relocations during | |
279 | * command submission. In practice, you need to submit at least | |
280 | * a dozen IBs to move all buffers to VRAM if they are in GTT. | |
281 | * | |
282 | * Also, things can get pretty crazy under memory pressure and actual | |
283 | * VRAM usage can change a lot, so playing safe even at 50% does | |
284 | * consistently increase performance. | |
285 | */ | |
286 | ||
287 | u64 half_vram = real_vram_size >> 1; | |
288 | u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; | |
289 | u64 bytes_moved_threshold = half_free_vram >> 1; | |
290 | return max(bytes_moved_threshold, 1024*1024ull); | |
291 | } | |
292 | ||
f69f90a1 | 293 | int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, |
a5b75058 | 294 | struct list_head *validated) |
d38ceaf9 | 295 | { |
d38ceaf9 | 296 | struct amdgpu_bo_list_entry *lobj; |
f69f90a1 | 297 | u64 initial_bytes_moved; |
d38ceaf9 AD |
298 | int r; |
299 | ||
a5b75058 | 300 | list_for_each_entry(lobj, validated, tv.head) { |
36409d12 | 301 | struct amdgpu_bo *bo = lobj->robj; |
2f568dbd | 302 | bool binding_userptr = false; |
cc325d19 | 303 | struct mm_struct *usermm; |
36409d12 | 304 | uint32_t domain; |
d38ceaf9 | 305 | |
cc325d19 CK |
306 | usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm); |
307 | if (usermm && usermm != current->mm) | |
308 | return -EPERM; | |
309 | ||
2f568dbd CK |
310 | /* Check if we have user pages and nobody bound the BO already */ |
311 | if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) { | |
312 | size_t size = sizeof(struct page *); | |
313 | ||
314 | size *= bo->tbo.ttm->num_pages; | |
315 | memcpy(bo->tbo.ttm->pages, lobj->user_pages, size); | |
316 | binding_userptr = true; | |
317 | } | |
318 | ||
36409d12 CK |
319 | if (bo->pin_count) |
320 | continue; | |
321 | ||
322 | /* Avoid moving this one if we have moved too many buffers | |
323 | * for this IB already. | |
324 | * | |
325 | * Note that this allows moving at least one buffer of | |
326 | * any size, because it doesn't take the current "bo" | |
327 | * into account. We don't want to disallow buffer moves | |
328 | * completely. | |
329 | */ | |
330 | if (p->bytes_moved <= p->bytes_moved_threshold) | |
1ea863fd | 331 | domain = bo->prefered_domains; |
36409d12 | 332 | else |
1ea863fd | 333 | domain = bo->allowed_domains; |
36409d12 CK |
334 | |
335 | retry: | |
336 | amdgpu_ttm_placement_from_domain(bo, domain); | |
337 | initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved); | |
338 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
339 | p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) - | |
340 | initial_bytes_moved; | |
341 | ||
342 | if (unlikely(r)) { | |
1ea863fd CK |
343 | if (r != -ERESTARTSYS && domain != bo->allowed_domains) { |
344 | domain = bo->allowed_domains; | |
36409d12 | 345 | goto retry; |
d38ceaf9 | 346 | } |
36409d12 | 347 | return r; |
d38ceaf9 | 348 | } |
2f568dbd CK |
349 | |
350 | if (binding_userptr) { | |
351 | drm_free_large(lobj->user_pages); | |
352 | lobj->user_pages = NULL; | |
353 | } | |
d38ceaf9 AD |
354 | } |
355 | return 0; | |
356 | } | |
357 | ||
2a7d9bda CK |
358 | static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, |
359 | union drm_amdgpu_cs *cs) | |
d38ceaf9 AD |
360 | { |
361 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
2f568dbd | 362 | struct amdgpu_bo_list_entry *e; |
a5b75058 | 363 | struct list_head duplicates; |
840d5144 | 364 | bool need_mmap_lock = false; |
2f568dbd | 365 | unsigned i, tries = 10; |
636ce25c | 366 | int r; |
d38ceaf9 | 367 | |
2a7d9bda CK |
368 | INIT_LIST_HEAD(&p->validated); |
369 | ||
370 | p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); | |
840d5144 | 371 | if (p->bo_list) { |
211dff55 CK |
372 | need_mmap_lock = p->bo_list->first_userptr != |
373 | p->bo_list->num_entries; | |
636ce25c | 374 | amdgpu_bo_list_get_list(p->bo_list, &p->validated); |
840d5144 | 375 | } |
d38ceaf9 | 376 | |
3c0eea6c | 377 | INIT_LIST_HEAD(&duplicates); |
56467ebf | 378 | amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); |
d38ceaf9 | 379 | |
758ac17f | 380 | if (p->uf_entry.robj) |
91acbeb6 CK |
381 | list_add(&p->uf_entry.tv.head, &p->validated); |
382 | ||
d38ceaf9 AD |
383 | if (need_mmap_lock) |
384 | down_read(¤t->mm->mmap_sem); | |
385 | ||
2f568dbd CK |
386 | while (1) { |
387 | struct list_head need_pages; | |
388 | unsigned i; | |
389 | ||
390 | r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, | |
391 | &duplicates); | |
392 | if (unlikely(r != 0)) | |
393 | goto error_free_pages; | |
394 | ||
395 | /* Without a BO list we don't have userptr BOs */ | |
396 | if (!p->bo_list) | |
397 | break; | |
398 | ||
399 | INIT_LIST_HEAD(&need_pages); | |
400 | for (i = p->bo_list->first_userptr; | |
401 | i < p->bo_list->num_entries; ++i) { | |
402 | ||
403 | e = &p->bo_list->array[i]; | |
404 | ||
405 | if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm, | |
406 | &e->user_invalidated) && e->user_pages) { | |
407 | ||
408 | /* We acquired a page array, but somebody | |
409 | * invalidated it. Free it an try again | |
410 | */ | |
411 | release_pages(e->user_pages, | |
412 | e->robj->tbo.ttm->num_pages, | |
413 | false); | |
414 | drm_free_large(e->user_pages); | |
415 | e->user_pages = NULL; | |
416 | } | |
417 | ||
418 | if (e->robj->tbo.ttm->state != tt_bound && | |
419 | !e->user_pages) { | |
420 | list_del(&e->tv.head); | |
421 | list_add(&e->tv.head, &need_pages); | |
422 | ||
423 | amdgpu_bo_unreserve(e->robj); | |
424 | } | |
425 | } | |
426 | ||
427 | if (list_empty(&need_pages)) | |
428 | break; | |
429 | ||
430 | /* Unreserve everything again. */ | |
431 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); | |
432 | ||
433 | /* We tried to often, just abort */ | |
434 | if (!--tries) { | |
435 | r = -EDEADLK; | |
436 | goto error_free_pages; | |
437 | } | |
438 | ||
439 | /* Fill the page arrays for all useptrs. */ | |
440 | list_for_each_entry(e, &need_pages, tv.head) { | |
441 | struct ttm_tt *ttm = e->robj->tbo.ttm; | |
442 | ||
443 | e->user_pages = drm_calloc_large(ttm->num_pages, | |
444 | sizeof(struct page*)); | |
445 | if (!e->user_pages) { | |
446 | r = -ENOMEM; | |
447 | goto error_free_pages; | |
448 | } | |
449 | ||
450 | r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages); | |
451 | if (r) { | |
452 | drm_free_large(e->user_pages); | |
453 | e->user_pages = NULL; | |
454 | goto error_free_pages; | |
455 | } | |
456 | } | |
457 | ||
458 | /* And try again. */ | |
459 | list_splice(&need_pages, &p->validated); | |
460 | } | |
a5b75058 | 461 | |
5a712a87 | 462 | amdgpu_vm_get_pt_bos(p->adev, &fpriv->vm, &duplicates); |
56467ebf | 463 | |
f69f90a1 CK |
464 | p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev); |
465 | p->bytes_moved = 0; | |
466 | ||
467 | r = amdgpu_cs_list_validate(p, &duplicates); | |
a5b75058 CK |
468 | if (r) |
469 | goto error_validate; | |
470 | ||
f69f90a1 | 471 | r = amdgpu_cs_list_validate(p, &p->validated); |
a8480309 CK |
472 | if (r) |
473 | goto error_validate; | |
474 | ||
5a712a87 CK |
475 | fpriv->vm.last_eviction_counter = |
476 | atomic64_read(&p->adev->num_evictions); | |
477 | ||
a8480309 | 478 | if (p->bo_list) { |
d88bf583 CK |
479 | struct amdgpu_bo *gds = p->bo_list->gds_obj; |
480 | struct amdgpu_bo *gws = p->bo_list->gws_obj; | |
481 | struct amdgpu_bo *oa = p->bo_list->oa_obj; | |
a8480309 CK |
482 | struct amdgpu_vm *vm = &fpriv->vm; |
483 | unsigned i; | |
484 | ||
485 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
486 | struct amdgpu_bo *bo = p->bo_list->array[i].robj; | |
487 | ||
488 | p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo); | |
489 | } | |
d88bf583 CK |
490 | |
491 | if (gds) { | |
492 | p->job->gds_base = amdgpu_bo_gpu_offset(gds); | |
493 | p->job->gds_size = amdgpu_bo_size(gds); | |
494 | } | |
495 | if (gws) { | |
496 | p->job->gws_base = amdgpu_bo_gpu_offset(gws); | |
497 | p->job->gws_size = amdgpu_bo_size(gws); | |
498 | } | |
499 | if (oa) { | |
500 | p->job->oa_base = amdgpu_bo_gpu_offset(oa); | |
501 | p->job->oa_size = amdgpu_bo_size(oa); | |
502 | } | |
a8480309 | 503 | } |
a5b75058 CK |
504 | |
505 | error_validate: | |
eceb8a15 CK |
506 | if (r) { |
507 | amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm); | |
a5b75058 | 508 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); |
eceb8a15 | 509 | } |
d38ceaf9 | 510 | |
2f568dbd CK |
511 | error_free_pages: |
512 | ||
d38ceaf9 AD |
513 | if (need_mmap_lock) |
514 | up_read(¤t->mm->mmap_sem); | |
515 | ||
2f568dbd CK |
516 | if (p->bo_list) { |
517 | for (i = p->bo_list->first_userptr; | |
518 | i < p->bo_list->num_entries; ++i) { | |
519 | e = &p->bo_list->array[i]; | |
520 | ||
521 | if (!e->user_pages) | |
522 | continue; | |
523 | ||
524 | release_pages(e->user_pages, | |
525 | e->robj->tbo.ttm->num_pages, | |
526 | false); | |
527 | drm_free_large(e->user_pages); | |
528 | } | |
529 | } | |
530 | ||
d38ceaf9 AD |
531 | return r; |
532 | } | |
533 | ||
534 | static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
535 | { | |
536 | struct amdgpu_bo_list_entry *e; | |
537 | int r; | |
538 | ||
539 | list_for_each_entry(e, &p->validated, tv.head) { | |
540 | struct reservation_object *resv = e->robj->tbo.resv; | |
e86f9cee | 541 | r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp); |
d38ceaf9 AD |
542 | |
543 | if (r) | |
544 | return r; | |
545 | } | |
546 | return 0; | |
547 | } | |
548 | ||
984810fc CK |
549 | /** |
550 | * cs_parser_fini() - clean parser states | |
551 | * @parser: parser structure holding parsing context. | |
552 | * @error: error number | |
553 | * | |
554 | * If error is set than unvalidate buffer, otherwise just free memory | |
555 | * used by parsing context. | |
556 | **/ | |
557 | static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) | |
049fc527 | 558 | { |
eceb8a15 | 559 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; |
984810fc CK |
560 | unsigned i; |
561 | ||
d38ceaf9 | 562 | if (!error) { |
28b8d66e NH |
563 | amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm); |
564 | ||
d38ceaf9 | 565 | ttm_eu_fence_buffer_objects(&parser->ticket, |
984810fc CK |
566 | &parser->validated, |
567 | parser->fence); | |
d38ceaf9 AD |
568 | } else if (backoff) { |
569 | ttm_eu_backoff_reservation(&parser->ticket, | |
570 | &parser->validated); | |
571 | } | |
984810fc | 572 | fence_put(parser->fence); |
7e52a81c | 573 | |
3cb485f3 CK |
574 | if (parser->ctx) |
575 | amdgpu_ctx_put(parser->ctx); | |
a3348bb8 CZ |
576 | if (parser->bo_list) |
577 | amdgpu_bo_list_put(parser->bo_list); | |
578 | ||
d38ceaf9 AD |
579 | for (i = 0; i < parser->nchunks; i++) |
580 | drm_free_large(parser->chunks[i].kdata); | |
581 | kfree(parser->chunks); | |
50838c8c CK |
582 | if (parser->job) |
583 | amdgpu_job_free(parser->job); | |
91acbeb6 | 584 | amdgpu_bo_unref(&parser->uf_entry.robj); |
d38ceaf9 AD |
585 | } |
586 | ||
587 | static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, | |
588 | struct amdgpu_vm *vm) | |
589 | { | |
590 | struct amdgpu_device *adev = p->adev; | |
591 | struct amdgpu_bo_va *bo_va; | |
592 | struct amdgpu_bo *bo; | |
593 | int i, r; | |
594 | ||
595 | r = amdgpu_vm_update_page_directory(adev, vm); | |
596 | if (r) | |
597 | return r; | |
598 | ||
e86f9cee | 599 | r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence); |
05906dec BN |
600 | if (r) |
601 | return r; | |
602 | ||
d38ceaf9 AD |
603 | r = amdgpu_vm_clear_freed(adev, vm); |
604 | if (r) | |
605 | return r; | |
606 | ||
607 | if (p->bo_list) { | |
608 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
91e1a520 CK |
609 | struct fence *f; |
610 | ||
d38ceaf9 AD |
611 | /* ignore duplicates */ |
612 | bo = p->bo_list->array[i].robj; | |
613 | if (!bo) | |
614 | continue; | |
615 | ||
616 | bo_va = p->bo_list->array[i].bo_va; | |
617 | if (bo_va == NULL) | |
618 | continue; | |
619 | ||
620 | r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem); | |
621 | if (r) | |
622 | return r; | |
623 | ||
bb1e38a4 | 624 | f = bo_va->last_pt_update; |
e86f9cee | 625 | r = amdgpu_sync_fence(adev, &p->job->sync, f); |
91e1a520 CK |
626 | if (r) |
627 | return r; | |
d38ceaf9 | 628 | } |
b495bd3a CK |
629 | |
630 | } | |
631 | ||
e86f9cee | 632 | r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync); |
b495bd3a CK |
633 | |
634 | if (amdgpu_vm_debug && p->bo_list) { | |
635 | /* Invalidate all BOs to test for userspace bugs */ | |
636 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
637 | /* ignore duplicates */ | |
638 | bo = p->bo_list->array[i].robj; | |
639 | if (!bo) | |
640 | continue; | |
641 | ||
642 | amdgpu_vm_bo_invalidate(adev, bo); | |
643 | } | |
d38ceaf9 AD |
644 | } |
645 | ||
b495bd3a | 646 | return r; |
d38ceaf9 AD |
647 | } |
648 | ||
649 | static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, | |
b07c60c0 | 650 | struct amdgpu_cs_parser *p) |
d38ceaf9 | 651 | { |
b07c60c0 | 652 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
d38ceaf9 | 653 | struct amdgpu_vm *vm = &fpriv->vm; |
b07c60c0 | 654 | struct amdgpu_ring *ring = p->job->ring; |
d38ceaf9 AD |
655 | int i, r; |
656 | ||
d38ceaf9 | 657 | /* Only for UVD/VCE VM emulation */ |
b07c60c0 | 658 | if (ring->funcs->parse_cs) { |
9a79588c | 659 | p->job->vm = NULL; |
b07c60c0 CK |
660 | for (i = 0; i < p->job->num_ibs; i++) { |
661 | r = amdgpu_ring_parse_cs(ring, p, i); | |
d38ceaf9 AD |
662 | if (r) |
663 | return r; | |
664 | } | |
9a79588c CK |
665 | } else { |
666 | p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); | |
281d144d | 667 | |
9a79588c CK |
668 | r = amdgpu_bo_vm_update_pte(p, vm); |
669 | if (r) | |
670 | return r; | |
671 | } | |
d38ceaf9 | 672 | |
9a79588c | 673 | return amdgpu_cs_sync_rings(p); |
d38ceaf9 AD |
674 | } |
675 | ||
676 | static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r) | |
677 | { | |
678 | if (r == -EDEADLK) { | |
679 | r = amdgpu_gpu_reset(adev); | |
680 | if (!r) | |
681 | r = -EAGAIN; | |
682 | } | |
683 | return r; | |
684 | } | |
685 | ||
686 | static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, | |
687 | struct amdgpu_cs_parser *parser) | |
688 | { | |
689 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
690 | struct amdgpu_vm *vm = &fpriv->vm; | |
691 | int i, j; | |
692 | int r; | |
693 | ||
50838c8c | 694 | for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) { |
d38ceaf9 AD |
695 | struct amdgpu_cs_chunk *chunk; |
696 | struct amdgpu_ib *ib; | |
697 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
d38ceaf9 | 698 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
699 | |
700 | chunk = &parser->chunks[i]; | |
50838c8c | 701 | ib = &parser->job->ibs[j]; |
d38ceaf9 AD |
702 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; |
703 | ||
704 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
705 | continue; | |
706 | ||
d38ceaf9 AD |
707 | r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type, |
708 | chunk_ib->ip_instance, chunk_ib->ring, | |
709 | &ring); | |
3ccec53c | 710 | if (r) |
d38ceaf9 | 711 | return r; |
d38ceaf9 | 712 | |
b07c60c0 CK |
713 | if (parser->job->ring && parser->job->ring != ring) |
714 | return -EINVAL; | |
715 | ||
716 | parser->job->ring = ring; | |
717 | ||
d38ceaf9 | 718 | if (ring->funcs->parse_cs) { |
4802ce11 | 719 | struct amdgpu_bo_va_mapping *m; |
3ccec53c | 720 | struct amdgpu_bo *aobj = NULL; |
4802ce11 CK |
721 | uint64_t offset; |
722 | uint8_t *kptr; | |
3ccec53c | 723 | |
4802ce11 CK |
724 | m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, |
725 | &aobj); | |
3ccec53c MO |
726 | if (!aobj) { |
727 | DRM_ERROR("IB va_start is invalid\n"); | |
728 | return -EINVAL; | |
d38ceaf9 AD |
729 | } |
730 | ||
4802ce11 CK |
731 | if ((chunk_ib->va_start + chunk_ib->ib_bytes) > |
732 | (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) { | |
733 | DRM_ERROR("IB va_start+ib_bytes is invalid\n"); | |
734 | return -EINVAL; | |
735 | } | |
736 | ||
3ccec53c | 737 | /* the IB should be reserved at this point */ |
4802ce11 | 738 | r = amdgpu_bo_kmap(aobj, (void **)&kptr); |
d38ceaf9 | 739 | if (r) { |
d38ceaf9 AD |
740 | return r; |
741 | } | |
742 | ||
4802ce11 CK |
743 | offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE; |
744 | kptr += chunk_ib->va_start - offset; | |
745 | ||
b07c60c0 | 746 | r = amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib); |
d38ceaf9 AD |
747 | if (r) { |
748 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
749 | return r; |
750 | } | |
751 | ||
752 | memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); | |
753 | amdgpu_bo_kunmap(aobj); | |
d38ceaf9 | 754 | } else { |
b07c60c0 | 755 | r = amdgpu_ib_get(adev, vm, 0, ib); |
d38ceaf9 AD |
756 | if (r) { |
757 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
758 | return r; |
759 | } | |
760 | ||
761 | ib->gpu_addr = chunk_ib->va_start; | |
762 | } | |
d38ceaf9 | 763 | |
3ccec53c | 764 | ib->length_dw = chunk_ib->ib_bytes / 4; |
de807f81 | 765 | ib->flags = chunk_ib->flags; |
d38ceaf9 AD |
766 | j++; |
767 | } | |
768 | ||
758ac17f CK |
769 | /* UVD & VCE fw doesn't support user fences */ |
770 | if (parser->job->uf_bo && ( | |
771 | parser->job->ring->type == AMDGPU_RING_TYPE_UVD || | |
772 | parser->job->ring->type == AMDGPU_RING_TYPE_VCE)) | |
773 | return -EINVAL; | |
d38ceaf9 AD |
774 | |
775 | return 0; | |
776 | } | |
777 | ||
2b48d323 CK |
778 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, |
779 | struct amdgpu_cs_parser *p) | |
780 | { | |
76a1ea61 | 781 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
2b48d323 CK |
782 | int i, j, r; |
783 | ||
2b48d323 CK |
784 | for (i = 0; i < p->nchunks; ++i) { |
785 | struct drm_amdgpu_cs_chunk_dep *deps; | |
786 | struct amdgpu_cs_chunk *chunk; | |
787 | unsigned num_deps; | |
788 | ||
789 | chunk = &p->chunks[i]; | |
790 | ||
791 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES) | |
792 | continue; | |
793 | ||
794 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; | |
795 | num_deps = chunk->length_dw * 4 / | |
796 | sizeof(struct drm_amdgpu_cs_chunk_dep); | |
797 | ||
798 | for (j = 0; j < num_deps; ++j) { | |
2b48d323 | 799 | struct amdgpu_ring *ring; |
76a1ea61 | 800 | struct amdgpu_ctx *ctx; |
21c16bf6 | 801 | struct fence *fence; |
2b48d323 CK |
802 | |
803 | r = amdgpu_cs_get_ring(adev, deps[j].ip_type, | |
804 | deps[j].ip_instance, | |
805 | deps[j].ring, &ring); | |
806 | if (r) | |
807 | return r; | |
808 | ||
76a1ea61 CK |
809 | ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id); |
810 | if (ctx == NULL) | |
811 | return -EINVAL; | |
812 | ||
21c16bf6 CK |
813 | fence = amdgpu_ctx_get_fence(ctx, ring, |
814 | deps[j].handle); | |
815 | if (IS_ERR(fence)) { | |
816 | r = PTR_ERR(fence); | |
76a1ea61 | 817 | amdgpu_ctx_put(ctx); |
2b48d323 | 818 | return r; |
91e1a520 | 819 | |
21c16bf6 | 820 | } else if (fence) { |
e86f9cee CK |
821 | r = amdgpu_sync_fence(adev, &p->job->sync, |
822 | fence); | |
21c16bf6 CK |
823 | fence_put(fence); |
824 | amdgpu_ctx_put(ctx); | |
825 | if (r) | |
826 | return r; | |
827 | } | |
2b48d323 CK |
828 | } |
829 | } | |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
cd75dc68 CK |
834 | static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, |
835 | union drm_amdgpu_cs *cs) | |
836 | { | |
b07c60c0 | 837 | struct amdgpu_ring *ring = p->job->ring; |
92f25098 | 838 | struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity; |
e686941a | 839 | struct fence *fence; |
cd75dc68 | 840 | struct amdgpu_job *job; |
e686941a | 841 | int r; |
cd75dc68 | 842 | |
50838c8c CK |
843 | job = p->job; |
844 | p->job = NULL; | |
cd75dc68 | 845 | |
e686941a | 846 | r = amd_sched_job_init(&job->base, &ring->sched, |
c5f74f78 | 847 | entity, p->filp, &fence); |
e686941a | 848 | if (r) { |
d71518b5 | 849 | amdgpu_job_free(job); |
e686941a | 850 | return r; |
cd75dc68 CK |
851 | } |
852 | ||
e686941a | 853 | job->owner = p->filp; |
92f25098 | 854 | job->ctx = entity->fence_context; |
e686941a ML |
855 | p->fence = fence_get(fence); |
856 | cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, fence); | |
758ac17f | 857 | job->uf_sequence = cs->out.handle; |
cd75dc68 CK |
858 | |
859 | trace_amdgpu_cs_ioctl(job); | |
860 | amd_sched_entity_push_job(&job->base); | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
049fc527 CZ |
865 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
866 | { | |
867 | struct amdgpu_device *adev = dev->dev_private; | |
868 | union drm_amdgpu_cs *cs = data; | |
7e52a81c | 869 | struct amdgpu_cs_parser parser = {}; |
26a6980c CK |
870 | bool reserved_buffers = false; |
871 | int i, r; | |
049fc527 | 872 | |
0c418f10 | 873 | if (!adev->accel_working) |
049fc527 | 874 | return -EBUSY; |
2b48d323 | 875 | |
7e52a81c CK |
876 | parser.adev = adev; |
877 | parser.filp = filp; | |
878 | ||
879 | r = amdgpu_cs_parser_init(&parser, data); | |
d38ceaf9 | 880 | if (r) { |
049fc527 | 881 | DRM_ERROR("Failed to initialize parser !\n"); |
7e52a81c | 882 | amdgpu_cs_parser_fini(&parser, r, false); |
d38ceaf9 AD |
883 | r = amdgpu_cs_handle_lockup(adev, r); |
884 | return r; | |
885 | } | |
2a7d9bda | 886 | r = amdgpu_cs_parser_bos(&parser, data); |
26a6980c CK |
887 | if (r == -ENOMEM) |
888 | DRM_ERROR("Not enough memory for command submission!\n"); | |
889 | else if (r && r != -ERESTARTSYS) | |
890 | DRM_ERROR("Failed to process the buffer list %d!\n", r); | |
891 | else if (!r) { | |
892 | reserved_buffers = true; | |
7e52a81c | 893 | r = amdgpu_cs_ib_fill(adev, &parser); |
26a6980c CK |
894 | } |
895 | ||
896 | if (!r) { | |
7e52a81c | 897 | r = amdgpu_cs_dependencies(adev, &parser); |
26a6980c CK |
898 | if (r) |
899 | DRM_ERROR("Failed in the dependencies handling %d!\n", r); | |
900 | } | |
901 | ||
902 | if (r) | |
903 | goto out; | |
904 | ||
50838c8c | 905 | for (i = 0; i < parser.job->num_ibs; i++) |
7e52a81c | 906 | trace_amdgpu_cs(&parser, i); |
26a6980c | 907 | |
7e52a81c | 908 | r = amdgpu_cs_ib_vm_chunk(adev, &parser); |
4fe63117 CZ |
909 | if (r) |
910 | goto out; | |
911 | ||
4acabfe3 | 912 | r = amdgpu_cs_submit(&parser, cs); |
d38ceaf9 | 913 | |
d38ceaf9 | 914 | out: |
7e52a81c | 915 | amdgpu_cs_parser_fini(&parser, r, reserved_buffers); |
d38ceaf9 AD |
916 | r = amdgpu_cs_handle_lockup(adev, r); |
917 | return r; | |
918 | } | |
919 | ||
920 | /** | |
921 | * amdgpu_cs_wait_ioctl - wait for a command submission to finish | |
922 | * | |
923 | * @dev: drm device | |
924 | * @data: data from userspace | |
925 | * @filp: file private | |
926 | * | |
927 | * Wait for the command submission identified by handle to finish. | |
928 | */ | |
929 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, | |
930 | struct drm_file *filp) | |
931 | { | |
932 | union drm_amdgpu_wait_cs *wait = data; | |
933 | struct amdgpu_device *adev = dev->dev_private; | |
d38ceaf9 | 934 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); |
03507c4f | 935 | struct amdgpu_ring *ring = NULL; |
66b3cf2a | 936 | struct amdgpu_ctx *ctx; |
21c16bf6 | 937 | struct fence *fence; |
d38ceaf9 AD |
938 | long r; |
939 | ||
21c16bf6 CK |
940 | r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance, |
941 | wait->in.ring, &ring); | |
942 | if (r) | |
943 | return r; | |
944 | ||
66b3cf2a JZ |
945 | ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); |
946 | if (ctx == NULL) | |
947 | return -EINVAL; | |
d38ceaf9 | 948 | |
4b559c90 CZ |
949 | fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); |
950 | if (IS_ERR(fence)) | |
951 | r = PTR_ERR(fence); | |
952 | else if (fence) { | |
953 | r = fence_wait_timeout(fence, true, timeout); | |
954 | fence_put(fence); | |
955 | } else | |
956 | r = 1; | |
049fc527 | 957 | |
66b3cf2a | 958 | amdgpu_ctx_put(ctx); |
d38ceaf9 AD |
959 | if (r < 0) |
960 | return r; | |
961 | ||
962 | memset(wait, 0, sizeof(*wait)); | |
963 | wait->out.status = (r == 0); | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
968 | /** | |
969 | * amdgpu_cs_find_bo_va - find bo_va for VM address | |
970 | * | |
971 | * @parser: command submission parser context | |
972 | * @addr: VM address | |
973 | * @bo: resulting BO of the mapping found | |
974 | * | |
975 | * Search the buffer objects in the command submission context for a certain | |
976 | * virtual memory address. Returns allocation structure when found, NULL | |
977 | * otherwise. | |
978 | */ | |
979 | struct amdgpu_bo_va_mapping * | |
980 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
981 | uint64_t addr, struct amdgpu_bo **bo) | |
982 | { | |
d38ceaf9 | 983 | struct amdgpu_bo_va_mapping *mapping; |
15486fd2 CK |
984 | unsigned i; |
985 | ||
986 | if (!parser->bo_list) | |
987 | return NULL; | |
d38ceaf9 AD |
988 | |
989 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
990 | ||
15486fd2 CK |
991 | for (i = 0; i < parser->bo_list->num_entries; i++) { |
992 | struct amdgpu_bo_list_entry *lobj; | |
993 | ||
994 | lobj = &parser->bo_list->array[i]; | |
995 | if (!lobj->bo_va) | |
d38ceaf9 AD |
996 | continue; |
997 | ||
15486fd2 | 998 | list_for_each_entry(mapping, &lobj->bo_va->valids, list) { |
7fc11959 CK |
999 | if (mapping->it.start > addr || |
1000 | addr > mapping->it.last) | |
1001 | continue; | |
1002 | ||
15486fd2 | 1003 | *bo = lobj->bo_va->bo; |
7fc11959 CK |
1004 | return mapping; |
1005 | } | |
1006 | ||
15486fd2 | 1007 | list_for_each_entry(mapping, &lobj->bo_va->invalids, list) { |
d38ceaf9 AD |
1008 | if (mapping->it.start > addr || |
1009 | addr > mapping->it.last) | |
1010 | continue; | |
1011 | ||
15486fd2 | 1012 | *bo = lobj->bo_va->bo; |
d38ceaf9 AD |
1013 | return mapping; |
1014 | } | |
1015 | } | |
1016 | ||
1017 | return NULL; | |
1018 | } |