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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
568d7c76 | 27 | #include <linux/pagemap.h> |
d38ceaf9 AD |
28 | #include <drm/drmP.h> |
29 | #include <drm/amdgpu_drm.h> | |
660e8558 | 30 | #include <drm/drm_syncobj.h> |
d38ceaf9 AD |
31 | #include "amdgpu.h" |
32 | #include "amdgpu_trace.h" | |
33 | ||
91acbeb6 | 34 | static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p, |
758ac17f CK |
35 | struct drm_amdgpu_cs_chunk_fence *data, |
36 | uint32_t *offset) | |
91acbeb6 CK |
37 | { |
38 | struct drm_gem_object *gobj; | |
aa29040b | 39 | unsigned long size; |
91acbeb6 | 40 | |
a8ad0bd8 | 41 | gobj = drm_gem_object_lookup(p->filp, data->handle); |
91acbeb6 CK |
42 | if (gobj == NULL) |
43 | return -EINVAL; | |
44 | ||
758ac17f | 45 | p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj)); |
91acbeb6 CK |
46 | p->uf_entry.priority = 0; |
47 | p->uf_entry.tv.bo = &p->uf_entry.robj->tbo; | |
48 | p->uf_entry.tv.shared = true; | |
2f568dbd | 49 | p->uf_entry.user_pages = NULL; |
aa29040b CK |
50 | |
51 | size = amdgpu_bo_size(p->uf_entry.robj); | |
52 | if (size != PAGE_SIZE || (data->offset + 8) > size) | |
53 | return -EINVAL; | |
54 | ||
758ac17f | 55 | *offset = data->offset; |
91acbeb6 | 56 | |
f62facc2 | 57 | drm_gem_object_put_unlocked(gobj); |
758ac17f CK |
58 | |
59 | if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) { | |
60 | amdgpu_bo_unref(&p->uf_entry.robj); | |
61 | return -EINVAL; | |
62 | } | |
63 | ||
91acbeb6 CK |
64 | return 0; |
65 | } | |
66 | ||
9211c784 | 67 | static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) |
d38ceaf9 | 68 | { |
4c0b242c | 69 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
c5637837 | 70 | struct amdgpu_vm *vm = &fpriv->vm; |
d38ceaf9 AD |
71 | union drm_amdgpu_cs *cs = data; |
72 | uint64_t *chunk_array_user; | |
1d263474 | 73 | uint64_t *chunk_array; |
50838c8c | 74 | unsigned size, num_ibs = 0; |
758ac17f | 75 | uint32_t uf_offset = 0; |
54313503 | 76 | int i; |
1d263474 | 77 | int ret; |
d38ceaf9 | 78 | |
1d263474 DC |
79 | if (cs->in.num_chunks == 0) |
80 | return 0; | |
81 | ||
82 | chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL); | |
83 | if (!chunk_array) | |
84 | return -ENOMEM; | |
d38ceaf9 | 85 | |
3cb485f3 CK |
86 | p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id); |
87 | if (!p->ctx) { | |
1d263474 DC |
88 | ret = -EINVAL; |
89 | goto free_chunk; | |
3cb485f3 | 90 | } |
1d263474 | 91 | |
d38ceaf9 | 92 | /* get chunks */ |
7ecc245a | 93 | chunk_array_user = u64_to_user_ptr(cs->in.chunks); |
d38ceaf9 AD |
94 | if (copy_from_user(chunk_array, chunk_array_user, |
95 | sizeof(uint64_t)*cs->in.num_chunks)) { | |
1d263474 | 96 | ret = -EFAULT; |
2a7d9bda | 97 | goto put_ctx; |
d38ceaf9 AD |
98 | } |
99 | ||
100 | p->nchunks = cs->in.num_chunks; | |
e60b344f | 101 | p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), |
d38ceaf9 | 102 | GFP_KERNEL); |
1d263474 DC |
103 | if (!p->chunks) { |
104 | ret = -ENOMEM; | |
2a7d9bda | 105 | goto put_ctx; |
d38ceaf9 AD |
106 | } |
107 | ||
108 | for (i = 0; i < p->nchunks; i++) { | |
109 | struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL; | |
110 | struct drm_amdgpu_cs_chunk user_chunk; | |
111 | uint32_t __user *cdata; | |
112 | ||
7ecc245a | 113 | chunk_ptr = u64_to_user_ptr(chunk_array[i]); |
d38ceaf9 AD |
114 | if (copy_from_user(&user_chunk, chunk_ptr, |
115 | sizeof(struct drm_amdgpu_cs_chunk))) { | |
1d263474 DC |
116 | ret = -EFAULT; |
117 | i--; | |
118 | goto free_partial_kdata; | |
d38ceaf9 AD |
119 | } |
120 | p->chunks[i].chunk_id = user_chunk.chunk_id; | |
121 | p->chunks[i].length_dw = user_chunk.length_dw; | |
d38ceaf9 AD |
122 | |
123 | size = p->chunks[i].length_dw; | |
7ecc245a | 124 | cdata = u64_to_user_ptr(user_chunk.chunk_data); |
d38ceaf9 | 125 | |
2098105e | 126 | p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); |
d38ceaf9 | 127 | if (p->chunks[i].kdata == NULL) { |
1d263474 DC |
128 | ret = -ENOMEM; |
129 | i--; | |
130 | goto free_partial_kdata; | |
d38ceaf9 AD |
131 | } |
132 | size *= sizeof(uint32_t); | |
133 | if (copy_from_user(p->chunks[i].kdata, cdata, size)) { | |
1d263474 DC |
134 | ret = -EFAULT; |
135 | goto free_partial_kdata; | |
d38ceaf9 AD |
136 | } |
137 | ||
9a5e8fb1 CK |
138 | switch (p->chunks[i].chunk_id) { |
139 | case AMDGPU_CHUNK_ID_IB: | |
50838c8c | 140 | ++num_ibs; |
9a5e8fb1 CK |
141 | break; |
142 | ||
143 | case AMDGPU_CHUNK_ID_FENCE: | |
d38ceaf9 | 144 | size = sizeof(struct drm_amdgpu_cs_chunk_fence); |
91acbeb6 | 145 | if (p->chunks[i].length_dw * sizeof(uint32_t) < size) { |
1d263474 DC |
146 | ret = -EINVAL; |
147 | goto free_partial_kdata; | |
d38ceaf9 | 148 | } |
91acbeb6 | 149 | |
758ac17f CK |
150 | ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata, |
151 | &uf_offset); | |
91acbeb6 CK |
152 | if (ret) |
153 | goto free_partial_kdata; | |
154 | ||
9a5e8fb1 CK |
155 | break; |
156 | ||
2b48d323 | 157 | case AMDGPU_CHUNK_ID_DEPENDENCIES: |
660e8558 DA |
158 | case AMDGPU_CHUNK_ID_SYNCOBJ_IN: |
159 | case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: | |
2b48d323 CK |
160 | break; |
161 | ||
9a5e8fb1 | 162 | default: |
1d263474 DC |
163 | ret = -EINVAL; |
164 | goto free_partial_kdata; | |
d38ceaf9 AD |
165 | } |
166 | } | |
167 | ||
c5637837 | 168 | ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm); |
50838c8c | 169 | if (ret) |
4acabfe3 | 170 | goto free_all_kdata; |
d38ceaf9 | 171 | |
b5f5acbc CK |
172 | if (p->uf_entry.robj) |
173 | p->job->uf_addr = uf_offset; | |
d38ceaf9 | 174 | kfree(chunk_array); |
1d263474 DC |
175 | return 0; |
176 | ||
177 | free_all_kdata: | |
178 | i = p->nchunks - 1; | |
179 | free_partial_kdata: | |
180 | for (; i >= 0; i--) | |
2098105e | 181 | kvfree(p->chunks[i].kdata); |
1d263474 | 182 | kfree(p->chunks); |
607523d1 DA |
183 | p->chunks = NULL; |
184 | p->nchunks = 0; | |
2a7d9bda | 185 | put_ctx: |
1d263474 DC |
186 | amdgpu_ctx_put(p->ctx); |
187 | free_chunk: | |
188 | kfree(chunk_array); | |
189 | ||
190 | return ret; | |
d38ceaf9 AD |
191 | } |
192 | ||
95844d20 MO |
193 | /* Convert microseconds to bytes. */ |
194 | static u64 us_to_bytes(struct amdgpu_device *adev, s64 us) | |
195 | { | |
196 | if (us <= 0 || !adev->mm_stats.log2_max_MBps) | |
197 | return 0; | |
198 | ||
199 | /* Since accum_us is incremented by a million per second, just | |
200 | * multiply it by the number of MB/s to get the number of bytes. | |
201 | */ | |
202 | return us << adev->mm_stats.log2_max_MBps; | |
203 | } | |
204 | ||
205 | static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes) | |
206 | { | |
207 | if (!adev->mm_stats.log2_max_MBps) | |
208 | return 0; | |
209 | ||
210 | return bytes >> adev->mm_stats.log2_max_MBps; | |
211 | } | |
212 | ||
213 | /* Returns how many bytes TTM can move right now. If no bytes can be moved, | |
214 | * it returns 0. If it returns non-zero, it's OK to move at least one buffer, | |
215 | * which means it can go over the threshold once. If that happens, the driver | |
216 | * will be in debt and no other buffer migrations can be done until that debt | |
217 | * is repaid. | |
218 | * | |
219 | * This approach allows moving a buffer of any size (it's important to allow | |
220 | * that). | |
221 | * | |
222 | * The currency is simply time in microseconds and it increases as the clock | |
223 | * ticks. The accumulated microseconds (us) are converted to bytes and | |
224 | * returned. | |
d38ceaf9 | 225 | */ |
00f06b24 JB |
226 | static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, |
227 | u64 *max_bytes, | |
228 | u64 *max_vis_bytes) | |
d38ceaf9 | 229 | { |
95844d20 | 230 | s64 time_us, increment_us; |
95844d20 | 231 | u64 free_vram, total_vram, used_vram; |
d38ceaf9 | 232 | |
95844d20 MO |
233 | /* Allow a maximum of 200 accumulated ms. This is basically per-IB |
234 | * throttling. | |
d38ceaf9 | 235 | * |
95844d20 MO |
236 | * It means that in order to get full max MBps, at least 5 IBs per |
237 | * second must be submitted and not more than 200ms apart from each | |
238 | * other. | |
239 | */ | |
240 | const s64 us_upper_bound = 200000; | |
d38ceaf9 | 241 | |
00f06b24 JB |
242 | if (!adev->mm_stats.log2_max_MBps) { |
243 | *max_bytes = 0; | |
244 | *max_vis_bytes = 0; | |
245 | return; | |
246 | } | |
95844d20 MO |
247 | |
248 | total_vram = adev->mc.real_vram_size - adev->vram_pin_size; | |
3c848bb3 | 249 | used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); |
95844d20 MO |
250 | free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram; |
251 | ||
252 | spin_lock(&adev->mm_stats.lock); | |
253 | ||
254 | /* Increase the amount of accumulated us. */ | |
255 | time_us = ktime_to_us(ktime_get()); | |
256 | increment_us = time_us - adev->mm_stats.last_update_us; | |
257 | adev->mm_stats.last_update_us = time_us; | |
258 | adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us, | |
259 | us_upper_bound); | |
260 | ||
261 | /* This prevents the short period of low performance when the VRAM | |
262 | * usage is low and the driver is in debt or doesn't have enough | |
263 | * accumulated us to fill VRAM quickly. | |
d38ceaf9 | 264 | * |
95844d20 MO |
265 | * The situation can occur in these cases: |
266 | * - a lot of VRAM is freed by userspace | |
267 | * - the presence of a big buffer causes a lot of evictions | |
268 | * (solution: split buffers into smaller ones) | |
d38ceaf9 | 269 | * |
95844d20 MO |
270 | * If 128 MB or 1/8th of VRAM is free, start filling it now by setting |
271 | * accum_us to a positive number. | |
d38ceaf9 | 272 | */ |
95844d20 MO |
273 | if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) { |
274 | s64 min_us; | |
275 | ||
276 | /* Be more aggresive on dGPUs. Try to fill a portion of free | |
277 | * VRAM now. | |
278 | */ | |
279 | if (!(adev->flags & AMD_IS_APU)) | |
280 | min_us = bytes_to_us(adev, free_vram / 4); | |
281 | else | |
282 | min_us = 0; /* Reset accum_us on APUs. */ | |
283 | ||
284 | adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us); | |
285 | } | |
d38ceaf9 | 286 | |
00f06b24 | 287 | /* This is set to 0 if the driver is in debt to disallow (optional) |
95844d20 MO |
288 | * buffer moves. |
289 | */ | |
00f06b24 JB |
290 | *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us); |
291 | ||
292 | /* Do the same for visible VRAM if half of it is free */ | |
293 | if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { | |
294 | u64 total_vis_vram = adev->mc.visible_vram_size; | |
3c848bb3 CK |
295 | u64 used_vis_vram = |
296 | amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); | |
00f06b24 JB |
297 | |
298 | if (used_vis_vram < total_vis_vram) { | |
299 | u64 free_vis_vram = total_vis_vram - used_vis_vram; | |
300 | adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis + | |
301 | increment_us, us_upper_bound); | |
302 | ||
303 | if (free_vis_vram >= total_vis_vram / 2) | |
304 | adev->mm_stats.accum_us_vis = | |
305 | max(bytes_to_us(adev, free_vis_vram / 2), | |
306 | adev->mm_stats.accum_us_vis); | |
307 | } | |
308 | ||
309 | *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis); | |
310 | } else { | |
311 | *max_vis_bytes = 0; | |
312 | } | |
95844d20 MO |
313 | |
314 | spin_unlock(&adev->mm_stats.lock); | |
95844d20 MO |
315 | } |
316 | ||
317 | /* Report how many bytes have really been moved for the last command | |
318 | * submission. This can result in a debt that can stop buffer migrations | |
319 | * temporarily. | |
320 | */ | |
00f06b24 JB |
321 | void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, |
322 | u64 num_vis_bytes) | |
95844d20 MO |
323 | { |
324 | spin_lock(&adev->mm_stats.lock); | |
325 | adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes); | |
00f06b24 | 326 | adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes); |
95844d20 | 327 | spin_unlock(&adev->mm_stats.lock); |
d38ceaf9 AD |
328 | } |
329 | ||
14fd833e CZ |
330 | static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, |
331 | struct amdgpu_bo *bo) | |
332 | { | |
a7d64de6 | 333 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
00f06b24 | 334 | u64 initial_bytes_moved, bytes_moved; |
14fd833e CZ |
335 | uint32_t domain; |
336 | int r; | |
337 | ||
338 | if (bo->pin_count) | |
339 | return 0; | |
340 | ||
95844d20 MO |
341 | /* Don't move this buffer if we have depleted our allowance |
342 | * to move it. Don't move anything if the threshold is zero. | |
14fd833e | 343 | */ |
00f06b24 JB |
344 | if (p->bytes_moved < p->bytes_moved_threshold) { |
345 | if (adev->mc.visible_vram_size < adev->mc.real_vram_size && | |
346 | (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) { | |
347 | /* And don't move a CPU_ACCESS_REQUIRED BO to limited | |
348 | * visible VRAM if we've depleted our allowance to do | |
349 | * that. | |
350 | */ | |
351 | if (p->bytes_moved_vis < p->bytes_moved_vis_threshold) | |
6d7d9c5a | 352 | domain = bo->preferred_domains; |
00f06b24 JB |
353 | else |
354 | domain = bo->allowed_domains; | |
355 | } else { | |
6d7d9c5a | 356 | domain = bo->preferred_domains; |
00f06b24 JB |
357 | } |
358 | } else { | |
14fd833e | 359 | domain = bo->allowed_domains; |
00f06b24 | 360 | } |
14fd833e CZ |
361 | |
362 | retry: | |
363 | amdgpu_ttm_placement_from_domain(bo, domain); | |
a7d64de6 | 364 | initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); |
14fd833e | 365 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
00f06b24 JB |
366 | bytes_moved = atomic64_read(&adev->num_bytes_moved) - |
367 | initial_bytes_moved; | |
368 | p->bytes_moved += bytes_moved; | |
369 | if (adev->mc.visible_vram_size < adev->mc.real_vram_size && | |
370 | bo->tbo.mem.mem_type == TTM_PL_VRAM && | |
371 | bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) | |
372 | p->bytes_moved_vis += bytes_moved; | |
14fd833e | 373 | |
1abdc3d7 CK |
374 | if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { |
375 | domain = bo->allowed_domains; | |
376 | goto retry; | |
14fd833e CZ |
377 | } |
378 | ||
379 | return r; | |
380 | } | |
381 | ||
662bfa61 CK |
382 | /* Last resort, try to evict something from the current working set */ |
383 | static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, | |
f7da30d9 | 384 | struct amdgpu_bo *validated) |
662bfa61 | 385 | { |
f7da30d9 | 386 | uint32_t domain = validated->allowed_domains; |
662bfa61 CK |
387 | int r; |
388 | ||
389 | if (!p->evictable) | |
390 | return false; | |
391 | ||
392 | for (;&p->evictable->tv.head != &p->validated; | |
393 | p->evictable = list_prev_entry(p->evictable, tv.head)) { | |
394 | ||
395 | struct amdgpu_bo_list_entry *candidate = p->evictable; | |
396 | struct amdgpu_bo *bo = candidate->robj; | |
a7d64de6 | 397 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
00f06b24 JB |
398 | u64 initial_bytes_moved, bytes_moved; |
399 | bool update_bytes_moved_vis; | |
662bfa61 CK |
400 | uint32_t other; |
401 | ||
402 | /* If we reached our current BO we can forget it */ | |
f7da30d9 | 403 | if (candidate->robj == validated) |
662bfa61 CK |
404 | break; |
405 | ||
406 | other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
407 | ||
408 | /* Check if this BO is in one of the domains we need space for */ | |
409 | if (!(other & domain)) | |
410 | continue; | |
411 | ||
412 | /* Check if we can move this BO somewhere else */ | |
413 | other = bo->allowed_domains & ~domain; | |
414 | if (!other) | |
415 | continue; | |
416 | ||
417 | /* Good we can try to move this BO somewhere else */ | |
418 | amdgpu_ttm_placement_from_domain(bo, other); | |
00f06b24 JB |
419 | update_bytes_moved_vis = |
420 | adev->mc.visible_vram_size < adev->mc.real_vram_size && | |
421 | bo->tbo.mem.mem_type == TTM_PL_VRAM && | |
422 | bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT; | |
a7d64de6 | 423 | initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); |
662bfa61 | 424 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
00f06b24 | 425 | bytes_moved = atomic64_read(&adev->num_bytes_moved) - |
662bfa61 | 426 | initial_bytes_moved; |
00f06b24 JB |
427 | p->bytes_moved += bytes_moved; |
428 | if (update_bytes_moved_vis) | |
429 | p->bytes_moved_vis += bytes_moved; | |
662bfa61 CK |
430 | |
431 | if (unlikely(r)) | |
432 | break; | |
433 | ||
434 | p->evictable = list_prev_entry(p->evictable, tv.head); | |
435 | list_move(&candidate->tv.head, &p->validated); | |
436 | ||
437 | return true; | |
438 | } | |
439 | ||
440 | return false; | |
441 | } | |
442 | ||
f7da30d9 CK |
443 | static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo) |
444 | { | |
445 | struct amdgpu_cs_parser *p = param; | |
446 | int r; | |
447 | ||
448 | do { | |
449 | r = amdgpu_cs_bo_validate(p, bo); | |
450 | } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo)); | |
451 | if (r) | |
452 | return r; | |
453 | ||
454 | if (bo->shadow) | |
1cd99a8d | 455 | r = amdgpu_cs_bo_validate(p, bo->shadow); |
f7da30d9 CK |
456 | |
457 | return r; | |
458 | } | |
459 | ||
761c2e82 | 460 | static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, |
a5b75058 | 461 | struct list_head *validated) |
d38ceaf9 | 462 | { |
d38ceaf9 | 463 | struct amdgpu_bo_list_entry *lobj; |
d38ceaf9 AD |
464 | int r; |
465 | ||
a5b75058 | 466 | list_for_each_entry(lobj, validated, tv.head) { |
36409d12 | 467 | struct amdgpu_bo *bo = lobj->robj; |
2f568dbd | 468 | bool binding_userptr = false; |
cc325d19 | 469 | struct mm_struct *usermm; |
d38ceaf9 | 470 | |
cc325d19 CK |
471 | usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm); |
472 | if (usermm && usermm != current->mm) | |
473 | return -EPERM; | |
474 | ||
2f568dbd | 475 | /* Check if we have user pages and nobody bound the BO already */ |
ca666a3c CK |
476 | if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && |
477 | lobj->user_pages) { | |
1b0c0f9d CK |
478 | amdgpu_ttm_placement_from_domain(bo, |
479 | AMDGPU_GEM_DOMAIN_CPU); | |
480 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, | |
481 | false); | |
482 | if (r) | |
483 | return r; | |
a216ab09 CK |
484 | amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, |
485 | lobj->user_pages); | |
2f568dbd CK |
486 | binding_userptr = true; |
487 | } | |
488 | ||
662bfa61 CK |
489 | if (p->evictable == lobj) |
490 | p->evictable = NULL; | |
491 | ||
f7da30d9 | 492 | r = amdgpu_cs_validate(p, bo); |
14fd833e | 493 | if (r) |
36409d12 | 494 | return r; |
662bfa61 | 495 | |
2f568dbd | 496 | if (binding_userptr) { |
2098105e | 497 | kvfree(lobj->user_pages); |
2f568dbd CK |
498 | lobj->user_pages = NULL; |
499 | } | |
d38ceaf9 AD |
500 | } |
501 | return 0; | |
502 | } | |
503 | ||
2a7d9bda CK |
504 | static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, |
505 | union drm_amdgpu_cs *cs) | |
d38ceaf9 AD |
506 | { |
507 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; | |
2f568dbd | 508 | struct amdgpu_bo_list_entry *e; |
a5b75058 | 509 | struct list_head duplicates; |
2f568dbd | 510 | unsigned i, tries = 10; |
636ce25c | 511 | int r; |
d38ceaf9 | 512 | |
2a7d9bda CK |
513 | INIT_LIST_HEAD(&p->validated); |
514 | ||
515 | p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle); | |
3fe89771 | 516 | if (p->bo_list) { |
636ce25c | 517 | amdgpu_bo_list_get_list(p->bo_list, &p->validated); |
3fe89771 CK |
518 | if (p->bo_list->first_userptr != p->bo_list->num_entries) |
519 | p->mn = amdgpu_mn_get(p->adev); | |
520 | } | |
d38ceaf9 | 521 | |
3c0eea6c | 522 | INIT_LIST_HEAD(&duplicates); |
56467ebf | 523 | amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd); |
d38ceaf9 | 524 | |
758ac17f | 525 | if (p->uf_entry.robj) |
91acbeb6 CK |
526 | list_add(&p->uf_entry.tv.head, &p->validated); |
527 | ||
2f568dbd CK |
528 | while (1) { |
529 | struct list_head need_pages; | |
530 | unsigned i; | |
531 | ||
532 | r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, | |
533 | &duplicates); | |
f1037950 | 534 | if (unlikely(r != 0)) { |
57d7f9b6 | 535 | if (r != -ERESTARTSYS) |
536 | DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); | |
2f568dbd | 537 | goto error_free_pages; |
f1037950 | 538 | } |
2f568dbd CK |
539 | |
540 | /* Without a BO list we don't have userptr BOs */ | |
541 | if (!p->bo_list) | |
542 | break; | |
543 | ||
544 | INIT_LIST_HEAD(&need_pages); | |
545 | for (i = p->bo_list->first_userptr; | |
546 | i < p->bo_list->num_entries; ++i) { | |
ca666a3c | 547 | struct amdgpu_bo *bo; |
2f568dbd CK |
548 | |
549 | e = &p->bo_list->array[i]; | |
ca666a3c | 550 | bo = e->robj; |
2f568dbd | 551 | |
ca666a3c | 552 | if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, |
2f568dbd CK |
553 | &e->user_invalidated) && e->user_pages) { |
554 | ||
555 | /* We acquired a page array, but somebody | |
9f69c0fd | 556 | * invalidated it. Free it and try again |
2f568dbd CK |
557 | */ |
558 | release_pages(e->user_pages, | |
ca666a3c | 559 | bo->tbo.ttm->num_pages, |
2f568dbd | 560 | false); |
2098105e | 561 | kvfree(e->user_pages); |
2f568dbd CK |
562 | e->user_pages = NULL; |
563 | } | |
564 | ||
ca666a3c | 565 | if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && |
2f568dbd CK |
566 | !e->user_pages) { |
567 | list_del(&e->tv.head); | |
568 | list_add(&e->tv.head, &need_pages); | |
569 | ||
570 | amdgpu_bo_unreserve(e->robj); | |
571 | } | |
572 | } | |
573 | ||
574 | if (list_empty(&need_pages)) | |
575 | break; | |
576 | ||
577 | /* Unreserve everything again. */ | |
578 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); | |
579 | ||
f1037950 | 580 | /* We tried too many times, just abort */ |
2f568dbd CK |
581 | if (!--tries) { |
582 | r = -EDEADLK; | |
f1037950 | 583 | DRM_ERROR("deadlock in %s\n", __func__); |
2f568dbd CK |
584 | goto error_free_pages; |
585 | } | |
586 | ||
eb0f0373 | 587 | /* Fill the page arrays for all userptrs. */ |
2f568dbd CK |
588 | list_for_each_entry(e, &need_pages, tv.head) { |
589 | struct ttm_tt *ttm = e->robj->tbo.ttm; | |
590 | ||
2098105e MH |
591 | e->user_pages = kvmalloc_array(ttm->num_pages, |
592 | sizeof(struct page*), | |
593 | GFP_KERNEL | __GFP_ZERO); | |
2f568dbd CK |
594 | if (!e->user_pages) { |
595 | r = -ENOMEM; | |
f1037950 | 596 | DRM_ERROR("calloc failure in %s\n", __func__); |
2f568dbd CK |
597 | goto error_free_pages; |
598 | } | |
599 | ||
600 | r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages); | |
601 | if (r) { | |
f1037950 | 602 | DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); |
2098105e | 603 | kvfree(e->user_pages); |
2f568dbd CK |
604 | e->user_pages = NULL; |
605 | goto error_free_pages; | |
606 | } | |
607 | } | |
608 | ||
609 | /* And try again. */ | |
610 | list_splice(&need_pages, &p->validated); | |
611 | } | |
a5b75058 | 612 | |
00f06b24 JB |
613 | amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold, |
614 | &p->bytes_moved_vis_threshold); | |
f69f90a1 | 615 | p->bytes_moved = 0; |
00f06b24 | 616 | p->bytes_moved_vis = 0; |
662bfa61 CK |
617 | p->evictable = list_last_entry(&p->validated, |
618 | struct amdgpu_bo_list_entry, | |
619 | tv.head); | |
f69f90a1 | 620 | |
f7da30d9 CK |
621 | r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm, |
622 | amdgpu_cs_validate, p); | |
623 | if (r) { | |
624 | DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n"); | |
625 | goto error_validate; | |
626 | } | |
627 | ||
f69f90a1 | 628 | r = amdgpu_cs_list_validate(p, &duplicates); |
f1037950 MO |
629 | if (r) { |
630 | DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n"); | |
a5b75058 | 631 | goto error_validate; |
f1037950 | 632 | } |
a5b75058 | 633 | |
f69f90a1 | 634 | r = amdgpu_cs_list_validate(p, &p->validated); |
f1037950 MO |
635 | if (r) { |
636 | DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n"); | |
a8480309 | 637 | goto error_validate; |
f1037950 | 638 | } |
a8480309 | 639 | |
00f06b24 JB |
640 | amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved, |
641 | p->bytes_moved_vis); | |
a8480309 | 642 | if (p->bo_list) { |
d88bf583 CK |
643 | struct amdgpu_bo *gds = p->bo_list->gds_obj; |
644 | struct amdgpu_bo *gws = p->bo_list->gws_obj; | |
645 | struct amdgpu_bo *oa = p->bo_list->oa_obj; | |
a8480309 CK |
646 | struct amdgpu_vm *vm = &fpriv->vm; |
647 | unsigned i; | |
648 | ||
649 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
650 | struct amdgpu_bo *bo = p->bo_list->array[i].robj; | |
651 | ||
652 | p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo); | |
653 | } | |
d88bf583 CK |
654 | |
655 | if (gds) { | |
656 | p->job->gds_base = amdgpu_bo_gpu_offset(gds); | |
657 | p->job->gds_size = amdgpu_bo_size(gds); | |
658 | } | |
659 | if (gws) { | |
660 | p->job->gws_base = amdgpu_bo_gpu_offset(gws); | |
661 | p->job->gws_size = amdgpu_bo_size(gws); | |
662 | } | |
663 | if (oa) { | |
664 | p->job->oa_base = amdgpu_bo_gpu_offset(oa); | |
665 | p->job->oa_size = amdgpu_bo_size(oa); | |
666 | } | |
a8480309 | 667 | } |
a5b75058 | 668 | |
c855e250 CK |
669 | if (!r && p->uf_entry.robj) { |
670 | struct amdgpu_bo *uf = p->uf_entry.robj; | |
671 | ||
bb990bb0 | 672 | r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem); |
c855e250 CK |
673 | p->job->uf_addr += amdgpu_bo_gpu_offset(uf); |
674 | } | |
b5f5acbc | 675 | |
a5b75058 | 676 | error_validate: |
b6369225 | 677 | if (r) |
a5b75058 | 678 | ttm_eu_backoff_reservation(&p->ticket, &p->validated); |
d38ceaf9 | 679 | |
2f568dbd CK |
680 | error_free_pages: |
681 | ||
2f568dbd CK |
682 | if (p->bo_list) { |
683 | for (i = p->bo_list->first_userptr; | |
684 | i < p->bo_list->num_entries; ++i) { | |
685 | e = &p->bo_list->array[i]; | |
686 | ||
687 | if (!e->user_pages) | |
688 | continue; | |
689 | ||
690 | release_pages(e->user_pages, | |
691 | e->robj->tbo.ttm->num_pages, | |
692 | false); | |
2098105e | 693 | kvfree(e->user_pages); |
2f568dbd CK |
694 | } |
695 | } | |
696 | ||
d38ceaf9 AD |
697 | return r; |
698 | } | |
699 | ||
700 | static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) | |
701 | { | |
702 | struct amdgpu_bo_list_entry *e; | |
703 | int r; | |
704 | ||
705 | list_for_each_entry(e, &p->validated, tv.head) { | |
706 | struct reservation_object *resv = e->robj->tbo.resv; | |
e86f9cee | 707 | r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp); |
d38ceaf9 AD |
708 | |
709 | if (r) | |
710 | return r; | |
711 | } | |
712 | return 0; | |
713 | } | |
714 | ||
984810fc CK |
715 | /** |
716 | * cs_parser_fini() - clean parser states | |
717 | * @parser: parser structure holding parsing context. | |
718 | * @error: error number | |
719 | * | |
720 | * If error is set than unvalidate buffer, otherwise just free memory | |
721 | * used by parsing context. | |
722 | **/ | |
b6369225 CK |
723 | static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, |
724 | bool backoff) | |
049fc527 | 725 | { |
984810fc CK |
726 | unsigned i; |
727 | ||
3fe89771 | 728 | if (error && backoff) |
d38ceaf9 AD |
729 | ttm_eu_backoff_reservation(&parser->ticket, |
730 | &parser->validated); | |
660e8558 DA |
731 | |
732 | for (i = 0; i < parser->num_post_dep_syncobjs; i++) | |
733 | drm_syncobj_put(parser->post_dep_syncobjs[i]); | |
734 | kfree(parser->post_dep_syncobjs); | |
735 | ||
f54d1867 | 736 | dma_fence_put(parser->fence); |
7e52a81c | 737 | |
3cb485f3 CK |
738 | if (parser->ctx) |
739 | amdgpu_ctx_put(parser->ctx); | |
a3348bb8 CZ |
740 | if (parser->bo_list) |
741 | amdgpu_bo_list_put(parser->bo_list); | |
742 | ||
d38ceaf9 | 743 | for (i = 0; i < parser->nchunks; i++) |
2098105e | 744 | kvfree(parser->chunks[i].kdata); |
d38ceaf9 | 745 | kfree(parser->chunks); |
50838c8c CK |
746 | if (parser->job) |
747 | amdgpu_job_free(parser->job); | |
91acbeb6 | 748 | amdgpu_bo_unref(&parser->uf_entry.robj); |
d38ceaf9 AD |
749 | } |
750 | ||
b85891bd | 751 | static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) |
d38ceaf9 AD |
752 | { |
753 | struct amdgpu_device *adev = p->adev; | |
b85891bd JZ |
754 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
755 | struct amdgpu_vm *vm = &fpriv->vm; | |
d38ceaf9 AD |
756 | struct amdgpu_bo_va *bo_va; |
757 | struct amdgpu_bo *bo; | |
758 | int i, r; | |
759 | ||
194d2161 | 760 | r = amdgpu_vm_update_directories(adev, vm); |
d38ceaf9 AD |
761 | if (r) |
762 | return r; | |
763 | ||
a24960f3 | 764 | r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update); |
05906dec BN |
765 | if (r) |
766 | return r; | |
767 | ||
f3467818 | 768 | r = amdgpu_vm_clear_freed(adev, vm, NULL); |
d38ceaf9 AD |
769 | if (r) |
770 | return r; | |
771 | ||
b85891bd JZ |
772 | r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false); |
773 | if (r) | |
774 | return r; | |
775 | ||
776 | r = amdgpu_sync_fence(adev, &p->job->sync, | |
777 | fpriv->prt_va->last_pt_update); | |
778 | if (r) | |
779 | return r; | |
780 | ||
2493664f ML |
781 | if (amdgpu_sriov_vf(adev)) { |
782 | struct dma_fence *f; | |
0f4b3c68 CK |
783 | |
784 | bo_va = fpriv->csa_va; | |
2493664f ML |
785 | BUG_ON(!bo_va); |
786 | r = amdgpu_vm_bo_update(adev, bo_va, false); | |
787 | if (r) | |
788 | return r; | |
789 | ||
790 | f = bo_va->last_pt_update; | |
791 | r = amdgpu_sync_fence(adev, &p->job->sync, f); | |
792 | if (r) | |
793 | return r; | |
794 | } | |
795 | ||
d38ceaf9 AD |
796 | if (p->bo_list) { |
797 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
f54d1867 | 798 | struct dma_fence *f; |
91e1a520 | 799 | |
d38ceaf9 AD |
800 | /* ignore duplicates */ |
801 | bo = p->bo_list->array[i].robj; | |
802 | if (!bo) | |
803 | continue; | |
804 | ||
805 | bo_va = p->bo_list->array[i].bo_va; | |
806 | if (bo_va == NULL) | |
807 | continue; | |
808 | ||
99e124f4 | 809 | r = amdgpu_vm_bo_update(adev, bo_va, false); |
d38ceaf9 AD |
810 | if (r) |
811 | return r; | |
812 | ||
bb1e38a4 | 813 | f = bo_va->last_pt_update; |
e86f9cee | 814 | r = amdgpu_sync_fence(adev, &p->job->sync, f); |
91e1a520 CK |
815 | if (r) |
816 | return r; | |
d38ceaf9 | 817 | } |
b495bd3a CK |
818 | |
819 | } | |
820 | ||
73fb16e7 | 821 | r = amdgpu_vm_handle_moved(adev, vm, &p->job->sync); |
b495bd3a CK |
822 | |
823 | if (amdgpu_vm_debug && p->bo_list) { | |
824 | /* Invalidate all BOs to test for userspace bugs */ | |
825 | for (i = 0; i < p->bo_list->num_entries; i++) { | |
826 | /* ignore duplicates */ | |
827 | bo = p->bo_list->array[i].robj; | |
828 | if (!bo) | |
829 | continue; | |
830 | ||
3f3333f8 | 831 | amdgpu_vm_bo_invalidate(adev, bo, false); |
b495bd3a | 832 | } |
d38ceaf9 AD |
833 | } |
834 | ||
b495bd3a | 835 | return r; |
d38ceaf9 AD |
836 | } |
837 | ||
838 | static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, | |
b07c60c0 | 839 | struct amdgpu_cs_parser *p) |
d38ceaf9 | 840 | { |
b07c60c0 | 841 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
d38ceaf9 | 842 | struct amdgpu_vm *vm = &fpriv->vm; |
b07c60c0 | 843 | struct amdgpu_ring *ring = p->job->ring; |
d38ceaf9 AD |
844 | int i, r; |
845 | ||
d38ceaf9 | 846 | /* Only for UVD/VCE VM emulation */ |
b07c60c0 CK |
847 | if (ring->funcs->parse_cs) { |
848 | for (i = 0; i < p->job->num_ibs; i++) { | |
849 | r = amdgpu_ring_parse_cs(ring, p, i); | |
d38ceaf9 AD |
850 | if (r) |
851 | return r; | |
852 | } | |
45088efc CK |
853 | } |
854 | ||
855 | if (p->job->vm) { | |
3f3333f8 | 856 | p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo); |
281d144d | 857 | |
b85891bd | 858 | r = amdgpu_bo_vm_update_pte(p); |
9a79588c CK |
859 | if (r) |
860 | return r; | |
861 | } | |
d38ceaf9 | 862 | |
9a79588c | 863 | return amdgpu_cs_sync_rings(p); |
d38ceaf9 AD |
864 | } |
865 | ||
d38ceaf9 AD |
866 | static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, |
867 | struct amdgpu_cs_parser *parser) | |
868 | { | |
869 | struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; | |
870 | struct amdgpu_vm *vm = &fpriv->vm; | |
871 | int i, j; | |
9a1b3af1 | 872 | int r, ce_preempt = 0, de_preempt = 0; |
d38ceaf9 | 873 | |
50838c8c | 874 | for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) { |
d38ceaf9 AD |
875 | struct amdgpu_cs_chunk *chunk; |
876 | struct amdgpu_ib *ib; | |
877 | struct drm_amdgpu_cs_chunk_ib *chunk_ib; | |
d38ceaf9 | 878 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
879 | |
880 | chunk = &parser->chunks[i]; | |
50838c8c | 881 | ib = &parser->job->ibs[j]; |
d38ceaf9 AD |
882 | chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata; |
883 | ||
884 | if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) | |
885 | continue; | |
886 | ||
65333e44 | 887 | if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) { |
e51a3226 | 888 | if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) { |
65333e44 ML |
889 | if (chunk_ib->flags & AMDGPU_IB_FLAG_CE) |
890 | ce_preempt++; | |
891 | else | |
892 | de_preempt++; | |
e51a3226 | 893 | } |
65333e44 ML |
894 | |
895 | /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */ | |
896 | if (ce_preempt > 1 || de_preempt > 1) | |
e9d672b2 | 897 | return -EINVAL; |
9a1b3af1 ML |
898 | } |
899 | ||
effd924d AR |
900 | r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type, |
901 | chunk_ib->ip_instance, chunk_ib->ring, &ring); | |
3ccec53c | 902 | if (r) |
d38ceaf9 | 903 | return r; |
d38ceaf9 | 904 | |
2a9ceb8d | 905 | if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) { |
753ad49c ML |
906 | parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT; |
907 | if (!parser->ctx->preamble_presented) { | |
908 | parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST; | |
909 | parser->ctx->preamble_presented = true; | |
910 | } | |
911 | } | |
912 | ||
b07c60c0 CK |
913 | if (parser->job->ring && parser->job->ring != ring) |
914 | return -EINVAL; | |
915 | ||
916 | parser->job->ring = ring; | |
917 | ||
d38ceaf9 | 918 | if (ring->funcs->parse_cs) { |
4802ce11 | 919 | struct amdgpu_bo_va_mapping *m; |
3ccec53c | 920 | struct amdgpu_bo *aobj = NULL; |
4802ce11 CK |
921 | uint64_t offset; |
922 | uint8_t *kptr; | |
3ccec53c | 923 | |
4802ce11 CK |
924 | m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start, |
925 | &aobj); | |
3ccec53c MO |
926 | if (!aobj) { |
927 | DRM_ERROR("IB va_start is invalid\n"); | |
928 | return -EINVAL; | |
d38ceaf9 AD |
929 | } |
930 | ||
4802ce11 | 931 | if ((chunk_ib->va_start + chunk_ib->ib_bytes) > |
a9f87f64 | 932 | (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) { |
4802ce11 CK |
933 | DRM_ERROR("IB va_start+ib_bytes is invalid\n"); |
934 | return -EINVAL; | |
935 | } | |
936 | ||
3ccec53c | 937 | /* the IB should be reserved at this point */ |
4802ce11 | 938 | r = amdgpu_bo_kmap(aobj, (void **)&kptr); |
d38ceaf9 | 939 | if (r) { |
d38ceaf9 AD |
940 | return r; |
941 | } | |
942 | ||
a9f87f64 | 943 | offset = m->start * AMDGPU_GPU_PAGE_SIZE; |
4802ce11 CK |
944 | kptr += chunk_ib->va_start - offset; |
945 | ||
45088efc | 946 | r = amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib); |
d38ceaf9 AD |
947 | if (r) { |
948 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
949 | return r; |
950 | } | |
951 | ||
952 | memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); | |
953 | amdgpu_bo_kunmap(aobj); | |
d38ceaf9 | 954 | } else { |
b07c60c0 | 955 | r = amdgpu_ib_get(adev, vm, 0, ib); |
d38ceaf9 AD |
956 | if (r) { |
957 | DRM_ERROR("Failed to get ib !\n"); | |
d38ceaf9 AD |
958 | return r; |
959 | } | |
960 | ||
d38ceaf9 | 961 | } |
d38ceaf9 | 962 | |
45088efc | 963 | ib->gpu_addr = chunk_ib->va_start; |
3ccec53c | 964 | ib->length_dw = chunk_ib->ib_bytes / 4; |
de807f81 | 965 | ib->flags = chunk_ib->flags; |
d38ceaf9 AD |
966 | j++; |
967 | } | |
968 | ||
758ac17f | 969 | /* UVD & VCE fw doesn't support user fences */ |
b5f5acbc | 970 | if (parser->job->uf_addr && ( |
21cd942e CK |
971 | parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD || |
972 | parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE)) | |
758ac17f | 973 | return -EINVAL; |
d38ceaf9 AD |
974 | |
975 | return 0; | |
976 | } | |
977 | ||
6f0308eb DA |
978 | static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, |
979 | struct amdgpu_cs_chunk *chunk) | |
2b48d323 | 980 | { |
76a1ea61 | 981 | struct amdgpu_fpriv *fpriv = p->filp->driver_priv; |
6f0308eb DA |
982 | unsigned num_deps; |
983 | int i, r; | |
984 | struct drm_amdgpu_cs_chunk_dep *deps; | |
2b48d323 | 985 | |
6f0308eb DA |
986 | deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata; |
987 | num_deps = chunk->length_dw * 4 / | |
988 | sizeof(struct drm_amdgpu_cs_chunk_dep); | |
2b48d323 | 989 | |
6f0308eb DA |
990 | for (i = 0; i < num_deps; ++i) { |
991 | struct amdgpu_ring *ring; | |
992 | struct amdgpu_ctx *ctx; | |
993 | struct dma_fence *fence; | |
2b48d323 | 994 | |
6f0308eb DA |
995 | ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id); |
996 | if (ctx == NULL) | |
997 | return -EINVAL; | |
2b48d323 | 998 | |
6f0308eb DA |
999 | r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr, |
1000 | deps[i].ip_type, | |
1001 | deps[i].ip_instance, | |
1002 | deps[i].ring, &ring); | |
1003 | if (r) { | |
1004 | amdgpu_ctx_put(ctx); | |
1005 | return r; | |
1006 | } | |
2b48d323 | 1007 | |
6f0308eb DA |
1008 | fence = amdgpu_ctx_get_fence(ctx, ring, |
1009 | deps[i].handle); | |
1010 | if (IS_ERR(fence)) { | |
1011 | r = PTR_ERR(fence); | |
1012 | amdgpu_ctx_put(ctx); | |
1013 | return r; | |
1014 | } else if (fence) { | |
1015 | r = amdgpu_sync_fence(p->adev, &p->job->sync, | |
1016 | fence); | |
1017 | dma_fence_put(fence); | |
1018 | amdgpu_ctx_put(ctx); | |
1019 | if (r) | |
1020 | return r; | |
1021 | } | |
1022 | } | |
1023 | return 0; | |
1024 | } | |
2b48d323 | 1025 | |
660e8558 DA |
1026 | static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p, |
1027 | uint32_t handle) | |
1028 | { | |
1029 | int r; | |
1030 | struct dma_fence *fence; | |
afaf5923 | 1031 | r = drm_syncobj_find_fence(p->filp, handle, &fence); |
660e8558 DA |
1032 | if (r) |
1033 | return r; | |
1034 | ||
1035 | r = amdgpu_sync_fence(p->adev, &p->job->sync, fence); | |
1036 | dma_fence_put(fence); | |
1037 | ||
1038 | return r; | |
1039 | } | |
1040 | ||
1041 | static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p, | |
1042 | struct amdgpu_cs_chunk *chunk) | |
1043 | { | |
1044 | unsigned num_deps; | |
1045 | int i, r; | |
1046 | struct drm_amdgpu_cs_chunk_sem *deps; | |
1047 | ||
1048 | deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata; | |
1049 | num_deps = chunk->length_dw * 4 / | |
1050 | sizeof(struct drm_amdgpu_cs_chunk_sem); | |
1051 | ||
1052 | for (i = 0; i < num_deps; ++i) { | |
1053 | r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle); | |
1054 | if (r) | |
1055 | return r; | |
1056 | } | |
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p, | |
1061 | struct amdgpu_cs_chunk *chunk) | |
1062 | { | |
1063 | unsigned num_deps; | |
1064 | int i; | |
1065 | struct drm_amdgpu_cs_chunk_sem *deps; | |
1066 | deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata; | |
1067 | num_deps = chunk->length_dw * 4 / | |
1068 | sizeof(struct drm_amdgpu_cs_chunk_sem); | |
1069 | ||
1070 | p->post_dep_syncobjs = kmalloc_array(num_deps, | |
1071 | sizeof(struct drm_syncobj *), | |
1072 | GFP_KERNEL); | |
1073 | p->num_post_dep_syncobjs = 0; | |
1074 | ||
06f10a53 CJ |
1075 | if (!p->post_dep_syncobjs) |
1076 | return -ENOMEM; | |
1077 | ||
660e8558 DA |
1078 | for (i = 0; i < num_deps; ++i) { |
1079 | p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle); | |
1080 | if (!p->post_dep_syncobjs[i]) | |
1081 | return -EINVAL; | |
1082 | p->num_post_dep_syncobjs++; | |
1083 | } | |
1084 | return 0; | |
1085 | } | |
1086 | ||
6f0308eb DA |
1087 | static int amdgpu_cs_dependencies(struct amdgpu_device *adev, |
1088 | struct amdgpu_cs_parser *p) | |
1089 | { | |
1090 | int i, r; | |
76a1ea61 | 1091 | |
6f0308eb DA |
1092 | for (i = 0; i < p->nchunks; ++i) { |
1093 | struct amdgpu_cs_chunk *chunk; | |
effd924d | 1094 | |
6f0308eb | 1095 | chunk = &p->chunks[i]; |
91e1a520 | 1096 | |
6f0308eb DA |
1097 | if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) { |
1098 | r = amdgpu_cs_process_fence_dep(p, chunk); | |
1099 | if (r) | |
1100 | return r; | |
660e8558 DA |
1101 | } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) { |
1102 | r = amdgpu_cs_process_syncobj_in_dep(p, chunk); | |
1103 | if (r) | |
1104 | return r; | |
1105 | } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) { | |
1106 | r = amdgpu_cs_process_syncobj_out_dep(p, chunk); | |
1107 | if (r) | |
1108 | return r; | |
2b48d323 CK |
1109 | } |
1110 | } | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
660e8558 DA |
1115 | static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) |
1116 | { | |
1117 | int i; | |
1118 | ||
00fc2c26 CW |
1119 | for (i = 0; i < p->num_post_dep_syncobjs; ++i) |
1120 | drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence); | |
660e8558 DA |
1121 | } |
1122 | ||
cd75dc68 CK |
1123 | static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, |
1124 | union drm_amdgpu_cs *cs) | |
1125 | { | |
b07c60c0 | 1126 | struct amdgpu_ring *ring = p->job->ring; |
92f25098 | 1127 | struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity; |
cd75dc68 | 1128 | struct amdgpu_job *job; |
3fe89771 | 1129 | unsigned i; |
e686941a | 1130 | int r; |
cd75dc68 | 1131 | |
3fe89771 CK |
1132 | amdgpu_mn_lock(p->mn); |
1133 | if (p->bo_list) { | |
1134 | for (i = p->bo_list->first_userptr; | |
1135 | i < p->bo_list->num_entries; ++i) { | |
1136 | struct amdgpu_bo *bo = p->bo_list->array[i].robj; | |
1137 | ||
1138 | if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { | |
1139 | amdgpu_mn_unlock(p->mn); | |
1140 | return -ERESTARTSYS; | |
1141 | } | |
1142 | } | |
1143 | } | |
1144 | ||
50838c8c CK |
1145 | job = p->job; |
1146 | p->job = NULL; | |
cd75dc68 | 1147 | |
595a9cd6 | 1148 | r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp); |
e686941a | 1149 | if (r) { |
d71518b5 | 1150 | amdgpu_job_free(job); |
3fe89771 | 1151 | amdgpu_mn_unlock(p->mn); |
e686941a | 1152 | return r; |
cd75dc68 CK |
1153 | } |
1154 | ||
e686941a | 1155 | job->owner = p->filp; |
3aecd24c | 1156 | job->fence_ctx = entity->fence_context; |
f54d1867 | 1157 | p->fence = dma_fence_get(&job->base.s_fence->finished); |
660e8558 DA |
1158 | |
1159 | amdgpu_cs_post_dependencies(p); | |
1160 | ||
595a9cd6 | 1161 | cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence); |
758ac17f | 1162 | job->uf_sequence = cs->out.handle; |
a5fb4ec2 | 1163 | amdgpu_job_free_resources(job); |
cd75dc68 CK |
1164 | |
1165 | trace_amdgpu_cs_ioctl(job); | |
1166 | amd_sched_entity_push_job(&job->base); | |
3fe89771 CK |
1167 | |
1168 | ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence); | |
1169 | amdgpu_mn_unlock(p->mn); | |
1170 | ||
cd75dc68 CK |
1171 | return 0; |
1172 | } | |
1173 | ||
049fc527 CZ |
1174 | int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
1175 | { | |
1176 | struct amdgpu_device *adev = dev->dev_private; | |
f1892138 | 1177 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
049fc527 | 1178 | union drm_amdgpu_cs *cs = data; |
7e52a81c | 1179 | struct amdgpu_cs_parser parser = {}; |
26a6980c CK |
1180 | bool reserved_buffers = false; |
1181 | int i, r; | |
049fc527 | 1182 | |
0c418f10 | 1183 | if (!adev->accel_working) |
049fc527 | 1184 | return -EBUSY; |
f1892138 CZ |
1185 | if (amdgpu_kms_vram_lost(adev, fpriv)) |
1186 | return -ENODEV; | |
2b48d323 | 1187 | |
7e52a81c CK |
1188 | parser.adev = adev; |
1189 | parser.filp = filp; | |
1190 | ||
1191 | r = amdgpu_cs_parser_init(&parser, data); | |
d38ceaf9 | 1192 | if (r) { |
049fc527 | 1193 | DRM_ERROR("Failed to initialize parser !\n"); |
a414cd70 | 1194 | goto out; |
26a6980c CK |
1195 | } |
1196 | ||
a414cd70 HR |
1197 | r = amdgpu_cs_parser_bos(&parser, data); |
1198 | if (r) { | |
1199 | if (r == -ENOMEM) | |
1200 | DRM_ERROR("Not enough memory for command submission!\n"); | |
1201 | else if (r != -ERESTARTSYS) | |
1202 | DRM_ERROR("Failed to process the buffer list %d!\n", r); | |
1203 | goto out; | |
26a6980c CK |
1204 | } |
1205 | ||
a414cd70 HR |
1206 | reserved_buffers = true; |
1207 | r = amdgpu_cs_ib_fill(adev, &parser); | |
26a6980c CK |
1208 | if (r) |
1209 | goto out; | |
1210 | ||
a414cd70 HR |
1211 | r = amdgpu_cs_dependencies(adev, &parser); |
1212 | if (r) { | |
1213 | DRM_ERROR("Failed in the dependencies handling %d!\n", r); | |
1214 | goto out; | |
1215 | } | |
1216 | ||
50838c8c | 1217 | for (i = 0; i < parser.job->num_ibs; i++) |
7e52a81c | 1218 | trace_amdgpu_cs(&parser, i); |
26a6980c | 1219 | |
7e52a81c | 1220 | r = amdgpu_cs_ib_vm_chunk(adev, &parser); |
4fe63117 CZ |
1221 | if (r) |
1222 | goto out; | |
1223 | ||
4acabfe3 | 1224 | r = amdgpu_cs_submit(&parser, cs); |
d38ceaf9 | 1225 | |
d38ceaf9 | 1226 | out: |
7e52a81c | 1227 | amdgpu_cs_parser_fini(&parser, r, reserved_buffers); |
d38ceaf9 AD |
1228 | return r; |
1229 | } | |
1230 | ||
1231 | /** | |
1232 | * amdgpu_cs_wait_ioctl - wait for a command submission to finish | |
1233 | * | |
1234 | * @dev: drm device | |
1235 | * @data: data from userspace | |
1236 | * @filp: file private | |
1237 | * | |
1238 | * Wait for the command submission identified by handle to finish. | |
1239 | */ | |
1240 | int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, | |
1241 | struct drm_file *filp) | |
1242 | { | |
1243 | union drm_amdgpu_wait_cs *wait = data; | |
1244 | struct amdgpu_device *adev = dev->dev_private; | |
f1892138 | 1245 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
d38ceaf9 | 1246 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout); |
03507c4f | 1247 | struct amdgpu_ring *ring = NULL; |
66b3cf2a | 1248 | struct amdgpu_ctx *ctx; |
f54d1867 | 1249 | struct dma_fence *fence; |
d38ceaf9 AD |
1250 | long r; |
1251 | ||
f1892138 CZ |
1252 | if (amdgpu_kms_vram_lost(adev, fpriv)) |
1253 | return -ENODEV; | |
21c16bf6 | 1254 | |
66b3cf2a JZ |
1255 | ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id); |
1256 | if (ctx == NULL) | |
1257 | return -EINVAL; | |
d38ceaf9 | 1258 | |
effd924d AR |
1259 | r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, |
1260 | wait->in.ip_type, wait->in.ip_instance, | |
1261 | wait->in.ring, &ring); | |
1262 | if (r) { | |
1263 | amdgpu_ctx_put(ctx); | |
1264 | return r; | |
1265 | } | |
1266 | ||
4b559c90 CZ |
1267 | fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle); |
1268 | if (IS_ERR(fence)) | |
1269 | r = PTR_ERR(fence); | |
1270 | else if (fence) { | |
f54d1867 CW |
1271 | r = dma_fence_wait_timeout(fence, true, timeout); |
1272 | dma_fence_put(fence); | |
4b559c90 CZ |
1273 | } else |
1274 | r = 1; | |
049fc527 | 1275 | |
66b3cf2a | 1276 | amdgpu_ctx_put(ctx); |
d38ceaf9 AD |
1277 | if (r < 0) |
1278 | return r; | |
1279 | ||
1280 | memset(wait, 0, sizeof(*wait)); | |
1281 | wait->out.status = (r == 0); | |
1282 | ||
1283 | return 0; | |
1284 | } | |
1285 | ||
eef18a82 JZ |
1286 | /** |
1287 | * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence | |
1288 | * | |
1289 | * @adev: amdgpu device | |
1290 | * @filp: file private | |
1291 | * @user: drm_amdgpu_fence copied from user space | |
1292 | */ | |
1293 | static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev, | |
1294 | struct drm_file *filp, | |
1295 | struct drm_amdgpu_fence *user) | |
1296 | { | |
1297 | struct amdgpu_ring *ring; | |
1298 | struct amdgpu_ctx *ctx; | |
1299 | struct dma_fence *fence; | |
1300 | int r; | |
1301 | ||
eef18a82 JZ |
1302 | ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id); |
1303 | if (ctx == NULL) | |
1304 | return ERR_PTR(-EINVAL); | |
1305 | ||
effd924d AR |
1306 | r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type, |
1307 | user->ip_instance, user->ring, &ring); | |
1308 | if (r) { | |
1309 | amdgpu_ctx_put(ctx); | |
1310 | return ERR_PTR(r); | |
1311 | } | |
1312 | ||
eef18a82 JZ |
1313 | fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no); |
1314 | amdgpu_ctx_put(ctx); | |
1315 | ||
1316 | return fence; | |
1317 | } | |
1318 | ||
1319 | /** | |
1320 | * amdgpu_cs_wait_all_fence - wait on all fences to signal | |
1321 | * | |
1322 | * @adev: amdgpu device | |
1323 | * @filp: file private | |
1324 | * @wait: wait parameters | |
1325 | * @fences: array of drm_amdgpu_fence | |
1326 | */ | |
1327 | static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev, | |
1328 | struct drm_file *filp, | |
1329 | union drm_amdgpu_wait_fences *wait, | |
1330 | struct drm_amdgpu_fence *fences) | |
1331 | { | |
1332 | uint32_t fence_count = wait->in.fence_count; | |
1333 | unsigned int i; | |
1334 | long r = 1; | |
1335 | ||
1336 | for (i = 0; i < fence_count; i++) { | |
1337 | struct dma_fence *fence; | |
1338 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns); | |
1339 | ||
1340 | fence = amdgpu_cs_get_fence(adev, filp, &fences[i]); | |
1341 | if (IS_ERR(fence)) | |
1342 | return PTR_ERR(fence); | |
1343 | else if (!fence) | |
1344 | continue; | |
1345 | ||
1346 | r = dma_fence_wait_timeout(fence, true, timeout); | |
32df87df | 1347 | dma_fence_put(fence); |
eef18a82 JZ |
1348 | if (r < 0) |
1349 | return r; | |
1350 | ||
1351 | if (r == 0) | |
1352 | break; | |
1353 | } | |
1354 | ||
1355 | memset(wait, 0, sizeof(*wait)); | |
1356 | wait->out.status = (r > 0); | |
1357 | ||
1358 | return 0; | |
1359 | } | |
1360 | ||
1361 | /** | |
1362 | * amdgpu_cs_wait_any_fence - wait on any fence to signal | |
1363 | * | |
1364 | * @adev: amdgpu device | |
1365 | * @filp: file private | |
1366 | * @wait: wait parameters | |
1367 | * @fences: array of drm_amdgpu_fence | |
1368 | */ | |
1369 | static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev, | |
1370 | struct drm_file *filp, | |
1371 | union drm_amdgpu_wait_fences *wait, | |
1372 | struct drm_amdgpu_fence *fences) | |
1373 | { | |
1374 | unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns); | |
1375 | uint32_t fence_count = wait->in.fence_count; | |
1376 | uint32_t first = ~0; | |
1377 | struct dma_fence **array; | |
1378 | unsigned int i; | |
1379 | long r; | |
1380 | ||
1381 | /* Prepare the fence array */ | |
1382 | array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL); | |
1383 | ||
1384 | if (array == NULL) | |
1385 | return -ENOMEM; | |
1386 | ||
1387 | for (i = 0; i < fence_count; i++) { | |
1388 | struct dma_fence *fence; | |
1389 | ||
1390 | fence = amdgpu_cs_get_fence(adev, filp, &fences[i]); | |
1391 | if (IS_ERR(fence)) { | |
1392 | r = PTR_ERR(fence); | |
1393 | goto err_free_fence_array; | |
1394 | } else if (fence) { | |
1395 | array[i] = fence; | |
1396 | } else { /* NULL, the fence has been already signaled */ | |
1397 | r = 1; | |
a2138eaf | 1398 | first = i; |
eef18a82 JZ |
1399 | goto out; |
1400 | } | |
1401 | } | |
1402 | ||
1403 | r = dma_fence_wait_any_timeout(array, fence_count, true, timeout, | |
1404 | &first); | |
1405 | if (r < 0) | |
1406 | goto err_free_fence_array; | |
1407 | ||
1408 | out: | |
1409 | memset(wait, 0, sizeof(*wait)); | |
1410 | wait->out.status = (r > 0); | |
1411 | wait->out.first_signaled = first; | |
1412 | /* set return value 0 to indicate success */ | |
1413 | r = 0; | |
1414 | ||
1415 | err_free_fence_array: | |
1416 | for (i = 0; i < fence_count; i++) | |
1417 | dma_fence_put(array[i]); | |
1418 | kfree(array); | |
1419 | ||
1420 | return r; | |
1421 | } | |
1422 | ||
1423 | /** | |
1424 | * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish | |
1425 | * | |
1426 | * @dev: drm device | |
1427 | * @data: data from userspace | |
1428 | * @filp: file private | |
1429 | */ | |
1430 | int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, | |
1431 | struct drm_file *filp) | |
1432 | { | |
1433 | struct amdgpu_device *adev = dev->dev_private; | |
f1892138 | 1434 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
eef18a82 JZ |
1435 | union drm_amdgpu_wait_fences *wait = data; |
1436 | uint32_t fence_count = wait->in.fence_count; | |
1437 | struct drm_amdgpu_fence *fences_user; | |
1438 | struct drm_amdgpu_fence *fences; | |
1439 | int r; | |
1440 | ||
f1892138 CZ |
1441 | if (amdgpu_kms_vram_lost(adev, fpriv)) |
1442 | return -ENODEV; | |
eef18a82 JZ |
1443 | /* Get the fences from userspace */ |
1444 | fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence), | |
1445 | GFP_KERNEL); | |
1446 | if (fences == NULL) | |
1447 | return -ENOMEM; | |
1448 | ||
7ecc245a | 1449 | fences_user = u64_to_user_ptr(wait->in.fences); |
eef18a82 JZ |
1450 | if (copy_from_user(fences, fences_user, |
1451 | sizeof(struct drm_amdgpu_fence) * fence_count)) { | |
1452 | r = -EFAULT; | |
1453 | goto err_free_fences; | |
1454 | } | |
1455 | ||
1456 | if (wait->in.wait_all) | |
1457 | r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences); | |
1458 | else | |
1459 | r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences); | |
1460 | ||
1461 | err_free_fences: | |
1462 | kfree(fences); | |
1463 | ||
1464 | return r; | |
1465 | } | |
1466 | ||
d38ceaf9 AD |
1467 | /** |
1468 | * amdgpu_cs_find_bo_va - find bo_va for VM address | |
1469 | * | |
1470 | * @parser: command submission parser context | |
1471 | * @addr: VM address | |
1472 | * @bo: resulting BO of the mapping found | |
1473 | * | |
1474 | * Search the buffer objects in the command submission context for a certain | |
1475 | * virtual memory address. Returns allocation structure when found, NULL | |
1476 | * otherwise. | |
1477 | */ | |
1478 | struct amdgpu_bo_va_mapping * | |
1479 | amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, | |
1480 | uint64_t addr, struct amdgpu_bo **bo) | |
1481 | { | |
d38ceaf9 | 1482 | struct amdgpu_bo_va_mapping *mapping; |
15486fd2 CK |
1483 | unsigned i; |
1484 | ||
1485 | if (!parser->bo_list) | |
1486 | return NULL; | |
d38ceaf9 AD |
1487 | |
1488 | addr /= AMDGPU_GPU_PAGE_SIZE; | |
1489 | ||
15486fd2 CK |
1490 | for (i = 0; i < parser->bo_list->num_entries; i++) { |
1491 | struct amdgpu_bo_list_entry *lobj; | |
1492 | ||
1493 | lobj = &parser->bo_list->array[i]; | |
1494 | if (!lobj->bo_va) | |
d38ceaf9 AD |
1495 | continue; |
1496 | ||
15486fd2 | 1497 | list_for_each_entry(mapping, &lobj->bo_va->valids, list) { |
a9f87f64 CK |
1498 | if (mapping->start > addr || |
1499 | addr > mapping->last) | |
7fc11959 CK |
1500 | continue; |
1501 | ||
ec681545 | 1502 | *bo = lobj->bo_va->base.bo; |
7fc11959 CK |
1503 | return mapping; |
1504 | } | |
1505 | ||
15486fd2 | 1506 | list_for_each_entry(mapping, &lobj->bo_va->invalids, list) { |
a9f87f64 CK |
1507 | if (mapping->start > addr || |
1508 | addr > mapping->last) | |
d38ceaf9 AD |
1509 | continue; |
1510 | ||
ec681545 | 1511 | *bo = lobj->bo_va->base.bo; |
d38ceaf9 AD |
1512 | return mapping; |
1513 | } | |
1514 | } | |
1515 | ||
1516 | return NULL; | |
1517 | } | |
c855e250 CK |
1518 | |
1519 | /** | |
1520 | * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM | |
1521 | * | |
1522 | * @parser: command submission parser context | |
1523 | * | |
1524 | * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM. | |
1525 | */ | |
1526 | int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser) | |
1527 | { | |
1528 | unsigned i; | |
1529 | int r; | |
1530 | ||
1531 | if (!parser->bo_list) | |
1532 | return 0; | |
1533 | ||
1534 | for (i = 0; i < parser->bo_list->num_entries; i++) { | |
1535 | struct amdgpu_bo *bo = parser->bo_list->array[i].robj; | |
1536 | ||
bb990bb0 | 1537 | r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); |
c855e250 CK |
1538 | if (unlikely(r)) |
1539 | return r; | |
03f48dd5 CK |
1540 | |
1541 | if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) | |
1542 | continue; | |
1543 | ||
1544 | bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; | |
1545 | amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains); | |
1546 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); | |
1547 | if (unlikely(r)) | |
1548 | return r; | |
c855e250 CK |
1549 | } |
1550 | ||
1551 | return 0; | |
1552 | } |