]>
Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
0875dc9e | 28 | #include <linux/kthread.h> |
d38ceaf9 AD |
29 | #include <linux/console.h> |
30 | #include <linux/slab.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <drm/drmP.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/amdgpu_drm.h> | |
35 | #include <linux/vgaarb.h> | |
36 | #include <linux/vga_switcheroo.h> | |
37 | #include <linux/efi.h> | |
38 | #include "amdgpu.h" | |
f4b373f4 | 39 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
40 | #include "amdgpu_i2c.h" |
41 | #include "atom.h" | |
42 | #include "amdgpu_atombios.h" | |
d0dd7f0c | 43 | #include "amd_pcie.h" |
33f34802 KW |
44 | #ifdef CONFIG_DRM_AMDGPU_SI |
45 | #include "si.h" | |
46 | #endif | |
a2e73f56 AD |
47 | #ifdef CONFIG_DRM_AMDGPU_CIK |
48 | #include "cik.h" | |
49 | #endif | |
aaa36a97 | 50 | #include "vi.h" |
d38ceaf9 | 51 | #include "bif/bif_4_1_d.h" |
9accf2fd | 52 | #include <linux/pci.h> |
bec86378 | 53 | #include <linux/firmware.h> |
d38ceaf9 AD |
54 | |
55 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); | |
56 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
57 | ||
58 | static const char *amdgpu_asic_name[] = { | |
da69c161 KW |
59 | "TAHITI", |
60 | "PITCAIRN", | |
61 | "VERDE", | |
62 | "OLAND", | |
63 | "HAINAN", | |
d38ceaf9 AD |
64 | "BONAIRE", |
65 | "KAVERI", | |
66 | "KABINI", | |
67 | "HAWAII", | |
68 | "MULLINS", | |
69 | "TOPAZ", | |
70 | "TONGA", | |
48299f95 | 71 | "FIJI", |
d38ceaf9 | 72 | "CARRIZO", |
139f4917 | 73 | "STONEY", |
2cc0c0b5 FC |
74 | "POLARIS10", |
75 | "POLARIS11", | |
d38ceaf9 AD |
76 | "LAST", |
77 | }; | |
78 | ||
79 | bool amdgpu_device_is_px(struct drm_device *dev) | |
80 | { | |
81 | struct amdgpu_device *adev = dev->dev_private; | |
82 | ||
2f7d10b3 | 83 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
84 | return true; |
85 | return false; | |
86 | } | |
87 | ||
88 | /* | |
89 | * MMIO register access helper functions. | |
90 | */ | |
91 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
92 | bool always_indirect) | |
93 | { | |
f4b373f4 TSD |
94 | uint32_t ret; |
95 | ||
d38ceaf9 | 96 | if ((reg * 4) < adev->rmmio_size && !always_indirect) |
f4b373f4 | 97 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
98 | else { |
99 | unsigned long flags; | |
d38ceaf9 AD |
100 | |
101 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
102 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
103 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
104 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 105 | } |
f4b373f4 TSD |
106 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
107 | return ret; | |
d38ceaf9 AD |
108 | } |
109 | ||
110 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
111 | bool always_indirect) | |
112 | { | |
f4b373f4 | 113 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 114 | |
d38ceaf9 AD |
115 | if ((reg * 4) < adev->rmmio_size && !always_indirect) |
116 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
117 | else { | |
118 | unsigned long flags; | |
119 | ||
120 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
121 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
122 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
123 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
124 | } | |
125 | } | |
126 | ||
127 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
128 | { | |
129 | if ((reg * 4) < adev->rio_mem_size) | |
130 | return ioread32(adev->rio_mem + (reg * 4)); | |
131 | else { | |
132 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
133 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
134 | } | |
135 | } | |
136 | ||
137 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
138 | { | |
139 | ||
140 | if ((reg * 4) < adev->rio_mem_size) | |
141 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
142 | else { | |
143 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
144 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
145 | } | |
146 | } | |
147 | ||
148 | /** | |
149 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
150 | * | |
151 | * @adev: amdgpu_device pointer | |
152 | * @index: doorbell index | |
153 | * | |
154 | * Returns the value in the doorbell aperture at the | |
155 | * requested doorbell index (CIK). | |
156 | */ | |
157 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
158 | { | |
159 | if (index < adev->doorbell.num_doorbells) { | |
160 | return readl(adev->doorbell.ptr + index); | |
161 | } else { | |
162 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
163 | return 0; | |
164 | } | |
165 | } | |
166 | ||
167 | /** | |
168 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
169 | * | |
170 | * @adev: amdgpu_device pointer | |
171 | * @index: doorbell index | |
172 | * @v: value to write | |
173 | * | |
174 | * Writes @v to the doorbell aperture at the | |
175 | * requested doorbell index (CIK). | |
176 | */ | |
177 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
178 | { | |
179 | if (index < adev->doorbell.num_doorbells) { | |
180 | writel(v, adev->doorbell.ptr + index); | |
181 | } else { | |
182 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
183 | } | |
184 | } | |
185 | ||
186 | /** | |
187 | * amdgpu_invalid_rreg - dummy reg read function | |
188 | * | |
189 | * @adev: amdgpu device pointer | |
190 | * @reg: offset of register | |
191 | * | |
192 | * Dummy register read function. Used for register blocks | |
193 | * that certain asics don't have (all asics). | |
194 | * Returns the value in the register. | |
195 | */ | |
196 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
197 | { | |
198 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
199 | BUG(); | |
200 | return 0; | |
201 | } | |
202 | ||
203 | /** | |
204 | * amdgpu_invalid_wreg - dummy reg write function | |
205 | * | |
206 | * @adev: amdgpu device pointer | |
207 | * @reg: offset of register | |
208 | * @v: value to write to the register | |
209 | * | |
210 | * Dummy register read function. Used for register blocks | |
211 | * that certain asics don't have (all asics). | |
212 | */ | |
213 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
214 | { | |
215 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
216 | reg, v); | |
217 | BUG(); | |
218 | } | |
219 | ||
220 | /** | |
221 | * amdgpu_block_invalid_rreg - dummy reg read function | |
222 | * | |
223 | * @adev: amdgpu device pointer | |
224 | * @block: offset of instance | |
225 | * @reg: offset of register | |
226 | * | |
227 | * Dummy register read function. Used for register blocks | |
228 | * that certain asics don't have (all asics). | |
229 | * Returns the value in the register. | |
230 | */ | |
231 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
232 | uint32_t block, uint32_t reg) | |
233 | { | |
234 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
235 | reg, block); | |
236 | BUG(); | |
237 | return 0; | |
238 | } | |
239 | ||
240 | /** | |
241 | * amdgpu_block_invalid_wreg - dummy reg write function | |
242 | * | |
243 | * @adev: amdgpu device pointer | |
244 | * @block: offset of instance | |
245 | * @reg: offset of register | |
246 | * @v: value to write to the register | |
247 | * | |
248 | * Dummy register read function. Used for register blocks | |
249 | * that certain asics don't have (all asics). | |
250 | */ | |
251 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
252 | uint32_t block, | |
253 | uint32_t reg, uint32_t v) | |
254 | { | |
255 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
256 | reg, block, v); | |
257 | BUG(); | |
258 | } | |
259 | ||
260 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
261 | { | |
262 | int r; | |
263 | ||
264 | if (adev->vram_scratch.robj == NULL) { | |
265 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
857d913d | 266 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
267 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
268 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
72d7668b | 269 | NULL, NULL, &adev->vram_scratch.robj); |
d38ceaf9 AD |
270 | if (r) { |
271 | return r; | |
272 | } | |
273 | } | |
274 | ||
275 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
276 | if (unlikely(r != 0)) | |
277 | return r; | |
278 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
279 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
280 | if (r) { | |
281 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
282 | return r; | |
283 | } | |
284 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
285 | (void **)&adev->vram_scratch.ptr); | |
286 | if (r) | |
287 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
288 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
289 | ||
290 | return r; | |
291 | } | |
292 | ||
293 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
294 | { | |
295 | int r; | |
296 | ||
297 | if (adev->vram_scratch.robj == NULL) { | |
298 | return; | |
299 | } | |
300 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
301 | if (likely(r == 0)) { | |
302 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
303 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
304 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
305 | } | |
306 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
307 | } | |
308 | ||
309 | /** | |
310 | * amdgpu_program_register_sequence - program an array of registers. | |
311 | * | |
312 | * @adev: amdgpu_device pointer | |
313 | * @registers: pointer to the register array | |
314 | * @array_size: size of the register array | |
315 | * | |
316 | * Programs an array or registers with and and or masks. | |
317 | * This is a helper for setting golden registers. | |
318 | */ | |
319 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
320 | const u32 *registers, | |
321 | const u32 array_size) | |
322 | { | |
323 | u32 tmp, reg, and_mask, or_mask; | |
324 | int i; | |
325 | ||
326 | if (array_size % 3) | |
327 | return; | |
328 | ||
329 | for (i = 0; i < array_size; i +=3) { | |
330 | reg = registers[i + 0]; | |
331 | and_mask = registers[i + 1]; | |
332 | or_mask = registers[i + 2]; | |
333 | ||
334 | if (and_mask == 0xffffffff) { | |
335 | tmp = or_mask; | |
336 | } else { | |
337 | tmp = RREG32(reg); | |
338 | tmp &= ~and_mask; | |
339 | tmp |= or_mask; | |
340 | } | |
341 | WREG32(reg, tmp); | |
342 | } | |
343 | } | |
344 | ||
345 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
346 | { | |
347 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
348 | } | |
349 | ||
350 | /* | |
351 | * GPU doorbell aperture helpers function. | |
352 | */ | |
353 | /** | |
354 | * amdgpu_doorbell_init - Init doorbell driver information. | |
355 | * | |
356 | * @adev: amdgpu_device pointer | |
357 | * | |
358 | * Init doorbell driver information (CIK) | |
359 | * Returns 0 on success, error on failure. | |
360 | */ | |
361 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
362 | { | |
363 | /* doorbell bar mapping */ | |
364 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
365 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
366 | ||
edf600da | 367 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
d38ceaf9 AD |
368 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); |
369 | if (adev->doorbell.num_doorbells == 0) | |
370 | return -EINVAL; | |
371 | ||
372 | adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32)); | |
373 | if (adev->doorbell.ptr == NULL) { | |
374 | return -ENOMEM; | |
375 | } | |
376 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base); | |
377 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | /** | |
383 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
384 | * | |
385 | * @adev: amdgpu_device pointer | |
386 | * | |
387 | * Tear down doorbell driver information (CIK) | |
388 | */ | |
389 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
390 | { | |
391 | iounmap(adev->doorbell.ptr); | |
392 | adev->doorbell.ptr = NULL; | |
393 | } | |
394 | ||
395 | /** | |
396 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
397 | * setup amdkfd | |
398 | * | |
399 | * @adev: amdgpu_device pointer | |
400 | * @aperture_base: output returning doorbell aperture base physical address | |
401 | * @aperture_size: output returning doorbell aperture size in bytes | |
402 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
403 | * | |
404 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
405 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
406 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
407 | */ | |
408 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
409 | phys_addr_t *aperture_base, | |
410 | size_t *aperture_size, | |
411 | size_t *start_offset) | |
412 | { | |
413 | /* | |
414 | * The first num_doorbells are used by amdgpu. | |
415 | * amdkfd takes whatever's left in the aperture. | |
416 | */ | |
417 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
418 | *aperture_base = adev->doorbell.base; | |
419 | *aperture_size = adev->doorbell.size; | |
420 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
421 | } else { | |
422 | *aperture_base = 0; | |
423 | *aperture_size = 0; | |
424 | *start_offset = 0; | |
425 | } | |
426 | } | |
427 | ||
428 | /* | |
429 | * amdgpu_wb_*() | |
430 | * Writeback is the the method by which the the GPU updates special pages | |
431 | * in memory with the status of certain GPU events (fences, ring pointers, | |
432 | * etc.). | |
433 | */ | |
434 | ||
435 | /** | |
436 | * amdgpu_wb_fini - Disable Writeback and free memory | |
437 | * | |
438 | * @adev: amdgpu_device pointer | |
439 | * | |
440 | * Disables Writeback and frees the Writeback memory (all asics). | |
441 | * Used at driver shutdown. | |
442 | */ | |
443 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
444 | { | |
445 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
446 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
447 | &adev->wb.gpu_addr, | |
448 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
449 | adev->wb.wb_obj = NULL; |
450 | } | |
451 | } | |
452 | ||
453 | /** | |
454 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
455 | * | |
456 | * @adev: amdgpu_device pointer | |
457 | * | |
458 | * Disables Writeback and frees the Writeback memory (all asics). | |
459 | * Used at driver startup. | |
460 | * Returns 0 on success or an -error on failure. | |
461 | */ | |
462 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
463 | { | |
464 | int r; | |
465 | ||
466 | if (adev->wb.wb_obj == NULL) { | |
a76ed485 AD |
467 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * 4, |
468 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, | |
469 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
470 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
471 | if (r) { |
472 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
473 | return r; | |
474 | } | |
d38ceaf9 AD |
475 | |
476 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
477 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
478 | ||
479 | /* clear wb memory */ | |
480 | memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE); | |
481 | } | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | /** | |
487 | * amdgpu_wb_get - Allocate a wb entry | |
488 | * | |
489 | * @adev: amdgpu_device pointer | |
490 | * @wb: wb index | |
491 | * | |
492 | * Allocate a wb slot for use by the driver (all asics). | |
493 | * Returns 0 on success or -EINVAL on failure. | |
494 | */ | |
495 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
496 | { | |
497 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
498 | if (offset < adev->wb.num_wb) { | |
499 | __set_bit(offset, adev->wb.used); | |
500 | *wb = offset; | |
501 | return 0; | |
502 | } else { | |
503 | return -EINVAL; | |
504 | } | |
505 | } | |
506 | ||
507 | /** | |
508 | * amdgpu_wb_free - Free a wb entry | |
509 | * | |
510 | * @adev: amdgpu_device pointer | |
511 | * @wb: wb index | |
512 | * | |
513 | * Free a wb slot allocated for use by the driver (all asics) | |
514 | */ | |
515 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
516 | { | |
517 | if (wb < adev->wb.num_wb) | |
518 | __clear_bit(wb, adev->wb.used); | |
519 | } | |
520 | ||
521 | /** | |
522 | * amdgpu_vram_location - try to find VRAM location | |
523 | * @adev: amdgpu device structure holding all necessary informations | |
524 | * @mc: memory controller structure holding memory informations | |
525 | * @base: base address at which to put VRAM | |
526 | * | |
527 | * Function will place try to place VRAM at base address provided | |
528 | * as parameter (which is so far either PCI aperture address or | |
529 | * for IGP TOM base address). | |
530 | * | |
531 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
532 | * address space then we limit the VRAM size to the aperture. | |
533 | * | |
534 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
535 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
536 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
537 | * not IGP. | |
538 | * | |
539 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
540 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
541 | * Novell bug 204882 + along with lots of ubuntu ones | |
542 | * | |
543 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
544 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
545 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
546 | * ones) | |
547 | * | |
548 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
549 | * explicitly check for that thought. | |
550 | * | |
551 | * FIXME: when reducing VRAM size align new size on power of 2. | |
552 | */ | |
553 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
554 | { | |
555 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
556 | ||
557 | mc->vram_start = base; | |
558 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
559 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
560 | mc->real_vram_size = mc->aper_size; | |
561 | mc->mc_vram_size = mc->aper_size; | |
562 | } | |
563 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
564 | if (limit && limit < mc->real_vram_size) | |
565 | mc->real_vram_size = limit; | |
566 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
567 | mc->mc_vram_size >> 20, mc->vram_start, | |
568 | mc->vram_end, mc->real_vram_size >> 20); | |
569 | } | |
570 | ||
571 | /** | |
572 | * amdgpu_gtt_location - try to find GTT location | |
573 | * @adev: amdgpu device structure holding all necessary informations | |
574 | * @mc: memory controller structure holding memory informations | |
575 | * | |
576 | * Function will place try to place GTT before or after VRAM. | |
577 | * | |
578 | * If GTT size is bigger than space left then we ajust GTT size. | |
579 | * Thus function will never fails. | |
580 | * | |
581 | * FIXME: when reducing GTT size align new size on power of 2. | |
582 | */ | |
583 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
584 | { | |
585 | u64 size_af, size_bf; | |
586 | ||
587 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
588 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
589 | if (size_bf > size_af) { | |
590 | if (mc->gtt_size > size_bf) { | |
591 | dev_warn(adev->dev, "limiting GTT\n"); | |
592 | mc->gtt_size = size_bf; | |
593 | } | |
594 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; | |
595 | } else { | |
596 | if (mc->gtt_size > size_af) { | |
597 | dev_warn(adev->dev, "limiting GTT\n"); | |
598 | mc->gtt_size = size_af; | |
599 | } | |
600 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
601 | } | |
602 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
603 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
604 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
605 | } | |
606 | ||
607 | /* | |
608 | * GPU helpers function. | |
609 | */ | |
610 | /** | |
611 | * amdgpu_card_posted - check if the hw has already been initialized | |
612 | * | |
613 | * @adev: amdgpu_device pointer | |
614 | * | |
615 | * Check if the asic has been initialized (all asics). | |
616 | * Used at driver startup. | |
617 | * Returns true if initialized or false if not. | |
618 | */ | |
619 | bool amdgpu_card_posted(struct amdgpu_device *adev) | |
620 | { | |
621 | uint32_t reg; | |
622 | ||
623 | /* then check MEM_SIZE, in case the crtcs are off */ | |
624 | reg = RREG32(mmCONFIG_MEMSIZE); | |
625 | ||
626 | if (reg) | |
627 | return true; | |
628 | ||
629 | return false; | |
630 | ||
631 | } | |
632 | ||
bec86378 ML |
633 | static bool amdgpu_vpost_needed(struct amdgpu_device *adev) |
634 | { | |
635 | if (amdgpu_sriov_vf(adev)) | |
636 | return false; | |
637 | ||
638 | if (amdgpu_passthrough(adev)) { | |
639 | /* for FIJI: In whole GPU pass-through virtualization case | |
640 | * old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH) | |
641 | * so amdgpu_card_posted return false and driver will incorrectly skip vPost. | |
642 | * but if we force vPost do in pass-through case, the driver reload will hang. | |
643 | * whether doing vPost depends on amdgpu_card_posted if smc version is above | |
644 | * 00160e00 for FIJI. | |
645 | */ | |
646 | if (adev->asic_type == CHIP_FIJI) { | |
647 | int err; | |
648 | uint32_t fw_ver; | |
649 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
650 | /* force vPost if error occured */ | |
651 | if (err) | |
652 | return true; | |
653 | ||
654 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
655 | if (fw_ver >= 0x00160e00) | |
656 | return !amdgpu_card_posted(adev); | |
657 | } | |
658 | } else { | |
659 | /* in bare-metal case, amdgpu_card_posted return false | |
660 | * after system reboot/boot, and return true if driver | |
661 | * reloaded. | |
662 | * we shouldn't do vPost after driver reload otherwise GPU | |
663 | * could hang. | |
664 | */ | |
665 | if (amdgpu_card_posted(adev)) | |
666 | return false; | |
667 | } | |
668 | ||
669 | /* we assume vPost is neede for all other cases */ | |
670 | return true; | |
671 | } | |
672 | ||
d38ceaf9 AD |
673 | /** |
674 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
675 | * | |
676 | * @adev: amdgpu_device pointer | |
677 | * | |
678 | * Allocate the dummy page used by the driver (all asics). | |
679 | * This dummy page is used by the driver as a filler for gart entries | |
680 | * when pages are taken out of the GART | |
681 | * Returns 0 on sucess, -ENOMEM on failure. | |
682 | */ | |
683 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
684 | { | |
685 | if (adev->dummy_page.page) | |
686 | return 0; | |
687 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
688 | if (adev->dummy_page.page == NULL) | |
689 | return -ENOMEM; | |
690 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
691 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
692 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
693 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
694 | __free_page(adev->dummy_page.page); | |
695 | adev->dummy_page.page = NULL; | |
696 | return -ENOMEM; | |
697 | } | |
698 | return 0; | |
699 | } | |
700 | ||
701 | /** | |
702 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
703 | * | |
704 | * @adev: amdgpu_device pointer | |
705 | * | |
706 | * Frees the dummy page used by the driver (all asics). | |
707 | */ | |
708 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
709 | { | |
710 | if (adev->dummy_page.page == NULL) | |
711 | return; | |
712 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
713 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
714 | __free_page(adev->dummy_page.page); | |
715 | adev->dummy_page.page = NULL; | |
716 | } | |
717 | ||
718 | ||
719 | /* ATOM accessor methods */ | |
720 | /* | |
721 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
722 | * driver registers callbacks to access registers and the interpreter | |
723 | * in the driver parses the tables and executes then to program specific | |
724 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
725 | * atombios.h, and atom.c | |
726 | */ | |
727 | ||
728 | /** | |
729 | * cail_pll_read - read PLL register | |
730 | * | |
731 | * @info: atom card_info pointer | |
732 | * @reg: PLL register offset | |
733 | * | |
734 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
735 | * Returns the value of the PLL register. | |
736 | */ | |
737 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
738 | { | |
739 | return 0; | |
740 | } | |
741 | ||
742 | /** | |
743 | * cail_pll_write - write PLL register | |
744 | * | |
745 | * @info: atom card_info pointer | |
746 | * @reg: PLL register offset | |
747 | * @val: value to write to the pll register | |
748 | * | |
749 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
750 | */ | |
751 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
752 | { | |
753 | ||
754 | } | |
755 | ||
756 | /** | |
757 | * cail_mc_read - read MC (Memory Controller) register | |
758 | * | |
759 | * @info: atom card_info pointer | |
760 | * @reg: MC register offset | |
761 | * | |
762 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
763 | * Returns the value of the MC register. | |
764 | */ | |
765 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
766 | { | |
767 | return 0; | |
768 | } | |
769 | ||
770 | /** | |
771 | * cail_mc_write - write MC (Memory Controller) register | |
772 | * | |
773 | * @info: atom card_info pointer | |
774 | * @reg: MC register offset | |
775 | * @val: value to write to the pll register | |
776 | * | |
777 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
778 | */ | |
779 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
780 | { | |
781 | ||
782 | } | |
783 | ||
784 | /** | |
785 | * cail_reg_write - write MMIO register | |
786 | * | |
787 | * @info: atom card_info pointer | |
788 | * @reg: MMIO register offset | |
789 | * @val: value to write to the pll register | |
790 | * | |
791 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
792 | */ | |
793 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
794 | { | |
795 | struct amdgpu_device *adev = info->dev->dev_private; | |
796 | ||
797 | WREG32(reg, val); | |
798 | } | |
799 | ||
800 | /** | |
801 | * cail_reg_read - read MMIO register | |
802 | * | |
803 | * @info: atom card_info pointer | |
804 | * @reg: MMIO register offset | |
805 | * | |
806 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
807 | * Returns the value of the MMIO register. | |
808 | */ | |
809 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
810 | { | |
811 | struct amdgpu_device *adev = info->dev->dev_private; | |
812 | uint32_t r; | |
813 | ||
814 | r = RREG32(reg); | |
815 | return r; | |
816 | } | |
817 | ||
818 | /** | |
819 | * cail_ioreg_write - write IO register | |
820 | * | |
821 | * @info: atom card_info pointer | |
822 | * @reg: IO register offset | |
823 | * @val: value to write to the pll register | |
824 | * | |
825 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
826 | */ | |
827 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
828 | { | |
829 | struct amdgpu_device *adev = info->dev->dev_private; | |
830 | ||
831 | WREG32_IO(reg, val); | |
832 | } | |
833 | ||
834 | /** | |
835 | * cail_ioreg_read - read IO register | |
836 | * | |
837 | * @info: atom card_info pointer | |
838 | * @reg: IO register offset | |
839 | * | |
840 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
841 | * Returns the value of the IO register. | |
842 | */ | |
843 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
844 | { | |
845 | struct amdgpu_device *adev = info->dev->dev_private; | |
846 | uint32_t r; | |
847 | ||
848 | r = RREG32_IO(reg); | |
849 | return r; | |
850 | } | |
851 | ||
852 | /** | |
853 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
854 | * | |
855 | * @adev: amdgpu_device pointer | |
856 | * | |
857 | * Frees the driver info and register access callbacks for the ATOM | |
858 | * interpreter (r4xx+). | |
859 | * Called at driver shutdown. | |
860 | */ | |
861 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
862 | { | |
89e0ec9f | 863 | if (adev->mode_info.atom_context) { |
d38ceaf9 | 864 | kfree(adev->mode_info.atom_context->scratch); |
89e0ec9f ML |
865 | kfree(adev->mode_info.atom_context->iio); |
866 | } | |
d38ceaf9 AD |
867 | kfree(adev->mode_info.atom_context); |
868 | adev->mode_info.atom_context = NULL; | |
869 | kfree(adev->mode_info.atom_card_info); | |
870 | adev->mode_info.atom_card_info = NULL; | |
871 | } | |
872 | ||
873 | /** | |
874 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
875 | * | |
876 | * @adev: amdgpu_device pointer | |
877 | * | |
878 | * Initializes the driver info and register access callbacks for the | |
879 | * ATOM interpreter (r4xx+). | |
880 | * Returns 0 on sucess, -ENOMEM on failure. | |
881 | * Called at driver startup. | |
882 | */ | |
883 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
884 | { | |
885 | struct card_info *atom_card_info = | |
886 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
887 | ||
888 | if (!atom_card_info) | |
889 | return -ENOMEM; | |
890 | ||
891 | adev->mode_info.atom_card_info = atom_card_info; | |
892 | atom_card_info->dev = adev->ddev; | |
893 | atom_card_info->reg_read = cail_reg_read; | |
894 | atom_card_info->reg_write = cail_reg_write; | |
895 | /* needed for iio ops */ | |
896 | if (adev->rio_mem) { | |
897 | atom_card_info->ioreg_read = cail_ioreg_read; | |
898 | atom_card_info->ioreg_write = cail_ioreg_write; | |
899 | } else { | |
900 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); | |
901 | atom_card_info->ioreg_read = cail_reg_read; | |
902 | atom_card_info->ioreg_write = cail_reg_write; | |
903 | } | |
904 | atom_card_info->mc_read = cail_mc_read; | |
905 | atom_card_info->mc_write = cail_mc_write; | |
906 | atom_card_info->pll_read = cail_pll_read; | |
907 | atom_card_info->pll_write = cail_pll_write; | |
908 | ||
909 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
910 | if (!adev->mode_info.atom_context) { | |
911 | amdgpu_atombios_fini(adev); | |
912 | return -ENOMEM; | |
913 | } | |
914 | ||
915 | mutex_init(&adev->mode_info.atom_context->mutex); | |
916 | amdgpu_atombios_scratch_regs_init(adev); | |
917 | amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context); | |
918 | return 0; | |
919 | } | |
920 | ||
921 | /* if we get transitioned to only one device, take VGA back */ | |
922 | /** | |
923 | * amdgpu_vga_set_decode - enable/disable vga decode | |
924 | * | |
925 | * @cookie: amdgpu_device pointer | |
926 | * @state: enable/disable vga decode | |
927 | * | |
928 | * Enable/disable vga decode (all asics). | |
929 | * Returns VGA resource flags. | |
930 | */ | |
931 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
932 | { | |
933 | struct amdgpu_device *adev = cookie; | |
934 | amdgpu_asic_set_vga_state(adev, state); | |
935 | if (state) | |
936 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
937 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
938 | else | |
939 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
940 | } | |
941 | ||
942 | /** | |
943 | * amdgpu_check_pot_argument - check that argument is a power of two | |
944 | * | |
945 | * @arg: value to check | |
946 | * | |
947 | * Validates that a certain argument is a power of two (all asics). | |
948 | * Returns true if argument is valid. | |
949 | */ | |
950 | static bool amdgpu_check_pot_argument(int arg) | |
951 | { | |
952 | return (arg & (arg - 1)) == 0; | |
953 | } | |
954 | ||
955 | /** | |
956 | * amdgpu_check_arguments - validate module params | |
957 | * | |
958 | * @adev: amdgpu_device pointer | |
959 | * | |
960 | * Validates certain module parameters and updates | |
961 | * the associated values used by the driver (all asics). | |
962 | */ | |
963 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
964 | { | |
5b011235 CZ |
965 | if (amdgpu_sched_jobs < 4) { |
966 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
967 | amdgpu_sched_jobs); | |
968 | amdgpu_sched_jobs = 4; | |
969 | } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){ | |
970 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", | |
971 | amdgpu_sched_jobs); | |
972 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
973 | } | |
d38ceaf9 AD |
974 | |
975 | if (amdgpu_gart_size != -1) { | |
c4e1a13a | 976 | /* gtt size must be greater or equal to 32M */ |
d38ceaf9 AD |
977 | if (amdgpu_gart_size < 32) { |
978 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
979 | amdgpu_gart_size); | |
980 | amdgpu_gart_size = -1; | |
d38ceaf9 AD |
981 | } |
982 | } | |
983 | ||
984 | if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { | |
985 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", | |
986 | amdgpu_vm_size); | |
8dacc127 | 987 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
988 | } |
989 | ||
990 | if (amdgpu_vm_size < 1) { | |
991 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
992 | amdgpu_vm_size); | |
8dacc127 | 993 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
994 | } |
995 | ||
996 | /* | |
997 | * Max GPUVM size for Cayman, SI and CI are 40 bits. | |
998 | */ | |
999 | if (amdgpu_vm_size > 1024) { | |
1000 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
1001 | amdgpu_vm_size); | |
8dacc127 | 1002 | amdgpu_vm_size = 8; |
d38ceaf9 AD |
1003 | } |
1004 | ||
1005 | /* defines number of bits in page table versus page directory, | |
1006 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1007 | * page table and the remaining bits are in the page directory */ | |
1008 | if (amdgpu_vm_block_size == -1) { | |
1009 | ||
1010 | /* Total bits covered by PD + PTs */ | |
1011 | unsigned bits = ilog2(amdgpu_vm_size) + 18; | |
1012 | ||
1013 | /* Make sure the PD is 4K in size up to 8GB address space. | |
1014 | Above that split equal between PD and PTs */ | |
1015 | if (amdgpu_vm_size <= 8) | |
1016 | amdgpu_vm_block_size = bits - 9; | |
1017 | else | |
1018 | amdgpu_vm_block_size = (bits + 3) / 2; | |
1019 | ||
1020 | } else if (amdgpu_vm_block_size < 9) { | |
1021 | dev_warn(adev->dev, "VM page table size (%d) too small\n", | |
1022 | amdgpu_vm_block_size); | |
1023 | amdgpu_vm_block_size = 9; | |
1024 | } | |
1025 | ||
1026 | if (amdgpu_vm_block_size > 24 || | |
1027 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1028 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1029 | amdgpu_vm_block_size); | |
1030 | amdgpu_vm_block_size = 9; | |
1031 | } | |
6a7f76e7 CK |
1032 | |
1033 | if ((amdgpu_vram_page_split != -1 && amdgpu_vram_page_split < 16) || | |
1034 | !amdgpu_check_pot_argument(amdgpu_vram_page_split)) { | |
1035 | dev_warn(adev->dev, "invalid VRAM page split (%d)\n", | |
1036 | amdgpu_vram_page_split); | |
1037 | amdgpu_vram_page_split = 1024; | |
1038 | } | |
d38ceaf9 AD |
1039 | } |
1040 | ||
1041 | /** | |
1042 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1043 | * | |
1044 | * @pdev: pci dev pointer | |
1694467b | 1045 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1046 | * |
1047 | * Callback for the switcheroo driver. Suspends or resumes the | |
1048 | * the asics before or after it is powered up using ACPI methods. | |
1049 | */ | |
1050 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1051 | { | |
1052 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1053 | ||
1054 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1055 | return; | |
1056 | ||
1057 | if (state == VGA_SWITCHEROO_ON) { | |
1058 | unsigned d3_delay = dev->pdev->d3_delay; | |
1059 | ||
1060 | printk(KERN_INFO "amdgpu: switched on\n"); | |
1061 | /* don't suspend or resume card normally */ | |
1062 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1063 | ||
810ddc3a | 1064 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 AD |
1065 | |
1066 | dev->pdev->d3_delay = d3_delay; | |
1067 | ||
1068 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1069 | drm_kms_helper_poll_enable(dev); | |
1070 | } else { | |
1071 | printk(KERN_INFO "amdgpu: switched off\n"); | |
1072 | drm_kms_helper_poll_disable(dev); | |
1073 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1074 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1075 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1076 | } | |
1077 | } | |
1078 | ||
1079 | /** | |
1080 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1081 | * | |
1082 | * @pdev: pci dev pointer | |
1083 | * | |
1084 | * Callback for the switcheroo driver. Check of the switcheroo | |
1085 | * state can be changed. | |
1086 | * Returns true if the state can be changed, false if not. | |
1087 | */ | |
1088 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1089 | { | |
1090 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1091 | ||
1092 | /* | |
1093 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1094 | * locking inversion with the driver load path. And the access here is | |
1095 | * completely racy anyway. So don't bother with locking for now. | |
1096 | */ | |
1097 | return dev->open_count == 0; | |
1098 | } | |
1099 | ||
1100 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1101 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1102 | .reprobe = NULL, | |
1103 | .can_switch = amdgpu_switcheroo_can_switch, | |
1104 | }; | |
1105 | ||
1106 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1107 | enum amd_ip_block_type block_type, |
1108 | enum amd_clockgating_state state) | |
d38ceaf9 AD |
1109 | { |
1110 | int i, r = 0; | |
1111 | ||
1112 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1113 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1114 | continue; |
a1255107 AD |
1115 | if (adev->ip_blocks[i].version->type == block_type) { |
1116 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, | |
1117 | state); | |
d38ceaf9 AD |
1118 | if (r) |
1119 | return r; | |
a225bf1c | 1120 | break; |
d38ceaf9 AD |
1121 | } |
1122 | } | |
1123 | return r; | |
1124 | } | |
1125 | ||
1126 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
5fc3aeeb | 1127 | enum amd_ip_block_type block_type, |
1128 | enum amd_powergating_state state) | |
d38ceaf9 AD |
1129 | { |
1130 | int i, r = 0; | |
1131 | ||
1132 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1133 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1134 | continue; |
a1255107 AD |
1135 | if (adev->ip_blocks[i].version->type == block_type) { |
1136 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1137 | state); | |
d38ceaf9 AD |
1138 | if (r) |
1139 | return r; | |
a225bf1c | 1140 | break; |
d38ceaf9 AD |
1141 | } |
1142 | } | |
1143 | return r; | |
1144 | } | |
1145 | ||
5dbbb60b AD |
1146 | int amdgpu_wait_for_idle(struct amdgpu_device *adev, |
1147 | enum amd_ip_block_type block_type) | |
1148 | { | |
1149 | int i, r; | |
1150 | ||
1151 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1152 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1153 | continue; |
a1255107 AD |
1154 | if (adev->ip_blocks[i].version->type == block_type) { |
1155 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1156 | if (r) |
1157 | return r; | |
1158 | break; | |
1159 | } | |
1160 | } | |
1161 | return 0; | |
1162 | ||
1163 | } | |
1164 | ||
1165 | bool amdgpu_is_idle(struct amdgpu_device *adev, | |
1166 | enum amd_ip_block_type block_type) | |
1167 | { | |
1168 | int i; | |
1169 | ||
1170 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1171 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1172 | continue; |
a1255107 AD |
1173 | if (adev->ip_blocks[i].version->type == block_type) |
1174 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1175 | } |
1176 | return true; | |
1177 | ||
1178 | } | |
1179 | ||
a1255107 AD |
1180 | struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, |
1181 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1182 | { |
1183 | int i; | |
1184 | ||
1185 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1186 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1187 | return &adev->ip_blocks[i]; |
1188 | ||
1189 | return NULL; | |
1190 | } | |
1191 | ||
1192 | /** | |
1193 | * amdgpu_ip_block_version_cmp | |
1194 | * | |
1195 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1196 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1197 | * @major: major version |
1198 | * @minor: minor version | |
1199 | * | |
1200 | * return 0 if equal or greater | |
1201 | * return 1 if smaller or the ip_block doesn't exist | |
1202 | */ | |
1203 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
5fc3aeeb | 1204 | enum amd_ip_block_type type, |
d38ceaf9 AD |
1205 | u32 major, u32 minor) |
1206 | { | |
a1255107 | 1207 | struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); |
d38ceaf9 | 1208 | |
a1255107 AD |
1209 | if (ip_block && ((ip_block->version->major > major) || |
1210 | ((ip_block->version->major == major) && | |
1211 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1212 | return 0; |
1213 | ||
1214 | return 1; | |
1215 | } | |
1216 | ||
a1255107 AD |
1217 | /** |
1218 | * amdgpu_ip_block_add | |
1219 | * | |
1220 | * @adev: amdgpu_device pointer | |
1221 | * @ip_block_version: pointer to the IP to add | |
1222 | * | |
1223 | * Adds the IP block driver information to the collection of IPs | |
1224 | * on the asic. | |
1225 | */ | |
1226 | int amdgpu_ip_block_add(struct amdgpu_device *adev, | |
1227 | const struct amdgpu_ip_block_version *ip_block_version) | |
1228 | { | |
1229 | if (!ip_block_version) | |
1230 | return -EINVAL; | |
1231 | ||
1232 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
483ef985 | 1237 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1238 | { |
1239 | adev->enable_virtual_display = false; | |
1240 | ||
1241 | if (amdgpu_virtual_display) { | |
1242 | struct drm_device *ddev = adev->ddev; | |
1243 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1244 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1245 | |
1246 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1247 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1248 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1249 | pciaddname = strsep(&pciaddname_tmp, ","); | |
9accf2fd | 1250 | if (!strcmp(pci_address_name, pciaddname)) { |
0f66356d ED |
1251 | long num_crtc; |
1252 | int res = -1; | |
1253 | ||
9accf2fd | 1254 | adev->enable_virtual_display = true; |
0f66356d ED |
1255 | |
1256 | if (pciaddname_tmp) | |
1257 | res = kstrtol(pciaddname_tmp, 10, | |
1258 | &num_crtc); | |
1259 | ||
1260 | if (!res) { | |
1261 | if (num_crtc < 1) | |
1262 | num_crtc = 1; | |
1263 | if (num_crtc > 6) | |
1264 | num_crtc = 6; | |
1265 | adev->mode_info.num_crtc = num_crtc; | |
1266 | } else { | |
1267 | adev->mode_info.num_crtc = 1; | |
1268 | } | |
9accf2fd ED |
1269 | break; |
1270 | } | |
1271 | } | |
1272 | ||
0f66356d ED |
1273 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1274 | amdgpu_virtual_display, pci_address_name, | |
1275 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1276 | |
1277 | kfree(pciaddstr); | |
1278 | } | |
1279 | } | |
1280 | ||
d38ceaf9 AD |
1281 | static int amdgpu_early_init(struct amdgpu_device *adev) |
1282 | { | |
aaa36a97 | 1283 | int i, r; |
d38ceaf9 | 1284 | |
483ef985 | 1285 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1286 | |
d38ceaf9 | 1287 | switch (adev->asic_type) { |
aaa36a97 AD |
1288 | case CHIP_TOPAZ: |
1289 | case CHIP_TONGA: | |
48299f95 | 1290 | case CHIP_FIJI: |
2cc0c0b5 FC |
1291 | case CHIP_POLARIS11: |
1292 | case CHIP_POLARIS10: | |
aaa36a97 | 1293 | case CHIP_CARRIZO: |
39bb0c92 SL |
1294 | case CHIP_STONEY: |
1295 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1296 | adev->family = AMDGPU_FAMILY_CZ; |
1297 | else | |
1298 | adev->family = AMDGPU_FAMILY_VI; | |
1299 | ||
1300 | r = vi_set_ip_blocks(adev); | |
1301 | if (r) | |
1302 | return r; | |
1303 | break; | |
33f34802 KW |
1304 | #ifdef CONFIG_DRM_AMDGPU_SI |
1305 | case CHIP_VERDE: | |
1306 | case CHIP_TAHITI: | |
1307 | case CHIP_PITCAIRN: | |
1308 | case CHIP_OLAND: | |
1309 | case CHIP_HAINAN: | |
295d0daf | 1310 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1311 | r = si_set_ip_blocks(adev); |
1312 | if (r) | |
1313 | return r; | |
1314 | break; | |
1315 | #endif | |
a2e73f56 AD |
1316 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1317 | case CHIP_BONAIRE: | |
1318 | case CHIP_HAWAII: | |
1319 | case CHIP_KAVERI: | |
1320 | case CHIP_KABINI: | |
1321 | case CHIP_MULLINS: | |
1322 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1323 | adev->family = AMDGPU_FAMILY_CI; | |
1324 | else | |
1325 | adev->family = AMDGPU_FAMILY_KV; | |
1326 | ||
1327 | r = cik_set_ip_blocks(adev); | |
1328 | if (r) | |
1329 | return r; | |
1330 | break; | |
1331 | #endif | |
d38ceaf9 AD |
1332 | default: |
1333 | /* FIXME: not supported yet */ | |
1334 | return -EINVAL; | |
1335 | } | |
1336 | ||
d38ceaf9 AD |
1337 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1338 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
1339 | DRM_ERROR("disabled ip block: %d\n", i); | |
a1255107 | 1340 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1341 | } else { |
a1255107 AD |
1342 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1343 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1344 | if (r == -ENOENT) { |
a1255107 | 1345 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1346 | } else if (r) { |
a1255107 AD |
1347 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1348 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1349 | return r; |
2c1a2784 | 1350 | } else { |
a1255107 | 1351 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1352 | } |
974e6b64 | 1353 | } else { |
a1255107 | 1354 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1355 | } |
d38ceaf9 AD |
1356 | } |
1357 | } | |
1358 | ||
395d1fb9 NH |
1359 | adev->cg_flags &= amdgpu_cg_mask; |
1360 | adev->pg_flags &= amdgpu_pg_mask; | |
1361 | ||
d38ceaf9 AD |
1362 | return 0; |
1363 | } | |
1364 | ||
1365 | static int amdgpu_init(struct amdgpu_device *adev) | |
1366 | { | |
1367 | int i, r; | |
1368 | ||
1369 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1370 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1371 | continue; |
a1255107 | 1372 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1373 | if (r) { |
a1255107 AD |
1374 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1375 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1376 | return r; |
2c1a2784 | 1377 | } |
a1255107 | 1378 | adev->ip_blocks[i].status.sw = true; |
d38ceaf9 | 1379 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1380 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 | 1381 | r = amdgpu_vram_scratch_init(adev); |
2c1a2784 AD |
1382 | if (r) { |
1383 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
d38ceaf9 | 1384 | return r; |
2c1a2784 | 1385 | } |
a1255107 | 1386 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1387 | if (r) { |
1388 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
d38ceaf9 | 1389 | return r; |
2c1a2784 | 1390 | } |
d38ceaf9 | 1391 | r = amdgpu_wb_init(adev); |
2c1a2784 AD |
1392 | if (r) { |
1393 | DRM_ERROR("amdgpu_wb_init failed %d\n", r); | |
d38ceaf9 | 1394 | return r; |
2c1a2784 | 1395 | } |
a1255107 | 1396 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1397 | } |
1398 | } | |
1399 | ||
1400 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1401 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 AD |
1402 | continue; |
1403 | /* gmc hw init is done early */ | |
a1255107 | 1404 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) |
d38ceaf9 | 1405 | continue; |
a1255107 | 1406 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 | 1407 | if (r) { |
a1255107 AD |
1408 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", |
1409 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1410 | return r; |
2c1a2784 | 1411 | } |
a1255107 | 1412 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
1413 | } |
1414 | ||
1415 | return 0; | |
1416 | } | |
1417 | ||
1418 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1419 | { | |
1420 | int i = 0, r; | |
1421 | ||
1422 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1423 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1424 | continue; |
a1255107 AD |
1425 | if (adev->ip_blocks[i].version->funcs->late_init) { |
1426 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2c1a2784 | 1427 | if (r) { |
a1255107 AD |
1428 | DRM_ERROR("late_init of IP block <%s> failed %d\n", |
1429 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1430 | return r; |
2c1a2784 | 1431 | } |
a1255107 | 1432 | adev->ip_blocks[i].status.late_initialized = true; |
d38ceaf9 | 1433 | } |
4a446d55 | 1434 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 AD |
1435 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
1436 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) { | |
4a446d55 | 1437 | /* enable clockgating to save power */ |
a1255107 AD |
1438 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1439 | AMD_CG_STATE_GATE); | |
4a446d55 AD |
1440 | if (r) { |
1441 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1442 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1443 | return r; |
1444 | } | |
b0b00ff1 | 1445 | } |
d38ceaf9 AD |
1446 | } |
1447 | ||
1448 | return 0; | |
1449 | } | |
1450 | ||
1451 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1452 | { | |
1453 | int i, r; | |
1454 | ||
3e96dbfd AD |
1455 | /* need to disable SMC first */ |
1456 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1457 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1458 | continue; |
a1255107 | 1459 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
3e96dbfd | 1460 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ |
a1255107 AD |
1461 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1462 | AMD_CG_STATE_UNGATE); | |
3e96dbfd AD |
1463 | if (r) { |
1464 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", | |
a1255107 | 1465 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd AD |
1466 | return r; |
1467 | } | |
a1255107 | 1468 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1469 | /* XXX handle errors */ |
1470 | if (r) { | |
1471 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1472 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1473 | } |
a1255107 | 1474 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1475 | break; |
1476 | } | |
1477 | } | |
1478 | ||
d38ceaf9 | 1479 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1480 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1481 | continue; |
a1255107 | 1482 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
d38ceaf9 AD |
1483 | amdgpu_wb_fini(adev); |
1484 | amdgpu_vram_scratch_fini(adev); | |
1485 | } | |
1486 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
a1255107 AD |
1487 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1488 | AMD_CG_STATE_UNGATE); | |
2c1a2784 | 1489 | if (r) { |
a1255107 AD |
1490 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1491 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1492 | return r; |
2c1a2784 | 1493 | } |
a1255107 | 1494 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1495 | /* XXX handle errors */ |
2c1a2784 | 1496 | if (r) { |
a1255107 AD |
1497 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1498 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1499 | } |
a1255107 | 1500 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1501 | } |
1502 | ||
1503 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 1504 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 1505 | continue; |
a1255107 | 1506 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 1507 | /* XXX handle errors */ |
2c1a2784 | 1508 | if (r) { |
a1255107 AD |
1509 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
1510 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1511 | } |
a1255107 AD |
1512 | adev->ip_blocks[i].status.sw = false; |
1513 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
1514 | } |
1515 | ||
a6dcfd9c | 1516 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1517 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 1518 | continue; |
a1255107 AD |
1519 | if (adev->ip_blocks[i].version->funcs->late_fini) |
1520 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
1521 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
1522 | } |
1523 | ||
d38ceaf9 AD |
1524 | return 0; |
1525 | } | |
1526 | ||
1527 | static int amdgpu_suspend(struct amdgpu_device *adev) | |
1528 | { | |
1529 | int i, r; | |
1530 | ||
c5a93a28 FC |
1531 | /* ungate SMC block first */ |
1532 | r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, | |
1533 | AMD_CG_STATE_UNGATE); | |
1534 | if (r) { | |
1535 | DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); | |
1536 | } | |
1537 | ||
d38ceaf9 | 1538 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1539 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 AD |
1540 | continue; |
1541 | /* ungate blocks so that suspend can properly shut them down */ | |
c5a93a28 | 1542 | if (i != AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 AD |
1543 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1544 | AMD_CG_STATE_UNGATE); | |
c5a93a28 | 1545 | if (r) { |
a1255107 AD |
1546 | DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", |
1547 | adev->ip_blocks[i].version->funcs->name, r); | |
c5a93a28 | 1548 | } |
2c1a2784 | 1549 | } |
d38ceaf9 | 1550 | /* XXX handle errors */ |
a1255107 | 1551 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 1552 | /* XXX handle errors */ |
2c1a2784 | 1553 | if (r) { |
a1255107 AD |
1554 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
1555 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1556 | } |
d38ceaf9 AD |
1557 | } |
1558 | ||
1559 | return 0; | |
1560 | } | |
1561 | ||
1562 | static int amdgpu_resume(struct amdgpu_device *adev) | |
1563 | { | |
1564 | int i, r; | |
1565 | ||
1566 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1567 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1568 | continue; |
a1255107 | 1569 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 1570 | if (r) { |
a1255107 AD |
1571 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
1572 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1573 | return r; |
2c1a2784 | 1574 | } |
d38ceaf9 AD |
1575 | } |
1576 | ||
1577 | return 0; | |
1578 | } | |
1579 | ||
4e99a44e | 1580 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 1581 | { |
4e99a44e ML |
1582 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) |
1583 | adev->virtualization.virtual_caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
048765ad AR |
1584 | } |
1585 | ||
d38ceaf9 AD |
1586 | /** |
1587 | * amdgpu_device_init - initialize the driver | |
1588 | * | |
1589 | * @adev: amdgpu_device pointer | |
1590 | * @pdev: drm dev pointer | |
1591 | * @pdev: pci dev pointer | |
1592 | * @flags: driver flags | |
1593 | * | |
1594 | * Initializes the driver info and hw (all asics). | |
1595 | * Returns 0 for success or an error on failure. | |
1596 | * Called at driver startup. | |
1597 | */ | |
1598 | int amdgpu_device_init(struct amdgpu_device *adev, | |
1599 | struct drm_device *ddev, | |
1600 | struct pci_dev *pdev, | |
1601 | uint32_t flags) | |
1602 | { | |
1603 | int r, i; | |
1604 | bool runtime = false; | |
95844d20 | 1605 | u32 max_MBps; |
d38ceaf9 AD |
1606 | |
1607 | adev->shutdown = false; | |
1608 | adev->dev = &pdev->dev; | |
1609 | adev->ddev = ddev; | |
1610 | adev->pdev = pdev; | |
1611 | adev->flags = flags; | |
2f7d10b3 | 1612 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 AD |
1613 | adev->is_atom_bios = false; |
1614 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; | |
1615 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
1616 | adev->accel_working = false; | |
1617 | adev->num_rings = 0; | |
1618 | adev->mman.buffer_funcs = NULL; | |
1619 | adev->mman.buffer_funcs_ring = NULL; | |
1620 | adev->vm_manager.vm_pte_funcs = NULL; | |
2d55e45a | 1621 | adev->vm_manager.vm_pte_num_rings = 0; |
d38ceaf9 | 1622 | adev->gart.gart_funcs = NULL; |
f54d1867 | 1623 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
d38ceaf9 AD |
1624 | |
1625 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
1626 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
1627 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
1628 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
1629 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
1630 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1631 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
1632 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
1633 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
1634 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
1635 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
1636 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
1637 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
1638 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
1639 | ||
ccdbb20a | 1640 | |
3e39ab90 AD |
1641 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
1642 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
1643 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
1644 | |
1645 | /* mutex initialization are all done here so we | |
1646 | * can recall function without having locking issues */ | |
8d0a7cea | 1647 | mutex_init(&adev->vm_manager.lock); |
d38ceaf9 | 1648 | atomic_set(&adev->irq.ih.lock, 0); |
d38ceaf9 AD |
1649 | mutex_init(&adev->pm.mutex); |
1650 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
1651 | mutex_init(&adev->srbm_mutex); | |
1652 | mutex_init(&adev->grbm_idx_mutex); | |
d38ceaf9 AD |
1653 | mutex_init(&adev->mn_lock); |
1654 | hash_init(adev->mn_hash); | |
1655 | ||
1656 | amdgpu_check_arguments(adev); | |
1657 | ||
1658 | /* Registers mapping */ | |
1659 | /* TODO: block userspace mapping of io register */ | |
1660 | spin_lock_init(&adev->mmio_idx_lock); | |
1661 | spin_lock_init(&adev->smc_idx_lock); | |
1662 | spin_lock_init(&adev->pcie_idx_lock); | |
1663 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
1664 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 1665 | spin_lock_init(&adev->gc_cac_idx_lock); |
d38ceaf9 | 1666 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 1667 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 1668 | |
0c4e7fa5 CZ |
1669 | INIT_LIST_HEAD(&adev->shadow_list); |
1670 | mutex_init(&adev->shadow_list_lock); | |
1671 | ||
5c1354bd CZ |
1672 | INIT_LIST_HEAD(&adev->gtt_list); |
1673 | spin_lock_init(&adev->gtt_list_lock); | |
1674 | ||
da69c161 KW |
1675 | if (adev->asic_type >= CHIP_BONAIRE) { |
1676 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
1677 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
1678 | } else { | |
1679 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
1680 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
1681 | } | |
d38ceaf9 | 1682 | |
d38ceaf9 AD |
1683 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
1684 | if (adev->rmmio == NULL) { | |
1685 | return -ENOMEM; | |
1686 | } | |
1687 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
1688 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
1689 | ||
da69c161 KW |
1690 | if (adev->asic_type >= CHIP_BONAIRE) |
1691 | /* doorbell bar mapping */ | |
1692 | amdgpu_doorbell_init(adev); | |
d38ceaf9 AD |
1693 | |
1694 | /* io port mapping */ | |
1695 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1696 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
1697 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
1698 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
1699 | break; | |
1700 | } | |
1701 | } | |
1702 | if (adev->rio_mem == NULL) | |
1703 | DRM_ERROR("Unable to find PCI I/O BAR\n"); | |
1704 | ||
1705 | /* early init functions */ | |
1706 | r = amdgpu_early_init(adev); | |
1707 | if (r) | |
1708 | return r; | |
1709 | ||
1710 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
1711 | /* this will fail for cards that aren't VGA class devices, just | |
1712 | * ignore it */ | |
1713 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
1714 | ||
1715 | if (amdgpu_runtime_pm == 1) | |
1716 | runtime = true; | |
e9bef455 | 1717 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 AD |
1718 | runtime = true; |
1719 | vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime); | |
1720 | if (runtime) | |
1721 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
1722 | ||
1723 | /* Read BIOS */ | |
83ba126a AD |
1724 | if (!amdgpu_get_bios(adev)) { |
1725 | r = -EINVAL; | |
1726 | goto failed; | |
1727 | } | |
d38ceaf9 AD |
1728 | /* Must be an ATOMBIOS */ |
1729 | if (!adev->is_atom_bios) { | |
1730 | dev_err(adev->dev, "Expecting atombios for GPU\n"); | |
83ba126a AD |
1731 | r = -EINVAL; |
1732 | goto failed; | |
d38ceaf9 AD |
1733 | } |
1734 | r = amdgpu_atombios_init(adev); | |
2c1a2784 AD |
1735 | if (r) { |
1736 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
83ba126a | 1737 | goto failed; |
2c1a2784 | 1738 | } |
d38ceaf9 | 1739 | |
4e99a44e ML |
1740 | /* detect if we are with an SRIOV vbios */ |
1741 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 1742 | |
d38ceaf9 | 1743 | /* Post card if necessary */ |
bec86378 | 1744 | if (amdgpu_vpost_needed(adev)) { |
d38ceaf9 | 1745 | if (!adev->bios) { |
bec86378 | 1746 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
1747 | r = -EINVAL; |
1748 | goto failed; | |
d38ceaf9 | 1749 | } |
bec86378 | 1750 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
1751 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
1752 | if (r) { | |
1753 | dev_err(adev->dev, "gpu post error!\n"); | |
1754 | goto failed; | |
1755 | } | |
1756 | } else { | |
1757 | DRM_INFO("GPU post is not needed\n"); | |
d38ceaf9 AD |
1758 | } |
1759 | ||
1760 | /* Initialize clocks */ | |
1761 | r = amdgpu_atombios_get_clock_info(adev); | |
2c1a2784 AD |
1762 | if (r) { |
1763 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
83ba126a | 1764 | goto failed; |
2c1a2784 | 1765 | } |
d38ceaf9 AD |
1766 | /* init i2c buses */ |
1767 | amdgpu_atombios_i2c_init(adev); | |
1768 | ||
1769 | /* Fence driver */ | |
1770 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
1771 | if (r) { |
1772 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
83ba126a | 1773 | goto failed; |
2c1a2784 | 1774 | } |
d38ceaf9 AD |
1775 | |
1776 | /* init the mode config */ | |
1777 | drm_mode_config_init(adev->ddev); | |
1778 | ||
1779 | r = amdgpu_init(adev); | |
1780 | if (r) { | |
2c1a2784 | 1781 | dev_err(adev->dev, "amdgpu_init failed\n"); |
d38ceaf9 | 1782 | amdgpu_fini(adev); |
83ba126a | 1783 | goto failed; |
d38ceaf9 AD |
1784 | } |
1785 | ||
1786 | adev->accel_working = true; | |
1787 | ||
95844d20 MO |
1788 | /* Initialize the buffer migration limit. */ |
1789 | if (amdgpu_moverate >= 0) | |
1790 | max_MBps = amdgpu_moverate; | |
1791 | else | |
1792 | max_MBps = 8; /* Allow 8 MB/s. */ | |
1793 | /* Get a log2 for easy divisions. */ | |
1794 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
1795 | ||
d38ceaf9 AD |
1796 | amdgpu_fbdev_init(adev); |
1797 | ||
1798 | r = amdgpu_ib_pool_init(adev); | |
1799 | if (r) { | |
1800 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
83ba126a | 1801 | goto failed; |
d38ceaf9 AD |
1802 | } |
1803 | ||
1804 | r = amdgpu_ib_ring_tests(adev); | |
1805 | if (r) | |
1806 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1807 | ||
1808 | r = amdgpu_gem_debugfs_init(adev); | |
1809 | if (r) { | |
1810 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); | |
1811 | } | |
1812 | ||
1813 | r = amdgpu_debugfs_regs_init(adev); | |
1814 | if (r) { | |
1815 | DRM_ERROR("registering register debugfs failed (%d).\n", r); | |
1816 | } | |
1817 | ||
50ab2533 HR |
1818 | r = amdgpu_debugfs_firmware_init(adev); |
1819 | if (r) { | |
1820 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); | |
1821 | return r; | |
1822 | } | |
1823 | ||
d38ceaf9 AD |
1824 | if ((amdgpu_testing & 1)) { |
1825 | if (adev->accel_working) | |
1826 | amdgpu_test_moves(adev); | |
1827 | else | |
1828 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
1829 | } | |
1830 | if ((amdgpu_testing & 2)) { | |
1831 | if (adev->accel_working) | |
1832 | amdgpu_test_syncing(adev); | |
1833 | else | |
1834 | DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n"); | |
1835 | } | |
1836 | if (amdgpu_benchmarking) { | |
1837 | if (adev->accel_working) | |
1838 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
1839 | else | |
1840 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
1841 | } | |
1842 | ||
1843 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
1844 | * explicit gating rather than handling it automatically. | |
1845 | */ | |
1846 | r = amdgpu_late_init(adev); | |
2c1a2784 AD |
1847 | if (r) { |
1848 | dev_err(adev->dev, "amdgpu_late_init failed\n"); | |
83ba126a | 1849 | goto failed; |
2c1a2784 | 1850 | } |
d38ceaf9 AD |
1851 | |
1852 | return 0; | |
83ba126a AD |
1853 | |
1854 | failed: | |
1855 | if (runtime) | |
1856 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
1857 | return r; | |
d38ceaf9 AD |
1858 | } |
1859 | ||
1860 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev); | |
1861 | ||
1862 | /** | |
1863 | * amdgpu_device_fini - tear down the driver | |
1864 | * | |
1865 | * @adev: amdgpu_device pointer | |
1866 | * | |
1867 | * Tear down the driver info (all asics). | |
1868 | * Called at driver shutdown. | |
1869 | */ | |
1870 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
1871 | { | |
1872 | int r; | |
1873 | ||
1874 | DRM_INFO("amdgpu: finishing device.\n"); | |
1875 | adev->shutdown = true; | |
a951ed85 | 1876 | drm_crtc_force_disable_all(adev->ddev); |
d38ceaf9 AD |
1877 | /* evict vram memory */ |
1878 | amdgpu_bo_evict_vram(adev); | |
1879 | amdgpu_ib_pool_fini(adev); | |
1880 | amdgpu_fence_driver_fini(adev); | |
1881 | amdgpu_fbdev_fini(adev); | |
1882 | r = amdgpu_fini(adev); | |
d38ceaf9 AD |
1883 | adev->accel_working = false; |
1884 | /* free i2c buses */ | |
1885 | amdgpu_i2c_fini(adev); | |
1886 | amdgpu_atombios_fini(adev); | |
1887 | kfree(adev->bios); | |
1888 | adev->bios = NULL; | |
1889 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
1890 | if (adev->flags & AMD_IS_PX) |
1891 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
1892 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
1893 | if (adev->rio_mem) | |
1894 | pci_iounmap(adev->pdev, adev->rio_mem); | |
1895 | adev->rio_mem = NULL; | |
1896 | iounmap(adev->rmmio); | |
1897 | adev->rmmio = NULL; | |
da69c161 KW |
1898 | if (adev->asic_type >= CHIP_BONAIRE) |
1899 | amdgpu_doorbell_fini(adev); | |
d38ceaf9 AD |
1900 | amdgpu_debugfs_regs_cleanup(adev); |
1901 | amdgpu_debugfs_remove_files(adev); | |
1902 | } | |
1903 | ||
1904 | ||
1905 | /* | |
1906 | * Suspend & resume. | |
1907 | */ | |
1908 | /** | |
810ddc3a | 1909 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 AD |
1910 | * |
1911 | * @pdev: drm dev pointer | |
1912 | * @state: suspend state | |
1913 | * | |
1914 | * Puts the hw in the suspend state (all asics). | |
1915 | * Returns 0 for success or an error on failure. | |
1916 | * Called at driver suspend. | |
1917 | */ | |
810ddc3a | 1918 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
1919 | { |
1920 | struct amdgpu_device *adev; | |
1921 | struct drm_crtc *crtc; | |
1922 | struct drm_connector *connector; | |
5ceb54c6 | 1923 | int r; |
d38ceaf9 AD |
1924 | |
1925 | if (dev == NULL || dev->dev_private == NULL) { | |
1926 | return -ENODEV; | |
1927 | } | |
1928 | ||
1929 | adev = dev->dev_private; | |
1930 | ||
1931 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1932 | return 0; | |
1933 | ||
1934 | drm_kms_helper_poll_disable(dev); | |
1935 | ||
1936 | /* turn off display hw */ | |
4c7fbc39 | 1937 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
1938 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
1939 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
1940 | } | |
4c7fbc39 | 1941 | drm_modeset_unlock_all(dev); |
d38ceaf9 | 1942 | |
756e6880 | 1943 | /* unpin the front buffers and cursors */ |
d38ceaf9 | 1944 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
756e6880 | 1945 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
d38ceaf9 AD |
1946 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); |
1947 | struct amdgpu_bo *robj; | |
1948 | ||
756e6880 AD |
1949 | if (amdgpu_crtc->cursor_bo) { |
1950 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
1951 | r = amdgpu_bo_reserve(aobj, false); | |
1952 | if (r == 0) { | |
1953 | amdgpu_bo_unpin(aobj); | |
1954 | amdgpu_bo_unreserve(aobj); | |
1955 | } | |
1956 | } | |
1957 | ||
d38ceaf9 AD |
1958 | if (rfb == NULL || rfb->obj == NULL) { |
1959 | continue; | |
1960 | } | |
1961 | robj = gem_to_amdgpu_bo(rfb->obj); | |
1962 | /* don't unpin kernel fb objects */ | |
1963 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
1964 | r = amdgpu_bo_reserve(robj, false); | |
1965 | if (r == 0) { | |
1966 | amdgpu_bo_unpin(robj); | |
1967 | amdgpu_bo_unreserve(robj); | |
1968 | } | |
1969 | } | |
1970 | } | |
1971 | /* evict vram memory */ | |
1972 | amdgpu_bo_evict_vram(adev); | |
1973 | ||
5ceb54c6 | 1974 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 AD |
1975 | |
1976 | r = amdgpu_suspend(adev); | |
1977 | ||
a0a71e49 AD |
1978 | /* evict remaining vram memory |
1979 | * This second call to evict vram is to evict the gart page table | |
1980 | * using the CPU. | |
1981 | */ | |
d38ceaf9 AD |
1982 | amdgpu_bo_evict_vram(adev); |
1983 | ||
e695e77c | 1984 | amdgpu_atombios_scratch_regs_save(adev); |
d38ceaf9 AD |
1985 | pci_save_state(dev->pdev); |
1986 | if (suspend) { | |
1987 | /* Shut down the device */ | |
1988 | pci_disable_device(dev->pdev); | |
1989 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 1990 | } else { |
1991 | r = amdgpu_asic_reset(adev); | |
1992 | if (r) | |
1993 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
1994 | } |
1995 | ||
1996 | if (fbcon) { | |
1997 | console_lock(); | |
1998 | amdgpu_fbdev_set_suspend(adev, 1); | |
1999 | console_unlock(); | |
2000 | } | |
2001 | return 0; | |
2002 | } | |
2003 | ||
2004 | /** | |
810ddc3a | 2005 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 AD |
2006 | * |
2007 | * @pdev: drm dev pointer | |
2008 | * | |
2009 | * Bring the hw back to operating state (all asics). | |
2010 | * Returns 0 for success or an error on failure. | |
2011 | * Called at driver resume. | |
2012 | */ | |
810ddc3a | 2013 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2014 | { |
2015 | struct drm_connector *connector; | |
2016 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2017 | struct drm_crtc *crtc; |
d38ceaf9 AD |
2018 | int r; |
2019 | ||
2020 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2021 | return 0; | |
2022 | ||
74b0b157 | 2023 | if (fbcon) |
d38ceaf9 | 2024 | console_lock(); |
74b0b157 | 2025 | |
d38ceaf9 AD |
2026 | if (resume) { |
2027 | pci_set_power_state(dev->pdev, PCI_D0); | |
2028 | pci_restore_state(dev->pdev); | |
74b0b157 | 2029 | r = pci_enable_device(dev->pdev); |
2030 | if (r) { | |
d38ceaf9 AD |
2031 | if (fbcon) |
2032 | console_unlock(); | |
74b0b157 | 2033 | return r; |
d38ceaf9 AD |
2034 | } |
2035 | } | |
e695e77c | 2036 | amdgpu_atombios_scratch_regs_restore(adev); |
d38ceaf9 AD |
2037 | |
2038 | /* post card */ | |
74b0b157 | 2039 | if (!amdgpu_card_posted(adev) || !resume) { |
2040 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2041 | if (r) | |
2042 | DRM_ERROR("amdgpu asic init failed\n"); | |
2043 | } | |
d38ceaf9 AD |
2044 | |
2045 | r = amdgpu_resume(adev); | |
ca198528 FC |
2046 | if (r) |
2047 | DRM_ERROR("amdgpu_resume failed (%d).\n", r); | |
d38ceaf9 | 2048 | |
5ceb54c6 AD |
2049 | amdgpu_fence_driver_resume(adev); |
2050 | ||
ca198528 FC |
2051 | if (resume) { |
2052 | r = amdgpu_ib_ring_tests(adev); | |
2053 | if (r) | |
2054 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2055 | } | |
d38ceaf9 AD |
2056 | |
2057 | r = amdgpu_late_init(adev); | |
2058 | if (r) | |
2059 | return r; | |
2060 | ||
756e6880 AD |
2061 | /* pin cursors */ |
2062 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2063 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2064 | ||
2065 | if (amdgpu_crtc->cursor_bo) { | |
2066 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); | |
2067 | r = amdgpu_bo_reserve(aobj, false); | |
2068 | if (r == 0) { | |
2069 | r = amdgpu_bo_pin(aobj, | |
2070 | AMDGPU_GEM_DOMAIN_VRAM, | |
2071 | &amdgpu_crtc->cursor_addr); | |
2072 | if (r != 0) | |
2073 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2074 | amdgpu_bo_unreserve(aobj); | |
2075 | } | |
2076 | } | |
2077 | } | |
2078 | ||
d38ceaf9 AD |
2079 | /* blat the mode back in */ |
2080 | if (fbcon) { | |
2081 | drm_helper_resume_force_mode(dev); | |
2082 | /* turn on display hw */ | |
4c7fbc39 | 2083 | drm_modeset_lock_all(dev); |
d38ceaf9 AD |
2084 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
2085 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
2086 | } | |
4c7fbc39 | 2087 | drm_modeset_unlock_all(dev); |
d38ceaf9 AD |
2088 | } |
2089 | ||
2090 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 L |
2091 | |
2092 | /* | |
2093 | * Most of the connector probing functions try to acquire runtime pm | |
2094 | * refs to ensure that the GPU is powered on when connector polling is | |
2095 | * performed. Since we're calling this from a runtime PM callback, | |
2096 | * trying to acquire rpm refs will cause us to deadlock. | |
2097 | * | |
2098 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
2099 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
2100 | */ | |
2101 | #ifdef CONFIG_PM | |
2102 | dev->dev->power.disable_depth++; | |
2103 | #endif | |
54fb2a5c | 2104 | drm_helper_hpd_irq_event(dev); |
23a1a9e5 L |
2105 | #ifdef CONFIG_PM |
2106 | dev->dev->power.disable_depth--; | |
2107 | #endif | |
d38ceaf9 AD |
2108 | |
2109 | if (fbcon) { | |
2110 | amdgpu_fbdev_set_suspend(adev, 0); | |
2111 | console_unlock(); | |
2112 | } | |
2113 | ||
2114 | return 0; | |
2115 | } | |
2116 | ||
63fbf42f CZ |
2117 | static bool amdgpu_check_soft_reset(struct amdgpu_device *adev) |
2118 | { | |
2119 | int i; | |
2120 | bool asic_hang = false; | |
2121 | ||
2122 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2123 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 2124 | continue; |
a1255107 AD |
2125 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
2126 | adev->ip_blocks[i].status.hang = | |
2127 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
2128 | if (adev->ip_blocks[i].status.hang) { | |
2129 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
2130 | asic_hang = true; |
2131 | } | |
2132 | } | |
2133 | return asic_hang; | |
2134 | } | |
2135 | ||
4d446656 | 2136 | static int amdgpu_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
2137 | { |
2138 | int i, r = 0; | |
2139 | ||
2140 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2141 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 2142 | continue; |
a1255107 AD |
2143 | if (adev->ip_blocks[i].status.hang && |
2144 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
2145 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
2146 | if (r) |
2147 | return r; | |
2148 | } | |
2149 | } | |
2150 | ||
2151 | return 0; | |
2152 | } | |
2153 | ||
35d782fe CZ |
2154 | static bool amdgpu_need_full_reset(struct amdgpu_device *adev) |
2155 | { | |
da146d3b AD |
2156 | int i; |
2157 | ||
2158 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2159 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 2160 | continue; |
a1255107 AD |
2161 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
2162 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
2163 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
2164 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) { | |
2165 | if (adev->ip_blocks[i].status.hang) { | |
da146d3b AD |
2166 | DRM_INFO("Some block need full reset!\n"); |
2167 | return true; | |
2168 | } | |
2169 | } | |
35d782fe CZ |
2170 | } |
2171 | return false; | |
2172 | } | |
2173 | ||
2174 | static int amdgpu_soft_reset(struct amdgpu_device *adev) | |
2175 | { | |
2176 | int i, r = 0; | |
2177 | ||
2178 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2179 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2180 | continue; |
a1255107 AD |
2181 | if (adev->ip_blocks[i].status.hang && |
2182 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
2183 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
2184 | if (r) |
2185 | return r; | |
2186 | } | |
2187 | } | |
2188 | ||
2189 | return 0; | |
2190 | } | |
2191 | ||
2192 | static int amdgpu_post_soft_reset(struct amdgpu_device *adev) | |
2193 | { | |
2194 | int i, r = 0; | |
2195 | ||
2196 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2197 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 2198 | continue; |
a1255107 AD |
2199 | if (adev->ip_blocks[i].status.hang && |
2200 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
2201 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
2202 | if (r) |
2203 | return r; | |
2204 | } | |
2205 | ||
2206 | return 0; | |
2207 | } | |
2208 | ||
3ad81f16 CZ |
2209 | bool amdgpu_need_backup(struct amdgpu_device *adev) |
2210 | { | |
2211 | if (adev->flags & AMD_IS_APU) | |
2212 | return false; | |
2213 | ||
2214 | return amdgpu_lockup_timeout > 0 ? true : false; | |
2215 | } | |
2216 | ||
53cdccd5 CZ |
2217 | static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev, |
2218 | struct amdgpu_ring *ring, | |
2219 | struct amdgpu_bo *bo, | |
f54d1867 | 2220 | struct dma_fence **fence) |
53cdccd5 CZ |
2221 | { |
2222 | uint32_t domain; | |
2223 | int r; | |
2224 | ||
2225 | if (!bo->shadow) | |
2226 | return 0; | |
2227 | ||
2228 | r = amdgpu_bo_reserve(bo, false); | |
2229 | if (r) | |
2230 | return r; | |
2231 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
2232 | /* if bo has been evicted, then no need to recover */ | |
2233 | if (domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
2234 | r = amdgpu_bo_restore_from_shadow(adev, ring, bo, | |
2235 | NULL, fence, true); | |
2236 | if (r) { | |
2237 | DRM_ERROR("recover page table failed!\n"); | |
2238 | goto err; | |
2239 | } | |
2240 | } | |
2241 | err: | |
2242 | amdgpu_bo_unreserve(bo); | |
2243 | return r; | |
2244 | } | |
2245 | ||
d38ceaf9 AD |
2246 | /** |
2247 | * amdgpu_gpu_reset - reset the asic | |
2248 | * | |
2249 | * @adev: amdgpu device pointer | |
2250 | * | |
2251 | * Attempt the reset the GPU if it has hung (all asics). | |
2252 | * Returns 0 for success or an error on failure. | |
2253 | */ | |
2254 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
2255 | { | |
d38ceaf9 AD |
2256 | int i, r; |
2257 | int resched; | |
35d782fe | 2258 | bool need_full_reset; |
d38ceaf9 | 2259 | |
63fbf42f CZ |
2260 | if (!amdgpu_check_soft_reset(adev)) { |
2261 | DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); | |
2262 | return 0; | |
2263 | } | |
d38ceaf9 | 2264 | |
d94aed5a | 2265 | atomic_inc(&adev->gpu_reset_counter); |
d38ceaf9 | 2266 | |
a3c47d6b CZ |
2267 | /* block TTM */ |
2268 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
2269 | ||
0875dc9e CZ |
2270 | /* block scheduler */ |
2271 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
2272 | struct amdgpu_ring *ring = adev->rings[i]; | |
2273 | ||
2274 | if (!ring) | |
2275 | continue; | |
2276 | kthread_park(ring->sched.thread); | |
aa1c8900 | 2277 | amd_sched_hw_job_reset(&ring->sched); |
0875dc9e | 2278 | } |
2200edac CZ |
2279 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
2280 | amdgpu_fence_driver_force_completion(adev); | |
d38ceaf9 | 2281 | |
35d782fe | 2282 | need_full_reset = amdgpu_need_full_reset(adev); |
d38ceaf9 | 2283 | |
35d782fe CZ |
2284 | if (!need_full_reset) { |
2285 | amdgpu_pre_soft_reset(adev); | |
2286 | r = amdgpu_soft_reset(adev); | |
2287 | amdgpu_post_soft_reset(adev); | |
2288 | if (r || amdgpu_check_soft_reset(adev)) { | |
2289 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
2290 | need_full_reset = true; | |
2291 | } | |
f1aa7e08 CZ |
2292 | } |
2293 | ||
35d782fe | 2294 | if (need_full_reset) { |
35d782fe | 2295 | r = amdgpu_suspend(adev); |
bfa99269 | 2296 | |
35d782fe CZ |
2297 | retry: |
2298 | /* Disable fb access */ | |
2299 | if (adev->mode_info.num_crtc) { | |
2300 | struct amdgpu_mode_mc_save save; | |
2301 | amdgpu_display_stop_mc_access(adev, &save); | |
2302 | amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC); | |
2303 | } | |
e695e77c | 2304 | amdgpu_atombios_scratch_regs_save(adev); |
35d782fe | 2305 | r = amdgpu_asic_reset(adev); |
e695e77c | 2306 | amdgpu_atombios_scratch_regs_restore(adev); |
35d782fe CZ |
2307 | /* post card */ |
2308 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
2309 | ||
2310 | if (!r) { | |
2311 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
2312 | r = amdgpu_resume(adev); | |
2313 | } | |
d38ceaf9 | 2314 | } |
d38ceaf9 | 2315 | if (!r) { |
e72cfd58 | 2316 | amdgpu_irq_gpu_reset_resume_helper(adev); |
2c0d7318 CZ |
2317 | if (need_full_reset && amdgpu_need_backup(adev)) { |
2318 | r = amdgpu_ttm_recover_gart(adev); | |
2319 | if (r) | |
2320 | DRM_ERROR("gart recovery failed!!!\n"); | |
2321 | } | |
1f465087 CZ |
2322 | r = amdgpu_ib_ring_tests(adev); |
2323 | if (r) { | |
2324 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
40019dc4 | 2325 | r = amdgpu_suspend(adev); |
53cdccd5 | 2326 | need_full_reset = true; |
40019dc4 | 2327 | goto retry; |
1f465087 | 2328 | } |
53cdccd5 CZ |
2329 | /** |
2330 | * recovery vm page tables, since we cannot depend on VRAM is | |
2331 | * consistent after gpu full reset. | |
2332 | */ | |
2333 | if (need_full_reset && amdgpu_need_backup(adev)) { | |
2334 | struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; | |
2335 | struct amdgpu_bo *bo, *tmp; | |
f54d1867 | 2336 | struct dma_fence *fence = NULL, *next = NULL; |
53cdccd5 CZ |
2337 | |
2338 | DRM_INFO("recover vram bo from shadow\n"); | |
2339 | mutex_lock(&adev->shadow_list_lock); | |
2340 | list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { | |
2341 | amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); | |
2342 | if (fence) { | |
f54d1867 | 2343 | r = dma_fence_wait(fence, false); |
53cdccd5 CZ |
2344 | if (r) { |
2345 | WARN(r, "recovery from shadow isn't comleted\n"); | |
2346 | break; | |
2347 | } | |
2348 | } | |
1f465087 | 2349 | |
f54d1867 | 2350 | dma_fence_put(fence); |
53cdccd5 CZ |
2351 | fence = next; |
2352 | } | |
2353 | mutex_unlock(&adev->shadow_list_lock); | |
2354 | if (fence) { | |
f54d1867 | 2355 | r = dma_fence_wait(fence, false); |
53cdccd5 CZ |
2356 | if (r) |
2357 | WARN(r, "recovery from shadow isn't comleted\n"); | |
2358 | } | |
f54d1867 | 2359 | dma_fence_put(fence); |
53cdccd5 | 2360 | } |
d38ceaf9 AD |
2361 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
2362 | struct amdgpu_ring *ring = adev->rings[i]; | |
2363 | if (!ring) | |
2364 | continue; | |
53cdccd5 | 2365 | |
aa1c8900 | 2366 | amd_sched_job_recovery(&ring->sched); |
0875dc9e | 2367 | kthread_unpark(ring->sched.thread); |
d38ceaf9 | 2368 | } |
d38ceaf9 | 2369 | } else { |
2200edac | 2370 | dev_err(adev->dev, "asic resume failed (%d).\n", r); |
d38ceaf9 | 2371 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
0875dc9e CZ |
2372 | if (adev->rings[i]) { |
2373 | kthread_unpark(adev->rings[i]->sched.thread); | |
0875dc9e | 2374 | } |
d38ceaf9 AD |
2375 | } |
2376 | } | |
2377 | ||
2378 | drm_helper_resume_force_mode(adev->ddev); | |
2379 | ||
2380 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
2381 | if (r) { | |
2382 | /* bad news, how to tell it to userspace ? */ | |
2383 | dev_info(adev->dev, "GPU reset failed\n"); | |
2384 | } | |
2385 | ||
d38ceaf9 AD |
2386 | return r; |
2387 | } | |
2388 | ||
d0dd7f0c AD |
2389 | void amdgpu_get_pcie_info(struct amdgpu_device *adev) |
2390 | { | |
2391 | u32 mask; | |
2392 | int ret; | |
2393 | ||
cd474ba0 AD |
2394 | if (amdgpu_pcie_gen_cap) |
2395 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 2396 | |
cd474ba0 AD |
2397 | if (amdgpu_pcie_lane_cap) |
2398 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 2399 | |
cd474ba0 AD |
2400 | /* covers APUs as well */ |
2401 | if (pci_is_root_bus(adev->pdev->bus)) { | |
2402 | if (adev->pm.pcie_gen_mask == 0) | |
2403 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2404 | if (adev->pm.pcie_mlw_mask == 0) | |
2405 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 2406 | return; |
cd474ba0 | 2407 | } |
d0dd7f0c | 2408 | |
cd474ba0 AD |
2409 | if (adev->pm.pcie_gen_mask == 0) { |
2410 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | |
2411 | if (!ret) { | |
2412 | adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
2413 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
2414 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
2415 | ||
2416 | if (mask & DRM_PCIE_SPEED_25) | |
2417 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
2418 | if (mask & DRM_PCIE_SPEED_50) | |
2419 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2; | |
2420 | if (mask & DRM_PCIE_SPEED_80) | |
2421 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3; | |
2422 | } else { | |
2423 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
2424 | } | |
2425 | } | |
2426 | if (adev->pm.pcie_mlw_mask == 0) { | |
2427 | ret = drm_pcie_get_max_link_width(adev->ddev, &mask); | |
2428 | if (!ret) { | |
2429 | switch (mask) { | |
2430 | case 32: | |
2431 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | | |
2432 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2433 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2434 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2435 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2436 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2437 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2438 | break; | |
2439 | case 16: | |
2440 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
2441 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2442 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2443 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2444 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2445 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2446 | break; | |
2447 | case 12: | |
2448 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
2449 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2450 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2451 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2452 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2453 | break; | |
2454 | case 8: | |
2455 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
2456 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2457 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2458 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2459 | break; | |
2460 | case 4: | |
2461 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
2462 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2463 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2464 | break; | |
2465 | case 2: | |
2466 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
2467 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
2468 | break; | |
2469 | case 1: | |
2470 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; | |
2471 | break; | |
2472 | default: | |
2473 | break; | |
2474 | } | |
2475 | } else { | |
2476 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c AD |
2477 | } |
2478 | } | |
2479 | } | |
d38ceaf9 AD |
2480 | |
2481 | /* | |
2482 | * Debugfs | |
2483 | */ | |
2484 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
06ab6832 | 2485 | const struct drm_info_list *files, |
d38ceaf9 AD |
2486 | unsigned nfiles) |
2487 | { | |
2488 | unsigned i; | |
2489 | ||
2490 | for (i = 0; i < adev->debugfs_count; i++) { | |
2491 | if (adev->debugfs[i].files == files) { | |
2492 | /* Already registered */ | |
2493 | return 0; | |
2494 | } | |
2495 | } | |
2496 | ||
2497 | i = adev->debugfs_count + 1; | |
2498 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
2499 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
2500 | DRM_ERROR("Report so we increase " | |
2501 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
2502 | return -EINVAL; | |
2503 | } | |
2504 | adev->debugfs[adev->debugfs_count].files = files; | |
2505 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
2506 | adev->debugfs_count = i; | |
2507 | #if defined(CONFIG_DEBUG_FS) | |
2508 | drm_debugfs_create_files(files, nfiles, | |
2509 | adev->ddev->control->debugfs_root, | |
2510 | adev->ddev->control); | |
2511 | drm_debugfs_create_files(files, nfiles, | |
2512 | adev->ddev->primary->debugfs_root, | |
2513 | adev->ddev->primary); | |
2514 | #endif | |
2515 | return 0; | |
2516 | } | |
2517 | ||
2518 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev) | |
2519 | { | |
2520 | #if defined(CONFIG_DEBUG_FS) | |
2521 | unsigned i; | |
2522 | ||
2523 | for (i = 0; i < adev->debugfs_count; i++) { | |
2524 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
2525 | adev->debugfs[i].num_files, | |
2526 | adev->ddev->control); | |
2527 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
2528 | adev->debugfs[i].num_files, | |
2529 | adev->ddev->primary); | |
2530 | } | |
2531 | #endif | |
2532 | } | |
2533 | ||
2534 | #if defined(CONFIG_DEBUG_FS) | |
2535 | ||
2536 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
2537 | size_t size, loff_t *pos) | |
2538 | { | |
2539 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2540 | ssize_t result = 0; | |
2541 | int r; | |
bd12267d | 2542 | bool pm_pg_lock, use_bank; |
56628159 | 2543 | unsigned instance_bank, sh_bank, se_bank; |
d38ceaf9 AD |
2544 | |
2545 | if (size & 0x3 || *pos & 0x3) | |
2546 | return -EINVAL; | |
2547 | ||
bd12267d TSD |
2548 | /* are we reading registers for which a PG lock is necessary? */ |
2549 | pm_pg_lock = (*pos >> 23) & 1; | |
2550 | ||
56628159 TSD |
2551 | if (*pos & (1ULL << 62)) { |
2552 | se_bank = (*pos >> 24) & 0x3FF; | |
2553 | sh_bank = (*pos >> 34) & 0x3FF; | |
2554 | instance_bank = (*pos >> 44) & 0x3FF; | |
32977f93 TSD |
2555 | |
2556 | if (se_bank == 0x3FF) | |
2557 | se_bank = 0xFFFFFFFF; | |
2558 | if (sh_bank == 0x3FF) | |
2559 | sh_bank = 0xFFFFFFFF; | |
2560 | if (instance_bank == 0x3FF) | |
2561 | instance_bank = 0xFFFFFFFF; | |
56628159 | 2562 | use_bank = 1; |
56628159 TSD |
2563 | } else { |
2564 | use_bank = 0; | |
2565 | } | |
2566 | ||
bd12267d TSD |
2567 | *pos &= 0x3FFFF; |
2568 | ||
56628159 | 2569 | if (use_bank) { |
32977f93 TSD |
2570 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || |
2571 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
56628159 TSD |
2572 | return -EINVAL; |
2573 | mutex_lock(&adev->grbm_idx_mutex); | |
2574 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
2575 | sh_bank, instance_bank); | |
2576 | } | |
2577 | ||
bd12267d TSD |
2578 | if (pm_pg_lock) |
2579 | mutex_lock(&adev->pm.mutex); | |
2580 | ||
d38ceaf9 AD |
2581 | while (size) { |
2582 | uint32_t value; | |
2583 | ||
2584 | if (*pos > adev->rmmio_size) | |
56628159 | 2585 | goto end; |
d38ceaf9 AD |
2586 | |
2587 | value = RREG32(*pos >> 2); | |
2588 | r = put_user(value, (uint32_t *)buf); | |
56628159 TSD |
2589 | if (r) { |
2590 | result = r; | |
2591 | goto end; | |
2592 | } | |
d38ceaf9 AD |
2593 | |
2594 | result += 4; | |
2595 | buf += 4; | |
2596 | *pos += 4; | |
2597 | size -= 4; | |
2598 | } | |
2599 | ||
56628159 TSD |
2600 | end: |
2601 | if (use_bank) { | |
2602 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
2603 | mutex_unlock(&adev->grbm_idx_mutex); | |
2604 | } | |
2605 | ||
bd12267d TSD |
2606 | if (pm_pg_lock) |
2607 | mutex_unlock(&adev->pm.mutex); | |
2608 | ||
d38ceaf9 AD |
2609 | return result; |
2610 | } | |
2611 | ||
2612 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
2613 | size_t size, loff_t *pos) | |
2614 | { | |
2615 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2616 | ssize_t result = 0; | |
2617 | int r; | |
394fdde2 TSD |
2618 | bool pm_pg_lock, use_bank; |
2619 | unsigned instance_bank, sh_bank, se_bank; | |
d38ceaf9 AD |
2620 | |
2621 | if (size & 0x3 || *pos & 0x3) | |
2622 | return -EINVAL; | |
2623 | ||
394fdde2 TSD |
2624 | /* are we reading registers for which a PG lock is necessary? */ |
2625 | pm_pg_lock = (*pos >> 23) & 1; | |
2626 | ||
2627 | if (*pos & (1ULL << 62)) { | |
2628 | se_bank = (*pos >> 24) & 0x3FF; | |
2629 | sh_bank = (*pos >> 34) & 0x3FF; | |
2630 | instance_bank = (*pos >> 44) & 0x3FF; | |
2631 | ||
2632 | if (se_bank == 0x3FF) | |
2633 | se_bank = 0xFFFFFFFF; | |
2634 | if (sh_bank == 0x3FF) | |
2635 | sh_bank = 0xFFFFFFFF; | |
2636 | if (instance_bank == 0x3FF) | |
2637 | instance_bank = 0xFFFFFFFF; | |
2638 | use_bank = 1; | |
2639 | } else { | |
2640 | use_bank = 0; | |
2641 | } | |
2642 | ||
2643 | *pos &= 0x3FFFF; | |
2644 | ||
2645 | if (use_bank) { | |
2646 | if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || | |
2647 | (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) | |
2648 | return -EINVAL; | |
2649 | mutex_lock(&adev->grbm_idx_mutex); | |
2650 | amdgpu_gfx_select_se_sh(adev, se_bank, | |
2651 | sh_bank, instance_bank); | |
2652 | } | |
2653 | ||
2654 | if (pm_pg_lock) | |
2655 | mutex_lock(&adev->pm.mutex); | |
2656 | ||
d38ceaf9 AD |
2657 | while (size) { |
2658 | uint32_t value; | |
2659 | ||
2660 | if (*pos > adev->rmmio_size) | |
2661 | return result; | |
2662 | ||
2663 | r = get_user(value, (uint32_t *)buf); | |
2664 | if (r) | |
2665 | return r; | |
2666 | ||
2667 | WREG32(*pos >> 2, value); | |
2668 | ||
2669 | result += 4; | |
2670 | buf += 4; | |
2671 | *pos += 4; | |
2672 | size -= 4; | |
2673 | } | |
2674 | ||
394fdde2 TSD |
2675 | if (use_bank) { |
2676 | amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); | |
2677 | mutex_unlock(&adev->grbm_idx_mutex); | |
2678 | } | |
2679 | ||
2680 | if (pm_pg_lock) | |
2681 | mutex_unlock(&adev->pm.mutex); | |
2682 | ||
d38ceaf9 AD |
2683 | return result; |
2684 | } | |
2685 | ||
adcec288 TSD |
2686 | static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, |
2687 | size_t size, loff_t *pos) | |
2688 | { | |
2689 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2690 | ssize_t result = 0; | |
2691 | int r; | |
2692 | ||
2693 | if (size & 0x3 || *pos & 0x3) | |
2694 | return -EINVAL; | |
2695 | ||
2696 | while (size) { | |
2697 | uint32_t value; | |
2698 | ||
2699 | value = RREG32_PCIE(*pos >> 2); | |
2700 | r = put_user(value, (uint32_t *)buf); | |
2701 | if (r) | |
2702 | return r; | |
2703 | ||
2704 | result += 4; | |
2705 | buf += 4; | |
2706 | *pos += 4; | |
2707 | size -= 4; | |
2708 | } | |
2709 | ||
2710 | return result; | |
2711 | } | |
2712 | ||
2713 | static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, | |
2714 | size_t size, loff_t *pos) | |
2715 | { | |
2716 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2717 | ssize_t result = 0; | |
2718 | int r; | |
2719 | ||
2720 | if (size & 0x3 || *pos & 0x3) | |
2721 | return -EINVAL; | |
2722 | ||
2723 | while (size) { | |
2724 | uint32_t value; | |
2725 | ||
2726 | r = get_user(value, (uint32_t *)buf); | |
2727 | if (r) | |
2728 | return r; | |
2729 | ||
2730 | WREG32_PCIE(*pos >> 2, value); | |
2731 | ||
2732 | result += 4; | |
2733 | buf += 4; | |
2734 | *pos += 4; | |
2735 | size -= 4; | |
2736 | } | |
2737 | ||
2738 | return result; | |
2739 | } | |
2740 | ||
2741 | static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, | |
2742 | size_t size, loff_t *pos) | |
2743 | { | |
2744 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2745 | ssize_t result = 0; | |
2746 | int r; | |
2747 | ||
2748 | if (size & 0x3 || *pos & 0x3) | |
2749 | return -EINVAL; | |
2750 | ||
2751 | while (size) { | |
2752 | uint32_t value; | |
2753 | ||
2754 | value = RREG32_DIDT(*pos >> 2); | |
2755 | r = put_user(value, (uint32_t *)buf); | |
2756 | if (r) | |
2757 | return r; | |
2758 | ||
2759 | result += 4; | |
2760 | buf += 4; | |
2761 | *pos += 4; | |
2762 | size -= 4; | |
2763 | } | |
2764 | ||
2765 | return result; | |
2766 | } | |
2767 | ||
2768 | static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, | |
2769 | size_t size, loff_t *pos) | |
2770 | { | |
2771 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2772 | ssize_t result = 0; | |
2773 | int r; | |
2774 | ||
2775 | if (size & 0x3 || *pos & 0x3) | |
2776 | return -EINVAL; | |
2777 | ||
2778 | while (size) { | |
2779 | uint32_t value; | |
2780 | ||
2781 | r = get_user(value, (uint32_t *)buf); | |
2782 | if (r) | |
2783 | return r; | |
2784 | ||
2785 | WREG32_DIDT(*pos >> 2, value); | |
2786 | ||
2787 | result += 4; | |
2788 | buf += 4; | |
2789 | *pos += 4; | |
2790 | size -= 4; | |
2791 | } | |
2792 | ||
2793 | return result; | |
2794 | } | |
2795 | ||
2796 | static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, | |
2797 | size_t size, loff_t *pos) | |
2798 | { | |
2799 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2800 | ssize_t result = 0; | |
2801 | int r; | |
2802 | ||
2803 | if (size & 0x3 || *pos & 0x3) | |
2804 | return -EINVAL; | |
2805 | ||
2806 | while (size) { | |
2807 | uint32_t value; | |
2808 | ||
6fc0deaf | 2809 | value = RREG32_SMC(*pos); |
adcec288 TSD |
2810 | r = put_user(value, (uint32_t *)buf); |
2811 | if (r) | |
2812 | return r; | |
2813 | ||
2814 | result += 4; | |
2815 | buf += 4; | |
2816 | *pos += 4; | |
2817 | size -= 4; | |
2818 | } | |
2819 | ||
2820 | return result; | |
2821 | } | |
2822 | ||
2823 | static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, | |
2824 | size_t size, loff_t *pos) | |
2825 | { | |
2826 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2827 | ssize_t result = 0; | |
2828 | int r; | |
2829 | ||
2830 | if (size & 0x3 || *pos & 0x3) | |
2831 | return -EINVAL; | |
2832 | ||
2833 | while (size) { | |
2834 | uint32_t value; | |
2835 | ||
2836 | r = get_user(value, (uint32_t *)buf); | |
2837 | if (r) | |
2838 | return r; | |
2839 | ||
6fc0deaf | 2840 | WREG32_SMC(*pos, value); |
adcec288 TSD |
2841 | |
2842 | result += 4; | |
2843 | buf += 4; | |
2844 | *pos += 4; | |
2845 | size -= 4; | |
2846 | } | |
2847 | ||
2848 | return result; | |
2849 | } | |
2850 | ||
1e051413 TSD |
2851 | static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, |
2852 | size_t size, loff_t *pos) | |
2853 | { | |
2854 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2855 | ssize_t result = 0; | |
2856 | int r; | |
2857 | uint32_t *config, no_regs = 0; | |
2858 | ||
2859 | if (size & 0x3 || *pos & 0x3) | |
2860 | return -EINVAL; | |
2861 | ||
ecab7668 | 2862 | config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); |
1e051413 TSD |
2863 | if (!config) |
2864 | return -ENOMEM; | |
2865 | ||
2866 | /* version, increment each time something is added */ | |
e9f11dc8 | 2867 | config[no_regs++] = 2; |
1e051413 TSD |
2868 | config[no_regs++] = adev->gfx.config.max_shader_engines; |
2869 | config[no_regs++] = adev->gfx.config.max_tile_pipes; | |
2870 | config[no_regs++] = adev->gfx.config.max_cu_per_sh; | |
2871 | config[no_regs++] = adev->gfx.config.max_sh_per_se; | |
2872 | config[no_regs++] = adev->gfx.config.max_backends_per_se; | |
2873 | config[no_regs++] = adev->gfx.config.max_texture_channel_caches; | |
2874 | config[no_regs++] = adev->gfx.config.max_gprs; | |
2875 | config[no_regs++] = adev->gfx.config.max_gs_threads; | |
2876 | config[no_regs++] = adev->gfx.config.max_hw_contexts; | |
2877 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; | |
2878 | config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; | |
2879 | config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; | |
2880 | config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; | |
2881 | config[no_regs++] = adev->gfx.config.num_tile_pipes; | |
2882 | config[no_regs++] = adev->gfx.config.backend_enable_mask; | |
2883 | config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; | |
2884 | config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; | |
2885 | config[no_regs++] = adev->gfx.config.shader_engine_tile_size; | |
2886 | config[no_regs++] = adev->gfx.config.num_gpus; | |
2887 | config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; | |
2888 | config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; | |
2889 | config[no_regs++] = adev->gfx.config.gb_addr_config; | |
2890 | config[no_regs++] = adev->gfx.config.num_rbs; | |
2891 | ||
89a8f309 TSD |
2892 | /* rev==1 */ |
2893 | config[no_regs++] = adev->rev_id; | |
2894 | config[no_regs++] = adev->pg_flags; | |
2895 | config[no_regs++] = adev->cg_flags; | |
2896 | ||
e9f11dc8 TSD |
2897 | /* rev==2 */ |
2898 | config[no_regs++] = adev->family; | |
2899 | config[no_regs++] = adev->external_rev_id; | |
2900 | ||
1e051413 TSD |
2901 | while (size && (*pos < no_regs * 4)) { |
2902 | uint32_t value; | |
2903 | ||
2904 | value = config[*pos >> 2]; | |
2905 | r = put_user(value, (uint32_t *)buf); | |
2906 | if (r) { | |
2907 | kfree(config); | |
2908 | return r; | |
2909 | } | |
2910 | ||
2911 | result += 4; | |
2912 | buf += 4; | |
2913 | *pos += 4; | |
2914 | size -= 4; | |
2915 | } | |
2916 | ||
2917 | kfree(config); | |
2918 | return result; | |
2919 | } | |
2920 | ||
f2cdaf20 TSD |
2921 | static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, |
2922 | size_t size, loff_t *pos) | |
2923 | { | |
2924 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2925 | int idx, r; | |
2926 | int32_t value; | |
2927 | ||
2928 | if (size != 4 || *pos & 0x3) | |
2929 | return -EINVAL; | |
2930 | ||
2931 | /* convert offset to sensor number */ | |
2932 | idx = *pos >> 2; | |
2933 | ||
2934 | if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor) | |
2935 | r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value); | |
2936 | else | |
2937 | return -EINVAL; | |
2938 | ||
2939 | if (!r) | |
2940 | r = put_user(value, (int32_t *)buf); | |
2941 | ||
2942 | return !r ? 4 : r; | |
2943 | } | |
1e051413 | 2944 | |
273d7aa1 TSD |
2945 | static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, |
2946 | size_t size, loff_t *pos) | |
2947 | { | |
2948 | struct amdgpu_device *adev = f->f_inode->i_private; | |
2949 | int r, x; | |
2950 | ssize_t result=0; | |
472259f0 | 2951 | uint32_t offset, se, sh, cu, wave, simd, data[32]; |
273d7aa1 TSD |
2952 | |
2953 | if (size & 3 || *pos & 3) | |
2954 | return -EINVAL; | |
2955 | ||
2956 | /* decode offset */ | |
2957 | offset = (*pos & 0x7F); | |
2958 | se = ((*pos >> 7) & 0xFF); | |
2959 | sh = ((*pos >> 15) & 0xFF); | |
2960 | cu = ((*pos >> 23) & 0xFF); | |
2961 | wave = ((*pos >> 31) & 0xFF); | |
2962 | simd = ((*pos >> 37) & 0xFF); | |
273d7aa1 TSD |
2963 | |
2964 | /* switch to the specific se/sh/cu */ | |
2965 | mutex_lock(&adev->grbm_idx_mutex); | |
2966 | amdgpu_gfx_select_se_sh(adev, se, sh, cu); | |
2967 | ||
2968 | x = 0; | |
472259f0 TSD |
2969 | if (adev->gfx.funcs->read_wave_data) |
2970 | adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); | |
273d7aa1 TSD |
2971 | |
2972 | amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); | |
2973 | mutex_unlock(&adev->grbm_idx_mutex); | |
2974 | ||
5ecfb3b8 TSD |
2975 | if (!x) |
2976 | return -EINVAL; | |
2977 | ||
472259f0 | 2978 | while (size && (offset < x * 4)) { |
273d7aa1 TSD |
2979 | uint32_t value; |
2980 | ||
472259f0 | 2981 | value = data[offset >> 2]; |
273d7aa1 TSD |
2982 | r = put_user(value, (uint32_t *)buf); |
2983 | if (r) | |
2984 | return r; | |
2985 | ||
2986 | result += 4; | |
2987 | buf += 4; | |
472259f0 | 2988 | offset += 4; |
273d7aa1 TSD |
2989 | size -= 4; |
2990 | } | |
2991 | ||
2992 | return result; | |
2993 | } | |
2994 | ||
d38ceaf9 AD |
2995 | static const struct file_operations amdgpu_debugfs_regs_fops = { |
2996 | .owner = THIS_MODULE, | |
2997 | .read = amdgpu_debugfs_regs_read, | |
2998 | .write = amdgpu_debugfs_regs_write, | |
2999 | .llseek = default_llseek | |
3000 | }; | |
adcec288 TSD |
3001 | static const struct file_operations amdgpu_debugfs_regs_didt_fops = { |
3002 | .owner = THIS_MODULE, | |
3003 | .read = amdgpu_debugfs_regs_didt_read, | |
3004 | .write = amdgpu_debugfs_regs_didt_write, | |
3005 | .llseek = default_llseek | |
3006 | }; | |
3007 | static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { | |
3008 | .owner = THIS_MODULE, | |
3009 | .read = amdgpu_debugfs_regs_pcie_read, | |
3010 | .write = amdgpu_debugfs_regs_pcie_write, | |
3011 | .llseek = default_llseek | |
3012 | }; | |
3013 | static const struct file_operations amdgpu_debugfs_regs_smc_fops = { | |
3014 | .owner = THIS_MODULE, | |
3015 | .read = amdgpu_debugfs_regs_smc_read, | |
3016 | .write = amdgpu_debugfs_regs_smc_write, | |
3017 | .llseek = default_llseek | |
3018 | }; | |
3019 | ||
1e051413 TSD |
3020 | static const struct file_operations amdgpu_debugfs_gca_config_fops = { |
3021 | .owner = THIS_MODULE, | |
3022 | .read = amdgpu_debugfs_gca_config_read, | |
3023 | .llseek = default_llseek | |
3024 | }; | |
3025 | ||
f2cdaf20 TSD |
3026 | static const struct file_operations amdgpu_debugfs_sensors_fops = { |
3027 | .owner = THIS_MODULE, | |
3028 | .read = amdgpu_debugfs_sensor_read, | |
3029 | .llseek = default_llseek | |
3030 | }; | |
3031 | ||
273d7aa1 TSD |
3032 | static const struct file_operations amdgpu_debugfs_wave_fops = { |
3033 | .owner = THIS_MODULE, | |
3034 | .read = amdgpu_debugfs_wave_read, | |
3035 | .llseek = default_llseek | |
3036 | }; | |
3037 | ||
adcec288 TSD |
3038 | static const struct file_operations *debugfs_regs[] = { |
3039 | &amdgpu_debugfs_regs_fops, | |
3040 | &amdgpu_debugfs_regs_didt_fops, | |
3041 | &amdgpu_debugfs_regs_pcie_fops, | |
3042 | &amdgpu_debugfs_regs_smc_fops, | |
1e051413 | 3043 | &amdgpu_debugfs_gca_config_fops, |
f2cdaf20 | 3044 | &amdgpu_debugfs_sensors_fops, |
273d7aa1 | 3045 | &amdgpu_debugfs_wave_fops, |
adcec288 TSD |
3046 | }; |
3047 | ||
3048 | static const char *debugfs_regs_names[] = { | |
3049 | "amdgpu_regs", | |
3050 | "amdgpu_regs_didt", | |
3051 | "amdgpu_regs_pcie", | |
3052 | "amdgpu_regs_smc", | |
1e051413 | 3053 | "amdgpu_gca_config", |
f2cdaf20 | 3054 | "amdgpu_sensors", |
273d7aa1 | 3055 | "amdgpu_wave", |
adcec288 | 3056 | }; |
d38ceaf9 AD |
3057 | |
3058 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3059 | { | |
3060 | struct drm_minor *minor = adev->ddev->primary; | |
3061 | struct dentry *ent, *root = minor->debugfs_root; | |
adcec288 TSD |
3062 | unsigned i, j; |
3063 | ||
3064 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3065 | ent = debugfs_create_file(debugfs_regs_names[i], | |
3066 | S_IFREG | S_IRUGO, root, | |
3067 | adev, debugfs_regs[i]); | |
3068 | if (IS_ERR(ent)) { | |
3069 | for (j = 0; j < i; j++) { | |
3070 | debugfs_remove(adev->debugfs_regs[i]); | |
3071 | adev->debugfs_regs[i] = NULL; | |
3072 | } | |
3073 | return PTR_ERR(ent); | |
3074 | } | |
d38ceaf9 | 3075 | |
adcec288 TSD |
3076 | if (!i) |
3077 | i_size_write(ent->d_inode, adev->rmmio_size); | |
3078 | adev->debugfs_regs[i] = ent; | |
3079 | } | |
d38ceaf9 AD |
3080 | |
3081 | return 0; | |
3082 | } | |
3083 | ||
3084 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
3085 | { | |
adcec288 TSD |
3086 | unsigned i; |
3087 | ||
3088 | for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { | |
3089 | if (adev->debugfs_regs[i]) { | |
3090 | debugfs_remove(adev->debugfs_regs[i]); | |
3091 | adev->debugfs_regs[i] = NULL; | |
3092 | } | |
3093 | } | |
d38ceaf9 AD |
3094 | } |
3095 | ||
3096 | int amdgpu_debugfs_init(struct drm_minor *minor) | |
3097 | { | |
3098 | return 0; | |
3099 | } | |
3100 | ||
3101 | void amdgpu_debugfs_cleanup(struct drm_minor *minor) | |
3102 | { | |
3103 | } | |
7cebc728 AK |
3104 | #else |
3105 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
3106 | { | |
3107 | return 0; | |
3108 | } | |
3109 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { } | |
d38ceaf9 | 3110 | #endif |