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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
d38ceaf9 AD |
30 | #include <linux/console.h> |
31 | #include <linux/slab.h> | |
d38ceaf9 | 32 | #include <drm/drmP.h> |
4562236b | 33 | #include <drm/drm_atomic_helper.h> |
fcd70cd3 | 34 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
35 | #include <drm/amdgpu_drm.h> |
36 | #include <linux/vgaarb.h> | |
37 | #include <linux/vga_switcheroo.h> | |
38 | #include <linux/efi.h> | |
39 | #include "amdgpu.h" | |
f4b373f4 | 40 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
41 | #include "amdgpu_i2c.h" |
42 | #include "atom.h" | |
43 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 44 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 45 | #include "amd_pcie.h" |
33f34802 KW |
46 | #ifdef CONFIG_DRM_AMDGPU_SI |
47 | #include "si.h" | |
48 | #endif | |
a2e73f56 AD |
49 | #ifdef CONFIG_DRM_AMDGPU_CIK |
50 | #include "cik.h" | |
51 | #endif | |
aaa36a97 | 52 | #include "vi.h" |
460826e6 | 53 | #include "soc15.h" |
d38ceaf9 | 54 | #include "bif/bif_4_1_d.h" |
9accf2fd | 55 | #include <linux/pci.h> |
bec86378 | 56 | #include <linux/firmware.h> |
89041940 | 57 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 58 | |
ba997709 | 59 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 60 | #include "amdgpu_pm.h" |
d38ceaf9 | 61 | |
5183411b | 62 | #include "amdgpu_xgmi.h" |
c030f2e4 | 63 | #include "amdgpu_ras.h" |
5183411b | 64 | |
e2a75f88 | 65 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 66 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 67 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 68 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 69 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
e2a75f88 | 70 | |
2dc80b00 S |
71 | #define AMDGPU_RESUME_MS 2000 |
72 | ||
d38ceaf9 | 73 | static const char *amdgpu_asic_name[] = { |
da69c161 KW |
74 | "TAHITI", |
75 | "PITCAIRN", | |
76 | "VERDE", | |
77 | "OLAND", | |
78 | "HAINAN", | |
d38ceaf9 AD |
79 | "BONAIRE", |
80 | "KAVERI", | |
81 | "KABINI", | |
82 | "HAWAII", | |
83 | "MULLINS", | |
84 | "TOPAZ", | |
85 | "TONGA", | |
48299f95 | 86 | "FIJI", |
d38ceaf9 | 87 | "CARRIZO", |
139f4917 | 88 | "STONEY", |
2cc0c0b5 FC |
89 | "POLARIS10", |
90 | "POLARIS11", | |
c4642a47 | 91 | "POLARIS12", |
48ff108d | 92 | "VEGAM", |
d4196f01 | 93 | "VEGA10", |
8fab806a | 94 | "VEGA12", |
956fcddc | 95 | "VEGA20", |
2ca8a5d2 | 96 | "RAVEN", |
d38ceaf9 AD |
97 | "LAST", |
98 | }; | |
99 | ||
dcea6e65 KR |
100 | /** |
101 | * DOC: pcie_replay_count | |
102 | * | |
103 | * The amdgpu driver provides a sysfs API for reporting the total number | |
104 | * of PCIe replays (NAKs) | |
105 | * The file pcie_replay_count is used for this and returns the total | |
106 | * number of replays as a sum of the NAKs generated and NAKs received | |
107 | */ | |
108 | ||
109 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
110 | struct device_attribute *attr, char *buf) | |
111 | { | |
112 | struct drm_device *ddev = dev_get_drvdata(dev); | |
113 | struct amdgpu_device *adev = ddev->dev_private; | |
114 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); | |
115 | ||
116 | return snprintf(buf, PAGE_SIZE, "%llu\n", cnt); | |
117 | } | |
118 | ||
119 | static DEVICE_ATTR(pcie_replay_count, S_IRUGO, | |
120 | amdgpu_device_get_pcie_replay_count, NULL); | |
121 | ||
5494d864 AD |
122 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
123 | ||
e3ecdffa AD |
124 | /** |
125 | * amdgpu_device_is_px - Is the device is a dGPU with HG/PX power control | |
126 | * | |
127 | * @dev: drm_device pointer | |
128 | * | |
129 | * Returns true if the device is a dGPU with HG/PX power control, | |
130 | * otherwise return false. | |
131 | */ | |
d38ceaf9 AD |
132 | bool amdgpu_device_is_px(struct drm_device *dev) |
133 | { | |
134 | struct amdgpu_device *adev = dev->dev_private; | |
135 | ||
2f7d10b3 | 136 | if (adev->flags & AMD_IS_PX) |
d38ceaf9 AD |
137 | return true; |
138 | return false; | |
139 | } | |
140 | ||
141 | /* | |
142 | * MMIO register access helper functions. | |
143 | */ | |
e3ecdffa AD |
144 | /** |
145 | * amdgpu_mm_rreg - read a memory mapped IO register | |
146 | * | |
147 | * @adev: amdgpu_device pointer | |
148 | * @reg: dword aligned register offset | |
149 | * @acc_flags: access flags which require special behavior | |
150 | * | |
151 | * Returns the 32 bit value from the offset specified. | |
152 | */ | |
d38ceaf9 | 153 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, |
15d72fd7 | 154 | uint32_t acc_flags) |
d38ceaf9 | 155 | { |
f4b373f4 TSD |
156 | uint32_t ret; |
157 | ||
43ca8efa | 158 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 159 | return amdgpu_virt_kiq_rreg(adev, reg); |
bc992ba5 | 160 | |
15d72fd7 | 161 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
f4b373f4 | 162 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); |
d38ceaf9 AD |
163 | else { |
164 | unsigned long flags; | |
d38ceaf9 AD |
165 | |
166 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
167 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
168 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
169 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
d38ceaf9 | 170 | } |
f4b373f4 TSD |
171 | trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret); |
172 | return ret; | |
d38ceaf9 AD |
173 | } |
174 | ||
421a2a30 ML |
175 | /* |
176 | * MMIO register read with bytes helper functions | |
177 | * @offset:bytes offset from MMIO start | |
178 | * | |
179 | */ | |
180 | ||
e3ecdffa AD |
181 | /** |
182 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
183 | * | |
184 | * @adev: amdgpu_device pointer | |
185 | * @offset: byte aligned register offset | |
186 | * | |
187 | * Returns the 8 bit value from the offset specified. | |
188 | */ | |
421a2a30 ML |
189 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) { |
190 | if (offset < adev->rmmio_size) | |
191 | return (readb(adev->rmmio + offset)); | |
192 | BUG(); | |
193 | } | |
194 | ||
195 | /* | |
196 | * MMIO register write with bytes helper functions | |
197 | * @offset:bytes offset from MMIO start | |
198 | * @value: the value want to be written to the register | |
199 | * | |
200 | */ | |
e3ecdffa AD |
201 | /** |
202 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
203 | * | |
204 | * @adev: amdgpu_device pointer | |
205 | * @offset: byte aligned register offset | |
206 | * @value: 8 bit value to write | |
207 | * | |
208 | * Writes the value specified to the offset specified. | |
209 | */ | |
421a2a30 ML |
210 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) { |
211 | if (offset < adev->rmmio_size) | |
212 | writeb(value, adev->rmmio + offset); | |
213 | else | |
214 | BUG(); | |
215 | } | |
216 | ||
e3ecdffa AD |
217 | /** |
218 | * amdgpu_mm_wreg - write to a memory mapped IO register | |
219 | * | |
220 | * @adev: amdgpu_device pointer | |
221 | * @reg: dword aligned register offset | |
222 | * @v: 32 bit value to write to the register | |
223 | * @acc_flags: access flags which require special behavior | |
224 | * | |
225 | * Writes the value specified to the offset specified. | |
226 | */ | |
d38ceaf9 | 227 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
15d72fd7 | 228 | uint32_t acc_flags) |
d38ceaf9 | 229 | { |
f4b373f4 | 230 | trace_amdgpu_mm_wreg(adev->pdev->device, reg, v); |
4e99a44e | 231 | |
47ed4e1c KW |
232 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
233 | adev->last_mm_index = v; | |
234 | } | |
235 | ||
43ca8efa | 236 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)) |
bc992ba5 | 237 | return amdgpu_virt_kiq_wreg(adev, reg, v); |
bc992ba5 | 238 | |
15d72fd7 | 239 | if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX)) |
d38ceaf9 AD |
240 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); |
241 | else { | |
242 | unsigned long flags; | |
243 | ||
244 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
245 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
246 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
247 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
248 | } | |
47ed4e1c KW |
249 | |
250 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
251 | udelay(500); | |
252 | } | |
d38ceaf9 AD |
253 | } |
254 | ||
e3ecdffa AD |
255 | /** |
256 | * amdgpu_io_rreg - read an IO register | |
257 | * | |
258 | * @adev: amdgpu_device pointer | |
259 | * @reg: dword aligned register offset | |
260 | * | |
261 | * Returns the 32 bit value from the offset specified. | |
262 | */ | |
d38ceaf9 AD |
263 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) |
264 | { | |
265 | if ((reg * 4) < adev->rio_mem_size) | |
266 | return ioread32(adev->rio_mem + (reg * 4)); | |
267 | else { | |
268 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
269 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
270 | } | |
271 | } | |
272 | ||
e3ecdffa AD |
273 | /** |
274 | * amdgpu_io_wreg - write to an IO register | |
275 | * | |
276 | * @adev: amdgpu_device pointer | |
277 | * @reg: dword aligned register offset | |
278 | * @v: 32 bit value to write to the register | |
279 | * | |
280 | * Writes the value specified to the offset specified. | |
281 | */ | |
d38ceaf9 AD |
282 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) |
283 | { | |
47ed4e1c KW |
284 | if (adev->asic_type >= CHIP_VEGA10 && reg == 0) { |
285 | adev->last_mm_index = v; | |
286 | } | |
d38ceaf9 AD |
287 | |
288 | if ((reg * 4) < adev->rio_mem_size) | |
289 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
290 | else { | |
291 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
292 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
293 | } | |
47ed4e1c KW |
294 | |
295 | if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) { | |
296 | udelay(500); | |
297 | } | |
d38ceaf9 AD |
298 | } |
299 | ||
300 | /** | |
301 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
302 | * | |
303 | * @adev: amdgpu_device pointer | |
304 | * @index: doorbell index | |
305 | * | |
306 | * Returns the value in the doorbell aperture at the | |
307 | * requested doorbell index (CIK). | |
308 | */ | |
309 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
310 | { | |
311 | if (index < adev->doorbell.num_doorbells) { | |
312 | return readl(adev->doorbell.ptr + index); | |
313 | } else { | |
314 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
315 | return 0; | |
316 | } | |
317 | } | |
318 | ||
319 | /** | |
320 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
321 | * | |
322 | * @adev: amdgpu_device pointer | |
323 | * @index: doorbell index | |
324 | * @v: value to write | |
325 | * | |
326 | * Writes @v to the doorbell aperture at the | |
327 | * requested doorbell index (CIK). | |
328 | */ | |
329 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
330 | { | |
331 | if (index < adev->doorbell.num_doorbells) { | |
332 | writel(v, adev->doorbell.ptr + index); | |
333 | } else { | |
334 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
335 | } | |
336 | } | |
337 | ||
832be404 KW |
338 | /** |
339 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
340 | * | |
341 | * @adev: amdgpu_device pointer | |
342 | * @index: doorbell index | |
343 | * | |
344 | * Returns the value in the doorbell aperture at the | |
345 | * requested doorbell index (VEGA10+). | |
346 | */ | |
347 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
348 | { | |
349 | if (index < adev->doorbell.num_doorbells) { | |
350 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
351 | } else { | |
352 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
353 | return 0; | |
354 | } | |
355 | } | |
356 | ||
357 | /** | |
358 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
359 | * | |
360 | * @adev: amdgpu_device pointer | |
361 | * @index: doorbell index | |
362 | * @v: value to write | |
363 | * | |
364 | * Writes @v to the doorbell aperture at the | |
365 | * requested doorbell index (VEGA10+). | |
366 | */ | |
367 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
368 | { | |
369 | if (index < adev->doorbell.num_doorbells) { | |
370 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
371 | } else { | |
372 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
373 | } | |
374 | } | |
375 | ||
d38ceaf9 AD |
376 | /** |
377 | * amdgpu_invalid_rreg - dummy reg read function | |
378 | * | |
379 | * @adev: amdgpu device pointer | |
380 | * @reg: offset of register | |
381 | * | |
382 | * Dummy register read function. Used for register blocks | |
383 | * that certain asics don't have (all asics). | |
384 | * Returns the value in the register. | |
385 | */ | |
386 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
387 | { | |
388 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
389 | BUG(); | |
390 | return 0; | |
391 | } | |
392 | ||
393 | /** | |
394 | * amdgpu_invalid_wreg - dummy reg write function | |
395 | * | |
396 | * @adev: amdgpu device pointer | |
397 | * @reg: offset of register | |
398 | * @v: value to write to the register | |
399 | * | |
400 | * Dummy register read function. Used for register blocks | |
401 | * that certain asics don't have (all asics). | |
402 | */ | |
403 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
404 | { | |
405 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
406 | reg, v); | |
407 | BUG(); | |
408 | } | |
409 | ||
410 | /** | |
411 | * amdgpu_block_invalid_rreg - dummy reg read function | |
412 | * | |
413 | * @adev: amdgpu device pointer | |
414 | * @block: offset of instance | |
415 | * @reg: offset of register | |
416 | * | |
417 | * Dummy register read function. Used for register blocks | |
418 | * that certain asics don't have (all asics). | |
419 | * Returns the value in the register. | |
420 | */ | |
421 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
422 | uint32_t block, uint32_t reg) | |
423 | { | |
424 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
425 | reg, block); | |
426 | BUG(); | |
427 | return 0; | |
428 | } | |
429 | ||
430 | /** | |
431 | * amdgpu_block_invalid_wreg - dummy reg write function | |
432 | * | |
433 | * @adev: amdgpu device pointer | |
434 | * @block: offset of instance | |
435 | * @reg: offset of register | |
436 | * @v: value to write to the register | |
437 | * | |
438 | * Dummy register read function. Used for register blocks | |
439 | * that certain asics don't have (all asics). | |
440 | */ | |
441 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
442 | uint32_t block, | |
443 | uint32_t reg, uint32_t v) | |
444 | { | |
445 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
446 | reg, block, v); | |
447 | BUG(); | |
448 | } | |
449 | ||
e3ecdffa AD |
450 | /** |
451 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
452 | * | |
453 | * @adev: amdgpu device pointer | |
454 | * | |
455 | * Allocates a scratch page of VRAM for use by various things in the | |
456 | * driver. | |
457 | */ | |
06ec9070 | 458 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 459 | { |
a4a02777 CK |
460 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
461 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
462 | &adev->vram_scratch.robj, | |
463 | &adev->vram_scratch.gpu_addr, | |
464 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
465 | } |
466 | ||
e3ecdffa AD |
467 | /** |
468 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
469 | * | |
470 | * @adev: amdgpu device pointer | |
471 | * | |
472 | * Frees the VRAM scratch page. | |
473 | */ | |
06ec9070 | 474 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 475 | { |
078af1a3 | 476 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
477 | } |
478 | ||
479 | /** | |
9c3f2b54 | 480 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
481 | * |
482 | * @adev: amdgpu_device pointer | |
483 | * @registers: pointer to the register array | |
484 | * @array_size: size of the register array | |
485 | * | |
486 | * Programs an array or registers with and and or masks. | |
487 | * This is a helper for setting golden registers. | |
488 | */ | |
9c3f2b54 AD |
489 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
490 | const u32 *registers, | |
491 | const u32 array_size) | |
d38ceaf9 AD |
492 | { |
493 | u32 tmp, reg, and_mask, or_mask; | |
494 | int i; | |
495 | ||
496 | if (array_size % 3) | |
497 | return; | |
498 | ||
499 | for (i = 0; i < array_size; i +=3) { | |
500 | reg = registers[i + 0]; | |
501 | and_mask = registers[i + 1]; | |
502 | or_mask = registers[i + 2]; | |
503 | ||
504 | if (and_mask == 0xffffffff) { | |
505 | tmp = or_mask; | |
506 | } else { | |
507 | tmp = RREG32(reg); | |
508 | tmp &= ~and_mask; | |
509 | tmp |= or_mask; | |
510 | } | |
511 | WREG32(reg, tmp); | |
512 | } | |
513 | } | |
514 | ||
e3ecdffa AD |
515 | /** |
516 | * amdgpu_device_pci_config_reset - reset the GPU | |
517 | * | |
518 | * @adev: amdgpu_device pointer | |
519 | * | |
520 | * Resets the GPU using the pci config reset sequence. | |
521 | * Only applicable to asics prior to vega10. | |
522 | */ | |
8111c387 | 523 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
524 | { |
525 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
526 | } | |
527 | ||
528 | /* | |
529 | * GPU doorbell aperture helpers function. | |
530 | */ | |
531 | /** | |
06ec9070 | 532 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
533 | * |
534 | * @adev: amdgpu_device pointer | |
535 | * | |
536 | * Init doorbell driver information (CIK) | |
537 | * Returns 0 on success, error on failure. | |
538 | */ | |
06ec9070 | 539 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 540 | { |
6585661d | 541 | |
705e519e CK |
542 | /* No doorbell on SI hardware generation */ |
543 | if (adev->asic_type < CHIP_BONAIRE) { | |
544 | adev->doorbell.base = 0; | |
545 | adev->doorbell.size = 0; | |
546 | adev->doorbell.num_doorbells = 0; | |
547 | adev->doorbell.ptr = NULL; | |
548 | return 0; | |
549 | } | |
550 | ||
d6895ad3 CK |
551 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
552 | return -EINVAL; | |
553 | ||
22357775 AD |
554 | amdgpu_asic_init_doorbell_index(adev); |
555 | ||
d38ceaf9 AD |
556 | /* doorbell bar mapping */ |
557 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
558 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
559 | ||
edf600da | 560 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
9564f192 | 561 | adev->doorbell_index.max_assignment+1); |
d38ceaf9 AD |
562 | if (adev->doorbell.num_doorbells == 0) |
563 | return -EINVAL; | |
564 | ||
ec3db8a6 | 565 | /* For Vega, reserve and map two pages on doorbell BAR since SDMA |
88dc26e4 OZ |
566 | * paging queue doorbell use the second page. The |
567 | * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the | |
568 | * doorbells are in the first page. So with paging queue enabled, | |
569 | * the max num_doorbells should + 1 page (0x400 in dword) | |
ec3db8a6 PY |
570 | */ |
571 | if (adev->asic_type >= CHIP_VEGA10) | |
88dc26e4 | 572 | adev->doorbell.num_doorbells += 0x400; |
ec3db8a6 | 573 | |
8972e5d2 CK |
574 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
575 | adev->doorbell.num_doorbells * | |
576 | sizeof(u32)); | |
577 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 578 | return -ENOMEM; |
d38ceaf9 AD |
579 | |
580 | return 0; | |
581 | } | |
582 | ||
583 | /** | |
06ec9070 | 584 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
585 | * |
586 | * @adev: amdgpu_device pointer | |
587 | * | |
588 | * Tear down doorbell driver information (CIK) | |
589 | */ | |
06ec9070 | 590 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
591 | { |
592 | iounmap(adev->doorbell.ptr); | |
593 | adev->doorbell.ptr = NULL; | |
594 | } | |
595 | ||
22cb0164 | 596 | |
d38ceaf9 AD |
597 | |
598 | /* | |
06ec9070 | 599 | * amdgpu_device_wb_*() |
455a7bc2 | 600 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 601 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
602 | */ |
603 | ||
604 | /** | |
06ec9070 | 605 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
606 | * |
607 | * @adev: amdgpu_device pointer | |
608 | * | |
609 | * Disables Writeback and frees the Writeback memory (all asics). | |
610 | * Used at driver shutdown. | |
611 | */ | |
06ec9070 | 612 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
613 | { |
614 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
615 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
616 | &adev->wb.gpu_addr, | |
617 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
618 | adev->wb.wb_obj = NULL; |
619 | } | |
620 | } | |
621 | ||
622 | /** | |
06ec9070 | 623 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
624 | * |
625 | * @adev: amdgpu_device pointer | |
626 | * | |
455a7bc2 | 627 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
628 | * Used at driver startup. |
629 | * Returns 0 on success or an -error on failure. | |
630 | */ | |
06ec9070 | 631 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
632 | { |
633 | int r; | |
634 | ||
635 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
636 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
637 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
638 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
639 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
640 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
641 | if (r) { |
642 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
643 | return r; | |
644 | } | |
d38ceaf9 AD |
645 | |
646 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
647 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
648 | ||
649 | /* clear wb memory */ | |
73469585 | 650 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
651 | } |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
656 | /** | |
131b4b36 | 657 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
658 | * |
659 | * @adev: amdgpu_device pointer | |
660 | * @wb: wb index | |
661 | * | |
662 | * Allocate a wb slot for use by the driver (all asics). | |
663 | * Returns 0 on success or -EINVAL on failure. | |
664 | */ | |
131b4b36 | 665 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
666 | { |
667 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 668 | |
97407b63 | 669 | if (offset < adev->wb.num_wb) { |
7014285a | 670 | __set_bit(offset, adev->wb.used); |
63ae07ca | 671 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
672 | return 0; |
673 | } else { | |
674 | return -EINVAL; | |
675 | } | |
676 | } | |
677 | ||
d38ceaf9 | 678 | /** |
131b4b36 | 679 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
680 | * |
681 | * @adev: amdgpu_device pointer | |
682 | * @wb: wb index | |
683 | * | |
684 | * Free a wb slot allocated for use by the driver (all asics) | |
685 | */ | |
131b4b36 | 686 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 687 | { |
73469585 | 688 | wb >>= 3; |
d38ceaf9 | 689 | if (wb < adev->wb.num_wb) |
73469585 | 690 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
691 | } |
692 | ||
d6895ad3 CK |
693 | /** |
694 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
695 | * | |
696 | * @adev: amdgpu_device pointer | |
697 | * | |
698 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
699 | * to fail, but if any of the BARs is not accessible after the size we abort | |
700 | * driver loading by returning -ENODEV. | |
701 | */ | |
702 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
703 | { | |
770d13b1 | 704 | u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size); |
d6895ad3 | 705 | u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; |
31b8adab CK |
706 | struct pci_bus *root; |
707 | struct resource *res; | |
708 | unsigned i; | |
d6895ad3 CK |
709 | u16 cmd; |
710 | int r; | |
711 | ||
0c03b912 | 712 | /* Bypass for VF */ |
713 | if (amdgpu_sriov_vf(adev)) | |
714 | return 0; | |
715 | ||
31b8adab CK |
716 | /* Check if the root BUS has 64bit memory resources */ |
717 | root = adev->pdev->bus; | |
718 | while (root->parent) | |
719 | root = root->parent; | |
720 | ||
721 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 722 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
723 | res->start > 0x100000000ull) |
724 | break; | |
725 | } | |
726 | ||
727 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
728 | if (!res) | |
729 | return 0; | |
730 | ||
d6895ad3 CK |
731 | /* Disable memory decoding while we change the BAR addresses and size */ |
732 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
733 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
734 | cmd & ~PCI_COMMAND_MEMORY); | |
735 | ||
736 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 737 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
738 | if (adev->asic_type >= CHIP_BONAIRE) |
739 | pci_release_resource(adev->pdev, 2); | |
740 | ||
741 | pci_release_resource(adev->pdev, 0); | |
742 | ||
743 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
744 | if (r == -ENOSPC) | |
745 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
746 | else if (r && r != -ENOTSUPP) | |
747 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
748 | ||
749 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
750 | ||
751 | /* When the doorbell or fb BAR isn't available we have no chance of | |
752 | * using the device. | |
753 | */ | |
06ec9070 | 754 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
755 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
756 | return -ENODEV; | |
757 | ||
758 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
759 | ||
760 | return 0; | |
761 | } | |
a05502e5 | 762 | |
d38ceaf9 AD |
763 | /* |
764 | * GPU helpers function. | |
765 | */ | |
766 | /** | |
39c640c0 | 767 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
768 | * |
769 | * @adev: amdgpu_device pointer | |
770 | * | |
c836fec5 JQ |
771 | * Check if the asic has been initialized (all asics) at driver startup |
772 | * or post is needed if hw reset is performed. | |
773 | * Returns true if need or false if not. | |
d38ceaf9 | 774 | */ |
39c640c0 | 775 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
776 | { |
777 | uint32_t reg; | |
778 | ||
bec86378 ML |
779 | if (amdgpu_sriov_vf(adev)) |
780 | return false; | |
781 | ||
782 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
783 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
784 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
785 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
786 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
787 | */ |
788 | if (adev->asic_type == CHIP_FIJI) { | |
789 | int err; | |
790 | uint32_t fw_ver; | |
791 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
792 | /* force vPost if error occured */ | |
793 | if (err) | |
794 | return true; | |
795 | ||
796 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
797 | if (fw_ver < 0x00160e00) |
798 | return true; | |
bec86378 | 799 | } |
bec86378 | 800 | } |
91fe77eb | 801 | |
802 | if (adev->has_hw_reset) { | |
803 | adev->has_hw_reset = false; | |
804 | return true; | |
805 | } | |
806 | ||
807 | /* bios scratch used on CIK+ */ | |
808 | if (adev->asic_type >= CHIP_BONAIRE) | |
809 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
810 | ||
811 | /* check MEM_SIZE for older asics */ | |
812 | reg = amdgpu_asic_get_config_memsize(adev); | |
813 | ||
814 | if ((reg != 0) && (reg != 0xffffffff)) | |
815 | return false; | |
816 | ||
817 | return true; | |
bec86378 ML |
818 | } |
819 | ||
d38ceaf9 AD |
820 | /* if we get transitioned to only one device, take VGA back */ |
821 | /** | |
06ec9070 | 822 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 AD |
823 | * |
824 | * @cookie: amdgpu_device pointer | |
825 | * @state: enable/disable vga decode | |
826 | * | |
827 | * Enable/disable vga decode (all asics). | |
828 | * Returns VGA resource flags. | |
829 | */ | |
06ec9070 | 830 | static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) |
d38ceaf9 AD |
831 | { |
832 | struct amdgpu_device *adev = cookie; | |
833 | amdgpu_asic_set_vga_state(adev, state); | |
834 | if (state) | |
835 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
836 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
837 | else | |
838 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
839 | } | |
840 | ||
e3ecdffa AD |
841 | /** |
842 | * amdgpu_device_check_block_size - validate the vm block size | |
843 | * | |
844 | * @adev: amdgpu_device pointer | |
845 | * | |
846 | * Validates the vm block size specified via module parameter. | |
847 | * The vm block size defines number of bits in page table versus page directory, | |
848 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
849 | * page table and the remaining bits are in the page directory. | |
850 | */ | |
06ec9070 | 851 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
852 | { |
853 | /* defines number of bits in page table versus page directory, | |
854 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
855 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
856 | if (amdgpu_vm_block_size == -1) |
857 | return; | |
a1adf8be | 858 | |
bab4fee7 | 859 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
860 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
861 | amdgpu_vm_block_size); | |
97489129 | 862 | amdgpu_vm_block_size = -1; |
a1adf8be | 863 | } |
a1adf8be CZ |
864 | } |
865 | ||
e3ecdffa AD |
866 | /** |
867 | * amdgpu_device_check_vm_size - validate the vm size | |
868 | * | |
869 | * @adev: amdgpu_device pointer | |
870 | * | |
871 | * Validates the vm size in GB specified via module parameter. | |
872 | * The VM size is the size of the GPU virtual memory space in GB. | |
873 | */ | |
06ec9070 | 874 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 875 | { |
64dab074 AD |
876 | /* no need to check the default value */ |
877 | if (amdgpu_vm_size == -1) | |
878 | return; | |
879 | ||
83ca145d ZJ |
880 | if (amdgpu_vm_size < 1) { |
881 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
882 | amdgpu_vm_size); | |
f3368128 | 883 | amdgpu_vm_size = -1; |
83ca145d | 884 | } |
83ca145d ZJ |
885 | } |
886 | ||
7951e376 RZ |
887 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
888 | { | |
889 | struct sysinfo si; | |
890 | bool is_os_64 = (sizeof(void *) == 8) ? true : false; | |
891 | uint64_t total_memory; | |
892 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
893 | uint64_t dram_size_three_GB = 0xB8000000; | |
894 | ||
895 | if (amdgpu_smu_memory_pool_size == 0) | |
896 | return; | |
897 | ||
898 | if (!is_os_64) { | |
899 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
900 | goto def_value; | |
901 | } | |
902 | si_meminfo(&si); | |
903 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
904 | ||
905 | if ((amdgpu_smu_memory_pool_size == 1) || | |
906 | (amdgpu_smu_memory_pool_size == 2)) { | |
907 | if (total_memory < dram_size_three_GB) | |
908 | goto def_value1; | |
909 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
910 | (amdgpu_smu_memory_pool_size == 8)) { | |
911 | if (total_memory < dram_size_seven_GB) | |
912 | goto def_value1; | |
913 | } else { | |
914 | DRM_WARN("Smu memory pool size not supported\n"); | |
915 | goto def_value; | |
916 | } | |
917 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
918 | ||
919 | return; | |
920 | ||
921 | def_value1: | |
922 | DRM_WARN("No enough system memory\n"); | |
923 | def_value: | |
924 | adev->pm.smu_prv_buffer_size = 0; | |
925 | } | |
926 | ||
d38ceaf9 | 927 | /** |
06ec9070 | 928 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
929 | * |
930 | * @adev: amdgpu_device pointer | |
931 | * | |
932 | * Validates certain module parameters and updates | |
933 | * the associated values used by the driver (all asics). | |
934 | */ | |
912dfc84 | 935 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 936 | { |
912dfc84 EQ |
937 | int ret = 0; |
938 | ||
5b011235 CZ |
939 | if (amdgpu_sched_jobs < 4) { |
940 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
941 | amdgpu_sched_jobs); | |
942 | amdgpu_sched_jobs = 4; | |
76117507 | 943 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
944 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
945 | amdgpu_sched_jobs); | |
946 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
947 | } | |
d38ceaf9 | 948 | |
83e74db6 | 949 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
950 | /* gart size must be greater or equal to 32M */ |
951 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
952 | amdgpu_gart_size); | |
83e74db6 | 953 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
954 | } |
955 | ||
36d38372 | 956 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 957 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
958 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
959 | amdgpu_gtt_size); | |
960 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
961 | } |
962 | ||
d07f14be RH |
963 | /* valid range is between 4 and 9 inclusive */ |
964 | if (amdgpu_vm_fragment_size != -1 && | |
965 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
966 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
967 | amdgpu_vm_fragment_size = -1; | |
968 | } | |
969 | ||
7951e376 RZ |
970 | amdgpu_device_check_smu_prv_buffer_size(adev); |
971 | ||
06ec9070 | 972 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 973 | |
06ec9070 | 974 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 975 | |
912dfc84 EQ |
976 | ret = amdgpu_device_get_job_timeout_settings(adev); |
977 | if (ret) { | |
978 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
979 | return ret; | |
8854695a | 980 | } |
19aede77 AD |
981 | |
982 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); | |
912dfc84 EQ |
983 | |
984 | return ret; | |
d38ceaf9 AD |
985 | } |
986 | ||
987 | /** | |
988 | * amdgpu_switcheroo_set_state - set switcheroo state | |
989 | * | |
990 | * @pdev: pci dev pointer | |
1694467b | 991 | * @state: vga_switcheroo state |
d38ceaf9 AD |
992 | * |
993 | * Callback for the switcheroo driver. Suspends or resumes the | |
994 | * the asics before or after it is powered up using ACPI methods. | |
995 | */ | |
996 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
997 | { | |
998 | struct drm_device *dev = pci_get_drvdata(pdev); | |
999 | ||
1000 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1001 | return; | |
1002 | ||
1003 | if (state == VGA_SWITCHEROO_ON) { | |
7ca85295 | 1004 | pr_info("amdgpu: switched on\n"); |
d38ceaf9 AD |
1005 | /* don't suspend or resume card normally */ |
1006 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1007 | ||
810ddc3a | 1008 | amdgpu_device_resume(dev, true, true); |
d38ceaf9 | 1009 | |
d38ceaf9 AD |
1010 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
1011 | drm_kms_helper_poll_enable(dev); | |
1012 | } else { | |
7ca85295 | 1013 | pr_info("amdgpu: switched off\n"); |
d38ceaf9 AD |
1014 | drm_kms_helper_poll_disable(dev); |
1015 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
810ddc3a | 1016 | amdgpu_device_suspend(dev, true, true); |
d38ceaf9 AD |
1017 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1018 | } | |
1019 | } | |
1020 | ||
1021 | /** | |
1022 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1023 | * | |
1024 | * @pdev: pci dev pointer | |
1025 | * | |
1026 | * Callback for the switcheroo driver. Check of the switcheroo | |
1027 | * state can be changed. | |
1028 | * Returns true if the state can be changed, false if not. | |
1029 | */ | |
1030 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1031 | { | |
1032 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1033 | ||
1034 | /* | |
1035 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1036 | * locking inversion with the driver load path. And the access here is | |
1037 | * completely racy anyway. So don't bother with locking for now. | |
1038 | */ | |
1039 | return dev->open_count == 0; | |
1040 | } | |
1041 | ||
1042 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1043 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1044 | .reprobe = NULL, | |
1045 | .can_switch = amdgpu_switcheroo_can_switch, | |
1046 | }; | |
1047 | ||
e3ecdffa AD |
1048 | /** |
1049 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1050 | * | |
87e3f136 | 1051 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1052 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1053 | * @state: clockgating state (gate or ungate) | |
1054 | * | |
1055 | * Sets the requested clockgating state for all instances of | |
1056 | * the hardware IP specified. | |
1057 | * Returns the error code from the last instance. | |
1058 | */ | |
43fa561f | 1059 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1060 | enum amd_ip_block_type block_type, |
1061 | enum amd_clockgating_state state) | |
d38ceaf9 | 1062 | { |
43fa561f | 1063 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1064 | int i, r = 0; |
1065 | ||
1066 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1067 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1068 | continue; |
c722865a RZ |
1069 | if (adev->ip_blocks[i].version->type != block_type) |
1070 | continue; | |
1071 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1072 | continue; | |
1073 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1074 | (void *)adev, state); | |
1075 | if (r) | |
1076 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1077 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1078 | } |
1079 | return r; | |
1080 | } | |
1081 | ||
e3ecdffa AD |
1082 | /** |
1083 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1084 | * | |
87e3f136 | 1085 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1086 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1087 | * @state: powergating state (gate or ungate) | |
1088 | * | |
1089 | * Sets the requested powergating state for all instances of | |
1090 | * the hardware IP specified. | |
1091 | * Returns the error code from the last instance. | |
1092 | */ | |
43fa561f | 1093 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1094 | enum amd_ip_block_type block_type, |
1095 | enum amd_powergating_state state) | |
d38ceaf9 | 1096 | { |
43fa561f | 1097 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1098 | int i, r = 0; |
1099 | ||
1100 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1101 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1102 | continue; |
c722865a RZ |
1103 | if (adev->ip_blocks[i].version->type != block_type) |
1104 | continue; | |
1105 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1106 | continue; | |
1107 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1108 | (void *)adev, state); | |
1109 | if (r) | |
1110 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1111 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1112 | } |
1113 | return r; | |
1114 | } | |
1115 | ||
e3ecdffa AD |
1116 | /** |
1117 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1118 | * | |
1119 | * @adev: amdgpu_device pointer | |
1120 | * @flags: clockgating feature flags | |
1121 | * | |
1122 | * Walks the list of IPs on the device and updates the clockgating | |
1123 | * flags for each IP. | |
1124 | * Updates @flags with the feature flags for each hardware IP where | |
1125 | * clockgating is enabled. | |
1126 | */ | |
2990a1fc AD |
1127 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1128 | u32 *flags) | |
6cb2d4e4 HR |
1129 | { |
1130 | int i; | |
1131 | ||
1132 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1133 | if (!adev->ip_blocks[i].status.valid) | |
1134 | continue; | |
1135 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1136 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1137 | } | |
1138 | } | |
1139 | ||
e3ecdffa AD |
1140 | /** |
1141 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1142 | * | |
1143 | * @adev: amdgpu_device pointer | |
1144 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1145 | * | |
1146 | * Waits for the request hardware IP to be idle. | |
1147 | * Returns 0 for success or a negative error code on failure. | |
1148 | */ | |
2990a1fc AD |
1149 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1150 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1151 | { |
1152 | int i, r; | |
1153 | ||
1154 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1155 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1156 | continue; |
a1255107 AD |
1157 | if (adev->ip_blocks[i].version->type == block_type) { |
1158 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1159 | if (r) |
1160 | return r; | |
1161 | break; | |
1162 | } | |
1163 | } | |
1164 | return 0; | |
1165 | ||
1166 | } | |
1167 | ||
e3ecdffa AD |
1168 | /** |
1169 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1170 | * | |
1171 | * @adev: amdgpu_device pointer | |
1172 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1173 | * | |
1174 | * Check if the hardware IP is idle or not. | |
1175 | * Returns true if it the IP is idle, false if not. | |
1176 | */ | |
2990a1fc AD |
1177 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1178 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1179 | { |
1180 | int i; | |
1181 | ||
1182 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1183 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1184 | continue; |
a1255107 AD |
1185 | if (adev->ip_blocks[i].version->type == block_type) |
1186 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1187 | } |
1188 | return true; | |
1189 | ||
1190 | } | |
1191 | ||
e3ecdffa AD |
1192 | /** |
1193 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1194 | * | |
1195 | * @adev: amdgpu_device pointer | |
87e3f136 | 1196 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1197 | * |
1198 | * Returns a pointer to the hardware IP block structure | |
1199 | * if it exists for the asic, otherwise NULL. | |
1200 | */ | |
2990a1fc AD |
1201 | struct amdgpu_ip_block * |
1202 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1203 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1204 | { |
1205 | int i; | |
1206 | ||
1207 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1208 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1209 | return &adev->ip_blocks[i]; |
1210 | ||
1211 | return NULL; | |
1212 | } | |
1213 | ||
1214 | /** | |
2990a1fc | 1215 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1216 | * |
1217 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1218 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1219 | * @major: major version |
1220 | * @minor: minor version | |
1221 | * | |
1222 | * return 0 if equal or greater | |
1223 | * return 1 if smaller or the ip_block doesn't exist | |
1224 | */ | |
2990a1fc AD |
1225 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1226 | enum amd_ip_block_type type, | |
1227 | u32 major, u32 minor) | |
d38ceaf9 | 1228 | { |
2990a1fc | 1229 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1230 | |
a1255107 AD |
1231 | if (ip_block && ((ip_block->version->major > major) || |
1232 | ((ip_block->version->major == major) && | |
1233 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1234 | return 0; |
1235 | ||
1236 | return 1; | |
1237 | } | |
1238 | ||
a1255107 | 1239 | /** |
2990a1fc | 1240 | * amdgpu_device_ip_block_add |
a1255107 AD |
1241 | * |
1242 | * @adev: amdgpu_device pointer | |
1243 | * @ip_block_version: pointer to the IP to add | |
1244 | * | |
1245 | * Adds the IP block driver information to the collection of IPs | |
1246 | * on the asic. | |
1247 | */ | |
2990a1fc AD |
1248 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1249 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1250 | { |
1251 | if (!ip_block_version) | |
1252 | return -EINVAL; | |
1253 | ||
e966a725 | 1254 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1255 | ip_block_version->funcs->name); |
1256 | ||
a1255107 AD |
1257 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1258 | ||
1259 | return 0; | |
1260 | } | |
1261 | ||
e3ecdffa AD |
1262 | /** |
1263 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1264 | * | |
1265 | * @adev: amdgpu_device pointer | |
1266 | * | |
1267 | * Enabled the virtual display feature if the user has enabled it via | |
1268 | * the module parameter virtual_display. This feature provides a virtual | |
1269 | * display hardware on headless boards or in virtualized environments. | |
1270 | * This function parses and validates the configuration string specified by | |
1271 | * the user and configues the virtual display configuration (number of | |
1272 | * virtual connectors, crtcs, etc.) specified. | |
1273 | */ | |
483ef985 | 1274 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1275 | { |
1276 | adev->enable_virtual_display = false; | |
1277 | ||
1278 | if (amdgpu_virtual_display) { | |
1279 | struct drm_device *ddev = adev->ddev; | |
1280 | const char *pci_address_name = pci_name(ddev->pdev); | |
0f66356d | 1281 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1282 | |
1283 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1284 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1285 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1286 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1287 | if (!strcmp("all", pciaddname) |
1288 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1289 | long num_crtc; |
1290 | int res = -1; | |
1291 | ||
9accf2fd | 1292 | adev->enable_virtual_display = true; |
0f66356d ED |
1293 | |
1294 | if (pciaddname_tmp) | |
1295 | res = kstrtol(pciaddname_tmp, 10, | |
1296 | &num_crtc); | |
1297 | ||
1298 | if (!res) { | |
1299 | if (num_crtc < 1) | |
1300 | num_crtc = 1; | |
1301 | if (num_crtc > 6) | |
1302 | num_crtc = 6; | |
1303 | adev->mode_info.num_crtc = num_crtc; | |
1304 | } else { | |
1305 | adev->mode_info.num_crtc = 1; | |
1306 | } | |
9accf2fd ED |
1307 | break; |
1308 | } | |
1309 | } | |
1310 | ||
0f66356d ED |
1311 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1312 | amdgpu_virtual_display, pci_address_name, | |
1313 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1314 | |
1315 | kfree(pciaddstr); | |
1316 | } | |
1317 | } | |
1318 | ||
e3ecdffa AD |
1319 | /** |
1320 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1321 | * | |
1322 | * @adev: amdgpu_device pointer | |
1323 | * | |
1324 | * Parses the asic configuration parameters specified in the gpu info | |
1325 | * firmware and makes them availale to the driver for use in configuring | |
1326 | * the asic. | |
1327 | * Returns 0 on success, -EINVAL on failure. | |
1328 | */ | |
e2a75f88 AD |
1329 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1330 | { | |
e2a75f88 AD |
1331 | const char *chip_name; |
1332 | char fw_name[30]; | |
1333 | int err; | |
1334 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1335 | ||
ab4fe3e1 HR |
1336 | adev->firmware.gpu_info_fw = NULL; |
1337 | ||
e2a75f88 AD |
1338 | switch (adev->asic_type) { |
1339 | case CHIP_TOPAZ: | |
1340 | case CHIP_TONGA: | |
1341 | case CHIP_FIJI: | |
e2a75f88 | 1342 | case CHIP_POLARIS10: |
cc07f18d | 1343 | case CHIP_POLARIS11: |
e2a75f88 | 1344 | case CHIP_POLARIS12: |
cc07f18d | 1345 | case CHIP_VEGAM: |
e2a75f88 AD |
1346 | case CHIP_CARRIZO: |
1347 | case CHIP_STONEY: | |
1348 | #ifdef CONFIG_DRM_AMDGPU_SI | |
1349 | case CHIP_VERDE: | |
1350 | case CHIP_TAHITI: | |
1351 | case CHIP_PITCAIRN: | |
1352 | case CHIP_OLAND: | |
1353 | case CHIP_HAINAN: | |
1354 | #endif | |
1355 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1356 | case CHIP_BONAIRE: | |
1357 | case CHIP_HAWAII: | |
1358 | case CHIP_KAVERI: | |
1359 | case CHIP_KABINI: | |
1360 | case CHIP_MULLINS: | |
1361 | #endif | |
27c0bc71 | 1362 | case CHIP_VEGA20: |
e2a75f88 AD |
1363 | default: |
1364 | return 0; | |
1365 | case CHIP_VEGA10: | |
1366 | chip_name = "vega10"; | |
1367 | break; | |
3f76dced AD |
1368 | case CHIP_VEGA12: |
1369 | chip_name = "vega12"; | |
1370 | break; | |
2d2e5e7e | 1371 | case CHIP_RAVEN: |
54c4d17e FX |
1372 | if (adev->rev_id >= 8) |
1373 | chip_name = "raven2"; | |
741deade AD |
1374 | else if (adev->pdev->device == 0x15d8) |
1375 | chip_name = "picasso"; | |
54c4d17e FX |
1376 | else |
1377 | chip_name = "raven"; | |
2d2e5e7e | 1378 | break; |
e2a75f88 AD |
1379 | } |
1380 | ||
1381 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1382 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1383 | if (err) { |
1384 | dev_err(adev->dev, | |
1385 | "Failed to load gpu_info firmware \"%s\"\n", | |
1386 | fw_name); | |
1387 | goto out; | |
1388 | } | |
ab4fe3e1 | 1389 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1390 | if (err) { |
1391 | dev_err(adev->dev, | |
1392 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1393 | fw_name); | |
1394 | goto out; | |
1395 | } | |
1396 | ||
ab4fe3e1 | 1397 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1398 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1399 | ||
1400 | switch (hdr->version_major) { | |
1401 | case 1: | |
1402 | { | |
1403 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 1404 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
1405 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
1406 | ||
b5ab16bf AD |
1407 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
1408 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
1409 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
1410 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 1411 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
1412 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
1413 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
1414 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
1415 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
1416 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 1417 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
1418 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
1419 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
1420 | adev->gfx.cu_info.max_waves_per_simd = |
1421 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
1422 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
1423 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
1424 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
e2a75f88 AD |
1425 | break; |
1426 | } | |
1427 | default: | |
1428 | dev_err(adev->dev, | |
1429 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
1430 | err = -EINVAL; | |
1431 | goto out; | |
1432 | } | |
1433 | out: | |
e2a75f88 AD |
1434 | return err; |
1435 | } | |
1436 | ||
e3ecdffa AD |
1437 | /** |
1438 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
1439 | * | |
1440 | * @adev: amdgpu_device pointer | |
1441 | * | |
1442 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
1443 | * up each asic are discovered each IP's early_init callback is run. This | |
1444 | * is the first stage in initializing the asic. | |
1445 | * Returns 0 on success, negative error code on failure. | |
1446 | */ | |
06ec9070 | 1447 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 1448 | { |
aaa36a97 | 1449 | int i, r; |
d38ceaf9 | 1450 | |
483ef985 | 1451 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 1452 | |
d38ceaf9 | 1453 | switch (adev->asic_type) { |
aaa36a97 AD |
1454 | case CHIP_TOPAZ: |
1455 | case CHIP_TONGA: | |
48299f95 | 1456 | case CHIP_FIJI: |
2cc0c0b5 | 1457 | case CHIP_POLARIS10: |
32cc7e53 | 1458 | case CHIP_POLARIS11: |
c4642a47 | 1459 | case CHIP_POLARIS12: |
32cc7e53 | 1460 | case CHIP_VEGAM: |
aaa36a97 | 1461 | case CHIP_CARRIZO: |
39bb0c92 SL |
1462 | case CHIP_STONEY: |
1463 | if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) | |
aaa36a97 AD |
1464 | adev->family = AMDGPU_FAMILY_CZ; |
1465 | else | |
1466 | adev->family = AMDGPU_FAMILY_VI; | |
1467 | ||
1468 | r = vi_set_ip_blocks(adev); | |
1469 | if (r) | |
1470 | return r; | |
1471 | break; | |
33f34802 KW |
1472 | #ifdef CONFIG_DRM_AMDGPU_SI |
1473 | case CHIP_VERDE: | |
1474 | case CHIP_TAHITI: | |
1475 | case CHIP_PITCAIRN: | |
1476 | case CHIP_OLAND: | |
1477 | case CHIP_HAINAN: | |
295d0daf | 1478 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
1479 | r = si_set_ip_blocks(adev); |
1480 | if (r) | |
1481 | return r; | |
1482 | break; | |
1483 | #endif | |
a2e73f56 AD |
1484 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1485 | case CHIP_BONAIRE: | |
1486 | case CHIP_HAWAII: | |
1487 | case CHIP_KAVERI: | |
1488 | case CHIP_KABINI: | |
1489 | case CHIP_MULLINS: | |
1490 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1491 | adev->family = AMDGPU_FAMILY_CI; | |
1492 | else | |
1493 | adev->family = AMDGPU_FAMILY_KV; | |
1494 | ||
1495 | r = cik_set_ip_blocks(adev); | |
1496 | if (r) | |
1497 | return r; | |
1498 | break; | |
1499 | #endif | |
e48a3cd9 AD |
1500 | case CHIP_VEGA10: |
1501 | case CHIP_VEGA12: | |
e4bd8170 | 1502 | case CHIP_VEGA20: |
e48a3cd9 | 1503 | case CHIP_RAVEN: |
741deade | 1504 | if (adev->asic_type == CHIP_RAVEN) |
2ca8a5d2 CZ |
1505 | adev->family = AMDGPU_FAMILY_RV; |
1506 | else | |
1507 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
1508 | |
1509 | r = soc15_set_ip_blocks(adev); | |
1510 | if (r) | |
1511 | return r; | |
1512 | break; | |
d38ceaf9 AD |
1513 | default: |
1514 | /* FIXME: not supported yet */ | |
1515 | return -EINVAL; | |
1516 | } | |
1517 | ||
e2a75f88 AD |
1518 | r = amdgpu_device_parse_gpu_info_fw(adev); |
1519 | if (r) | |
1520 | return r; | |
1521 | ||
1884734a | 1522 | amdgpu_amdkfd_device_probe(adev); |
1523 | ||
3149d9da XY |
1524 | if (amdgpu_sriov_vf(adev)) { |
1525 | r = amdgpu_virt_request_full_gpu(adev, true); | |
1526 | if (r) | |
5ffa61c1 | 1527 | return -EAGAIN; |
78d48112 TH |
1528 | |
1529 | /* query the reg access mode at the very beginning */ | |
1530 | amdgpu_virt_init_reg_access_mode(adev); | |
3149d9da XY |
1531 | } |
1532 | ||
3b94fb10 | 1533 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
00544006 HR |
1534 | if (amdgpu_sriov_vf(adev)) |
1535 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; | |
00f54b97 | 1536 | |
d38ceaf9 AD |
1537 | for (i = 0; i < adev->num_ip_blocks; i++) { |
1538 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
1539 | DRM_ERROR("disabled ip block: %d <%s>\n", |
1540 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 1541 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 1542 | } else { |
a1255107 AD |
1543 | if (adev->ip_blocks[i].version->funcs->early_init) { |
1544 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 1545 | if (r == -ENOENT) { |
a1255107 | 1546 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 1547 | } else if (r) { |
a1255107 AD |
1548 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
1549 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 1550 | return r; |
2c1a2784 | 1551 | } else { |
a1255107 | 1552 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 1553 | } |
974e6b64 | 1554 | } else { |
a1255107 | 1555 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 1556 | } |
d38ceaf9 | 1557 | } |
21a249ca AD |
1558 | /* get the vbios after the asic_funcs are set up */ |
1559 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
1560 | /* Read BIOS */ | |
1561 | if (!amdgpu_get_bios(adev)) | |
1562 | return -EINVAL; | |
1563 | ||
1564 | r = amdgpu_atombios_init(adev); | |
1565 | if (r) { | |
1566 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
1567 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
1568 | return r; | |
1569 | } | |
1570 | } | |
d38ceaf9 AD |
1571 | } |
1572 | ||
395d1fb9 NH |
1573 | adev->cg_flags &= amdgpu_cg_mask; |
1574 | adev->pg_flags &= amdgpu_pg_mask; | |
1575 | ||
d38ceaf9 AD |
1576 | return 0; |
1577 | } | |
1578 | ||
0a4f2520 RZ |
1579 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
1580 | { | |
1581 | int i, r; | |
1582 | ||
1583 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1584 | if (!adev->ip_blocks[i].status.sw) | |
1585 | continue; | |
1586 | if (adev->ip_blocks[i].status.hw) | |
1587 | continue; | |
1588 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 1589 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
1590 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
1591 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1592 | if (r) { | |
1593 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1594 | adev->ip_blocks[i].version->funcs->name, r); | |
1595 | return r; | |
1596 | } | |
1597 | adev->ip_blocks[i].status.hw = true; | |
1598 | } | |
1599 | } | |
1600 | ||
1601 | return 0; | |
1602 | } | |
1603 | ||
1604 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
1605 | { | |
1606 | int i, r; | |
1607 | ||
1608 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1609 | if (!adev->ip_blocks[i].status.sw) | |
1610 | continue; | |
1611 | if (adev->ip_blocks[i].status.hw) | |
1612 | continue; | |
1613 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1614 | if (r) { | |
1615 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1616 | adev->ip_blocks[i].version->funcs->name, r); | |
1617 | return r; | |
1618 | } | |
1619 | adev->ip_blocks[i].status.hw = true; | |
1620 | } | |
1621 | ||
1622 | return 0; | |
1623 | } | |
1624 | ||
7a3e0bb2 RZ |
1625 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
1626 | { | |
1627 | int r = 0; | |
1628 | int i; | |
80f41f84 | 1629 | uint32_t smu_version; |
7a3e0bb2 RZ |
1630 | |
1631 | if (adev->asic_type >= CHIP_VEGA10) { | |
1632 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1633 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
1634 | if (adev->in_gpu_reset || adev->in_suspend) { | |
1635 | if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) | |
1636 | break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */ | |
1637 | r = adev->ip_blocks[i].version->funcs->resume(adev); | |
1638 | if (r) { | |
1639 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
1640 | adev->ip_blocks[i].version->funcs->name, r); | |
1641 | return r; | |
1642 | } | |
1643 | } else { | |
1644 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
1645 | if (r) { | |
1646 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
1647 | adev->ip_blocks[i].version->funcs->name, r); | |
1648 | return r; | |
1649 | } | |
1650 | } | |
1651 | adev->ip_blocks[i].status.hw = true; | |
1652 | } | |
1653 | } | |
1654 | } | |
80f41f84 | 1655 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); |
7a3e0bb2 | 1656 | |
80f41f84 | 1657 | return r; |
7a3e0bb2 RZ |
1658 | } |
1659 | ||
e3ecdffa AD |
1660 | /** |
1661 | * amdgpu_device_ip_init - run init for hardware IPs | |
1662 | * | |
1663 | * @adev: amdgpu_device pointer | |
1664 | * | |
1665 | * Main initialization pass for hardware IPs. The list of all the hardware | |
1666 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
1667 | * are run. sw_init initializes the software state associated with each IP | |
1668 | * and hw_init initializes the hardware associated with each IP. | |
1669 | * Returns 0 on success, negative error code on failure. | |
1670 | */ | |
06ec9070 | 1671 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1672 | { |
1673 | int i, r; | |
1674 | ||
c030f2e4 | 1675 | r = amdgpu_ras_init(adev); |
1676 | if (r) | |
1677 | return r; | |
1678 | ||
d38ceaf9 | 1679 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 1680 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 1681 | continue; |
a1255107 | 1682 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 1683 | if (r) { |
a1255107 AD |
1684 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
1685 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 1686 | goto init_failed; |
2c1a2784 | 1687 | } |
a1255107 | 1688 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 1689 | |
d38ceaf9 | 1690 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 1691 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 1692 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
1693 | if (r) { |
1694 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
72d3f592 | 1695 | goto init_failed; |
2c1a2784 | 1696 | } |
a1255107 | 1697 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
1698 | if (r) { |
1699 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 1700 | goto init_failed; |
2c1a2784 | 1701 | } |
06ec9070 | 1702 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 1703 | if (r) { |
06ec9070 | 1704 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 1705 | goto init_failed; |
2c1a2784 | 1706 | } |
a1255107 | 1707 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
1708 | |
1709 | /* right after GMC hw init, we create CSA */ | |
1710 | if (amdgpu_sriov_vf(adev)) { | |
1e256e27 RZ |
1711 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
1712 | AMDGPU_GEM_DOMAIN_VRAM, | |
1713 | AMDGPU_CSA_SIZE); | |
2493664f ML |
1714 | if (r) { |
1715 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 1716 | goto init_failed; |
2493664f ML |
1717 | } |
1718 | } | |
d38ceaf9 AD |
1719 | } |
1720 | } | |
1721 | ||
533aed27 AG |
1722 | r = amdgpu_ib_pool_init(adev); |
1723 | if (r) { | |
1724 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
1725 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
1726 | goto init_failed; | |
1727 | } | |
1728 | ||
c8963ea4 RZ |
1729 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
1730 | if (r) | |
72d3f592 | 1731 | goto init_failed; |
0a4f2520 RZ |
1732 | |
1733 | r = amdgpu_device_ip_hw_init_phase1(adev); | |
1734 | if (r) | |
72d3f592 | 1735 | goto init_failed; |
0a4f2520 | 1736 | |
7a3e0bb2 RZ |
1737 | r = amdgpu_device_fw_loading(adev); |
1738 | if (r) | |
72d3f592 | 1739 | goto init_failed; |
7a3e0bb2 | 1740 | |
0a4f2520 RZ |
1741 | r = amdgpu_device_ip_hw_init_phase2(adev); |
1742 | if (r) | |
72d3f592 | 1743 | goto init_failed; |
d38ceaf9 | 1744 | |
3e2e2ab5 HZ |
1745 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
1746 | amdgpu_xgmi_add_device(adev); | |
1884734a | 1747 | amdgpu_amdkfd_device_init(adev); |
c6332b97 | 1748 | |
72d3f592 | 1749 | init_failed: |
d3c117e5 | 1750 | if (amdgpu_sriov_vf(adev)) { |
72d3f592 ED |
1751 | if (!r) |
1752 | amdgpu_virt_init_data_exchange(adev); | |
c6332b97 | 1753 | amdgpu_virt_release_full_gpu(adev, true); |
d3c117e5 | 1754 | } |
c6332b97 | 1755 | |
72d3f592 | 1756 | return r; |
d38ceaf9 AD |
1757 | } |
1758 | ||
e3ecdffa AD |
1759 | /** |
1760 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
1761 | * | |
1762 | * @adev: amdgpu_device pointer | |
1763 | * | |
1764 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
1765 | * this function before a GPU reset. If the value is retained after a | |
1766 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
1767 | */ | |
06ec9070 | 1768 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1769 | { |
1770 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
1771 | } | |
1772 | ||
e3ecdffa AD |
1773 | /** |
1774 | * amdgpu_device_check_vram_lost - check if vram is valid | |
1775 | * | |
1776 | * @adev: amdgpu_device pointer | |
1777 | * | |
1778 | * Checks the reset magic value written to the gart pointer in VRAM. | |
1779 | * The driver calls this after a GPU reset to see if the contents of | |
1780 | * VRAM is lost or now. | |
1781 | * returns true if vram is lost, false if not. | |
1782 | */ | |
06ec9070 | 1783 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 CZ |
1784 | { |
1785 | return !!memcmp(adev->gart.ptr, adev->reset_magic, | |
1786 | AMDGPU_RESET_MAGIC_NUM); | |
1787 | } | |
1788 | ||
e3ecdffa | 1789 | /** |
1112a46b | 1790 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
1791 | * |
1792 | * @adev: amdgpu_device pointer | |
1793 | * | |
e3ecdffa | 1794 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
1795 | * set_clockgating_state callbacks are run. |
1796 | * Late initialization pass enabling clockgating for hardware IPs. | |
1797 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
1798 | * Returns 0 on success, negative error code on failure. |
1799 | */ | |
fdd34271 | 1800 | |
1112a46b RZ |
1801 | static int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
1802 | enum amd_clockgating_state state) | |
d38ceaf9 | 1803 | { |
1112a46b | 1804 | int i, j, r; |
d38ceaf9 | 1805 | |
4a2ba394 SL |
1806 | if (amdgpu_emu_mode == 1) |
1807 | return 0; | |
1808 | ||
1112a46b RZ |
1809 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1810 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 1811 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 1812 | continue; |
4a446d55 | 1813 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 1814 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 1815 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 1816 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
57716327 | 1817 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 1818 | /* enable clockgating to save power */ |
a1255107 | 1819 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 1820 | state); |
4a446d55 AD |
1821 | if (r) { |
1822 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 1823 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
1824 | return r; |
1825 | } | |
b0b00ff1 | 1826 | } |
d38ceaf9 | 1827 | } |
06b18f61 | 1828 | |
c9f96fd5 RZ |
1829 | return 0; |
1830 | } | |
1831 | ||
1112a46b | 1832 | static int amdgpu_device_set_pg_state(struct amdgpu_device *adev, enum amd_powergating_state state) |
c9f96fd5 | 1833 | { |
1112a46b | 1834 | int i, j, r; |
06b18f61 | 1835 | |
c9f96fd5 RZ |
1836 | if (amdgpu_emu_mode == 1) |
1837 | return 0; | |
1838 | ||
1112a46b RZ |
1839 | for (j = 0; j < adev->num_ip_blocks; j++) { |
1840 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 1841 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 RZ |
1842 | continue; |
1843 | /* skip CG for VCE/UVD, it's handled specially */ | |
1844 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
1845 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
1846 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
1847 | adev->ip_blocks[i].version->funcs->set_powergating_state) { | |
1848 | /* enable powergating to save power */ | |
1849 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 1850 | state); |
c9f96fd5 RZ |
1851 | if (r) { |
1852 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
1853 | adev->ip_blocks[i].version->funcs->name, r); | |
1854 | return r; | |
1855 | } | |
1856 | } | |
1857 | } | |
2dc80b00 S |
1858 | return 0; |
1859 | } | |
1860 | ||
beff74bc AD |
1861 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
1862 | { | |
1863 | struct amdgpu_gpu_instance *gpu_ins; | |
1864 | struct amdgpu_device *adev; | |
1865 | int i, ret = 0; | |
1866 | ||
1867 | mutex_lock(&mgpu_info.mutex); | |
1868 | ||
1869 | /* | |
1870 | * MGPU fan boost feature should be enabled | |
1871 | * only when there are two or more dGPUs in | |
1872 | * the system | |
1873 | */ | |
1874 | if (mgpu_info.num_dgpu < 2) | |
1875 | goto out; | |
1876 | ||
1877 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
1878 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
1879 | adev = gpu_ins->adev; | |
1880 | if (!(adev->flags & AMD_IS_APU) && | |
1881 | !gpu_ins->mgpu_fan_enabled && | |
1882 | adev->powerplay.pp_funcs && | |
1883 | adev->powerplay.pp_funcs->enable_mgpu_fan_boost) { | |
1884 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); | |
1885 | if (ret) | |
1886 | break; | |
1887 | ||
1888 | gpu_ins->mgpu_fan_enabled = 1; | |
1889 | } | |
1890 | } | |
1891 | ||
1892 | out: | |
1893 | mutex_unlock(&mgpu_info.mutex); | |
1894 | ||
1895 | return ret; | |
1896 | } | |
1897 | ||
e3ecdffa AD |
1898 | /** |
1899 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
1900 | * | |
1901 | * @adev: amdgpu_device pointer | |
1902 | * | |
1903 | * Late initialization pass for hardware IPs. The list of all the hardware | |
1904 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
1905 | * late_init covers any special initialization that an IP requires | |
1906 | * after all of the have been initialized or something that needs to happen | |
1907 | * late in the init process. | |
1908 | * Returns 0 on success, negative error code on failure. | |
1909 | */ | |
06ec9070 | 1910 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 S |
1911 | { |
1912 | int i = 0, r; | |
1913 | ||
1914 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 1915 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
1916 | continue; |
1917 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
1918 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
1919 | if (r) { | |
1920 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
1921 | adev->ip_blocks[i].version->funcs->name, r); | |
1922 | return r; | |
1923 | } | |
2dc80b00 | 1924 | } |
73f847db | 1925 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
1926 | } |
1927 | ||
1112a46b RZ |
1928 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
1929 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 1930 | |
06ec9070 | 1931 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 1932 | |
beff74bc AD |
1933 | r = amdgpu_device_enable_mgpu_fan_boost(); |
1934 | if (r) | |
1935 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
1936 | ||
1937 | /* set to low pstate by default */ | |
1938 | amdgpu_xgmi_set_pstate(adev, 0); | |
1939 | ||
d38ceaf9 AD |
1940 | return 0; |
1941 | } | |
1942 | ||
e3ecdffa AD |
1943 | /** |
1944 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
1945 | * | |
1946 | * @adev: amdgpu_device pointer | |
1947 | * | |
1948 | * Main teardown pass for hardware IPs. The list of all the hardware | |
1949 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
1950 | * are run. hw_fini tears down the hardware associated with each IP | |
1951 | * and sw_fini tears down any software state associated with each IP. | |
1952 | * Returns 0 on success, negative error code on failure. | |
1953 | */ | |
06ec9070 | 1954 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1955 | { |
1956 | int i, r; | |
1957 | ||
c030f2e4 | 1958 | amdgpu_ras_pre_fini(adev); |
1959 | ||
a82400b5 AG |
1960 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
1961 | amdgpu_xgmi_remove_device(adev); | |
1962 | ||
1884734a | 1963 | amdgpu_amdkfd_device_fini(adev); |
05df1f01 RZ |
1964 | |
1965 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); | |
fdd34271 RZ |
1966 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
1967 | ||
3e96dbfd AD |
1968 | /* need to disable SMC first */ |
1969 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1970 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 1971 | continue; |
fdd34271 | 1972 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 | 1973 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
1974 | /* XXX handle errors */ |
1975 | if (r) { | |
1976 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 1977 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 1978 | } |
a1255107 | 1979 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
1980 | break; |
1981 | } | |
1982 | } | |
1983 | ||
d38ceaf9 | 1984 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 1985 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 1986 | continue; |
8201a67a | 1987 | |
a1255107 | 1988 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 1989 | /* XXX handle errors */ |
2c1a2784 | 1990 | if (r) { |
a1255107 AD |
1991 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
1992 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 1993 | } |
8201a67a | 1994 | |
a1255107 | 1995 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
1996 | } |
1997 | ||
9950cda2 | 1998 | |
d38ceaf9 | 1999 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2000 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2001 | continue; |
c12aba3a ML |
2002 | |
2003 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2004 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2005 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a ML |
2006 | amdgpu_device_wb_fini(adev); |
2007 | amdgpu_device_vram_scratch_fini(adev); | |
533aed27 | 2008 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2009 | } |
2010 | ||
a1255107 | 2011 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2012 | /* XXX handle errors */ |
2c1a2784 | 2013 | if (r) { |
a1255107 AD |
2014 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2015 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2016 | } |
a1255107 AD |
2017 | adev->ip_blocks[i].status.sw = false; |
2018 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2019 | } |
2020 | ||
a6dcfd9c | 2021 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2022 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2023 | continue; |
a1255107 AD |
2024 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2025 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2026 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2027 | } |
2028 | ||
c030f2e4 | 2029 | amdgpu_ras_fini(adev); |
2030 | ||
030308fc | 2031 | if (amdgpu_sriov_vf(adev)) |
24136135 ML |
2032 | if (amdgpu_virt_release_full_gpu(adev, false)) |
2033 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2493664f | 2034 | |
d38ceaf9 AD |
2035 | return 0; |
2036 | } | |
2037 | ||
e3ecdffa | 2038 | /** |
beff74bc | 2039 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2040 | * |
1112a46b | 2041 | * @work: work_struct. |
e3ecdffa | 2042 | */ |
beff74bc | 2043 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2044 | { |
2045 | struct amdgpu_device *adev = | |
beff74bc | 2046 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2047 | int r; |
2048 | ||
2049 | r = amdgpu_ib_ring_tests(adev); | |
2050 | if (r) | |
2051 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2052 | } |
2053 | ||
1e317b99 RZ |
2054 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2055 | { | |
2056 | struct amdgpu_device *adev = | |
2057 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2058 | ||
2059 | mutex_lock(&adev->gfx.gfx_off_mutex); | |
2060 | if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { | |
2061 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2062 | adev->gfx.gfx_off_state = true; | |
2063 | } | |
2064 | mutex_unlock(&adev->gfx.gfx_off_mutex); | |
2065 | } | |
2066 | ||
e3ecdffa | 2067 | /** |
e7854a03 | 2068 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2069 | * |
2070 | * @adev: amdgpu_device pointer | |
2071 | * | |
2072 | * Main suspend function for hardware IPs. The list of all the hardware | |
2073 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2074 | * suspend callbacks are run. suspend puts the hardware and software state | |
2075 | * in each IP into a state suitable for suspend. | |
2076 | * Returns 0 on success, negative error code on failure. | |
2077 | */ | |
e7854a03 AD |
2078 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2079 | { | |
2080 | int i, r; | |
2081 | ||
05df1f01 | 2082 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 | 2083 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
05df1f01 | 2084 | |
e7854a03 AD |
2085 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2086 | if (!adev->ip_blocks[i].status.valid) | |
2087 | continue; | |
2088 | /* displays are handled separately */ | |
2089 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) { | |
e7854a03 AD |
2090 | /* XXX handle errors */ |
2091 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2092 | /* XXX handle errors */ | |
2093 | if (r) { | |
2094 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2095 | adev->ip_blocks[i].version->funcs->name, r); | |
2096 | } | |
2097 | } | |
2098 | } | |
2099 | ||
e7854a03 AD |
2100 | return 0; |
2101 | } | |
2102 | ||
2103 | /** | |
2104 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2105 | * | |
2106 | * @adev: amdgpu_device pointer | |
2107 | * | |
2108 | * Main suspend function for hardware IPs. The list of all the hardware | |
2109 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2110 | * suspend callbacks are run. suspend puts the hardware and software state | |
2111 | * in each IP into a state suitable for suspend. | |
2112 | * Returns 0 on success, negative error code on failure. | |
2113 | */ | |
2114 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2115 | { |
2116 | int i, r; | |
2117 | ||
2118 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
a1255107 | 2119 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2120 | continue; |
e7854a03 AD |
2121 | /* displays are handled in phase1 */ |
2122 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2123 | continue; | |
d38ceaf9 | 2124 | /* XXX handle errors */ |
a1255107 | 2125 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2126 | /* XXX handle errors */ |
2c1a2784 | 2127 | if (r) { |
a1255107 AD |
2128 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2129 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2130 | } |
d38ceaf9 AD |
2131 | } |
2132 | ||
2133 | return 0; | |
2134 | } | |
2135 | ||
e7854a03 AD |
2136 | /** |
2137 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
2138 | * | |
2139 | * @adev: amdgpu_device pointer | |
2140 | * | |
2141 | * Main suspend function for hardware IPs. The list of all the hardware | |
2142 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2143 | * suspend callbacks are run. suspend puts the hardware and software state | |
2144 | * in each IP into a state suitable for suspend. | |
2145 | * Returns 0 on success, negative error code on failure. | |
2146 | */ | |
2147 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
2148 | { | |
2149 | int r; | |
2150 | ||
e7819644 YT |
2151 | if (amdgpu_sriov_vf(adev)) |
2152 | amdgpu_virt_request_full_gpu(adev, false); | |
2153 | ||
e7854a03 AD |
2154 | r = amdgpu_device_ip_suspend_phase1(adev); |
2155 | if (r) | |
2156 | return r; | |
2157 | r = amdgpu_device_ip_suspend_phase2(adev); | |
2158 | ||
e7819644 YT |
2159 | if (amdgpu_sriov_vf(adev)) |
2160 | amdgpu_virt_release_full_gpu(adev, false); | |
2161 | ||
e7854a03 AD |
2162 | return r; |
2163 | } | |
2164 | ||
06ec9070 | 2165 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2166 | { |
2167 | int i, r; | |
2168 | ||
2cb681b6 ML |
2169 | static enum amd_ip_block_type ip_order[] = { |
2170 | AMD_IP_BLOCK_TYPE_GMC, | |
2171 | AMD_IP_BLOCK_TYPE_COMMON, | |
39186aef | 2172 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
2173 | AMD_IP_BLOCK_TYPE_IH, |
2174 | }; | |
a90ad3c2 | 2175 | |
2cb681b6 ML |
2176 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2177 | int j; | |
2178 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2179 | |
2cb681b6 ML |
2180 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2181 | block = &adev->ip_blocks[j]; | |
2182 | ||
2183 | if (block->version->type != ip_order[i] || | |
2184 | !block->status.valid) | |
2185 | continue; | |
2186 | ||
2187 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 2188 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2189 | if (r) |
2190 | return r; | |
a90ad3c2 ML |
2191 | } |
2192 | } | |
2193 | ||
2194 | return 0; | |
2195 | } | |
2196 | ||
06ec9070 | 2197 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
2198 | { |
2199 | int i, r; | |
2200 | ||
2cb681b6 ML |
2201 | static enum amd_ip_block_type ip_order[] = { |
2202 | AMD_IP_BLOCK_TYPE_SMC, | |
2203 | AMD_IP_BLOCK_TYPE_DCE, | |
2204 | AMD_IP_BLOCK_TYPE_GFX, | |
2205 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c FM |
2206 | AMD_IP_BLOCK_TYPE_UVD, |
2207 | AMD_IP_BLOCK_TYPE_VCE | |
2cb681b6 | 2208 | }; |
a90ad3c2 | 2209 | |
2cb681b6 ML |
2210 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
2211 | int j; | |
2212 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 2213 | |
2cb681b6 ML |
2214 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2215 | block = &adev->ip_blocks[j]; | |
2216 | ||
2217 | if (block->version->type != ip_order[i] || | |
2218 | !block->status.valid) | |
2219 | continue; | |
2220 | ||
2221 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 2222 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
2223 | if (r) |
2224 | return r; | |
a90ad3c2 ML |
2225 | } |
2226 | } | |
2227 | ||
2228 | return 0; | |
2229 | } | |
2230 | ||
e3ecdffa AD |
2231 | /** |
2232 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
2233 | * | |
2234 | * @adev: amdgpu_device pointer | |
2235 | * | |
2236 | * First resume function for hardware IPs. The list of all the hardware | |
2237 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2238 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
2239 | * after a suspend and updates the software state as necessary. This | |
2240 | * function is also used for restoring the GPU after a GPU reset. | |
2241 | * Returns 0 on success, negative error code on failure. | |
2242 | */ | |
06ec9070 | 2243 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
2244 | { |
2245 | int i, r; | |
2246 | ||
a90ad3c2 ML |
2247 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2248 | if (!adev->ip_blocks[i].status.valid) | |
2249 | continue; | |
a90ad3c2 | 2250 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
2251 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
2252 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
fcf0649f CZ |
2253 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2254 | if (r) { | |
2255 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
2256 | adev->ip_blocks[i].version->funcs->name, r); | |
2257 | return r; | |
2258 | } | |
a90ad3c2 ML |
2259 | } |
2260 | } | |
2261 | ||
2262 | return 0; | |
2263 | } | |
2264 | ||
e3ecdffa AD |
2265 | /** |
2266 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
2267 | * | |
2268 | * @adev: amdgpu_device pointer | |
2269 | * | |
2270 | * First resume function for hardware IPs. The list of all the hardware | |
2271 | * IPs that make up the asic is walked and the resume callbacks are run for | |
2272 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
2273 | * functional state after a suspend and updates the software state as | |
2274 | * necessary. This function is also used for restoring the GPU after a GPU | |
2275 | * reset. | |
2276 | * Returns 0 on success, negative error code on failure. | |
2277 | */ | |
06ec9070 | 2278 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
2279 | { |
2280 | int i, r; | |
2281 | ||
2282 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2283 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2284 | continue; |
fcf0649f | 2285 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 2286 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
2287 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
2288 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 2289 | continue; |
a1255107 | 2290 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 2291 | if (r) { |
a1255107 AD |
2292 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
2293 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2294 | return r; |
2c1a2784 | 2295 | } |
d38ceaf9 AD |
2296 | } |
2297 | ||
2298 | return 0; | |
2299 | } | |
2300 | ||
e3ecdffa AD |
2301 | /** |
2302 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
2303 | * | |
2304 | * @adev: amdgpu_device pointer | |
2305 | * | |
2306 | * Main resume function for hardware IPs. The hardware IPs | |
2307 | * are split into two resume functions because they are | |
2308 | * are also used in in recovering from a GPU reset and some additional | |
2309 | * steps need to be take between them. In this case (S3/S4) they are | |
2310 | * run sequentially. | |
2311 | * Returns 0 on success, negative error code on failure. | |
2312 | */ | |
06ec9070 | 2313 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
2314 | { |
2315 | int r; | |
2316 | ||
06ec9070 | 2317 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
2318 | if (r) |
2319 | return r; | |
7a3e0bb2 RZ |
2320 | |
2321 | r = amdgpu_device_fw_loading(adev); | |
2322 | if (r) | |
2323 | return r; | |
2324 | ||
06ec9070 | 2325 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
2326 | |
2327 | return r; | |
2328 | } | |
2329 | ||
e3ecdffa AD |
2330 | /** |
2331 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
2332 | * | |
2333 | * @adev: amdgpu_device pointer | |
2334 | * | |
2335 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
2336 | */ | |
4e99a44e | 2337 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 2338 | { |
6867e1b5 ML |
2339 | if (amdgpu_sriov_vf(adev)) { |
2340 | if (adev->is_atom_fw) { | |
2341 | if (amdgpu_atomfirmware_gpu_supports_virtualization(adev)) | |
2342 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2343 | } else { | |
2344 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
2345 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
2346 | } | |
2347 | ||
2348 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
2349 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 2350 | } |
048765ad AR |
2351 | } |
2352 | ||
e3ecdffa AD |
2353 | /** |
2354 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
2355 | * | |
2356 | * @asic_type: AMD asic type | |
2357 | * | |
2358 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
2359 | * returns true if DC has support, false if not. | |
2360 | */ | |
4562236b HW |
2361 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
2362 | { | |
2363 | switch (asic_type) { | |
2364 | #if defined(CONFIG_DRM_AMD_DC) | |
2365 | case CHIP_BONAIRE: | |
0d6fbccb | 2366 | case CHIP_KAVERI: |
367e6687 AD |
2367 | case CHIP_KABINI: |
2368 | case CHIP_MULLINS: | |
d9fda248 HW |
2369 | /* |
2370 | * We have systems in the wild with these ASICs that require | |
2371 | * LVDS and VGA support which is not supported with DC. | |
2372 | * | |
2373 | * Fallback to the non-DC driver here by default so as not to | |
2374 | * cause regressions. | |
2375 | */ | |
2376 | return amdgpu_dc > 0; | |
2377 | case CHIP_HAWAII: | |
4562236b HW |
2378 | case CHIP_CARRIZO: |
2379 | case CHIP_STONEY: | |
4562236b | 2380 | case CHIP_POLARIS10: |
675fd32b | 2381 | case CHIP_POLARIS11: |
2c8ad2d5 | 2382 | case CHIP_POLARIS12: |
675fd32b | 2383 | case CHIP_VEGAM: |
4562236b HW |
2384 | case CHIP_TONGA: |
2385 | case CHIP_FIJI: | |
42f8ffa1 | 2386 | case CHIP_VEGA10: |
dca7b401 | 2387 | case CHIP_VEGA12: |
c6034aa2 | 2388 | case CHIP_VEGA20: |
dc37a9a0 | 2389 | #if defined(CONFIG_DRM_AMD_DC_DCN1_0) |
fd187853 | 2390 | case CHIP_RAVEN: |
42f8ffa1 | 2391 | #endif |
fd187853 | 2392 | return amdgpu_dc != 0; |
4562236b HW |
2393 | #endif |
2394 | default: | |
2395 | return false; | |
2396 | } | |
2397 | } | |
2398 | ||
2399 | /** | |
2400 | * amdgpu_device_has_dc_support - check if dc is supported | |
2401 | * | |
2402 | * @adev: amdgpu_device_pointer | |
2403 | * | |
2404 | * Returns true for supported, false for not supported | |
2405 | */ | |
2406 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
2407 | { | |
2555039d XY |
2408 | if (amdgpu_sriov_vf(adev)) |
2409 | return false; | |
2410 | ||
4562236b HW |
2411 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
2412 | } | |
2413 | ||
d4535e2c AG |
2414 | |
2415 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) | |
2416 | { | |
2417 | struct amdgpu_device *adev = | |
2418 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
2419 | ||
2420 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
2421 | if (adev->asic_reset_res) | |
fed184e9 | 2422 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
d4535e2c AG |
2423 | adev->asic_reset_res, adev->ddev->unique); |
2424 | } | |
2425 | ||
2426 | ||
d38ceaf9 AD |
2427 | /** |
2428 | * amdgpu_device_init - initialize the driver | |
2429 | * | |
2430 | * @adev: amdgpu_device pointer | |
87e3f136 | 2431 | * @ddev: drm dev pointer |
d38ceaf9 AD |
2432 | * @pdev: pci dev pointer |
2433 | * @flags: driver flags | |
2434 | * | |
2435 | * Initializes the driver info and hw (all asics). | |
2436 | * Returns 0 for success or an error on failure. | |
2437 | * Called at driver startup. | |
2438 | */ | |
2439 | int amdgpu_device_init(struct amdgpu_device *adev, | |
2440 | struct drm_device *ddev, | |
2441 | struct pci_dev *pdev, | |
2442 | uint32_t flags) | |
2443 | { | |
2444 | int r, i; | |
2445 | bool runtime = false; | |
95844d20 | 2446 | u32 max_MBps; |
d38ceaf9 AD |
2447 | |
2448 | adev->shutdown = false; | |
2449 | adev->dev = &pdev->dev; | |
2450 | adev->ddev = ddev; | |
2451 | adev->pdev = pdev; | |
2452 | adev->flags = flags; | |
2f7d10b3 | 2453 | adev->asic_type = flags & AMD_ASIC_MASK; |
d38ceaf9 | 2454 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 SL |
2455 | if (amdgpu_emu_mode == 1) |
2456 | adev->usec_timeout *= 2; | |
770d13b1 | 2457 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
2458 | adev->accel_working = false; |
2459 | adev->num_rings = 0; | |
2460 | adev->mman.buffer_funcs = NULL; | |
2461 | adev->mman.buffer_funcs_ring = NULL; | |
2462 | adev->vm_manager.vm_pte_funcs = NULL; | |
3798e9a6 | 2463 | adev->vm_manager.vm_pte_num_rqs = 0; |
132f34e4 | 2464 | adev->gmc.gmc_funcs = NULL; |
f54d1867 | 2465 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 2466 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
2467 | |
2468 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
2469 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
2470 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
2471 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
2472 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
2473 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2474 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
2475 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
2476 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
2477 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
2478 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
2479 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
2480 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
2481 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
2482 | ||
3e39ab90 AD |
2483 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
2484 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
2485 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
2486 | |
2487 | /* mutex initialization are all done here so we | |
2488 | * can recall function without having locking issues */ | |
d38ceaf9 | 2489 | atomic_set(&adev->irq.ih.lock, 0); |
0e5ca0d1 | 2490 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
2491 | mutex_init(&adev->pm.mutex); |
2492 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
2493 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 2494 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 2495 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 2496 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 2497 | mutex_init(&adev->mn_lock); |
e23b74aa | 2498 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 2499 | hash_init(adev->mn_hash); |
13a752e3 | 2500 | mutex_init(&adev->lock_reset); |
bb5a2bdf | 2501 | mutex_init(&adev->virt.dpm_mutex); |
d38ceaf9 | 2502 | |
912dfc84 EQ |
2503 | r = amdgpu_device_check_arguments(adev); |
2504 | if (r) | |
2505 | return r; | |
d38ceaf9 | 2506 | |
d38ceaf9 AD |
2507 | spin_lock_init(&adev->mmio_idx_lock); |
2508 | spin_lock_init(&adev->smc_idx_lock); | |
2509 | spin_lock_init(&adev->pcie_idx_lock); | |
2510 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
2511 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 2512 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 2513 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 2514 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 2515 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 2516 | |
0c4e7fa5 CZ |
2517 | INIT_LIST_HEAD(&adev->shadow_list); |
2518 | mutex_init(&adev->shadow_list_lock); | |
2519 | ||
795f2813 AR |
2520 | INIT_LIST_HEAD(&adev->ring_lru_list); |
2521 | spin_lock_init(&adev->ring_lru_list_lock); | |
2522 | ||
beff74bc AD |
2523 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
2524 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
2525 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
2526 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 2527 | |
d4535e2c AG |
2528 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
2529 | ||
d23ee13f | 2530 | adev->gfx.gfx_off_req_count = 1; |
b1ddf548 RZ |
2531 | adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false; |
2532 | ||
0fa49558 AX |
2533 | /* Registers mapping */ |
2534 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
2535 | if (adev->asic_type >= CHIP_BONAIRE) { |
2536 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
2537 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
2538 | } else { | |
2539 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
2540 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
2541 | } | |
d38ceaf9 | 2542 | |
d38ceaf9 AD |
2543 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
2544 | if (adev->rmmio == NULL) { | |
2545 | return -ENOMEM; | |
2546 | } | |
2547 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
2548 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
2549 | ||
d38ceaf9 AD |
2550 | /* io port mapping */ |
2551 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
2552 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
2553 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
2554 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
2555 | break; | |
2556 | } | |
2557 | } | |
2558 | if (adev->rio_mem == NULL) | |
b64a18c5 | 2559 | DRM_INFO("PCI I/O BAR is not found.\n"); |
d38ceaf9 | 2560 | |
5494d864 AD |
2561 | amdgpu_device_get_pcie_info(adev); |
2562 | ||
d38ceaf9 | 2563 | /* early init functions */ |
06ec9070 | 2564 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 AD |
2565 | if (r) |
2566 | return r; | |
2567 | ||
6585661d OZ |
2568 | /* doorbell bar mapping and doorbell index init*/ |
2569 | amdgpu_device_doorbell_init(adev); | |
2570 | ||
d38ceaf9 AD |
2571 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
2572 | /* this will fail for cards that aren't VGA class devices, just | |
2573 | * ignore it */ | |
06ec9070 | 2574 | vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); |
d38ceaf9 | 2575 | |
e9bef455 | 2576 | if (amdgpu_device_is_px(ddev)) |
d38ceaf9 | 2577 | runtime = true; |
84c8b22e LW |
2578 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2579 | vga_switcheroo_register_client(adev->pdev, | |
2580 | &amdgpu_switcheroo_ops, runtime); | |
d38ceaf9 AD |
2581 | if (runtime) |
2582 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
2583 | ||
9475a943 SL |
2584 | if (amdgpu_emu_mode == 1) { |
2585 | /* post the asic on emulation mode */ | |
2586 | emu_soc_asic_init(adev); | |
bfca0289 | 2587 | goto fence_driver_init; |
9475a943 | 2588 | } |
bfca0289 | 2589 | |
4e99a44e ML |
2590 | /* detect if we are with an SRIOV vbios */ |
2591 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 2592 | |
95e8e59e AD |
2593 | /* check if we need to reset the asic |
2594 | * E.g., driver was not cleanly unloaded previously, etc. | |
2595 | */ | |
f14899fd | 2596 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
95e8e59e AD |
2597 | r = amdgpu_asic_reset(adev); |
2598 | if (r) { | |
2599 | dev_err(adev->dev, "asic reset on init failed\n"); | |
2600 | goto failed; | |
2601 | } | |
2602 | } | |
2603 | ||
d38ceaf9 | 2604 | /* Post card if necessary */ |
39c640c0 | 2605 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 2606 | if (!adev->bios) { |
bec86378 | 2607 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
2608 | r = -EINVAL; |
2609 | goto failed; | |
d38ceaf9 | 2610 | } |
bec86378 | 2611 | DRM_INFO("GPU posting now...\n"); |
4e99a44e ML |
2612 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2613 | if (r) { | |
2614 | dev_err(adev->dev, "gpu post error!\n"); | |
2615 | goto failed; | |
2616 | } | |
d38ceaf9 AD |
2617 | } |
2618 | ||
88b64e95 AD |
2619 | if (adev->is_atom_fw) { |
2620 | /* Initialize clocks */ | |
2621 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
2622 | if (r) { | |
2623 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 2624 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
2625 | goto failed; |
2626 | } | |
2627 | } else { | |
a5bde2f9 AD |
2628 | /* Initialize clocks */ |
2629 | r = amdgpu_atombios_get_clock_info(adev); | |
2630 | if (r) { | |
2631 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 2632 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 2633 | goto failed; |
a5bde2f9 AD |
2634 | } |
2635 | /* init i2c buses */ | |
4562236b HW |
2636 | if (!amdgpu_device_has_dc_support(adev)) |
2637 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 2638 | } |
d38ceaf9 | 2639 | |
bfca0289 | 2640 | fence_driver_init: |
d38ceaf9 AD |
2641 | /* Fence driver */ |
2642 | r = amdgpu_fence_driver_init(adev); | |
2c1a2784 AD |
2643 | if (r) { |
2644 | dev_err(adev->dev, "amdgpu_fence_driver_init failed\n"); | |
e23b74aa | 2645 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 2646 | goto failed; |
2c1a2784 | 2647 | } |
d38ceaf9 AD |
2648 | |
2649 | /* init the mode config */ | |
2650 | drm_mode_config_init(adev->ddev); | |
2651 | ||
06ec9070 | 2652 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 2653 | if (r) { |
8840a387 | 2654 | /* failed in exclusive mode due to timeout */ |
2655 | if (amdgpu_sriov_vf(adev) && | |
2656 | !amdgpu_sriov_runtime(adev) && | |
2657 | amdgpu_virt_mmio_blocked(adev) && | |
2658 | !amdgpu_virt_wait_reset(adev)) { | |
2659 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
2660 | /* Don't send request since VF is inactive. */ |
2661 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
2662 | adev->virt.ops = NULL; | |
8840a387 | 2663 | r = -EAGAIN; |
2664 | goto failed; | |
2665 | } | |
06ec9070 | 2666 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 2667 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
72d3f592 ED |
2668 | if (amdgpu_virt_request_full_gpu(adev, false)) |
2669 | amdgpu_virt_release_full_gpu(adev, false); | |
83ba126a | 2670 | goto failed; |
d38ceaf9 AD |
2671 | } |
2672 | ||
2673 | adev->accel_working = true; | |
2674 | ||
e59c0205 AX |
2675 | amdgpu_vm_check_compute_bug(adev); |
2676 | ||
95844d20 MO |
2677 | /* Initialize the buffer migration limit. */ |
2678 | if (amdgpu_moverate >= 0) | |
2679 | max_MBps = amdgpu_moverate; | |
2680 | else | |
2681 | max_MBps = 8; /* Allow 8 MB/s. */ | |
2682 | /* Get a log2 for easy divisions. */ | |
2683 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
2684 | ||
9bc92b9c ML |
2685 | amdgpu_fbdev_init(adev); |
2686 | ||
e9bc1bf7 YT |
2687 | if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)) |
2688 | amdgpu_pm_virt_sysfs_init(adev); | |
2689 | ||
d2f52ac8 RZ |
2690 | r = amdgpu_pm_sysfs_init(adev); |
2691 | if (r) | |
2692 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); | |
2693 | ||
5bb23532 OM |
2694 | r = amdgpu_ucode_sysfs_init(adev); |
2695 | if (r) | |
2696 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); | |
2697 | ||
75758255 | 2698 | r = amdgpu_debugfs_gem_init(adev); |
3f14e623 | 2699 | if (r) |
d38ceaf9 | 2700 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); |
d38ceaf9 AD |
2701 | |
2702 | r = amdgpu_debugfs_regs_init(adev); | |
3f14e623 | 2703 | if (r) |
d38ceaf9 | 2704 | DRM_ERROR("registering register debugfs failed (%d).\n", r); |
d38ceaf9 | 2705 | |
50ab2533 | 2706 | r = amdgpu_debugfs_firmware_init(adev); |
3f14e623 | 2707 | if (r) |
50ab2533 | 2708 | DRM_ERROR("registering firmware debugfs failed (%d).\n", r); |
50ab2533 | 2709 | |
763efb6c | 2710 | r = amdgpu_debugfs_init(adev); |
db95e218 | 2711 | if (r) |
763efb6c | 2712 | DRM_ERROR("Creating debugfs files failed (%d).\n", r); |
db95e218 | 2713 | |
d38ceaf9 AD |
2714 | if ((amdgpu_testing & 1)) { |
2715 | if (adev->accel_working) | |
2716 | amdgpu_test_moves(adev); | |
2717 | else | |
2718 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
2719 | } | |
d38ceaf9 AD |
2720 | if (amdgpu_benchmarking) { |
2721 | if (adev->accel_working) | |
2722 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
2723 | else | |
2724 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
2725 | } | |
2726 | ||
2727 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
2728 | * explicit gating rather than handling it automatically. | |
2729 | */ | |
06ec9070 | 2730 | r = amdgpu_device_ip_late_init(adev); |
2c1a2784 | 2731 | if (r) { |
06ec9070 | 2732 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); |
e23b74aa | 2733 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); |
83ba126a | 2734 | goto failed; |
2c1a2784 | 2735 | } |
d38ceaf9 | 2736 | |
108c6a63 | 2737 | /* must succeed. */ |
511fdbc3 | 2738 | amdgpu_ras_resume(adev); |
108c6a63 | 2739 | |
beff74bc AD |
2740 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
2741 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2742 | ||
dcea6e65 KR |
2743 | r = device_create_file(adev->dev, &dev_attr_pcie_replay_count); |
2744 | if (r) { | |
2745 | dev_err(adev->dev, "Could not create pcie_replay_count"); | |
2746 | return r; | |
2747 | } | |
108c6a63 | 2748 | |
d38ceaf9 | 2749 | return 0; |
83ba126a AD |
2750 | |
2751 | failed: | |
89041940 | 2752 | amdgpu_vf_error_trans_all(adev); |
83ba126a AD |
2753 | if (runtime) |
2754 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
8840a387 | 2755 | |
83ba126a | 2756 | return r; |
d38ceaf9 AD |
2757 | } |
2758 | ||
d38ceaf9 AD |
2759 | /** |
2760 | * amdgpu_device_fini - tear down the driver | |
2761 | * | |
2762 | * @adev: amdgpu_device pointer | |
2763 | * | |
2764 | * Tear down the driver info (all asics). | |
2765 | * Called at driver shutdown. | |
2766 | */ | |
2767 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
2768 | { | |
2769 | int r; | |
2770 | ||
2771 | DRM_INFO("amdgpu: finishing device.\n"); | |
2772 | adev->shutdown = true; | |
e5b03032 ML |
2773 | /* disable all interrupts */ |
2774 | amdgpu_irq_disable_all(adev); | |
ff97cba8 ML |
2775 | if (adev->mode_info.mode_config_initialized){ |
2776 | if (!amdgpu_device_has_dc_support(adev)) | |
c2d88e06 | 2777 | drm_helper_force_disable_all(adev->ddev); |
ff97cba8 ML |
2778 | else |
2779 | drm_atomic_helper_shutdown(adev->ddev); | |
2780 | } | |
d38ceaf9 | 2781 | amdgpu_fence_driver_fini(adev); |
58e955d9 | 2782 | amdgpu_pm_sysfs_fini(adev); |
d38ceaf9 | 2783 | amdgpu_fbdev_fini(adev); |
06ec9070 | 2784 | r = amdgpu_device_ip_fini(adev); |
ab4fe3e1 HR |
2785 | if (adev->firmware.gpu_info_fw) { |
2786 | release_firmware(adev->firmware.gpu_info_fw); | |
2787 | adev->firmware.gpu_info_fw = NULL; | |
2788 | } | |
d38ceaf9 | 2789 | adev->accel_working = false; |
beff74bc | 2790 | cancel_delayed_work_sync(&adev->delayed_init_work); |
d38ceaf9 | 2791 | /* free i2c buses */ |
4562236b HW |
2792 | if (!amdgpu_device_has_dc_support(adev)) |
2793 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
2794 | |
2795 | if (amdgpu_emu_mode != 1) | |
2796 | amdgpu_atombios_fini(adev); | |
2797 | ||
d38ceaf9 AD |
2798 | kfree(adev->bios); |
2799 | adev->bios = NULL; | |
84c8b22e LW |
2800 | if (!pci_is_thunderbolt_attached(adev->pdev)) |
2801 | vga_switcheroo_unregister_client(adev->pdev); | |
83ba126a AD |
2802 | if (adev->flags & AMD_IS_PX) |
2803 | vga_switcheroo_fini_domain_pm_ops(adev->dev); | |
d38ceaf9 AD |
2804 | vga_client_register(adev->pdev, NULL, NULL, NULL); |
2805 | if (adev->rio_mem) | |
2806 | pci_iounmap(adev->pdev, adev->rio_mem); | |
2807 | adev->rio_mem = NULL; | |
2808 | iounmap(adev->rmmio); | |
2809 | adev->rmmio = NULL; | |
06ec9070 | 2810 | amdgpu_device_doorbell_fini(adev); |
e9bc1bf7 YT |
2811 | if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)) |
2812 | amdgpu_pm_virt_sysfs_fini(adev); | |
2813 | ||
d38ceaf9 | 2814 | amdgpu_debugfs_regs_cleanup(adev); |
dcea6e65 | 2815 | device_remove_file(adev->dev, &dev_attr_pcie_replay_count); |
5bb23532 | 2816 | amdgpu_ucode_sysfs_fini(adev); |
d38ceaf9 AD |
2817 | } |
2818 | ||
2819 | ||
2820 | /* | |
2821 | * Suspend & resume. | |
2822 | */ | |
2823 | /** | |
810ddc3a | 2824 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 2825 | * |
87e3f136 DP |
2826 | * @dev: drm dev pointer |
2827 | * @suspend: suspend state | |
2828 | * @fbcon : notify the fbdev of suspend | |
d38ceaf9 AD |
2829 | * |
2830 | * Puts the hw in the suspend state (all asics). | |
2831 | * Returns 0 for success or an error on failure. | |
2832 | * Called at driver suspend. | |
2833 | */ | |
810ddc3a | 2834 | int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon) |
d38ceaf9 AD |
2835 | { |
2836 | struct amdgpu_device *adev; | |
2837 | struct drm_crtc *crtc; | |
2838 | struct drm_connector *connector; | |
5ceb54c6 | 2839 | int r; |
d38ceaf9 AD |
2840 | |
2841 | if (dev == NULL || dev->dev_private == NULL) { | |
2842 | return -ENODEV; | |
2843 | } | |
2844 | ||
2845 | adev = dev->dev_private; | |
2846 | ||
2847 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2848 | return 0; | |
2849 | ||
44779b43 | 2850 | adev->in_suspend = true; |
d38ceaf9 AD |
2851 | drm_kms_helper_poll_disable(dev); |
2852 | ||
5f818173 S |
2853 | if (fbcon) |
2854 | amdgpu_fbdev_set_suspend(adev, 1); | |
2855 | ||
beff74bc | 2856 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 2857 | |
4562236b HW |
2858 | if (!amdgpu_device_has_dc_support(adev)) { |
2859 | /* turn off display hw */ | |
2860 | drm_modeset_lock_all(dev); | |
2861 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2862 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
2863 | } | |
2864 | drm_modeset_unlock_all(dev); | |
fe1053b7 AD |
2865 | /* unpin the front buffers and cursors */ |
2866 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2867 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2868 | struct drm_framebuffer *fb = crtc->primary->fb; | |
2869 | struct amdgpu_bo *robj; | |
2870 | ||
91334223 | 2871 | if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { |
fe1053b7 AD |
2872 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
2873 | r = amdgpu_bo_reserve(aobj, true); | |
2874 | if (r == 0) { | |
2875 | amdgpu_bo_unpin(aobj); | |
2876 | amdgpu_bo_unreserve(aobj); | |
2877 | } | |
756e6880 | 2878 | } |
756e6880 | 2879 | |
fe1053b7 AD |
2880 | if (fb == NULL || fb->obj[0] == NULL) { |
2881 | continue; | |
2882 | } | |
2883 | robj = gem_to_amdgpu_bo(fb->obj[0]); | |
2884 | /* don't unpin kernel fb objects */ | |
2885 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
2886 | r = amdgpu_bo_reserve(robj, true); | |
2887 | if (r == 0) { | |
2888 | amdgpu_bo_unpin(robj); | |
2889 | amdgpu_bo_unreserve(robj); | |
2890 | } | |
d38ceaf9 AD |
2891 | } |
2892 | } | |
2893 | } | |
fe1053b7 AD |
2894 | |
2895 | amdgpu_amdkfd_suspend(adev); | |
2896 | ||
5e6932fe | 2897 | amdgpu_ras_suspend(adev); |
2898 | ||
fe1053b7 AD |
2899 | r = amdgpu_device_ip_suspend_phase1(adev); |
2900 | ||
d38ceaf9 AD |
2901 | /* evict vram memory */ |
2902 | amdgpu_bo_evict_vram(adev); | |
2903 | ||
5ceb54c6 | 2904 | amdgpu_fence_driver_suspend(adev); |
d38ceaf9 | 2905 | |
fe1053b7 | 2906 | r = amdgpu_device_ip_suspend_phase2(adev); |
d38ceaf9 | 2907 | |
a0a71e49 AD |
2908 | /* evict remaining vram memory |
2909 | * This second call to evict vram is to evict the gart page table | |
2910 | * using the CPU. | |
2911 | */ | |
d38ceaf9 AD |
2912 | amdgpu_bo_evict_vram(adev); |
2913 | ||
2914 | pci_save_state(dev->pdev); | |
2915 | if (suspend) { | |
2916 | /* Shut down the device */ | |
2917 | pci_disable_device(dev->pdev); | |
2918 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
74b0b157 | 2919 | } else { |
2920 | r = amdgpu_asic_reset(adev); | |
2921 | if (r) | |
2922 | DRM_ERROR("amdgpu asic reset failed\n"); | |
d38ceaf9 AD |
2923 | } |
2924 | ||
d38ceaf9 AD |
2925 | return 0; |
2926 | } | |
2927 | ||
2928 | /** | |
810ddc3a | 2929 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 2930 | * |
87e3f136 DP |
2931 | * @dev: drm dev pointer |
2932 | * @resume: resume state | |
2933 | * @fbcon : notify the fbdev of resume | |
d38ceaf9 AD |
2934 | * |
2935 | * Bring the hw back to operating state (all asics). | |
2936 | * Returns 0 for success or an error on failure. | |
2937 | * Called at driver resume. | |
2938 | */ | |
810ddc3a | 2939 | int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) |
d38ceaf9 AD |
2940 | { |
2941 | struct drm_connector *connector; | |
2942 | struct amdgpu_device *adev = dev->dev_private; | |
756e6880 | 2943 | struct drm_crtc *crtc; |
03161a6e | 2944 | int r = 0; |
d38ceaf9 AD |
2945 | |
2946 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
2947 | return 0; | |
2948 | ||
d38ceaf9 AD |
2949 | if (resume) { |
2950 | pci_set_power_state(dev->pdev, PCI_D0); | |
2951 | pci_restore_state(dev->pdev); | |
74b0b157 | 2952 | r = pci_enable_device(dev->pdev); |
03161a6e | 2953 | if (r) |
4d3b9ae5 | 2954 | return r; |
d38ceaf9 AD |
2955 | } |
2956 | ||
2957 | /* post card */ | |
39c640c0 | 2958 | if (amdgpu_device_need_post(adev)) { |
74b0b157 | 2959 | r = amdgpu_atom_asic_init(adev->mode_info.atom_context); |
2960 | if (r) | |
2961 | DRM_ERROR("amdgpu asic init failed\n"); | |
2962 | } | |
d38ceaf9 | 2963 | |
06ec9070 | 2964 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 2965 | if (r) { |
06ec9070 | 2966 | DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 2967 | return r; |
e6707218 | 2968 | } |
5ceb54c6 AD |
2969 | amdgpu_fence_driver_resume(adev); |
2970 | ||
d38ceaf9 | 2971 | |
06ec9070 | 2972 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 2973 | if (r) |
4d3b9ae5 | 2974 | return r; |
d38ceaf9 | 2975 | |
beff74bc AD |
2976 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
2977 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2978 | ||
fe1053b7 AD |
2979 | if (!amdgpu_device_has_dc_support(adev)) { |
2980 | /* pin cursors */ | |
2981 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2982 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
2983 | ||
91334223 | 2984 | if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { |
fe1053b7 AD |
2985 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
2986 | r = amdgpu_bo_reserve(aobj, true); | |
2987 | if (r == 0) { | |
2988 | r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); | |
2989 | if (r != 0) | |
2990 | DRM_ERROR("Failed to pin cursor BO (%d)\n", r); | |
2991 | amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); | |
2992 | amdgpu_bo_unreserve(aobj); | |
2993 | } | |
756e6880 AD |
2994 | } |
2995 | } | |
2996 | } | |
ba997709 YZ |
2997 | r = amdgpu_amdkfd_resume(adev); |
2998 | if (r) | |
2999 | return r; | |
756e6880 | 3000 | |
96a5d8d4 | 3001 | /* Make sure IB tests flushed */ |
beff74bc | 3002 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 3003 | |
d38ceaf9 AD |
3004 | /* blat the mode back in */ |
3005 | if (fbcon) { | |
4562236b HW |
3006 | if (!amdgpu_device_has_dc_support(adev)) { |
3007 | /* pre DCE11 */ | |
3008 | drm_helper_resume_force_mode(dev); | |
3009 | ||
3010 | /* turn on display hw */ | |
3011 | drm_modeset_lock_all(dev); | |
3012 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3013 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
3014 | } | |
3015 | drm_modeset_unlock_all(dev); | |
d38ceaf9 | 3016 | } |
4d3b9ae5 | 3017 | amdgpu_fbdev_set_suspend(adev, 0); |
d38ceaf9 AD |
3018 | } |
3019 | ||
3020 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 | 3021 | |
5e6932fe | 3022 | amdgpu_ras_resume(adev); |
3023 | ||
23a1a9e5 L |
3024 | /* |
3025 | * Most of the connector probing functions try to acquire runtime pm | |
3026 | * refs to ensure that the GPU is powered on when connector polling is | |
3027 | * performed. Since we're calling this from a runtime PM callback, | |
3028 | * trying to acquire rpm refs will cause us to deadlock. | |
3029 | * | |
3030 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
3031 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
3032 | */ | |
3033 | #ifdef CONFIG_PM | |
3034 | dev->dev->power.disable_depth++; | |
3035 | #endif | |
4562236b HW |
3036 | if (!amdgpu_device_has_dc_support(adev)) |
3037 | drm_helper_hpd_irq_event(dev); | |
3038 | else | |
3039 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
3040 | #ifdef CONFIG_PM |
3041 | dev->dev->power.disable_depth--; | |
3042 | #endif | |
44779b43 RZ |
3043 | adev->in_suspend = false; |
3044 | ||
4d3b9ae5 | 3045 | return 0; |
d38ceaf9 AD |
3046 | } |
3047 | ||
e3ecdffa AD |
3048 | /** |
3049 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
3050 | * | |
3051 | * @adev: amdgpu_device pointer | |
3052 | * | |
3053 | * The list of all the hardware IPs that make up the asic is walked and | |
3054 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
3055 | * if the asic is still hung or not. | |
3056 | * Returns true if any of the IPs are still in a hung state, false if not. | |
3057 | */ | |
06ec9070 | 3058 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
3059 | { |
3060 | int i; | |
3061 | bool asic_hang = false; | |
3062 | ||
f993d628 ML |
3063 | if (amdgpu_sriov_vf(adev)) |
3064 | return true; | |
3065 | ||
8bc04c29 AD |
3066 | if (amdgpu_asic_need_full_reset(adev)) |
3067 | return true; | |
3068 | ||
63fbf42f | 3069 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3070 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 3071 | continue; |
a1255107 AD |
3072 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
3073 | adev->ip_blocks[i].status.hang = | |
3074 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
3075 | if (adev->ip_blocks[i].status.hang) { | |
3076 | DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); | |
63fbf42f CZ |
3077 | asic_hang = true; |
3078 | } | |
3079 | } | |
3080 | return asic_hang; | |
3081 | } | |
3082 | ||
e3ecdffa AD |
3083 | /** |
3084 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
3085 | * | |
3086 | * @adev: amdgpu_device pointer | |
3087 | * | |
3088 | * The list of all the hardware IPs that make up the asic is walked and the | |
3089 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
3090 | * handles any IP specific hardware or software state changes that are | |
3091 | * necessary for a soft reset to succeed. | |
3092 | * Returns 0 on success, negative error code on failure. | |
3093 | */ | |
06ec9070 | 3094 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
3095 | { |
3096 | int i, r = 0; | |
3097 | ||
3098 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3099 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 3100 | continue; |
a1255107 AD |
3101 | if (adev->ip_blocks[i].status.hang && |
3102 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
3103 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
3104 | if (r) |
3105 | return r; | |
3106 | } | |
3107 | } | |
3108 | ||
3109 | return 0; | |
3110 | } | |
3111 | ||
e3ecdffa AD |
3112 | /** |
3113 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
3114 | * | |
3115 | * @adev: amdgpu_device pointer | |
3116 | * | |
3117 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
3118 | * reset is necessary to recover. | |
3119 | * Returns true if a full asic reset is required, false if not. | |
3120 | */ | |
06ec9070 | 3121 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 3122 | { |
da146d3b AD |
3123 | int i; |
3124 | ||
8bc04c29 AD |
3125 | if (amdgpu_asic_need_full_reset(adev)) |
3126 | return true; | |
3127 | ||
da146d3b | 3128 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 3129 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 3130 | continue; |
a1255107 AD |
3131 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
3132 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
3133 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
3134 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
3135 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 3136 | if (adev->ip_blocks[i].status.hang) { |
da146d3b AD |
3137 | DRM_INFO("Some block need full reset!\n"); |
3138 | return true; | |
3139 | } | |
3140 | } | |
35d782fe CZ |
3141 | } |
3142 | return false; | |
3143 | } | |
3144 | ||
e3ecdffa AD |
3145 | /** |
3146 | * amdgpu_device_ip_soft_reset - do a soft reset | |
3147 | * | |
3148 | * @adev: amdgpu_device pointer | |
3149 | * | |
3150 | * The list of all the hardware IPs that make up the asic is walked and the | |
3151 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
3152 | * IP specific hardware or software state changes that are necessary to soft | |
3153 | * reset the IP. | |
3154 | * Returns 0 on success, negative error code on failure. | |
3155 | */ | |
06ec9070 | 3156 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3157 | { |
3158 | int i, r = 0; | |
3159 | ||
3160 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3161 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3162 | continue; |
a1255107 AD |
3163 | if (adev->ip_blocks[i].status.hang && |
3164 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
3165 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
3166 | if (r) |
3167 | return r; | |
3168 | } | |
3169 | } | |
3170 | ||
3171 | return 0; | |
3172 | } | |
3173 | ||
e3ecdffa AD |
3174 | /** |
3175 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
3176 | * | |
3177 | * @adev: amdgpu_device pointer | |
3178 | * | |
3179 | * The list of all the hardware IPs that make up the asic is walked and the | |
3180 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
3181 | * handles any IP specific hardware or software state changes that are | |
3182 | * necessary after the IP has been soft reset. | |
3183 | * Returns 0 on success, negative error code on failure. | |
3184 | */ | |
06ec9070 | 3185 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
3186 | { |
3187 | int i, r = 0; | |
3188 | ||
3189 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 3190 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 3191 | continue; |
a1255107 AD |
3192 | if (adev->ip_blocks[i].status.hang && |
3193 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
3194 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
3195 | if (r) |
3196 | return r; | |
3197 | } | |
3198 | ||
3199 | return 0; | |
3200 | } | |
3201 | ||
e3ecdffa | 3202 | /** |
c33adbc7 | 3203 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
3204 | * |
3205 | * @adev: amdgpu_device pointer | |
3206 | * | |
3207 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
3208 | * restore things like GPUVM page tables after a GPU reset where | |
3209 | * the contents of VRAM might be lost. | |
403009bf CK |
3210 | * |
3211 | * Returns: | |
3212 | * 0 on success, negative error code on failure. | |
e3ecdffa | 3213 | */ |
c33adbc7 | 3214 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 3215 | { |
c41d1cf6 | 3216 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf CK |
3217 | struct amdgpu_bo *shadow; |
3218 | long r = 1, tmo; | |
c41d1cf6 ML |
3219 | |
3220 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 3221 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
3222 | else |
3223 | tmo = msecs_to_jiffies(100); | |
3224 | ||
3225 | DRM_INFO("recover vram bo from shadow start\n"); | |
3226 | mutex_lock(&adev->shadow_list_lock); | |
403009bf CK |
3227 | list_for_each_entry(shadow, &adev->shadow_list, shadow_list) { |
3228 | ||
3229 | /* No need to recover an evicted BO */ | |
3230 | if (shadow->tbo.mem.mem_type != TTM_PL_TT || | |
b575f10d | 3231 | shadow->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET || |
403009bf CK |
3232 | shadow->parent->tbo.mem.mem_type != TTM_PL_VRAM) |
3233 | continue; | |
3234 | ||
3235 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
3236 | if (r) | |
3237 | break; | |
3238 | ||
c41d1cf6 | 3239 | if (fence) { |
1712fb1a | 3240 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
3241 | dma_fence_put(fence); |
3242 | fence = next; | |
1712fb1a | 3243 | if (tmo == 0) { |
3244 | r = -ETIMEDOUT; | |
c41d1cf6 | 3245 | break; |
1712fb1a | 3246 | } else if (tmo < 0) { |
3247 | r = tmo; | |
3248 | break; | |
3249 | } | |
403009bf CK |
3250 | } else { |
3251 | fence = next; | |
c41d1cf6 | 3252 | } |
c41d1cf6 ML |
3253 | } |
3254 | mutex_unlock(&adev->shadow_list_lock); | |
3255 | ||
403009bf CK |
3256 | if (fence) |
3257 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
3258 | dma_fence_put(fence); |
3259 | ||
1712fb1a | 3260 | if (r < 0 || tmo <= 0) { |
3261 | DRM_ERROR("recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); | |
403009bf CK |
3262 | return -EIO; |
3263 | } | |
c41d1cf6 | 3264 | |
403009bf CK |
3265 | DRM_INFO("recover vram bo from shadow done\n"); |
3266 | return 0; | |
c41d1cf6 ML |
3267 | } |
3268 | ||
a90ad3c2 | 3269 | |
e3ecdffa | 3270 | /** |
06ec9070 | 3271 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e ML |
3272 | * |
3273 | * @adev: amdgpu device pointer | |
87e3f136 | 3274 | * @from_hypervisor: request from hypervisor |
5740682e ML |
3275 | * |
3276 | * do VF FLR and reinitialize Asic | |
3f48c681 | 3277 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
3278 | */ |
3279 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
3280 | bool from_hypervisor) | |
5740682e ML |
3281 | { |
3282 | int r; | |
3283 | ||
3284 | if (from_hypervisor) | |
3285 | r = amdgpu_virt_request_full_gpu(adev, true); | |
3286 | else | |
3287 | r = amdgpu_virt_reset_gpu(adev); | |
3288 | if (r) | |
3289 | return r; | |
a90ad3c2 | 3290 | |
f81e8d53 WL |
3291 | amdgpu_amdkfd_pre_reset(adev); |
3292 | ||
a90ad3c2 | 3293 | /* Resume IP prior to SMC */ |
06ec9070 | 3294 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
3295 | if (r) |
3296 | goto error; | |
a90ad3c2 ML |
3297 | |
3298 | /* we need recover gart prior to run SMC/CP/SDMA resume */ | |
c1c7ce8f | 3299 | amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); |
a90ad3c2 | 3300 | |
7a3e0bb2 RZ |
3301 | r = amdgpu_device_fw_loading(adev); |
3302 | if (r) | |
3303 | return r; | |
3304 | ||
a90ad3c2 | 3305 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 3306 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
3307 | if (r) |
3308 | goto error; | |
a90ad3c2 ML |
3309 | |
3310 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 3311 | r = amdgpu_ib_ring_tests(adev); |
f81e8d53 | 3312 | amdgpu_amdkfd_post_reset(adev); |
a90ad3c2 | 3313 | |
abc34253 | 3314 | error: |
d3c117e5 | 3315 | amdgpu_virt_init_data_exchange(adev); |
abc34253 | 3316 | amdgpu_virt_release_full_gpu(adev, true); |
c41d1cf6 ML |
3317 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
3318 | atomic_inc(&adev->vram_lost_counter); | |
c33adbc7 | 3319 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 ML |
3320 | } |
3321 | ||
3322 | return r; | |
3323 | } | |
3324 | ||
12938fad CK |
3325 | /** |
3326 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
3327 | * | |
3328 | * @adev: amdgpu device pointer | |
3329 | * | |
3330 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
3331 | * a hung GPU. | |
3332 | */ | |
3333 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
3334 | { | |
3335 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
3336 | DRM_INFO("Timeout, but no hardware hang detected.\n"); | |
3337 | return false; | |
3338 | } | |
3339 | ||
3ba7b418 AG |
3340 | if (amdgpu_gpu_recovery == 0) |
3341 | goto disabled; | |
3342 | ||
3343 | if (amdgpu_sriov_vf(adev)) | |
3344 | return true; | |
3345 | ||
3346 | if (amdgpu_gpu_recovery == -1) { | |
3347 | switch (adev->asic_type) { | |
fc42d47c AG |
3348 | case CHIP_BONAIRE: |
3349 | case CHIP_HAWAII: | |
3ba7b418 AG |
3350 | case CHIP_TOPAZ: |
3351 | case CHIP_TONGA: | |
3352 | case CHIP_FIJI: | |
3353 | case CHIP_POLARIS10: | |
3354 | case CHIP_POLARIS11: | |
3355 | case CHIP_POLARIS12: | |
3356 | case CHIP_VEGAM: | |
3357 | case CHIP_VEGA20: | |
3358 | case CHIP_VEGA10: | |
3359 | case CHIP_VEGA12: | |
3360 | break; | |
3361 | default: | |
3362 | goto disabled; | |
3363 | } | |
12938fad CK |
3364 | } |
3365 | ||
3366 | return true; | |
3ba7b418 AG |
3367 | |
3368 | disabled: | |
3369 | DRM_INFO("GPU recovery disabled.\n"); | |
3370 | return false; | |
12938fad CK |
3371 | } |
3372 | ||
5c6dd71e | 3373 | |
26bc5340 AG |
3374 | static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
3375 | struct amdgpu_job *job, | |
3376 | bool *need_full_reset_arg) | |
3377 | { | |
3378 | int i, r = 0; | |
3379 | bool need_full_reset = *need_full_reset_arg; | |
71182665 | 3380 | |
71182665 | 3381 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
3382 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3383 | struct amdgpu_ring *ring = adev->rings[i]; | |
3384 | ||
51687759 | 3385 | if (!ring || !ring->sched.thread) |
0875dc9e | 3386 | continue; |
5740682e | 3387 | |
2f9d4084 ML |
3388 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
3389 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 3390 | } |
d38ceaf9 | 3391 | |
222b5f04 AG |
3392 | if(job) |
3393 | drm_sched_increase_karma(&job->base); | |
3394 | ||
1d721ed6 | 3395 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
3396 | if (!amdgpu_sriov_vf(adev)) { |
3397 | ||
3398 | if (!need_full_reset) | |
3399 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
3400 | ||
3401 | if (!need_full_reset) { | |
3402 | amdgpu_device_ip_pre_soft_reset(adev); | |
3403 | r = amdgpu_device_ip_soft_reset(adev); | |
3404 | amdgpu_device_ip_post_soft_reset(adev); | |
3405 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
3406 | DRM_INFO("soft reset failed, will fallback to full reset!\n"); | |
3407 | need_full_reset = true; | |
3408 | } | |
3409 | } | |
3410 | ||
3411 | if (need_full_reset) | |
3412 | r = amdgpu_device_ip_suspend(adev); | |
3413 | ||
3414 | *need_full_reset_arg = need_full_reset; | |
3415 | } | |
3416 | ||
3417 | return r; | |
3418 | } | |
3419 | ||
3420 | static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, | |
3421 | struct list_head *device_list_handle, | |
3422 | bool *need_full_reset_arg) | |
3423 | { | |
3424 | struct amdgpu_device *tmp_adev = NULL; | |
3425 | bool need_full_reset = *need_full_reset_arg, vram_lost = false; | |
3426 | int r = 0; | |
3427 | ||
3428 | /* | |
3429 | * ASIC reset has to be done on all HGMI hive nodes ASAP | |
3430 | * to allow proper links negotiation in FW (within 1 sec) | |
3431 | */ | |
3432 | if (need_full_reset) { | |
3433 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
d4535e2c AG |
3434 | /* For XGMI run all resets in parallel to speed up the process */ |
3435 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { | |
3436 | if (!queue_work(system_highpri_wq, &tmp_adev->xgmi_reset_work)) | |
3437 | r = -EALREADY; | |
3438 | } else | |
3439 | r = amdgpu_asic_reset(tmp_adev); | |
3440 | ||
3441 | if (r) { | |
fed184e9 | 3442 | DRM_ERROR("ASIC reset failed with error, %d for drm dev, %s", |
26bc5340 | 3443 | r, tmp_adev->ddev->unique); |
d4535e2c AG |
3444 | break; |
3445 | } | |
3446 | } | |
3447 | ||
3448 | /* For XGMI wait for all PSP resets to complete before proceed */ | |
3449 | if (!r) { | |
3450 | list_for_each_entry(tmp_adev, device_list_handle, | |
3451 | gmc.xgmi.head) { | |
3452 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { | |
3453 | flush_work(&tmp_adev->xgmi_reset_work); | |
3454 | r = tmp_adev->asic_reset_res; | |
3455 | if (r) | |
3456 | break; | |
3457 | } | |
3458 | } | |
2be4c4a9 | 3459 | |
3460 | list_for_each_entry(tmp_adev, device_list_handle, | |
3461 | gmc.xgmi.head) { | |
3462 | amdgpu_ras_reserve_bad_pages(tmp_adev); | |
3463 | } | |
26bc5340 AG |
3464 | } |
3465 | } | |
3466 | ||
3467 | ||
3468 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
3469 | if (need_full_reset) { | |
3470 | /* post card */ | |
3471 | if (amdgpu_atom_asic_init(tmp_adev->mode_info.atom_context)) | |
3472 | DRM_WARN("asic atom init failed!"); | |
3473 | ||
3474 | if (!r) { | |
3475 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); | |
3476 | r = amdgpu_device_ip_resume_phase1(tmp_adev); | |
3477 | if (r) | |
3478 | goto out; | |
3479 | ||
3480 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
3481 | if (vram_lost) { | |
77e7f829 | 3482 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
26bc5340 AG |
3483 | atomic_inc(&tmp_adev->vram_lost_counter); |
3484 | } | |
3485 | ||
3486 | r = amdgpu_gtt_mgr_recover( | |
3487 | &tmp_adev->mman.bdev.man[TTM_PL_TT]); | |
3488 | if (r) | |
3489 | goto out; | |
3490 | ||
3491 | r = amdgpu_device_fw_loading(tmp_adev); | |
3492 | if (r) | |
3493 | return r; | |
3494 | ||
3495 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
3496 | if (r) | |
3497 | goto out; | |
3498 | ||
3499 | if (vram_lost) | |
3500 | amdgpu_device_fill_reset_magic(tmp_adev); | |
3501 | ||
7c04ca50 | 3502 | r = amdgpu_device_ip_late_init(tmp_adev); |
3503 | if (r) | |
3504 | goto out; | |
3505 | ||
e79a04d5 | 3506 | /* must succeed. */ |
511fdbc3 | 3507 | amdgpu_ras_resume(tmp_adev); |
e79a04d5 | 3508 | |
26bc5340 AG |
3509 | /* Update PSP FW topology after reset */ |
3510 | if (hive && tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
3511 | r = amdgpu_xgmi_update_topology(hive, tmp_adev); | |
3512 | } | |
3513 | } | |
3514 | ||
3515 | ||
3516 | out: | |
3517 | if (!r) { | |
3518 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
3519 | r = amdgpu_ib_ring_tests(tmp_adev); | |
3520 | if (r) { | |
3521 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
3522 | r = amdgpu_device_ip_suspend(tmp_adev); | |
3523 | need_full_reset = true; | |
3524 | r = -EAGAIN; | |
3525 | goto end; | |
3526 | } | |
3527 | } | |
3528 | ||
3529 | if (!r) | |
3530 | r = amdgpu_device_recover_vram(tmp_adev); | |
3531 | else | |
3532 | tmp_adev->asic_reset_res = r; | |
3533 | } | |
3534 | ||
3535 | end: | |
3536 | *need_full_reset_arg = need_full_reset; | |
3537 | return r; | |
3538 | } | |
3539 | ||
1d721ed6 | 3540 | static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, bool trylock) |
26bc5340 | 3541 | { |
1d721ed6 AG |
3542 | if (trylock) { |
3543 | if (!mutex_trylock(&adev->lock_reset)) | |
3544 | return false; | |
3545 | } else | |
3546 | mutex_lock(&adev->lock_reset); | |
5740682e | 3547 | |
26bc5340 AG |
3548 | atomic_inc(&adev->gpu_reset_counter); |
3549 | adev->in_gpu_reset = 1; | |
7b184b00 | 3550 | /* Block kfd: SRIOV would do it separately */ |
3551 | if (!amdgpu_sriov_vf(adev)) | |
3552 | amdgpu_amdkfd_pre_reset(adev); | |
1d721ed6 AG |
3553 | |
3554 | return true; | |
26bc5340 | 3555 | } |
d38ceaf9 | 3556 | |
26bc5340 AG |
3557 | static void amdgpu_device_unlock_adev(struct amdgpu_device *adev) |
3558 | { | |
7b184b00 | 3559 | /*unlock kfd: SRIOV would do it separately */ |
3560 | if (!amdgpu_sriov_vf(adev)) | |
3561 | amdgpu_amdkfd_post_reset(adev); | |
89041940 | 3562 | amdgpu_vf_error_trans_all(adev); |
13a752e3 ML |
3563 | adev->in_gpu_reset = 0; |
3564 | mutex_unlock(&adev->lock_reset); | |
26bc5340 AG |
3565 | } |
3566 | ||
3567 | ||
3568 | /** | |
3569 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler | |
3570 | * | |
3571 | * @adev: amdgpu device pointer | |
3572 | * @job: which job trigger hang | |
3573 | * | |
3574 | * Attempt to reset the GPU if it has hung (all asics). | |
3575 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
3576 | * Returns 0 for success or an error on failure. | |
3577 | */ | |
3578 | ||
3579 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, | |
3580 | struct amdgpu_job *job) | |
3581 | { | |
1d721ed6 AG |
3582 | struct list_head device_list, *device_list_handle = NULL; |
3583 | bool need_full_reset, job_signaled; | |
26bc5340 | 3584 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 3585 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 3586 | int i, r = 0; |
26bc5340 | 3587 | |
1d721ed6 | 3588 | need_full_reset = job_signaled = false; |
26bc5340 AG |
3589 | INIT_LIST_HEAD(&device_list); |
3590 | ||
3591 | dev_info(adev->dev, "GPU reset begin!\n"); | |
3592 | ||
beff74bc | 3593 | cancel_delayed_work_sync(&adev->delayed_init_work); |
c53e4db7 | 3594 | |
1d721ed6 AG |
3595 | hive = amdgpu_get_xgmi_hive(adev, false); |
3596 | ||
26bc5340 | 3597 | /* |
1d721ed6 AG |
3598 | * Here we trylock to avoid chain of resets executing from |
3599 | * either trigger by jobs on different adevs in XGMI hive or jobs on | |
3600 | * different schedulers for same device while this TO handler is running. | |
3601 | * We always reset all schedulers for device and all devices for XGMI | |
3602 | * hive so that should take care of them too. | |
26bc5340 | 3603 | */ |
1d721ed6 AG |
3604 | |
3605 | if (hive && !mutex_trylock(&hive->reset_lock)) { | |
3606 | DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", | |
3607 | job->base.id, hive->hive_id); | |
26bc5340 | 3608 | return 0; |
1d721ed6 | 3609 | } |
26bc5340 AG |
3610 | |
3611 | /* Start with adev pre asic reset first for soft reset check.*/ | |
1d721ed6 AG |
3612 | if (!amdgpu_device_lock_adev(adev, !hive)) { |
3613 | DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress", | |
3614 | job->base.id); | |
3615 | return 0; | |
26bc5340 AG |
3616 | } |
3617 | ||
3618 | /* Build list of devices to reset */ | |
1d721ed6 | 3619 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
26bc5340 AG |
3620 | if (!hive) { |
3621 | amdgpu_device_unlock_adev(adev); | |
3622 | return -ENODEV; | |
3623 | } | |
3624 | ||
3625 | /* | |
3626 | * In case we are in XGMI hive mode device reset is done for all the | |
3627 | * nodes in the hive to retrain all XGMI links and hence the reset | |
3628 | * sequence is executed in loop on all nodes. | |
3629 | */ | |
3630 | device_list_handle = &hive->device_list; | |
3631 | } else { | |
3632 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
3633 | device_list_handle = &device_list; | |
3634 | } | |
3635 | ||
1d721ed6 AG |
3636 | /* block all schedulers and reset given job's ring */ |
3637 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
3638 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
3639 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
3640 | ||
3641 | if (!ring || !ring->sched.thread) | |
3642 | continue; | |
3643 | ||
3644 | drm_sched_stop(&ring->sched, &job->base); | |
3645 | } | |
3646 | } | |
3647 | ||
3648 | ||
3649 | /* | |
3650 | * Must check guilty signal here since after this point all old | |
3651 | * HW fences are force signaled. | |
3652 | * | |
3653 | * job->base holds a reference to parent fence | |
3654 | */ | |
3655 | if (job && job->base.s_fence->parent && | |
3656 | dma_fence_is_signaled(job->base.s_fence->parent)) | |
3657 | job_signaled = true; | |
3658 | ||
3659 | if (!amdgpu_device_ip_need_full_reset(adev)) | |
3660 | device_list_handle = &device_list; | |
3661 | ||
3662 | if (job_signaled) { | |
3663 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); | |
3664 | goto skip_hw_reset; | |
3665 | } | |
3666 | ||
3667 | ||
3668 | /* Guilty job will be freed after this*/ | |
3669 | r = amdgpu_device_pre_asic_reset(adev, | |
3670 | job, | |
3671 | &need_full_reset); | |
3672 | if (r) { | |
3673 | /*TODO Should we stop ?*/ | |
3674 | DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ", | |
3675 | r, adev->ddev->unique); | |
3676 | adev->asic_reset_res = r; | |
3677 | } | |
3678 | ||
26bc5340 AG |
3679 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
3680 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
3681 | ||
3682 | if (tmp_adev == adev) | |
3683 | continue; | |
3684 | ||
1d721ed6 | 3685 | amdgpu_device_lock_adev(tmp_adev, false); |
26bc5340 AG |
3686 | r = amdgpu_device_pre_asic_reset(tmp_adev, |
3687 | NULL, | |
3688 | &need_full_reset); | |
3689 | /*TODO Should we stop ?*/ | |
3690 | if (r) { | |
3691 | DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ", | |
3692 | r, tmp_adev->ddev->unique); | |
3693 | tmp_adev->asic_reset_res = r; | |
3694 | } | |
3695 | } | |
3696 | ||
3697 | /* Actual ASIC resets if needed.*/ | |
3698 | /* TODO Implement XGMI hive reset logic for SRIOV */ | |
3699 | if (amdgpu_sriov_vf(adev)) { | |
3700 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
3701 | if (r) | |
3702 | adev->asic_reset_res = r; | |
3703 | } else { | |
3704 | r = amdgpu_do_asic_reset(hive, device_list_handle, &need_full_reset); | |
3705 | if (r && r == -EAGAIN) | |
3706 | goto retry; | |
3707 | } | |
3708 | ||
1d721ed6 AG |
3709 | skip_hw_reset: |
3710 | ||
26bc5340 AG |
3711 | /* Post ASIC reset for all devs .*/ |
3712 | list_for_each_entry(tmp_adev, device_list_handle, gmc.xgmi.head) { | |
1d721ed6 AG |
3713 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
3714 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
3715 | ||
3716 | if (!ring || !ring->sched.thread) | |
3717 | continue; | |
3718 | ||
3719 | /* No point to resubmit jobs if we didn't HW reset*/ | |
3720 | if (!tmp_adev->asic_reset_res && !job_signaled) | |
3721 | drm_sched_resubmit_jobs(&ring->sched); | |
3722 | ||
3723 | drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); | |
3724 | } | |
3725 | ||
3726 | if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) { | |
3727 | drm_helper_resume_force_mode(tmp_adev->ddev); | |
3728 | } | |
3729 | ||
3730 | tmp_adev->asic_reset_res = 0; | |
26bc5340 AG |
3731 | |
3732 | if (r) { | |
3733 | /* bad news, how to tell it to userspace ? */ | |
3734 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter)); | |
3735 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); | |
3736 | } else { | |
3737 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&adev->gpu_reset_counter)); | |
3738 | } | |
3739 | ||
3740 | amdgpu_device_unlock_adev(tmp_adev); | |
3741 | } | |
3742 | ||
1d721ed6 | 3743 | if (hive) |
22d6575b | 3744 | mutex_unlock(&hive->reset_lock); |
26bc5340 AG |
3745 | |
3746 | if (r) | |
3747 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); | |
d38ceaf9 AD |
3748 | return r; |
3749 | } | |
3750 | ||
e3ecdffa AD |
3751 | /** |
3752 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
3753 | * | |
3754 | * @adev: amdgpu_device pointer | |
3755 | * | |
3756 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
3757 | * and lanes) of the slot the device is in. Handles APUs and | |
3758 | * virtualized environments where PCIE config space may not be available. | |
3759 | */ | |
5494d864 | 3760 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 3761 | { |
5d9a6330 | 3762 | struct pci_dev *pdev; |
c5313457 HK |
3763 | enum pci_bus_speed speed_cap, platform_speed_cap; |
3764 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 3765 | |
cd474ba0 AD |
3766 | if (amdgpu_pcie_gen_cap) |
3767 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 3768 | |
cd474ba0 AD |
3769 | if (amdgpu_pcie_lane_cap) |
3770 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 3771 | |
cd474ba0 AD |
3772 | /* covers APUs as well */ |
3773 | if (pci_is_root_bus(adev->pdev->bus)) { | |
3774 | if (adev->pm.pcie_gen_mask == 0) | |
3775 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
3776 | if (adev->pm.pcie_mlw_mask == 0) | |
3777 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 3778 | return; |
cd474ba0 | 3779 | } |
d0dd7f0c | 3780 | |
c5313457 HK |
3781 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
3782 | return; | |
3783 | ||
dbaa922b AD |
3784 | pcie_bandwidth_available(adev->pdev, NULL, |
3785 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 3786 | |
cd474ba0 | 3787 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
3788 | /* asic caps */ |
3789 | pdev = adev->pdev; | |
3790 | speed_cap = pcie_get_speed_cap(pdev); | |
3791 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
3792 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
3793 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
3794 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 3795 | } else { |
5d9a6330 AD |
3796 | if (speed_cap == PCIE_SPEED_16_0GT) |
3797 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3798 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3799 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
3800 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
3801 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
3802 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3803 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3804 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
3805 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
3806 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
3807 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
3808 | else | |
3809 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3810 | } | |
3811 | /* platform caps */ | |
c5313457 | 3812 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
3813 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
3814 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
3815 | } else { | |
c5313457 | 3816 | if (platform_speed_cap == PCIE_SPEED_16_0GT) |
5d9a6330 AD |
3817 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
3818 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3819 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
3820 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 3821 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
3822 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
3823 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
3824 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 3825 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
3826 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
3827 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
3828 | else | |
3829 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
3830 | ||
cd474ba0 AD |
3831 | } |
3832 | } | |
3833 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 3834 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
3835 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
3836 | } else { | |
c5313457 | 3837 | switch (platform_link_width) { |
5d9a6330 | 3838 | case PCIE_LNK_X32: |
cd474ba0 AD |
3839 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
3840 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
3841 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3842 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3843 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3844 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3845 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3846 | break; | |
5d9a6330 | 3847 | case PCIE_LNK_X16: |
cd474ba0 AD |
3848 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
3849 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
3850 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3851 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3852 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3853 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3854 | break; | |
5d9a6330 | 3855 | case PCIE_LNK_X12: |
cd474ba0 AD |
3856 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
3857 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
3858 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3859 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3860 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3861 | break; | |
5d9a6330 | 3862 | case PCIE_LNK_X8: |
cd474ba0 AD |
3863 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
3864 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
3865 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3866 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3867 | break; | |
5d9a6330 | 3868 | case PCIE_LNK_X4: |
cd474ba0 AD |
3869 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
3870 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
3871 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3872 | break; | |
5d9a6330 | 3873 | case PCIE_LNK_X2: |
cd474ba0 AD |
3874 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
3875 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
3876 | break; | |
5d9a6330 | 3877 | case PCIE_LNK_X1: |
cd474ba0 AD |
3878 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
3879 | break; | |
3880 | default: | |
3881 | break; | |
3882 | } | |
d0dd7f0c AD |
3883 | } |
3884 | } | |
3885 | } | |
d38ceaf9 | 3886 |