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drm/amdgpu: fix coding style in amdgpu_object.c
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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
0875dc9e 28#include <linux/kthread.h>
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29#include <linux/console.h>
30#include <linux/slab.h>
31#include <linux/debugfs.h>
32#include <drm/drmP.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/amdgpu_drm.h>
35#include <linux/vgaarb.h>
36#include <linux/vga_switcheroo.h>
37#include <linux/efi.h>
38#include "amdgpu.h"
f4b373f4 39#include "amdgpu_trace.h"
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40#include "amdgpu_i2c.h"
41#include "atom.h"
42#include "amdgpu_atombios.h"
d0dd7f0c 43#include "amd_pcie.h"
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44#ifdef CONFIG_DRM_AMDGPU_CIK
45#include "cik.h"
46#endif
aaa36a97 47#include "vi.h"
d38ceaf9 48#include "bif/bif_4_1_d.h"
9accf2fd 49#include <linux/pci.h>
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50
51static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
52static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
53
54static const char *amdgpu_asic_name[] = {
55 "BONAIRE",
56 "KAVERI",
57 "KABINI",
58 "HAWAII",
59 "MULLINS",
60 "TOPAZ",
61 "TONGA",
48299f95 62 "FIJI",
d38ceaf9 63 "CARRIZO",
139f4917 64 "STONEY",
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65 "POLARIS10",
66 "POLARIS11",
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67 "LAST",
68};
69
70bool amdgpu_device_is_px(struct drm_device *dev)
71{
72 struct amdgpu_device *adev = dev->dev_private;
73
2f7d10b3 74 if (adev->flags & AMD_IS_PX)
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75 return true;
76 return false;
77}
78
79/*
80 * MMIO register access helper functions.
81 */
82uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
83 bool always_indirect)
84{
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85 uint32_t ret;
86
d38ceaf9 87 if ((reg * 4) < adev->rmmio_size && !always_indirect)
f4b373f4 88 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
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89 else {
90 unsigned long flags;
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91
92 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
93 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
94 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
95 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
d38ceaf9 96 }
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97 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
98 return ret;
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99}
100
101void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
102 bool always_indirect)
103{
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104 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
105
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106 if ((reg * 4) < adev->rmmio_size && !always_indirect)
107 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
108 else {
109 unsigned long flags;
110
111 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
112 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
113 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
114 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
115 }
116}
117
118u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
119{
120 if ((reg * 4) < adev->rio_mem_size)
121 return ioread32(adev->rio_mem + (reg * 4));
122 else {
123 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
124 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
125 }
126}
127
128void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
129{
130
131 if ((reg * 4) < adev->rio_mem_size)
132 iowrite32(v, adev->rio_mem + (reg * 4));
133 else {
134 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
135 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
136 }
137}
138
139/**
140 * amdgpu_mm_rdoorbell - read a doorbell dword
141 *
142 * @adev: amdgpu_device pointer
143 * @index: doorbell index
144 *
145 * Returns the value in the doorbell aperture at the
146 * requested doorbell index (CIK).
147 */
148u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
149{
150 if (index < adev->doorbell.num_doorbells) {
151 return readl(adev->doorbell.ptr + index);
152 } else {
153 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
154 return 0;
155 }
156}
157
158/**
159 * amdgpu_mm_wdoorbell - write a doorbell dword
160 *
161 * @adev: amdgpu_device pointer
162 * @index: doorbell index
163 * @v: value to write
164 *
165 * Writes @v to the doorbell aperture at the
166 * requested doorbell index (CIK).
167 */
168void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
169{
170 if (index < adev->doorbell.num_doorbells) {
171 writel(v, adev->doorbell.ptr + index);
172 } else {
173 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
174 }
175}
176
177/**
178 * amdgpu_invalid_rreg - dummy reg read function
179 *
180 * @adev: amdgpu device pointer
181 * @reg: offset of register
182 *
183 * Dummy register read function. Used for register blocks
184 * that certain asics don't have (all asics).
185 * Returns the value in the register.
186 */
187static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
188{
189 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
190 BUG();
191 return 0;
192}
193
194/**
195 * amdgpu_invalid_wreg - dummy reg write function
196 *
197 * @adev: amdgpu device pointer
198 * @reg: offset of register
199 * @v: value to write to the register
200 *
201 * Dummy register read function. Used for register blocks
202 * that certain asics don't have (all asics).
203 */
204static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
205{
206 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
207 reg, v);
208 BUG();
209}
210
211/**
212 * amdgpu_block_invalid_rreg - dummy reg read function
213 *
214 * @adev: amdgpu device pointer
215 * @block: offset of instance
216 * @reg: offset of register
217 *
218 * Dummy register read function. Used for register blocks
219 * that certain asics don't have (all asics).
220 * Returns the value in the register.
221 */
222static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
223 uint32_t block, uint32_t reg)
224{
225 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
226 reg, block);
227 BUG();
228 return 0;
229}
230
231/**
232 * amdgpu_block_invalid_wreg - dummy reg write function
233 *
234 * @adev: amdgpu device pointer
235 * @block: offset of instance
236 * @reg: offset of register
237 * @v: value to write to the register
238 *
239 * Dummy register read function. Used for register blocks
240 * that certain asics don't have (all asics).
241 */
242static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
243 uint32_t block,
244 uint32_t reg, uint32_t v)
245{
246 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
247 reg, block, v);
248 BUG();
249}
250
251static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
252{
253 int r;
254
255 if (adev->vram_scratch.robj == NULL) {
256 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
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257 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
258 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b 259 NULL, NULL, &adev->vram_scratch.robj);
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260 if (r) {
261 return r;
262 }
263 }
264
265 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
266 if (unlikely(r != 0))
267 return r;
268 r = amdgpu_bo_pin(adev->vram_scratch.robj,
269 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
270 if (r) {
271 amdgpu_bo_unreserve(adev->vram_scratch.robj);
272 return r;
273 }
274 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
275 (void **)&adev->vram_scratch.ptr);
276 if (r)
277 amdgpu_bo_unpin(adev->vram_scratch.robj);
278 amdgpu_bo_unreserve(adev->vram_scratch.robj);
279
280 return r;
281}
282
283static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
284{
285 int r;
286
287 if (adev->vram_scratch.robj == NULL) {
288 return;
289 }
290 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
291 if (likely(r == 0)) {
292 amdgpu_bo_kunmap(adev->vram_scratch.robj);
293 amdgpu_bo_unpin(adev->vram_scratch.robj);
294 amdgpu_bo_unreserve(adev->vram_scratch.robj);
295 }
296 amdgpu_bo_unref(&adev->vram_scratch.robj);
297}
298
299/**
300 * amdgpu_program_register_sequence - program an array of registers.
301 *
302 * @adev: amdgpu_device pointer
303 * @registers: pointer to the register array
304 * @array_size: size of the register array
305 *
306 * Programs an array or registers with and and or masks.
307 * This is a helper for setting golden registers.
308 */
309void amdgpu_program_register_sequence(struct amdgpu_device *adev,
310 const u32 *registers,
311 const u32 array_size)
312{
313 u32 tmp, reg, and_mask, or_mask;
314 int i;
315
316 if (array_size % 3)
317 return;
318
319 for (i = 0; i < array_size; i +=3) {
320 reg = registers[i + 0];
321 and_mask = registers[i + 1];
322 or_mask = registers[i + 2];
323
324 if (and_mask == 0xffffffff) {
325 tmp = or_mask;
326 } else {
327 tmp = RREG32(reg);
328 tmp &= ~and_mask;
329 tmp |= or_mask;
330 }
331 WREG32(reg, tmp);
332 }
333}
334
335void amdgpu_pci_config_reset(struct amdgpu_device *adev)
336{
337 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
338}
339
340/*
341 * GPU doorbell aperture helpers function.
342 */
343/**
344 * amdgpu_doorbell_init - Init doorbell driver information.
345 *
346 * @adev: amdgpu_device pointer
347 *
348 * Init doorbell driver information (CIK)
349 * Returns 0 on success, error on failure.
350 */
351static int amdgpu_doorbell_init(struct amdgpu_device *adev)
352{
353 /* doorbell bar mapping */
354 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
355 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
356
edf600da 357 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
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358 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
359 if (adev->doorbell.num_doorbells == 0)
360 return -EINVAL;
361
362 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
363 if (adev->doorbell.ptr == NULL) {
364 return -ENOMEM;
365 }
366 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
367 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
368
369 return 0;
370}
371
372/**
373 * amdgpu_doorbell_fini - Tear down doorbell driver information.
374 *
375 * @adev: amdgpu_device pointer
376 *
377 * Tear down doorbell driver information (CIK)
378 */
379static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
380{
381 iounmap(adev->doorbell.ptr);
382 adev->doorbell.ptr = NULL;
383}
384
385/**
386 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
387 * setup amdkfd
388 *
389 * @adev: amdgpu_device pointer
390 * @aperture_base: output returning doorbell aperture base physical address
391 * @aperture_size: output returning doorbell aperture size in bytes
392 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
393 *
394 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
395 * takes doorbells required for its own rings and reports the setup to amdkfd.
396 * amdgpu reserved doorbells are at the start of the doorbell aperture.
397 */
398void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
399 phys_addr_t *aperture_base,
400 size_t *aperture_size,
401 size_t *start_offset)
402{
403 /*
404 * The first num_doorbells are used by amdgpu.
405 * amdkfd takes whatever's left in the aperture.
406 */
407 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
408 *aperture_base = adev->doorbell.base;
409 *aperture_size = adev->doorbell.size;
410 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
411 } else {
412 *aperture_base = 0;
413 *aperture_size = 0;
414 *start_offset = 0;
415 }
416}
417
418/*
419 * amdgpu_wb_*()
420 * Writeback is the the method by which the the GPU updates special pages
421 * in memory with the status of certain GPU events (fences, ring pointers,
422 * etc.).
423 */
424
425/**
426 * amdgpu_wb_fini - Disable Writeback and free memory
427 *
428 * @adev: amdgpu_device pointer
429 *
430 * Disables Writeback and frees the Writeback memory (all asics).
431 * Used at driver shutdown.
432 */
433static void amdgpu_wb_fini(struct amdgpu_device *adev)
434{
435 if (adev->wb.wb_obj) {
436 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
437 amdgpu_bo_kunmap(adev->wb.wb_obj);
438 amdgpu_bo_unpin(adev->wb.wb_obj);
439 amdgpu_bo_unreserve(adev->wb.wb_obj);
440 }
441 amdgpu_bo_unref(&adev->wb.wb_obj);
442 adev->wb.wb = NULL;
443 adev->wb.wb_obj = NULL;
444 }
445}
446
447/**
448 * amdgpu_wb_init- Init Writeback driver info and allocate memory
449 *
450 * @adev: amdgpu_device pointer
451 *
452 * Disables Writeback and frees the Writeback memory (all asics).
453 * Used at driver startup.
454 * Returns 0 on success or an -error on failure.
455 */
456static int amdgpu_wb_init(struct amdgpu_device *adev)
457{
458 int r;
459
460 if (adev->wb.wb_obj == NULL) {
461 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
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462 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
463 &adev->wb.wb_obj);
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464 if (r) {
465 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
466 return r;
467 }
468 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
469 if (unlikely(r != 0)) {
470 amdgpu_wb_fini(adev);
471 return r;
472 }
473 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
474 &adev->wb.gpu_addr);
475 if (r) {
476 amdgpu_bo_unreserve(adev->wb.wb_obj);
477 dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
478 amdgpu_wb_fini(adev);
479 return r;
480 }
481 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
482 amdgpu_bo_unreserve(adev->wb.wb_obj);
483 if (r) {
484 dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
485 amdgpu_wb_fini(adev);
486 return r;
487 }
488
489 adev->wb.num_wb = AMDGPU_MAX_WB;
490 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
491
492 /* clear wb memory */
493 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
494 }
495
496 return 0;
497}
498
499/**
500 * amdgpu_wb_get - Allocate a wb entry
501 *
502 * @adev: amdgpu_device pointer
503 * @wb: wb index
504 *
505 * Allocate a wb slot for use by the driver (all asics).
506 * Returns 0 on success or -EINVAL on failure.
507 */
508int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
509{
510 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
511 if (offset < adev->wb.num_wb) {
512 __set_bit(offset, adev->wb.used);
513 *wb = offset;
514 return 0;
515 } else {
516 return -EINVAL;
517 }
518}
519
520/**
521 * amdgpu_wb_free - Free a wb entry
522 *
523 * @adev: amdgpu_device pointer
524 * @wb: wb index
525 *
526 * Free a wb slot allocated for use by the driver (all asics)
527 */
528void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
529{
530 if (wb < adev->wb.num_wb)
531 __clear_bit(wb, adev->wb.used);
532}
533
534/**
535 * amdgpu_vram_location - try to find VRAM location
536 * @adev: amdgpu device structure holding all necessary informations
537 * @mc: memory controller structure holding memory informations
538 * @base: base address at which to put VRAM
539 *
540 * Function will place try to place VRAM at base address provided
541 * as parameter (which is so far either PCI aperture address or
542 * for IGP TOM base address).
543 *
544 * If there is not enough space to fit the unvisible VRAM in the 32bits
545 * address space then we limit the VRAM size to the aperture.
546 *
547 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
548 * this shouldn't be a problem as we are using the PCI aperture as a reference.
549 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
550 * not IGP.
551 *
552 * Note: we use mc_vram_size as on some board we need to program the mc to
553 * cover the whole aperture even if VRAM size is inferior to aperture size
554 * Novell bug 204882 + along with lots of ubuntu ones
555 *
556 * Note: when limiting vram it's safe to overwritte real_vram_size because
557 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
558 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
559 * ones)
560 *
561 * Note: IGP TOM addr should be the same as the aperture addr, we don't
562 * explicitly check for that thought.
563 *
564 * FIXME: when reducing VRAM size align new size on power of 2.
565 */
566void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
567{
568 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
569
570 mc->vram_start = base;
571 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
572 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
573 mc->real_vram_size = mc->aper_size;
574 mc->mc_vram_size = mc->aper_size;
575 }
576 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
577 if (limit && limit < mc->real_vram_size)
578 mc->real_vram_size = limit;
579 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
580 mc->mc_vram_size >> 20, mc->vram_start,
581 mc->vram_end, mc->real_vram_size >> 20);
582}
583
584/**
585 * amdgpu_gtt_location - try to find GTT location
586 * @adev: amdgpu device structure holding all necessary informations
587 * @mc: memory controller structure holding memory informations
588 *
589 * Function will place try to place GTT before or after VRAM.
590 *
591 * If GTT size is bigger than space left then we ajust GTT size.
592 * Thus function will never fails.
593 *
594 * FIXME: when reducing GTT size align new size on power of 2.
595 */
596void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
597{
598 u64 size_af, size_bf;
599
600 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
601 size_bf = mc->vram_start & ~mc->gtt_base_align;
602 if (size_bf > size_af) {
603 if (mc->gtt_size > size_bf) {
604 dev_warn(adev->dev, "limiting GTT\n");
605 mc->gtt_size = size_bf;
606 }
607 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
608 } else {
609 if (mc->gtt_size > size_af) {
610 dev_warn(adev->dev, "limiting GTT\n");
611 mc->gtt_size = size_af;
612 }
613 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
614 }
615 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
616 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
617 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
618}
619
620/*
621 * GPU helpers function.
622 */
623/**
624 * amdgpu_card_posted - check if the hw has already been initialized
625 *
626 * @adev: amdgpu_device pointer
627 *
628 * Check if the asic has been initialized (all asics).
629 * Used at driver startup.
630 * Returns true if initialized or false if not.
631 */
632bool amdgpu_card_posted(struct amdgpu_device *adev)
633{
634 uint32_t reg;
635
636 /* then check MEM_SIZE, in case the crtcs are off */
637 reg = RREG32(mmCONFIG_MEMSIZE);
638
639 if (reg)
640 return true;
641
642 return false;
643
644}
645
d38ceaf9
AD
646/**
647 * amdgpu_dummy_page_init - init dummy page used by the driver
648 *
649 * @adev: amdgpu_device pointer
650 *
651 * Allocate the dummy page used by the driver (all asics).
652 * This dummy page is used by the driver as a filler for gart entries
653 * when pages are taken out of the GART
654 * Returns 0 on sucess, -ENOMEM on failure.
655 */
656int amdgpu_dummy_page_init(struct amdgpu_device *adev)
657{
658 if (adev->dummy_page.page)
659 return 0;
660 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
661 if (adev->dummy_page.page == NULL)
662 return -ENOMEM;
663 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
664 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
665 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
666 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
667 __free_page(adev->dummy_page.page);
668 adev->dummy_page.page = NULL;
669 return -ENOMEM;
670 }
671 return 0;
672}
673
674/**
675 * amdgpu_dummy_page_fini - free dummy page used by the driver
676 *
677 * @adev: amdgpu_device pointer
678 *
679 * Frees the dummy page used by the driver (all asics).
680 */
681void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
682{
683 if (adev->dummy_page.page == NULL)
684 return;
685 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
686 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
687 __free_page(adev->dummy_page.page);
688 adev->dummy_page.page = NULL;
689}
690
691
692/* ATOM accessor methods */
693/*
694 * ATOM is an interpreted byte code stored in tables in the vbios. The
695 * driver registers callbacks to access registers and the interpreter
696 * in the driver parses the tables and executes then to program specific
697 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
698 * atombios.h, and atom.c
699 */
700
701/**
702 * cail_pll_read - read PLL register
703 *
704 * @info: atom card_info pointer
705 * @reg: PLL register offset
706 *
707 * Provides a PLL register accessor for the atom interpreter (r4xx+).
708 * Returns the value of the PLL register.
709 */
710static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
711{
712 return 0;
713}
714
715/**
716 * cail_pll_write - write PLL register
717 *
718 * @info: atom card_info pointer
719 * @reg: PLL register offset
720 * @val: value to write to the pll register
721 *
722 * Provides a PLL register accessor for the atom interpreter (r4xx+).
723 */
724static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
725{
726
727}
728
729/**
730 * cail_mc_read - read MC (Memory Controller) register
731 *
732 * @info: atom card_info pointer
733 * @reg: MC register offset
734 *
735 * Provides an MC register accessor for the atom interpreter (r4xx+).
736 * Returns the value of the MC register.
737 */
738static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
739{
740 return 0;
741}
742
743/**
744 * cail_mc_write - write MC (Memory Controller) register
745 *
746 * @info: atom card_info pointer
747 * @reg: MC register offset
748 * @val: value to write to the pll register
749 *
750 * Provides a MC register accessor for the atom interpreter (r4xx+).
751 */
752static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
753{
754
755}
756
757/**
758 * cail_reg_write - write MMIO register
759 *
760 * @info: atom card_info pointer
761 * @reg: MMIO register offset
762 * @val: value to write to the pll register
763 *
764 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
765 */
766static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
767{
768 struct amdgpu_device *adev = info->dev->dev_private;
769
770 WREG32(reg, val);
771}
772
773/**
774 * cail_reg_read - read MMIO register
775 *
776 * @info: atom card_info pointer
777 * @reg: MMIO register offset
778 *
779 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
780 * Returns the value of the MMIO register.
781 */
782static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
783{
784 struct amdgpu_device *adev = info->dev->dev_private;
785 uint32_t r;
786
787 r = RREG32(reg);
788 return r;
789}
790
791/**
792 * cail_ioreg_write - write IO register
793 *
794 * @info: atom card_info pointer
795 * @reg: IO register offset
796 * @val: value to write to the pll register
797 *
798 * Provides a IO register accessor for the atom interpreter (r4xx+).
799 */
800static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
801{
802 struct amdgpu_device *adev = info->dev->dev_private;
803
804 WREG32_IO(reg, val);
805}
806
807/**
808 * cail_ioreg_read - read IO register
809 *
810 * @info: atom card_info pointer
811 * @reg: IO register offset
812 *
813 * Provides an IO register accessor for the atom interpreter (r4xx+).
814 * Returns the value of the IO register.
815 */
816static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
817{
818 struct amdgpu_device *adev = info->dev->dev_private;
819 uint32_t r;
820
821 r = RREG32_IO(reg);
822 return r;
823}
824
825/**
826 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
827 *
828 * @adev: amdgpu_device pointer
829 *
830 * Frees the driver info and register access callbacks for the ATOM
831 * interpreter (r4xx+).
832 * Called at driver shutdown.
833 */
834static void amdgpu_atombios_fini(struct amdgpu_device *adev)
835{
89e0ec9f 836 if (adev->mode_info.atom_context) {
d38ceaf9 837 kfree(adev->mode_info.atom_context->scratch);
89e0ec9f
ML
838 kfree(adev->mode_info.atom_context->iio);
839 }
d38ceaf9
AD
840 kfree(adev->mode_info.atom_context);
841 adev->mode_info.atom_context = NULL;
842 kfree(adev->mode_info.atom_card_info);
843 adev->mode_info.atom_card_info = NULL;
844}
845
846/**
847 * amdgpu_atombios_init - init the driver info and callbacks for atombios
848 *
849 * @adev: amdgpu_device pointer
850 *
851 * Initializes the driver info and register access callbacks for the
852 * ATOM interpreter (r4xx+).
853 * Returns 0 on sucess, -ENOMEM on failure.
854 * Called at driver startup.
855 */
856static int amdgpu_atombios_init(struct amdgpu_device *adev)
857{
858 struct card_info *atom_card_info =
859 kzalloc(sizeof(struct card_info), GFP_KERNEL);
860
861 if (!atom_card_info)
862 return -ENOMEM;
863
864 adev->mode_info.atom_card_info = atom_card_info;
865 atom_card_info->dev = adev->ddev;
866 atom_card_info->reg_read = cail_reg_read;
867 atom_card_info->reg_write = cail_reg_write;
868 /* needed for iio ops */
869 if (adev->rio_mem) {
870 atom_card_info->ioreg_read = cail_ioreg_read;
871 atom_card_info->ioreg_write = cail_ioreg_write;
872 } else {
873 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
874 atom_card_info->ioreg_read = cail_reg_read;
875 atom_card_info->ioreg_write = cail_reg_write;
876 }
877 atom_card_info->mc_read = cail_mc_read;
878 atom_card_info->mc_write = cail_mc_write;
879 atom_card_info->pll_read = cail_pll_read;
880 atom_card_info->pll_write = cail_pll_write;
881
882 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
883 if (!adev->mode_info.atom_context) {
884 amdgpu_atombios_fini(adev);
885 return -ENOMEM;
886 }
887
888 mutex_init(&adev->mode_info.atom_context->mutex);
889 amdgpu_atombios_scratch_regs_init(adev);
890 amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
891 return 0;
892}
893
894/* if we get transitioned to only one device, take VGA back */
895/**
896 * amdgpu_vga_set_decode - enable/disable vga decode
897 *
898 * @cookie: amdgpu_device pointer
899 * @state: enable/disable vga decode
900 *
901 * Enable/disable vga decode (all asics).
902 * Returns VGA resource flags.
903 */
904static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
905{
906 struct amdgpu_device *adev = cookie;
907 amdgpu_asic_set_vga_state(adev, state);
908 if (state)
909 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
910 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
911 else
912 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
913}
914
915/**
916 * amdgpu_check_pot_argument - check that argument is a power of two
917 *
918 * @arg: value to check
919 *
920 * Validates that a certain argument is a power of two (all asics).
921 * Returns true if argument is valid.
922 */
923static bool amdgpu_check_pot_argument(int arg)
924{
925 return (arg & (arg - 1)) == 0;
926}
927
928/**
929 * amdgpu_check_arguments - validate module params
930 *
931 * @adev: amdgpu_device pointer
932 *
933 * Validates certain module parameters and updates
934 * the associated values used by the driver (all asics).
935 */
936static void amdgpu_check_arguments(struct amdgpu_device *adev)
937{
5b011235
CZ
938 if (amdgpu_sched_jobs < 4) {
939 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
940 amdgpu_sched_jobs);
941 amdgpu_sched_jobs = 4;
942 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
943 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
944 amdgpu_sched_jobs);
945 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
946 }
d38ceaf9
AD
947
948 if (amdgpu_gart_size != -1) {
c4e1a13a 949 /* gtt size must be greater or equal to 32M */
d38ceaf9
AD
950 if (amdgpu_gart_size < 32) {
951 dev_warn(adev->dev, "gart size (%d) too small\n",
952 amdgpu_gart_size);
953 amdgpu_gart_size = -1;
d38ceaf9
AD
954 }
955 }
956
957 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
958 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
959 amdgpu_vm_size);
8dacc127 960 amdgpu_vm_size = 8;
d38ceaf9
AD
961 }
962
963 if (amdgpu_vm_size < 1) {
964 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
965 amdgpu_vm_size);
8dacc127 966 amdgpu_vm_size = 8;
d38ceaf9
AD
967 }
968
969 /*
970 * Max GPUVM size for Cayman, SI and CI are 40 bits.
971 */
972 if (amdgpu_vm_size > 1024) {
973 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
974 amdgpu_vm_size);
8dacc127 975 amdgpu_vm_size = 8;
d38ceaf9
AD
976 }
977
978 /* defines number of bits in page table versus page directory,
979 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
980 * page table and the remaining bits are in the page directory */
981 if (amdgpu_vm_block_size == -1) {
982
983 /* Total bits covered by PD + PTs */
984 unsigned bits = ilog2(amdgpu_vm_size) + 18;
985
986 /* Make sure the PD is 4K in size up to 8GB address space.
987 Above that split equal between PD and PTs */
988 if (amdgpu_vm_size <= 8)
989 amdgpu_vm_block_size = bits - 9;
990 else
991 amdgpu_vm_block_size = (bits + 3) / 2;
992
993 } else if (amdgpu_vm_block_size < 9) {
994 dev_warn(adev->dev, "VM page table size (%d) too small\n",
995 amdgpu_vm_block_size);
996 amdgpu_vm_block_size = 9;
997 }
998
999 if (amdgpu_vm_block_size > 24 ||
1000 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1001 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1002 amdgpu_vm_block_size);
1003 amdgpu_vm_block_size = 9;
1004 }
1005}
1006
1007/**
1008 * amdgpu_switcheroo_set_state - set switcheroo state
1009 *
1010 * @pdev: pci dev pointer
1694467b 1011 * @state: vga_switcheroo state
d38ceaf9
AD
1012 *
1013 * Callback for the switcheroo driver. Suspends or resumes the
1014 * the asics before or after it is powered up using ACPI methods.
1015 */
1016static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1017{
1018 struct drm_device *dev = pci_get_drvdata(pdev);
1019
1020 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1021 return;
1022
1023 if (state == VGA_SWITCHEROO_ON) {
1024 unsigned d3_delay = dev->pdev->d3_delay;
1025
1026 printk(KERN_INFO "amdgpu: switched on\n");
1027 /* don't suspend or resume card normally */
1028 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1029
1030 amdgpu_resume_kms(dev, true, true);
1031
1032 dev->pdev->d3_delay = d3_delay;
1033
1034 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1035 drm_kms_helper_poll_enable(dev);
1036 } else {
1037 printk(KERN_INFO "amdgpu: switched off\n");
1038 drm_kms_helper_poll_disable(dev);
1039 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1040 amdgpu_suspend_kms(dev, true, true);
1041 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1042 }
1043}
1044
1045/**
1046 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1047 *
1048 * @pdev: pci dev pointer
1049 *
1050 * Callback for the switcheroo driver. Check of the switcheroo
1051 * state can be changed.
1052 * Returns true if the state can be changed, false if not.
1053 */
1054static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1055{
1056 struct drm_device *dev = pci_get_drvdata(pdev);
1057
1058 /*
1059 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1060 * locking inversion with the driver load path. And the access here is
1061 * completely racy anyway. So don't bother with locking for now.
1062 */
1063 return dev->open_count == 0;
1064}
1065
1066static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1067 .set_gpu_state = amdgpu_switcheroo_set_state,
1068 .reprobe = NULL,
1069 .can_switch = amdgpu_switcheroo_can_switch,
1070};
1071
1072int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 1073 enum amd_ip_block_type block_type,
1074 enum amd_clockgating_state state)
d38ceaf9
AD
1075{
1076 int i, r = 0;
1077
1078 for (i = 0; i < adev->num_ip_blocks; i++) {
9ecbe7f5
AD
1079 if (!adev->ip_block_status[i].valid)
1080 continue;
d38ceaf9 1081 if (adev->ip_blocks[i].type == block_type) {
5fc3aeeb 1082 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
d38ceaf9
AD
1083 state);
1084 if (r)
1085 return r;
a225bf1c 1086 break;
d38ceaf9
AD
1087 }
1088 }
1089 return r;
1090}
1091
1092int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 1093 enum amd_ip_block_type block_type,
1094 enum amd_powergating_state state)
d38ceaf9
AD
1095{
1096 int i, r = 0;
1097
1098 for (i = 0; i < adev->num_ip_blocks; i++) {
9ecbe7f5
AD
1099 if (!adev->ip_block_status[i].valid)
1100 continue;
d38ceaf9 1101 if (adev->ip_blocks[i].type == block_type) {
5fc3aeeb 1102 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
d38ceaf9
AD
1103 state);
1104 if (r)
1105 return r;
a225bf1c 1106 break;
d38ceaf9
AD
1107 }
1108 }
1109 return r;
1110}
1111
5dbbb60b
AD
1112int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1113 enum amd_ip_block_type block_type)
1114{
1115 int i, r;
1116
1117 for (i = 0; i < adev->num_ip_blocks; i++) {
9ecbe7f5
AD
1118 if (!adev->ip_block_status[i].valid)
1119 continue;
5dbbb60b
AD
1120 if (adev->ip_blocks[i].type == block_type) {
1121 r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev);
1122 if (r)
1123 return r;
1124 break;
1125 }
1126 }
1127 return 0;
1128
1129}
1130
1131bool amdgpu_is_idle(struct amdgpu_device *adev,
1132 enum amd_ip_block_type block_type)
1133{
1134 int i;
1135
1136 for (i = 0; i < adev->num_ip_blocks; i++) {
9ecbe7f5
AD
1137 if (!adev->ip_block_status[i].valid)
1138 continue;
5dbbb60b
AD
1139 if (adev->ip_blocks[i].type == block_type)
1140 return adev->ip_blocks[i].funcs->is_idle((void *)adev);
1141 }
1142 return true;
1143
1144}
1145
d38ceaf9
AD
1146const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1147 struct amdgpu_device *adev,
5fc3aeeb 1148 enum amd_ip_block_type type)
d38ceaf9
AD
1149{
1150 int i;
1151
1152 for (i = 0; i < adev->num_ip_blocks; i++)
1153 if (adev->ip_blocks[i].type == type)
1154 return &adev->ip_blocks[i];
1155
1156 return NULL;
1157}
1158
1159/**
1160 * amdgpu_ip_block_version_cmp
1161 *
1162 * @adev: amdgpu_device pointer
5fc3aeeb 1163 * @type: enum amd_ip_block_type
d38ceaf9
AD
1164 * @major: major version
1165 * @minor: minor version
1166 *
1167 * return 0 if equal or greater
1168 * return 1 if smaller or the ip_block doesn't exist
1169 */
1170int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 1171 enum amd_ip_block_type type,
d38ceaf9
AD
1172 u32 major, u32 minor)
1173{
1174 const struct amdgpu_ip_block_version *ip_block;
1175 ip_block = amdgpu_get_ip_block(adev, type);
1176
1177 if (ip_block && ((ip_block->major > major) ||
1178 ((ip_block->major == major) &&
1179 (ip_block->minor >= minor))))
1180 return 0;
1181
1182 return 1;
1183}
1184
9accf2fd
ED
1185static void amdgpu_whether_enable_virtual_display(struct amdgpu_device *adev)
1186{
1187 adev->enable_virtual_display = false;
1188
1189 if (amdgpu_virtual_display) {
1190 struct drm_device *ddev = adev->ddev;
1191 const char *pci_address_name = pci_name(ddev->pdev);
1192 char *pciaddstr, *pciaddstr_tmp, *pciaddname;
1193
1194 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1195 pciaddstr_tmp = pciaddstr;
1196 while ((pciaddname = strsep(&pciaddstr_tmp, ";"))) {
1197 if (!strcmp(pci_address_name, pciaddname)) {
1198 adev->enable_virtual_display = true;
1199 break;
1200 }
1201 }
1202
1203 DRM_INFO("virtual display string:%s, %s:virtual_display:%d\n",
1204 amdgpu_virtual_display, pci_address_name,
1205 adev->enable_virtual_display);
1206
1207 kfree(pciaddstr);
1208 }
1209}
1210
d38ceaf9
AD
1211static int amdgpu_early_init(struct amdgpu_device *adev)
1212{
aaa36a97 1213 int i, r;
d38ceaf9 1214
9accf2fd 1215 amdgpu_whether_enable_virtual_display(adev);
a6be7570 1216
d38ceaf9 1217 switch (adev->asic_type) {
aaa36a97
AD
1218 case CHIP_TOPAZ:
1219 case CHIP_TONGA:
48299f95 1220 case CHIP_FIJI:
2cc0c0b5
FC
1221 case CHIP_POLARIS11:
1222 case CHIP_POLARIS10:
aaa36a97 1223 case CHIP_CARRIZO:
39bb0c92
SL
1224 case CHIP_STONEY:
1225 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
aaa36a97
AD
1226 adev->family = AMDGPU_FAMILY_CZ;
1227 else
1228 adev->family = AMDGPU_FAMILY_VI;
1229
1230 r = vi_set_ip_blocks(adev);
1231 if (r)
1232 return r;
1233 break;
a2e73f56
AD
1234#ifdef CONFIG_DRM_AMDGPU_CIK
1235 case CHIP_BONAIRE:
1236 case CHIP_HAWAII:
1237 case CHIP_KAVERI:
1238 case CHIP_KABINI:
1239 case CHIP_MULLINS:
1240 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1241 adev->family = AMDGPU_FAMILY_CI;
1242 else
1243 adev->family = AMDGPU_FAMILY_KV;
1244
1245 r = cik_set_ip_blocks(adev);
1246 if (r)
1247 return r;
1248 break;
1249#endif
d38ceaf9
AD
1250 default:
1251 /* FIXME: not supported yet */
1252 return -EINVAL;
1253 }
1254
8faf0e08
AD
1255 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1256 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1257 if (adev->ip_block_status == NULL)
d8d090b7 1258 return -ENOMEM;
d38ceaf9
AD
1259
1260 if (adev->ip_blocks == NULL) {
1261 DRM_ERROR("No IP blocks found!\n");
1262 return r;
1263 }
1264
1265 for (i = 0; i < adev->num_ip_blocks; i++) {
1266 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1267 DRM_ERROR("disabled ip block: %d\n", i);
8faf0e08 1268 adev->ip_block_status[i].valid = false;
d38ceaf9
AD
1269 } else {
1270 if (adev->ip_blocks[i].funcs->early_init) {
5fc3aeeb 1271 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
2c1a2784 1272 if (r == -ENOENT) {
8faf0e08 1273 adev->ip_block_status[i].valid = false;
2c1a2784 1274 } else if (r) {
88a907d6 1275 DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
d38ceaf9 1276 return r;
2c1a2784 1277 } else {
8faf0e08 1278 adev->ip_block_status[i].valid = true;
2c1a2784 1279 }
974e6b64 1280 } else {
8faf0e08 1281 adev->ip_block_status[i].valid = true;
d38ceaf9 1282 }
d38ceaf9
AD
1283 }
1284 }
1285
395d1fb9
NH
1286 adev->cg_flags &= amdgpu_cg_mask;
1287 adev->pg_flags &= amdgpu_pg_mask;
1288
d38ceaf9
AD
1289 return 0;
1290}
1291
1292static int amdgpu_init(struct amdgpu_device *adev)
1293{
1294 int i, r;
1295
1296 for (i = 0; i < adev->num_ip_blocks; i++) {
8faf0e08 1297 if (!adev->ip_block_status[i].valid)
d38ceaf9 1298 continue;
5fc3aeeb 1299 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
2c1a2784 1300 if (r) {
822b2cef 1301 DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
d38ceaf9 1302 return r;
2c1a2784 1303 }
8faf0e08 1304 adev->ip_block_status[i].sw = true;
d38ceaf9 1305 /* need to do gmc hw init early so we can allocate gpu mem */
5fc3aeeb 1306 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
d38ceaf9 1307 r = amdgpu_vram_scratch_init(adev);
2c1a2784
AD
1308 if (r) {
1309 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
d38ceaf9 1310 return r;
2c1a2784 1311 }
5fc3aeeb 1312 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
2c1a2784
AD
1313 if (r) {
1314 DRM_ERROR("hw_init %d failed %d\n", i, r);
d38ceaf9 1315 return r;
2c1a2784 1316 }
d38ceaf9 1317 r = amdgpu_wb_init(adev);
2c1a2784
AD
1318 if (r) {
1319 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
d38ceaf9 1320 return r;
2c1a2784 1321 }
8faf0e08 1322 adev->ip_block_status[i].hw = true;
d38ceaf9
AD
1323 }
1324 }
1325
1326 for (i = 0; i < adev->num_ip_blocks; i++) {
8faf0e08 1327 if (!adev->ip_block_status[i].sw)
d38ceaf9
AD
1328 continue;
1329 /* gmc hw init is done early */
5fc3aeeb 1330 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
d38ceaf9 1331 continue;
5fc3aeeb 1332 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
2c1a2784 1333 if (r) {
822b2cef 1334 DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
d38ceaf9 1335 return r;
2c1a2784 1336 }
8faf0e08 1337 adev->ip_block_status[i].hw = true;
d38ceaf9
AD
1338 }
1339
1340 return 0;
1341}
1342
1343static int amdgpu_late_init(struct amdgpu_device *adev)
1344{
1345 int i = 0, r;
1346
1347 for (i = 0; i < adev->num_ip_blocks; i++) {
8faf0e08 1348 if (!adev->ip_block_status[i].valid)
d38ceaf9
AD
1349 continue;
1350 /* enable clockgating to save power */
5fc3aeeb 1351 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1352 AMD_CG_STATE_GATE);
2c1a2784 1353 if (r) {
822b2cef 1354 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
d38ceaf9 1355 return r;
2c1a2784 1356 }
d38ceaf9 1357 if (adev->ip_blocks[i].funcs->late_init) {
5fc3aeeb 1358 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
2c1a2784 1359 if (r) {
822b2cef 1360 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
d38ceaf9 1361 return r;
2c1a2784 1362 }
d38ceaf9
AD
1363 }
1364 }
1365
1366 return 0;
1367}
1368
1369static int amdgpu_fini(struct amdgpu_device *adev)
1370{
1371 int i, r;
1372
1373 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
8faf0e08 1374 if (!adev->ip_block_status[i].hw)
d38ceaf9 1375 continue;
5fc3aeeb 1376 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
d38ceaf9
AD
1377 amdgpu_wb_fini(adev);
1378 amdgpu_vram_scratch_fini(adev);
1379 }
1380 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
5fc3aeeb 1381 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1382 AMD_CG_STATE_UNGATE);
2c1a2784 1383 if (r) {
822b2cef 1384 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
d38ceaf9 1385 return r;
2c1a2784 1386 }
5fc3aeeb 1387 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
d38ceaf9 1388 /* XXX handle errors */
2c1a2784 1389 if (r) {
822b2cef 1390 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
2c1a2784 1391 }
8faf0e08 1392 adev->ip_block_status[i].hw = false;
d38ceaf9
AD
1393 }
1394
1395 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
8faf0e08 1396 if (!adev->ip_block_status[i].sw)
d38ceaf9 1397 continue;
5fc3aeeb 1398 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
d38ceaf9 1399 /* XXX handle errors */
2c1a2784 1400 if (r) {
822b2cef 1401 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
2c1a2784 1402 }
8faf0e08
AD
1403 adev->ip_block_status[i].sw = false;
1404 adev->ip_block_status[i].valid = false;
d38ceaf9
AD
1405 }
1406
a6dcfd9c
ML
1407 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1408 if (adev->ip_blocks[i].funcs->late_fini)
1409 adev->ip_blocks[i].funcs->late_fini((void *)adev);
1410 }
1411
d38ceaf9
AD
1412 return 0;
1413}
1414
1415static int amdgpu_suspend(struct amdgpu_device *adev)
1416{
1417 int i, r;
1418
c5a93a28
FC
1419 /* ungate SMC block first */
1420 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1421 AMD_CG_STATE_UNGATE);
1422 if (r) {
1423 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1424 }
1425
d38ceaf9 1426 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
8faf0e08 1427 if (!adev->ip_block_status[i].valid)
d38ceaf9
AD
1428 continue;
1429 /* ungate blocks so that suspend can properly shut them down */
c5a93a28
FC
1430 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1431 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1432 AMD_CG_STATE_UNGATE);
1433 if (r) {
822b2cef 1434 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
c5a93a28 1435 }
2c1a2784 1436 }
d38ceaf9
AD
1437 /* XXX handle errors */
1438 r = adev->ip_blocks[i].funcs->suspend(adev);
1439 /* XXX handle errors */
2c1a2784 1440 if (r) {
822b2cef 1441 DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
2c1a2784 1442 }
d38ceaf9
AD
1443 }
1444
1445 return 0;
1446}
1447
1448static int amdgpu_resume(struct amdgpu_device *adev)
1449{
1450 int i, r;
1451
1452 for (i = 0; i < adev->num_ip_blocks; i++) {
8faf0e08 1453 if (!adev->ip_block_status[i].valid)
d38ceaf9
AD
1454 continue;
1455 r = adev->ip_blocks[i].funcs->resume(adev);
2c1a2784 1456 if (r) {
822b2cef 1457 DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
d38ceaf9 1458 return r;
2c1a2784 1459 }
d38ceaf9
AD
1460 }
1461
1462 return 0;
1463}
1464
048765ad
AR
1465static bool amdgpu_device_is_virtual(void)
1466{
1467#ifdef CONFIG_X86
1468 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
1469#else
1470 return false;
1471#endif
1472}
1473
d38ceaf9
AD
1474/**
1475 * amdgpu_device_init - initialize the driver
1476 *
1477 * @adev: amdgpu_device pointer
1478 * @pdev: drm dev pointer
1479 * @pdev: pci dev pointer
1480 * @flags: driver flags
1481 *
1482 * Initializes the driver info and hw (all asics).
1483 * Returns 0 for success or an error on failure.
1484 * Called at driver startup.
1485 */
1486int amdgpu_device_init(struct amdgpu_device *adev,
1487 struct drm_device *ddev,
1488 struct pci_dev *pdev,
1489 uint32_t flags)
1490{
1491 int r, i;
1492 bool runtime = false;
1493
1494 adev->shutdown = false;
1495 adev->dev = &pdev->dev;
1496 adev->ddev = ddev;
1497 adev->pdev = pdev;
1498 adev->flags = flags;
2f7d10b3 1499 adev->asic_type = flags & AMD_ASIC_MASK;
d38ceaf9
AD
1500 adev->is_atom_bios = false;
1501 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1502 adev->mc.gtt_size = 512 * 1024 * 1024;
1503 adev->accel_working = false;
1504 adev->num_rings = 0;
1505 adev->mman.buffer_funcs = NULL;
1506 adev->mman.buffer_funcs_ring = NULL;
1507 adev->vm_manager.vm_pte_funcs = NULL;
2d55e45a 1508 adev->vm_manager.vm_pte_num_rings = 0;
d38ceaf9
AD
1509 adev->gart.gart_funcs = NULL;
1510 adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1511
1512 adev->smc_rreg = &amdgpu_invalid_rreg;
1513 adev->smc_wreg = &amdgpu_invalid_wreg;
1514 adev->pcie_rreg = &amdgpu_invalid_rreg;
1515 adev->pcie_wreg = &amdgpu_invalid_wreg;
1516 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1517 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1518 adev->didt_rreg = &amdgpu_invalid_rreg;
1519 adev->didt_wreg = &amdgpu_invalid_wreg;
ccdbb20a
RZ
1520 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1521 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
d38ceaf9
AD
1522 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1523 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1524
ccdbb20a 1525
3e39ab90
AD
1526 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1527 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1528 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
d38ceaf9
AD
1529
1530 /* mutex initialization are all done here so we
1531 * can recall function without having locking issues */
8d0a7cea 1532 mutex_init(&adev->vm_manager.lock);
d38ceaf9 1533 atomic_set(&adev->irq.ih.lock, 0);
d38ceaf9
AD
1534 mutex_init(&adev->pm.mutex);
1535 mutex_init(&adev->gfx.gpu_clock_mutex);
1536 mutex_init(&adev->srbm_mutex);
1537 mutex_init(&adev->grbm_idx_mutex);
d38ceaf9
AD
1538 mutex_init(&adev->mn_lock);
1539 hash_init(adev->mn_hash);
1540
1541 amdgpu_check_arguments(adev);
1542
1543 /* Registers mapping */
1544 /* TODO: block userspace mapping of io register */
1545 spin_lock_init(&adev->mmio_idx_lock);
1546 spin_lock_init(&adev->smc_idx_lock);
1547 spin_lock_init(&adev->pcie_idx_lock);
1548 spin_lock_init(&adev->uvd_ctx_idx_lock);
1549 spin_lock_init(&adev->didt_idx_lock);
ccdbb20a 1550 spin_lock_init(&adev->gc_cac_idx_lock);
d38ceaf9
AD
1551 spin_lock_init(&adev->audio_endpt_idx_lock);
1552
1553 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1554 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1555 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1556 if (adev->rmmio == NULL) {
1557 return -ENOMEM;
1558 }
1559 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1560 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1561
1562 /* doorbell bar mapping */
1563 amdgpu_doorbell_init(adev);
1564
1565 /* io port mapping */
1566 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1567 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1568 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1569 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1570 break;
1571 }
1572 }
1573 if (adev->rio_mem == NULL)
1574 DRM_ERROR("Unable to find PCI I/O BAR\n");
1575
1576 /* early init functions */
1577 r = amdgpu_early_init(adev);
1578 if (r)
1579 return r;
1580
1581 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1582 /* this will fail for cards that aren't VGA class devices, just
1583 * ignore it */
1584 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1585
1586 if (amdgpu_runtime_pm == 1)
1587 runtime = true;
e9bef455 1588 if (amdgpu_device_is_px(ddev))
d38ceaf9
AD
1589 runtime = true;
1590 vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1591 if (runtime)
1592 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1593
1594 /* Read BIOS */
83ba126a
AD
1595 if (!amdgpu_get_bios(adev)) {
1596 r = -EINVAL;
1597 goto failed;
1598 }
d38ceaf9
AD
1599 /* Must be an ATOMBIOS */
1600 if (!adev->is_atom_bios) {
1601 dev_err(adev->dev, "Expecting atombios for GPU\n");
83ba126a
AD
1602 r = -EINVAL;
1603 goto failed;
d38ceaf9
AD
1604 }
1605 r = amdgpu_atombios_init(adev);
2c1a2784
AD
1606 if (r) {
1607 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
83ba126a 1608 goto failed;
2c1a2784 1609 }
d38ceaf9 1610
7e471e6f
AD
1611 /* See if the asic supports SR-IOV */
1612 adev->virtualization.supports_sr_iov =
1613 amdgpu_atombios_has_gpu_virtualization_table(adev);
1614
048765ad
AR
1615 /* Check if we are executing in a virtualized environment */
1616 adev->virtualization.is_virtual = amdgpu_device_is_virtual();
1617 adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev);
1618
d38ceaf9 1619 /* Post card if necessary */
048765ad
AR
1620 if (!amdgpu_card_posted(adev) ||
1621 (adev->virtualization.is_virtual &&
48a70e1c 1622 !(adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN))) {
d38ceaf9
AD
1623 if (!adev->bios) {
1624 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
83ba126a
AD
1625 r = -EINVAL;
1626 goto failed;
d38ceaf9
AD
1627 }
1628 DRM_INFO("GPU not posted. posting now...\n");
1629 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1630 }
1631
1632 /* Initialize clocks */
1633 r = amdgpu_atombios_get_clock_info(adev);
2c1a2784
AD
1634 if (r) {
1635 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
83ba126a 1636 goto failed;
2c1a2784 1637 }
d38ceaf9
AD
1638 /* init i2c buses */
1639 amdgpu_atombios_i2c_init(adev);
1640
1641 /* Fence driver */
1642 r = amdgpu_fence_driver_init(adev);
2c1a2784
AD
1643 if (r) {
1644 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
83ba126a 1645 goto failed;
2c1a2784 1646 }
d38ceaf9
AD
1647
1648 /* init the mode config */
1649 drm_mode_config_init(adev->ddev);
1650
1651 r = amdgpu_init(adev);
1652 if (r) {
2c1a2784 1653 dev_err(adev->dev, "amdgpu_init failed\n");
d38ceaf9 1654 amdgpu_fini(adev);
83ba126a 1655 goto failed;
d38ceaf9
AD
1656 }
1657
1658 adev->accel_working = true;
1659
1660 amdgpu_fbdev_init(adev);
1661
1662 r = amdgpu_ib_pool_init(adev);
1663 if (r) {
1664 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
83ba126a 1665 goto failed;
d38ceaf9
AD
1666 }
1667
1668 r = amdgpu_ib_ring_tests(adev);
1669 if (r)
1670 DRM_ERROR("ib ring test failed (%d).\n", r);
1671
1672 r = amdgpu_gem_debugfs_init(adev);
1673 if (r) {
1674 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1675 }
1676
1677 r = amdgpu_debugfs_regs_init(adev);
1678 if (r) {
1679 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1680 }
1681
50ab2533
HR
1682 r = amdgpu_debugfs_firmware_init(adev);
1683 if (r) {
1684 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1685 return r;
1686 }
1687
d38ceaf9
AD
1688 if ((amdgpu_testing & 1)) {
1689 if (adev->accel_working)
1690 amdgpu_test_moves(adev);
1691 else
1692 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1693 }
1694 if ((amdgpu_testing & 2)) {
1695 if (adev->accel_working)
1696 amdgpu_test_syncing(adev);
1697 else
1698 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1699 }
1700 if (amdgpu_benchmarking) {
1701 if (adev->accel_working)
1702 amdgpu_benchmark(adev, amdgpu_benchmarking);
1703 else
1704 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1705 }
1706
1707 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1708 * explicit gating rather than handling it automatically.
1709 */
1710 r = amdgpu_late_init(adev);
2c1a2784
AD
1711 if (r) {
1712 dev_err(adev->dev, "amdgpu_late_init failed\n");
83ba126a 1713 goto failed;
2c1a2784 1714 }
d38ceaf9
AD
1715
1716 return 0;
83ba126a
AD
1717
1718failed:
1719 if (runtime)
1720 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1721 return r;
d38ceaf9
AD
1722}
1723
1724static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1725
1726/**
1727 * amdgpu_device_fini - tear down the driver
1728 *
1729 * @adev: amdgpu_device pointer
1730 *
1731 * Tear down the driver info (all asics).
1732 * Called at driver shutdown.
1733 */
1734void amdgpu_device_fini(struct amdgpu_device *adev)
1735{
1736 int r;
1737
1738 DRM_INFO("amdgpu: finishing device.\n");
1739 adev->shutdown = true;
1740 /* evict vram memory */
1741 amdgpu_bo_evict_vram(adev);
1742 amdgpu_ib_pool_fini(adev);
1743 amdgpu_fence_driver_fini(adev);
84b89bdc 1744 drm_crtc_force_disable_all(adev->ddev);
d38ceaf9
AD
1745 amdgpu_fbdev_fini(adev);
1746 r = amdgpu_fini(adev);
8faf0e08
AD
1747 kfree(adev->ip_block_status);
1748 adev->ip_block_status = NULL;
d38ceaf9
AD
1749 adev->accel_working = false;
1750 /* free i2c buses */
1751 amdgpu_i2c_fini(adev);
1752 amdgpu_atombios_fini(adev);
1753 kfree(adev->bios);
1754 adev->bios = NULL;
1755 vga_switcheroo_unregister_client(adev->pdev);
83ba126a
AD
1756 if (adev->flags & AMD_IS_PX)
1757 vga_switcheroo_fini_domain_pm_ops(adev->dev);
d38ceaf9
AD
1758 vga_client_register(adev->pdev, NULL, NULL, NULL);
1759 if (adev->rio_mem)
1760 pci_iounmap(adev->pdev, adev->rio_mem);
1761 adev->rio_mem = NULL;
1762 iounmap(adev->rmmio);
1763 adev->rmmio = NULL;
1764 amdgpu_doorbell_fini(adev);
1765 amdgpu_debugfs_regs_cleanup(adev);
1766 amdgpu_debugfs_remove_files(adev);
1767}
1768
1769
1770/*
1771 * Suspend & resume.
1772 */
1773/**
1774 * amdgpu_suspend_kms - initiate device suspend
1775 *
1776 * @pdev: drm dev pointer
1777 * @state: suspend state
1778 *
1779 * Puts the hw in the suspend state (all asics).
1780 * Returns 0 for success or an error on failure.
1781 * Called at driver suspend.
1782 */
1783int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1784{
1785 struct amdgpu_device *adev;
1786 struct drm_crtc *crtc;
1787 struct drm_connector *connector;
5ceb54c6 1788 int r;
d38ceaf9
AD
1789
1790 if (dev == NULL || dev->dev_private == NULL) {
1791 return -ENODEV;
1792 }
1793
1794 adev = dev->dev_private;
1795
1796 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1797 return 0;
1798
1799 drm_kms_helper_poll_disable(dev);
1800
1801 /* turn off display hw */
4c7fbc39 1802 drm_modeset_lock_all(dev);
d38ceaf9
AD
1803 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1804 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1805 }
4c7fbc39 1806 drm_modeset_unlock_all(dev);
d38ceaf9 1807
756e6880 1808 /* unpin the front buffers and cursors */
d38ceaf9 1809 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
756e6880 1810 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
d38ceaf9
AD
1811 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1812 struct amdgpu_bo *robj;
1813
756e6880
AD
1814 if (amdgpu_crtc->cursor_bo) {
1815 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1816 r = amdgpu_bo_reserve(aobj, false);
1817 if (r == 0) {
1818 amdgpu_bo_unpin(aobj);
1819 amdgpu_bo_unreserve(aobj);
1820 }
1821 }
1822
d38ceaf9
AD
1823 if (rfb == NULL || rfb->obj == NULL) {
1824 continue;
1825 }
1826 robj = gem_to_amdgpu_bo(rfb->obj);
1827 /* don't unpin kernel fb objects */
1828 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1829 r = amdgpu_bo_reserve(robj, false);
1830 if (r == 0) {
1831 amdgpu_bo_unpin(robj);
1832 amdgpu_bo_unreserve(robj);
1833 }
1834 }
1835 }
1836 /* evict vram memory */
1837 amdgpu_bo_evict_vram(adev);
1838
5ceb54c6 1839 amdgpu_fence_driver_suspend(adev);
d38ceaf9
AD
1840
1841 r = amdgpu_suspend(adev);
1842
1843 /* evict remaining vram memory */
1844 amdgpu_bo_evict_vram(adev);
1845
1846 pci_save_state(dev->pdev);
1847 if (suspend) {
1848 /* Shut down the device */
1849 pci_disable_device(dev->pdev);
1850 pci_set_power_state(dev->pdev, PCI_D3hot);
1851 }
1852
1853 if (fbcon) {
1854 console_lock();
1855 amdgpu_fbdev_set_suspend(adev, 1);
1856 console_unlock();
1857 }
1858 return 0;
1859}
1860
1861/**
1862 * amdgpu_resume_kms - initiate device resume
1863 *
1864 * @pdev: drm dev pointer
1865 *
1866 * Bring the hw back to operating state (all asics).
1867 * Returns 0 for success or an error on failure.
1868 * Called at driver resume.
1869 */
1870int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1871{
1872 struct drm_connector *connector;
1873 struct amdgpu_device *adev = dev->dev_private;
756e6880 1874 struct drm_crtc *crtc;
d38ceaf9
AD
1875 int r;
1876
1877 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1878 return 0;
1879
1880 if (fbcon) {
1881 console_lock();
1882 }
1883 if (resume) {
1884 pci_set_power_state(dev->pdev, PCI_D0);
1885 pci_restore_state(dev->pdev);
1886 if (pci_enable_device(dev->pdev)) {
1887 if (fbcon)
1888 console_unlock();
1889 return -1;
1890 }
1891 }
1892
1893 /* post card */
ca198528
FC
1894 if (!amdgpu_card_posted(adev))
1895 amdgpu_atom_asic_init(adev->mode_info.atom_context);
d38ceaf9
AD
1896
1897 r = amdgpu_resume(adev);
ca198528
FC
1898 if (r)
1899 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
d38ceaf9 1900
5ceb54c6
AD
1901 amdgpu_fence_driver_resume(adev);
1902
ca198528
FC
1903 if (resume) {
1904 r = amdgpu_ib_ring_tests(adev);
1905 if (r)
1906 DRM_ERROR("ib ring test failed (%d).\n", r);
1907 }
d38ceaf9
AD
1908
1909 r = amdgpu_late_init(adev);
1910 if (r)
1911 return r;
1912
756e6880
AD
1913 /* pin cursors */
1914 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1915 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1916
1917 if (amdgpu_crtc->cursor_bo) {
1918 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1919 r = amdgpu_bo_reserve(aobj, false);
1920 if (r == 0) {
1921 r = amdgpu_bo_pin(aobj,
1922 AMDGPU_GEM_DOMAIN_VRAM,
1923 &amdgpu_crtc->cursor_addr);
1924 if (r != 0)
1925 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1926 amdgpu_bo_unreserve(aobj);
1927 }
1928 }
1929 }
1930
d38ceaf9
AD
1931 /* blat the mode back in */
1932 if (fbcon) {
1933 drm_helper_resume_force_mode(dev);
1934 /* turn on display hw */
4c7fbc39 1935 drm_modeset_lock_all(dev);
d38ceaf9
AD
1936 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1937 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1938 }
4c7fbc39 1939 drm_modeset_unlock_all(dev);
d38ceaf9
AD
1940 }
1941
1942 drm_kms_helper_poll_enable(dev);
23a1a9e5
L
1943
1944 /*
1945 * Most of the connector probing functions try to acquire runtime pm
1946 * refs to ensure that the GPU is powered on when connector polling is
1947 * performed. Since we're calling this from a runtime PM callback,
1948 * trying to acquire rpm refs will cause us to deadlock.
1949 *
1950 * Since we're guaranteed to be holding the rpm lock, it's safe to
1951 * temporarily disable the rpm helpers so this doesn't deadlock us.
1952 */
1953#ifdef CONFIG_PM
1954 dev->dev->power.disable_depth++;
1955#endif
54fb2a5c 1956 drm_helper_hpd_irq_event(dev);
23a1a9e5
L
1957#ifdef CONFIG_PM
1958 dev->dev->power.disable_depth--;
1959#endif
d38ceaf9
AD
1960
1961 if (fbcon) {
1962 amdgpu_fbdev_set_suspend(adev, 0);
1963 console_unlock();
1964 }
1965
1966 return 0;
1967}
1968
63fbf42f
CZ
1969static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
1970{
1971 int i;
1972 bool asic_hang = false;
1973
1974 for (i = 0; i < adev->num_ip_blocks; i++) {
1975 if (!adev->ip_block_status[i].valid)
1976 continue;
1977 if (adev->ip_blocks[i].funcs->check_soft_reset)
1978 adev->ip_blocks[i].funcs->check_soft_reset(adev);
1979 if (adev->ip_block_status[i].hang) {
1980 DRM_INFO("IP block:%d is hang!\n", i);
1981 asic_hang = true;
1982 }
1983 }
1984 return asic_hang;
1985}
1986
d31a501e
CZ
1987int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
1988{
1989 int i, r = 0;
1990
1991 for (i = 0; i < adev->num_ip_blocks; i++) {
1992 if (!adev->ip_block_status[i].valid)
1993 continue;
35d782fe
CZ
1994 if (adev->ip_block_status[i].hang &&
1995 adev->ip_blocks[i].funcs->pre_soft_reset) {
d31a501e
CZ
1996 r = adev->ip_blocks[i].funcs->pre_soft_reset(adev);
1997 if (r)
1998 return r;
1999 }
2000 }
2001
2002 return 0;
2003}
2004
35d782fe
CZ
2005static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2006{
2007 if (adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang ||
35d782fe 2008 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SMC].hang ||
35d782fe
CZ
2009 adev->ip_block_status[AMD_IP_BLOCK_TYPE_ACP].hang ||
2010 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang) {
2011 DRM_INFO("Some block need full reset!\n");
2012 return true;
2013 }
2014 return false;
2015}
2016
2017static int amdgpu_soft_reset(struct amdgpu_device *adev)
2018{
2019 int i, r = 0;
2020
2021 for (i = 0; i < adev->num_ip_blocks; i++) {
2022 if (!adev->ip_block_status[i].valid)
2023 continue;
2024 if (adev->ip_block_status[i].hang &&
2025 adev->ip_blocks[i].funcs->soft_reset) {
2026 r = adev->ip_blocks[i].funcs->soft_reset(adev);
2027 if (r)
2028 return r;
2029 }
2030 }
2031
2032 return 0;
2033}
2034
2035static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2036{
2037 int i, r = 0;
2038
2039 for (i = 0; i < adev->num_ip_blocks; i++) {
2040 if (!adev->ip_block_status[i].valid)
2041 continue;
2042 if (adev->ip_block_status[i].hang &&
2043 adev->ip_blocks[i].funcs->post_soft_reset)
2044 r = adev->ip_blocks[i].funcs->post_soft_reset(adev);
2045 if (r)
2046 return r;
2047 }
2048
2049 return 0;
2050}
2051
d38ceaf9
AD
2052/**
2053 * amdgpu_gpu_reset - reset the asic
2054 *
2055 * @adev: amdgpu device pointer
2056 *
2057 * Attempt the reset the GPU if it has hung (all asics).
2058 * Returns 0 for success or an error on failure.
2059 */
2060int amdgpu_gpu_reset(struct amdgpu_device *adev)
2061{
d38ceaf9
AD
2062 int i, r;
2063 int resched;
35d782fe 2064 bool need_full_reset;
d38ceaf9 2065
63fbf42f
CZ
2066 if (!amdgpu_check_soft_reset(adev)) {
2067 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2068 return 0;
2069 }
2070
d94aed5a 2071 atomic_inc(&adev->gpu_reset_counter);
d38ceaf9 2072
a3c47d6b
CZ
2073 /* block TTM */
2074 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2075
0875dc9e
CZ
2076 /* block scheduler */
2077 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2078 struct amdgpu_ring *ring = adev->rings[i];
2079
2080 if (!ring)
2081 continue;
2082 kthread_park(ring->sched.thread);
aa1c8900 2083 amd_sched_hw_job_reset(&ring->sched);
0875dc9e 2084 }
2200edac
CZ
2085 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2086 amdgpu_fence_driver_force_completion(adev);
d38ceaf9 2087
35d782fe 2088 need_full_reset = amdgpu_need_full_reset(adev);
d38ceaf9 2089
35d782fe
CZ
2090 if (!need_full_reset) {
2091 amdgpu_pre_soft_reset(adev);
2092 r = amdgpu_soft_reset(adev);
2093 amdgpu_post_soft_reset(adev);
2094 if (r || amdgpu_check_soft_reset(adev)) {
2095 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2096 need_full_reset = true;
2097 }
f1aa7e08
CZ
2098 }
2099
35d782fe
CZ
2100 if (need_full_reset) {
2101 /* save scratch */
2102 amdgpu_atombios_scratch_regs_save(adev);
2103 r = amdgpu_suspend(adev);
bfa99269 2104
35d782fe
CZ
2105retry:
2106 /* Disable fb access */
2107 if (adev->mode_info.num_crtc) {
2108 struct amdgpu_mode_mc_save save;
2109 amdgpu_display_stop_mc_access(adev, &save);
2110 amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2111 }
2112
2113 r = amdgpu_asic_reset(adev);
2114 /* post card */
2115 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2116
2117 if (!r) {
2118 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2119 r = amdgpu_resume(adev);
2120 }
2121 /* restore scratch */
2122 amdgpu_atombios_scratch_regs_restore(adev);
d38ceaf9 2123 }
d38ceaf9 2124 if (!r) {
e72cfd58 2125 amdgpu_irq_gpu_reset_resume_helper(adev);
1f465087
CZ
2126 r = amdgpu_ib_ring_tests(adev);
2127 if (r) {
2128 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
40019dc4
CZ
2129 r = amdgpu_suspend(adev);
2130 goto retry;
1f465087
CZ
2131 }
2132
d38ceaf9
AD
2133 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2134 struct amdgpu_ring *ring = adev->rings[i];
2135 if (!ring)
2136 continue;
aa1c8900 2137 amd_sched_job_recovery(&ring->sched);
0875dc9e 2138 kthread_unpark(ring->sched.thread);
d38ceaf9 2139 }
d38ceaf9 2140 } else {
2200edac 2141 dev_err(adev->dev, "asic resume failed (%d).\n", r);
d38ceaf9 2142 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
0875dc9e
CZ
2143 if (adev->rings[i]) {
2144 kthread_unpark(adev->rings[i]->sched.thread);
0875dc9e 2145 }
d38ceaf9
AD
2146 }
2147 }
2148
2149 drm_helper_resume_force_mode(adev->ddev);
2150
2151 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2152 if (r) {
2153 /* bad news, how to tell it to userspace ? */
2154 dev_info(adev->dev, "GPU reset failed\n");
2155 }
2156
d38ceaf9
AD
2157 return r;
2158}
2159
d0dd7f0c
AD
2160void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2161{
2162 u32 mask;
2163 int ret;
2164
cd474ba0
AD
2165 if (amdgpu_pcie_gen_cap)
2166 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
d0dd7f0c 2167
cd474ba0
AD
2168 if (amdgpu_pcie_lane_cap)
2169 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
d0dd7f0c 2170
cd474ba0
AD
2171 /* covers APUs as well */
2172 if (pci_is_root_bus(adev->pdev->bus)) {
2173 if (adev->pm.pcie_gen_mask == 0)
2174 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2175 if (adev->pm.pcie_mlw_mask == 0)
2176 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
d0dd7f0c 2177 return;
cd474ba0 2178 }
d0dd7f0c 2179
cd474ba0
AD
2180 if (adev->pm.pcie_gen_mask == 0) {
2181 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2182 if (!ret) {
2183 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2184 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2185 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2186
2187 if (mask & DRM_PCIE_SPEED_25)
2188 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2189 if (mask & DRM_PCIE_SPEED_50)
2190 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2191 if (mask & DRM_PCIE_SPEED_80)
2192 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2193 } else {
2194 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2195 }
2196 }
2197 if (adev->pm.pcie_mlw_mask == 0) {
2198 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2199 if (!ret) {
2200 switch (mask) {
2201 case 32:
2202 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2203 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2204 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2205 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2206 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2207 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2208 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2209 break;
2210 case 16:
2211 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2212 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2213 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2214 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2215 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2216 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2217 break;
2218 case 12:
2219 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2220 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2221 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2222 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2223 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2224 break;
2225 case 8:
2226 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2227 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2228 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2229 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2230 break;
2231 case 4:
2232 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2233 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2234 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2235 break;
2236 case 2:
2237 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2238 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2239 break;
2240 case 1:
2241 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2242 break;
2243 default:
2244 break;
2245 }
2246 } else {
2247 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
d0dd7f0c
AD
2248 }
2249 }
2250}
d38ceaf9
AD
2251
2252/*
2253 * Debugfs
2254 */
2255int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
06ab6832 2256 const struct drm_info_list *files,
d38ceaf9
AD
2257 unsigned nfiles)
2258{
2259 unsigned i;
2260
2261 for (i = 0; i < adev->debugfs_count; i++) {
2262 if (adev->debugfs[i].files == files) {
2263 /* Already registered */
2264 return 0;
2265 }
2266 }
2267
2268 i = adev->debugfs_count + 1;
2269 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2270 DRM_ERROR("Reached maximum number of debugfs components.\n");
2271 DRM_ERROR("Report so we increase "
2272 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2273 return -EINVAL;
2274 }
2275 adev->debugfs[adev->debugfs_count].files = files;
2276 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2277 adev->debugfs_count = i;
2278#if defined(CONFIG_DEBUG_FS)
2279 drm_debugfs_create_files(files, nfiles,
2280 adev->ddev->control->debugfs_root,
2281 adev->ddev->control);
2282 drm_debugfs_create_files(files, nfiles,
2283 adev->ddev->primary->debugfs_root,
2284 adev->ddev->primary);
2285#endif
2286 return 0;
2287}
2288
2289static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2290{
2291#if defined(CONFIG_DEBUG_FS)
2292 unsigned i;
2293
2294 for (i = 0; i < adev->debugfs_count; i++) {
2295 drm_debugfs_remove_files(adev->debugfs[i].files,
2296 adev->debugfs[i].num_files,
2297 adev->ddev->control);
2298 drm_debugfs_remove_files(adev->debugfs[i].files,
2299 adev->debugfs[i].num_files,
2300 adev->ddev->primary);
2301 }
2302#endif
2303}
2304
2305#if defined(CONFIG_DEBUG_FS)
2306
2307static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2308 size_t size, loff_t *pos)
2309{
2310 struct amdgpu_device *adev = f->f_inode->i_private;
2311 ssize_t result = 0;
2312 int r;
bd12267d 2313 bool pm_pg_lock, use_bank;
56628159 2314 unsigned instance_bank, sh_bank, se_bank;
d38ceaf9
AD
2315
2316 if (size & 0x3 || *pos & 0x3)
2317 return -EINVAL;
2318
bd12267d
TSD
2319 /* are we reading registers for which a PG lock is necessary? */
2320 pm_pg_lock = (*pos >> 23) & 1;
2321
56628159
TSD
2322 if (*pos & (1ULL << 62)) {
2323 se_bank = (*pos >> 24) & 0x3FF;
2324 sh_bank = (*pos >> 34) & 0x3FF;
2325 instance_bank = (*pos >> 44) & 0x3FF;
2326 use_bank = 1;
56628159
TSD
2327 } else {
2328 use_bank = 0;
2329 }
2330
bd12267d
TSD
2331 *pos &= 0x3FFFF;
2332
56628159
TSD
2333 if (use_bank) {
2334 if (sh_bank >= adev->gfx.config.max_sh_per_se ||
2335 se_bank >= adev->gfx.config.max_shader_engines)
2336 return -EINVAL;
2337 mutex_lock(&adev->grbm_idx_mutex);
2338 amdgpu_gfx_select_se_sh(adev, se_bank,
2339 sh_bank, instance_bank);
2340 }
2341
bd12267d
TSD
2342 if (pm_pg_lock)
2343 mutex_lock(&adev->pm.mutex);
2344
d38ceaf9
AD
2345 while (size) {
2346 uint32_t value;
2347
2348 if (*pos > adev->rmmio_size)
56628159 2349 goto end;
d38ceaf9
AD
2350
2351 value = RREG32(*pos >> 2);
2352 r = put_user(value, (uint32_t *)buf);
56628159
TSD
2353 if (r) {
2354 result = r;
2355 goto end;
2356 }
d38ceaf9
AD
2357
2358 result += 4;
2359 buf += 4;
2360 *pos += 4;
2361 size -= 4;
2362 }
2363
56628159
TSD
2364end:
2365 if (use_bank) {
2366 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2367 mutex_unlock(&adev->grbm_idx_mutex);
2368 }
2369
bd12267d
TSD
2370 if (pm_pg_lock)
2371 mutex_unlock(&adev->pm.mutex);
2372
d38ceaf9
AD
2373 return result;
2374}
2375
2376static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2377 size_t size, loff_t *pos)
2378{
2379 struct amdgpu_device *adev = f->f_inode->i_private;
2380 ssize_t result = 0;
2381 int r;
2382
2383 if (size & 0x3 || *pos & 0x3)
2384 return -EINVAL;
2385
2386 while (size) {
2387 uint32_t value;
2388
2389 if (*pos > adev->rmmio_size)
2390 return result;
2391
2392 r = get_user(value, (uint32_t *)buf);
2393 if (r)
2394 return r;
2395
2396 WREG32(*pos >> 2, value);
2397
2398 result += 4;
2399 buf += 4;
2400 *pos += 4;
2401 size -= 4;
2402 }
2403
2404 return result;
2405}
2406
adcec288
TSD
2407static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2408 size_t size, loff_t *pos)
2409{
2410 struct amdgpu_device *adev = f->f_inode->i_private;
2411 ssize_t result = 0;
2412 int r;
2413
2414 if (size & 0x3 || *pos & 0x3)
2415 return -EINVAL;
2416
2417 while (size) {
2418 uint32_t value;
2419
2420 value = RREG32_PCIE(*pos >> 2);
2421 r = put_user(value, (uint32_t *)buf);
2422 if (r)
2423 return r;
2424
2425 result += 4;
2426 buf += 4;
2427 *pos += 4;
2428 size -= 4;
2429 }
2430
2431 return result;
2432}
2433
2434static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2435 size_t size, loff_t *pos)
2436{
2437 struct amdgpu_device *adev = f->f_inode->i_private;
2438 ssize_t result = 0;
2439 int r;
2440
2441 if (size & 0x3 || *pos & 0x3)
2442 return -EINVAL;
2443
2444 while (size) {
2445 uint32_t value;
2446
2447 r = get_user(value, (uint32_t *)buf);
2448 if (r)
2449 return r;
2450
2451 WREG32_PCIE(*pos >> 2, value);
2452
2453 result += 4;
2454 buf += 4;
2455 *pos += 4;
2456 size -= 4;
2457 }
2458
2459 return result;
2460}
2461
2462static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2463 size_t size, loff_t *pos)
2464{
2465 struct amdgpu_device *adev = f->f_inode->i_private;
2466 ssize_t result = 0;
2467 int r;
2468
2469 if (size & 0x3 || *pos & 0x3)
2470 return -EINVAL;
2471
2472 while (size) {
2473 uint32_t value;
2474
2475 value = RREG32_DIDT(*pos >> 2);
2476 r = put_user(value, (uint32_t *)buf);
2477 if (r)
2478 return r;
2479
2480 result += 4;
2481 buf += 4;
2482 *pos += 4;
2483 size -= 4;
2484 }
2485
2486 return result;
2487}
2488
2489static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2490 size_t size, loff_t *pos)
2491{
2492 struct amdgpu_device *adev = f->f_inode->i_private;
2493 ssize_t result = 0;
2494 int r;
2495
2496 if (size & 0x3 || *pos & 0x3)
2497 return -EINVAL;
2498
2499 while (size) {
2500 uint32_t value;
2501
2502 r = get_user(value, (uint32_t *)buf);
2503 if (r)
2504 return r;
2505
2506 WREG32_DIDT(*pos >> 2, value);
2507
2508 result += 4;
2509 buf += 4;
2510 *pos += 4;
2511 size -= 4;
2512 }
2513
2514 return result;
2515}
2516
2517static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2518 size_t size, loff_t *pos)
2519{
2520 struct amdgpu_device *adev = f->f_inode->i_private;
2521 ssize_t result = 0;
2522 int r;
2523
2524 if (size & 0x3 || *pos & 0x3)
2525 return -EINVAL;
2526
2527 while (size) {
2528 uint32_t value;
2529
2530 value = RREG32_SMC(*pos >> 2);
2531 r = put_user(value, (uint32_t *)buf);
2532 if (r)
2533 return r;
2534
2535 result += 4;
2536 buf += 4;
2537 *pos += 4;
2538 size -= 4;
2539 }
2540
2541 return result;
2542}
2543
2544static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2545 size_t size, loff_t *pos)
2546{
2547 struct amdgpu_device *adev = f->f_inode->i_private;
2548 ssize_t result = 0;
2549 int r;
2550
2551 if (size & 0x3 || *pos & 0x3)
2552 return -EINVAL;
2553
2554 while (size) {
2555 uint32_t value;
2556
2557 r = get_user(value, (uint32_t *)buf);
2558 if (r)
2559 return r;
2560
2561 WREG32_SMC(*pos >> 2, value);
2562
2563 result += 4;
2564 buf += 4;
2565 *pos += 4;
2566 size -= 4;
2567 }
2568
2569 return result;
2570}
2571
1e051413
TSD
2572static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
2573 size_t size, loff_t *pos)
2574{
2575 struct amdgpu_device *adev = f->f_inode->i_private;
2576 ssize_t result = 0;
2577 int r;
2578 uint32_t *config, no_regs = 0;
2579
2580 if (size & 0x3 || *pos & 0x3)
2581 return -EINVAL;
2582
2583 config = kmalloc(256 * sizeof(*config), GFP_KERNEL);
2584 if (!config)
2585 return -ENOMEM;
2586
2587 /* version, increment each time something is added */
2588 config[no_regs++] = 0;
2589 config[no_regs++] = adev->gfx.config.max_shader_engines;
2590 config[no_regs++] = adev->gfx.config.max_tile_pipes;
2591 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
2592 config[no_regs++] = adev->gfx.config.max_sh_per_se;
2593 config[no_regs++] = adev->gfx.config.max_backends_per_se;
2594 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
2595 config[no_regs++] = adev->gfx.config.max_gprs;
2596 config[no_regs++] = adev->gfx.config.max_gs_threads;
2597 config[no_regs++] = adev->gfx.config.max_hw_contexts;
2598 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
2599 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
2600 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
2601 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
2602 config[no_regs++] = adev->gfx.config.num_tile_pipes;
2603 config[no_regs++] = adev->gfx.config.backend_enable_mask;
2604 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
2605 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
2606 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
2607 config[no_regs++] = adev->gfx.config.num_gpus;
2608 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
2609 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
2610 config[no_regs++] = adev->gfx.config.gb_addr_config;
2611 config[no_regs++] = adev->gfx.config.num_rbs;
2612
2613 while (size && (*pos < no_regs * 4)) {
2614 uint32_t value;
2615
2616 value = config[*pos >> 2];
2617 r = put_user(value, (uint32_t *)buf);
2618 if (r) {
2619 kfree(config);
2620 return r;
2621 }
2622
2623 result += 4;
2624 buf += 4;
2625 *pos += 4;
2626 size -= 4;
2627 }
2628
2629 kfree(config);
2630 return result;
2631}
2632
2633
d38ceaf9
AD
2634static const struct file_operations amdgpu_debugfs_regs_fops = {
2635 .owner = THIS_MODULE,
2636 .read = amdgpu_debugfs_regs_read,
2637 .write = amdgpu_debugfs_regs_write,
2638 .llseek = default_llseek
2639};
adcec288
TSD
2640static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2641 .owner = THIS_MODULE,
2642 .read = amdgpu_debugfs_regs_didt_read,
2643 .write = amdgpu_debugfs_regs_didt_write,
2644 .llseek = default_llseek
2645};
2646static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2647 .owner = THIS_MODULE,
2648 .read = amdgpu_debugfs_regs_pcie_read,
2649 .write = amdgpu_debugfs_regs_pcie_write,
2650 .llseek = default_llseek
2651};
2652static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2653 .owner = THIS_MODULE,
2654 .read = amdgpu_debugfs_regs_smc_read,
2655 .write = amdgpu_debugfs_regs_smc_write,
2656 .llseek = default_llseek
2657};
2658
1e051413
TSD
2659static const struct file_operations amdgpu_debugfs_gca_config_fops = {
2660 .owner = THIS_MODULE,
2661 .read = amdgpu_debugfs_gca_config_read,
2662 .llseek = default_llseek
2663};
2664
adcec288
TSD
2665static const struct file_operations *debugfs_regs[] = {
2666 &amdgpu_debugfs_regs_fops,
2667 &amdgpu_debugfs_regs_didt_fops,
2668 &amdgpu_debugfs_regs_pcie_fops,
2669 &amdgpu_debugfs_regs_smc_fops,
1e051413 2670 &amdgpu_debugfs_gca_config_fops,
adcec288
TSD
2671};
2672
2673static const char *debugfs_regs_names[] = {
2674 "amdgpu_regs",
2675 "amdgpu_regs_didt",
2676 "amdgpu_regs_pcie",
2677 "amdgpu_regs_smc",
1e051413 2678 "amdgpu_gca_config",
adcec288 2679};
d38ceaf9
AD
2680
2681static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2682{
2683 struct drm_minor *minor = adev->ddev->primary;
2684 struct dentry *ent, *root = minor->debugfs_root;
adcec288
TSD
2685 unsigned i, j;
2686
2687 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2688 ent = debugfs_create_file(debugfs_regs_names[i],
2689 S_IFREG | S_IRUGO, root,
2690 adev, debugfs_regs[i]);
2691 if (IS_ERR(ent)) {
2692 for (j = 0; j < i; j++) {
2693 debugfs_remove(adev->debugfs_regs[i]);
2694 adev->debugfs_regs[i] = NULL;
2695 }
2696 return PTR_ERR(ent);
2697 }
d38ceaf9 2698
adcec288
TSD
2699 if (!i)
2700 i_size_write(ent->d_inode, adev->rmmio_size);
2701 adev->debugfs_regs[i] = ent;
2702 }
d38ceaf9
AD
2703
2704 return 0;
2705}
2706
2707static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2708{
adcec288
TSD
2709 unsigned i;
2710
2711 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2712 if (adev->debugfs_regs[i]) {
2713 debugfs_remove(adev->debugfs_regs[i]);
2714 adev->debugfs_regs[i] = NULL;
2715 }
2716 }
d38ceaf9
AD
2717}
2718
2719int amdgpu_debugfs_init(struct drm_minor *minor)
2720{
2721 return 0;
2722}
2723
2724void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2725{
2726}
7cebc728
AK
2727#else
2728static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2729{
2730 return 0;
2731}
2732static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
d38ceaf9 2733#endif