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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/console.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/debugfs.h> | |
31 | #include <drm/drmP.h> | |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/amdgpu_drm.h> | |
34 | #include <linux/vgaarb.h> | |
35 | #include <linux/vga_switcheroo.h> | |
36 | #include <linux/efi.h> | |
37 | #include "amdgpu.h" | |
38 | #include "amdgpu_i2c.h" | |
39 | #include "atom.h" | |
40 | #include "amdgpu_atombios.h" | |
a2e73f56 AD |
41 | #ifdef CONFIG_DRM_AMDGPU_CIK |
42 | #include "cik.h" | |
43 | #endif | |
d38ceaf9 AD |
44 | #include "bif/bif_4_1_d.h" |
45 | ||
46 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); | |
47 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev); | |
48 | ||
49 | static const char *amdgpu_asic_name[] = { | |
50 | "BONAIRE", | |
51 | "KAVERI", | |
52 | "KABINI", | |
53 | "HAWAII", | |
54 | "MULLINS", | |
55 | "TOPAZ", | |
56 | "TONGA", | |
57 | "CARRIZO", | |
58 | "LAST", | |
59 | }; | |
60 | ||
61 | bool amdgpu_device_is_px(struct drm_device *dev) | |
62 | { | |
63 | struct amdgpu_device *adev = dev->dev_private; | |
64 | ||
65 | if (adev->flags & AMDGPU_IS_PX) | |
66 | return true; | |
67 | return false; | |
68 | } | |
69 | ||
70 | /* | |
71 | * MMIO register access helper functions. | |
72 | */ | |
73 | uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | |
74 | bool always_indirect) | |
75 | { | |
76 | if ((reg * 4) < adev->rmmio_size && !always_indirect) | |
77 | return readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
78 | else { | |
79 | unsigned long flags; | |
80 | uint32_t ret; | |
81 | ||
82 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
83 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
84 | ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
85 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
86 | ||
87 | return ret; | |
88 | } | |
89 | } | |
90 | ||
91 | void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, | |
92 | bool always_indirect) | |
93 | { | |
94 | if ((reg * 4) < adev->rmmio_size && !always_indirect) | |
95 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
96 | else { | |
97 | unsigned long flags; | |
98 | ||
99 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
100 | writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4)); | |
101 | writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4)); | |
102 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
103 | } | |
104 | } | |
105 | ||
106 | u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg) | |
107 | { | |
108 | if ((reg * 4) < adev->rio_mem_size) | |
109 | return ioread32(adev->rio_mem + (reg * 4)); | |
110 | else { | |
111 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
112 | return ioread32(adev->rio_mem + (mmMM_DATA * 4)); | |
113 | } | |
114 | } | |
115 | ||
116 | void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v) | |
117 | { | |
118 | ||
119 | if ((reg * 4) < adev->rio_mem_size) | |
120 | iowrite32(v, adev->rio_mem + (reg * 4)); | |
121 | else { | |
122 | iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4)); | |
123 | iowrite32(v, adev->rio_mem + (mmMM_DATA * 4)); | |
124 | } | |
125 | } | |
126 | ||
127 | /** | |
128 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
129 | * | |
130 | * @adev: amdgpu_device pointer | |
131 | * @index: doorbell index | |
132 | * | |
133 | * Returns the value in the doorbell aperture at the | |
134 | * requested doorbell index (CIK). | |
135 | */ | |
136 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
137 | { | |
138 | if (index < adev->doorbell.num_doorbells) { | |
139 | return readl(adev->doorbell.ptr + index); | |
140 | } else { | |
141 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
142 | return 0; | |
143 | } | |
144 | } | |
145 | ||
146 | /** | |
147 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
148 | * | |
149 | * @adev: amdgpu_device pointer | |
150 | * @index: doorbell index | |
151 | * @v: value to write | |
152 | * | |
153 | * Writes @v to the doorbell aperture at the | |
154 | * requested doorbell index (CIK). | |
155 | */ | |
156 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
157 | { | |
158 | if (index < adev->doorbell.num_doorbells) { | |
159 | writel(v, adev->doorbell.ptr + index); | |
160 | } else { | |
161 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
162 | } | |
163 | } | |
164 | ||
165 | /** | |
166 | * amdgpu_invalid_rreg - dummy reg read function | |
167 | * | |
168 | * @adev: amdgpu device pointer | |
169 | * @reg: offset of register | |
170 | * | |
171 | * Dummy register read function. Used for register blocks | |
172 | * that certain asics don't have (all asics). | |
173 | * Returns the value in the register. | |
174 | */ | |
175 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
176 | { | |
177 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
178 | BUG(); | |
179 | return 0; | |
180 | } | |
181 | ||
182 | /** | |
183 | * amdgpu_invalid_wreg - dummy reg write function | |
184 | * | |
185 | * @adev: amdgpu device pointer | |
186 | * @reg: offset of register | |
187 | * @v: value to write to the register | |
188 | * | |
189 | * Dummy register read function. Used for register blocks | |
190 | * that certain asics don't have (all asics). | |
191 | */ | |
192 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
193 | { | |
194 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
195 | reg, v); | |
196 | BUG(); | |
197 | } | |
198 | ||
199 | /** | |
200 | * amdgpu_block_invalid_rreg - dummy reg read function | |
201 | * | |
202 | * @adev: amdgpu device pointer | |
203 | * @block: offset of instance | |
204 | * @reg: offset of register | |
205 | * | |
206 | * Dummy register read function. Used for register blocks | |
207 | * that certain asics don't have (all asics). | |
208 | * Returns the value in the register. | |
209 | */ | |
210 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
211 | uint32_t block, uint32_t reg) | |
212 | { | |
213 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
214 | reg, block); | |
215 | BUG(); | |
216 | return 0; | |
217 | } | |
218 | ||
219 | /** | |
220 | * amdgpu_block_invalid_wreg - dummy reg write function | |
221 | * | |
222 | * @adev: amdgpu device pointer | |
223 | * @block: offset of instance | |
224 | * @reg: offset of register | |
225 | * @v: value to write to the register | |
226 | * | |
227 | * Dummy register read function. Used for register blocks | |
228 | * that certain asics don't have (all asics). | |
229 | */ | |
230 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
231 | uint32_t block, | |
232 | uint32_t reg, uint32_t v) | |
233 | { | |
234 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
235 | reg, block, v); | |
236 | BUG(); | |
237 | } | |
238 | ||
239 | static int amdgpu_vram_scratch_init(struct amdgpu_device *adev) | |
240 | { | |
241 | int r; | |
242 | ||
243 | if (adev->vram_scratch.robj == NULL) { | |
244 | r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE, | |
245 | PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0, | |
246 | NULL, &adev->vram_scratch.robj); | |
247 | if (r) { | |
248 | return r; | |
249 | } | |
250 | } | |
251 | ||
252 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
253 | if (unlikely(r != 0)) | |
254 | return r; | |
255 | r = amdgpu_bo_pin(adev->vram_scratch.robj, | |
256 | AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr); | |
257 | if (r) { | |
258 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
259 | return r; | |
260 | } | |
261 | r = amdgpu_bo_kmap(adev->vram_scratch.robj, | |
262 | (void **)&adev->vram_scratch.ptr); | |
263 | if (r) | |
264 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
265 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
266 | ||
267 | return r; | |
268 | } | |
269 | ||
270 | static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev) | |
271 | { | |
272 | int r; | |
273 | ||
274 | if (adev->vram_scratch.robj == NULL) { | |
275 | return; | |
276 | } | |
277 | r = amdgpu_bo_reserve(adev->vram_scratch.robj, false); | |
278 | if (likely(r == 0)) { | |
279 | amdgpu_bo_kunmap(adev->vram_scratch.robj); | |
280 | amdgpu_bo_unpin(adev->vram_scratch.robj); | |
281 | amdgpu_bo_unreserve(adev->vram_scratch.robj); | |
282 | } | |
283 | amdgpu_bo_unref(&adev->vram_scratch.robj); | |
284 | } | |
285 | ||
286 | /** | |
287 | * amdgpu_program_register_sequence - program an array of registers. | |
288 | * | |
289 | * @adev: amdgpu_device pointer | |
290 | * @registers: pointer to the register array | |
291 | * @array_size: size of the register array | |
292 | * | |
293 | * Programs an array or registers with and and or masks. | |
294 | * This is a helper for setting golden registers. | |
295 | */ | |
296 | void amdgpu_program_register_sequence(struct amdgpu_device *adev, | |
297 | const u32 *registers, | |
298 | const u32 array_size) | |
299 | { | |
300 | u32 tmp, reg, and_mask, or_mask; | |
301 | int i; | |
302 | ||
303 | if (array_size % 3) | |
304 | return; | |
305 | ||
306 | for (i = 0; i < array_size; i +=3) { | |
307 | reg = registers[i + 0]; | |
308 | and_mask = registers[i + 1]; | |
309 | or_mask = registers[i + 2]; | |
310 | ||
311 | if (and_mask == 0xffffffff) { | |
312 | tmp = or_mask; | |
313 | } else { | |
314 | tmp = RREG32(reg); | |
315 | tmp &= ~and_mask; | |
316 | tmp |= or_mask; | |
317 | } | |
318 | WREG32(reg, tmp); | |
319 | } | |
320 | } | |
321 | ||
322 | void amdgpu_pci_config_reset(struct amdgpu_device *adev) | |
323 | { | |
324 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
325 | } | |
326 | ||
327 | /* | |
328 | * GPU doorbell aperture helpers function. | |
329 | */ | |
330 | /** | |
331 | * amdgpu_doorbell_init - Init doorbell driver information. | |
332 | * | |
333 | * @adev: amdgpu_device pointer | |
334 | * | |
335 | * Init doorbell driver information (CIK) | |
336 | * Returns 0 on success, error on failure. | |
337 | */ | |
338 | static int amdgpu_doorbell_init(struct amdgpu_device *adev) | |
339 | { | |
340 | /* doorbell bar mapping */ | |
341 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
342 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
343 | ||
344 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), | |
345 | AMDGPU_DOORBELL_MAX_ASSIGNMENT+1); | |
346 | if (adev->doorbell.num_doorbells == 0) | |
347 | return -EINVAL; | |
348 | ||
349 | adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32)); | |
350 | if (adev->doorbell.ptr == NULL) { | |
351 | return -ENOMEM; | |
352 | } | |
353 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base); | |
354 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size); | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | /** | |
360 | * amdgpu_doorbell_fini - Tear down doorbell driver information. | |
361 | * | |
362 | * @adev: amdgpu_device pointer | |
363 | * | |
364 | * Tear down doorbell driver information (CIK) | |
365 | */ | |
366 | static void amdgpu_doorbell_fini(struct amdgpu_device *adev) | |
367 | { | |
368 | iounmap(adev->doorbell.ptr); | |
369 | adev->doorbell.ptr = NULL; | |
370 | } | |
371 | ||
372 | /** | |
373 | * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to | |
374 | * setup amdkfd | |
375 | * | |
376 | * @adev: amdgpu_device pointer | |
377 | * @aperture_base: output returning doorbell aperture base physical address | |
378 | * @aperture_size: output returning doorbell aperture size in bytes | |
379 | * @start_offset: output returning # of doorbell bytes reserved for amdgpu. | |
380 | * | |
381 | * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, | |
382 | * takes doorbells required for its own rings and reports the setup to amdkfd. | |
383 | * amdgpu reserved doorbells are at the start of the doorbell aperture. | |
384 | */ | |
385 | void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, | |
386 | phys_addr_t *aperture_base, | |
387 | size_t *aperture_size, | |
388 | size_t *start_offset) | |
389 | { | |
390 | /* | |
391 | * The first num_doorbells are used by amdgpu. | |
392 | * amdkfd takes whatever's left in the aperture. | |
393 | */ | |
394 | if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { | |
395 | *aperture_base = adev->doorbell.base; | |
396 | *aperture_size = adev->doorbell.size; | |
397 | *start_offset = adev->doorbell.num_doorbells * sizeof(u32); | |
398 | } else { | |
399 | *aperture_base = 0; | |
400 | *aperture_size = 0; | |
401 | *start_offset = 0; | |
402 | } | |
403 | } | |
404 | ||
405 | /* | |
406 | * amdgpu_wb_*() | |
407 | * Writeback is the the method by which the the GPU updates special pages | |
408 | * in memory with the status of certain GPU events (fences, ring pointers, | |
409 | * etc.). | |
410 | */ | |
411 | ||
412 | /** | |
413 | * amdgpu_wb_fini - Disable Writeback and free memory | |
414 | * | |
415 | * @adev: amdgpu_device pointer | |
416 | * | |
417 | * Disables Writeback and frees the Writeback memory (all asics). | |
418 | * Used at driver shutdown. | |
419 | */ | |
420 | static void amdgpu_wb_fini(struct amdgpu_device *adev) | |
421 | { | |
422 | if (adev->wb.wb_obj) { | |
423 | if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) { | |
424 | amdgpu_bo_kunmap(adev->wb.wb_obj); | |
425 | amdgpu_bo_unpin(adev->wb.wb_obj); | |
426 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
427 | } | |
428 | amdgpu_bo_unref(&adev->wb.wb_obj); | |
429 | adev->wb.wb = NULL; | |
430 | adev->wb.wb_obj = NULL; | |
431 | } | |
432 | } | |
433 | ||
434 | /** | |
435 | * amdgpu_wb_init- Init Writeback driver info and allocate memory | |
436 | * | |
437 | * @adev: amdgpu_device pointer | |
438 | * | |
439 | * Disables Writeback and frees the Writeback memory (all asics). | |
440 | * Used at driver startup. | |
441 | * Returns 0 on success or an -error on failure. | |
442 | */ | |
443 | static int amdgpu_wb_init(struct amdgpu_device *adev) | |
444 | { | |
445 | int r; | |
446 | ||
447 | if (adev->wb.wb_obj == NULL) { | |
448 | r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true, | |
449 | AMDGPU_GEM_DOMAIN_GTT, 0, NULL, &adev->wb.wb_obj); | |
450 | if (r) { | |
451 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
452 | return r; | |
453 | } | |
454 | r = amdgpu_bo_reserve(adev->wb.wb_obj, false); | |
455 | if (unlikely(r != 0)) { | |
456 | amdgpu_wb_fini(adev); | |
457 | return r; | |
458 | } | |
459 | r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT, | |
460 | &adev->wb.gpu_addr); | |
461 | if (r) { | |
462 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
463 | dev_warn(adev->dev, "(%d) pin WB bo failed\n", r); | |
464 | amdgpu_wb_fini(adev); | |
465 | return r; | |
466 | } | |
467 | r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb); | |
468 | amdgpu_bo_unreserve(adev->wb.wb_obj); | |
469 | if (r) { | |
470 | dev_warn(adev->dev, "(%d) map WB bo failed\n", r); | |
471 | amdgpu_wb_fini(adev); | |
472 | return r; | |
473 | } | |
474 | ||
475 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
476 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
477 | ||
478 | /* clear wb memory */ | |
479 | memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE); | |
480 | } | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | /** | |
486 | * amdgpu_wb_get - Allocate a wb entry | |
487 | * | |
488 | * @adev: amdgpu_device pointer | |
489 | * @wb: wb index | |
490 | * | |
491 | * Allocate a wb slot for use by the driver (all asics). | |
492 | * Returns 0 on success or -EINVAL on failure. | |
493 | */ | |
494 | int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) | |
495 | { | |
496 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
497 | if (offset < adev->wb.num_wb) { | |
498 | __set_bit(offset, adev->wb.used); | |
499 | *wb = offset; | |
500 | return 0; | |
501 | } else { | |
502 | return -EINVAL; | |
503 | } | |
504 | } | |
505 | ||
506 | /** | |
507 | * amdgpu_wb_free - Free a wb entry | |
508 | * | |
509 | * @adev: amdgpu_device pointer | |
510 | * @wb: wb index | |
511 | * | |
512 | * Free a wb slot allocated for use by the driver (all asics) | |
513 | */ | |
514 | void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) | |
515 | { | |
516 | if (wb < adev->wb.num_wb) | |
517 | __clear_bit(wb, adev->wb.used); | |
518 | } | |
519 | ||
520 | /** | |
521 | * amdgpu_vram_location - try to find VRAM location | |
522 | * @adev: amdgpu device structure holding all necessary informations | |
523 | * @mc: memory controller structure holding memory informations | |
524 | * @base: base address at which to put VRAM | |
525 | * | |
526 | * Function will place try to place VRAM at base address provided | |
527 | * as parameter (which is so far either PCI aperture address or | |
528 | * for IGP TOM base address). | |
529 | * | |
530 | * If there is not enough space to fit the unvisible VRAM in the 32bits | |
531 | * address space then we limit the VRAM size to the aperture. | |
532 | * | |
533 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, | |
534 | * this shouldn't be a problem as we are using the PCI aperture as a reference. | |
535 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but | |
536 | * not IGP. | |
537 | * | |
538 | * Note: we use mc_vram_size as on some board we need to program the mc to | |
539 | * cover the whole aperture even if VRAM size is inferior to aperture size | |
540 | * Novell bug 204882 + along with lots of ubuntu ones | |
541 | * | |
542 | * Note: when limiting vram it's safe to overwritte real_vram_size because | |
543 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie | |
544 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu | |
545 | * ones) | |
546 | * | |
547 | * Note: IGP TOM addr should be the same as the aperture addr, we don't | |
548 | * explicitly check for that thought. | |
549 | * | |
550 | * FIXME: when reducing VRAM size align new size on power of 2. | |
551 | */ | |
552 | void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) | |
553 | { | |
554 | uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; | |
555 | ||
556 | mc->vram_start = base; | |
557 | if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { | |
558 | dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); | |
559 | mc->real_vram_size = mc->aper_size; | |
560 | mc->mc_vram_size = mc->aper_size; | |
561 | } | |
562 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
563 | if (limit && limit < mc->real_vram_size) | |
564 | mc->real_vram_size = limit; | |
565 | dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
566 | mc->mc_vram_size >> 20, mc->vram_start, | |
567 | mc->vram_end, mc->real_vram_size >> 20); | |
568 | } | |
569 | ||
570 | /** | |
571 | * amdgpu_gtt_location - try to find GTT location | |
572 | * @adev: amdgpu device structure holding all necessary informations | |
573 | * @mc: memory controller structure holding memory informations | |
574 | * | |
575 | * Function will place try to place GTT before or after VRAM. | |
576 | * | |
577 | * If GTT size is bigger than space left then we ajust GTT size. | |
578 | * Thus function will never fails. | |
579 | * | |
580 | * FIXME: when reducing GTT size align new size on power of 2. | |
581 | */ | |
582 | void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) | |
583 | { | |
584 | u64 size_af, size_bf; | |
585 | ||
586 | size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
587 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
588 | if (size_bf > size_af) { | |
589 | if (mc->gtt_size > size_bf) { | |
590 | dev_warn(adev->dev, "limiting GTT\n"); | |
591 | mc->gtt_size = size_bf; | |
592 | } | |
593 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; | |
594 | } else { | |
595 | if (mc->gtt_size > size_af) { | |
596 | dev_warn(adev->dev, "limiting GTT\n"); | |
597 | mc->gtt_size = size_af; | |
598 | } | |
599 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
600 | } | |
601 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
602 | dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
603 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
604 | } | |
605 | ||
606 | /* | |
607 | * GPU helpers function. | |
608 | */ | |
609 | /** | |
610 | * amdgpu_card_posted - check if the hw has already been initialized | |
611 | * | |
612 | * @adev: amdgpu_device pointer | |
613 | * | |
614 | * Check if the asic has been initialized (all asics). | |
615 | * Used at driver startup. | |
616 | * Returns true if initialized or false if not. | |
617 | */ | |
618 | bool amdgpu_card_posted(struct amdgpu_device *adev) | |
619 | { | |
620 | uint32_t reg; | |
621 | ||
622 | /* then check MEM_SIZE, in case the crtcs are off */ | |
623 | reg = RREG32(mmCONFIG_MEMSIZE); | |
624 | ||
625 | if (reg) | |
626 | return true; | |
627 | ||
628 | return false; | |
629 | ||
630 | } | |
631 | ||
632 | /** | |
633 | * amdgpu_boot_test_post_card - check and possibly initialize the hw | |
634 | * | |
635 | * @adev: amdgpu_device pointer | |
636 | * | |
637 | * Check if the asic is initialized and if not, attempt to initialize | |
638 | * it (all asics). | |
639 | * Returns true if initialized or false if not. | |
640 | */ | |
641 | bool amdgpu_boot_test_post_card(struct amdgpu_device *adev) | |
642 | { | |
643 | if (amdgpu_card_posted(adev)) | |
644 | return true; | |
645 | ||
646 | if (adev->bios) { | |
647 | DRM_INFO("GPU not posted. posting now...\n"); | |
648 | if (adev->is_atom_bios) | |
649 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
650 | return true; | |
651 | } else { | |
652 | dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n"); | |
653 | return false; | |
654 | } | |
655 | } | |
656 | ||
657 | /** | |
658 | * amdgpu_dummy_page_init - init dummy page used by the driver | |
659 | * | |
660 | * @adev: amdgpu_device pointer | |
661 | * | |
662 | * Allocate the dummy page used by the driver (all asics). | |
663 | * This dummy page is used by the driver as a filler for gart entries | |
664 | * when pages are taken out of the GART | |
665 | * Returns 0 on sucess, -ENOMEM on failure. | |
666 | */ | |
667 | int amdgpu_dummy_page_init(struct amdgpu_device *adev) | |
668 | { | |
669 | if (adev->dummy_page.page) | |
670 | return 0; | |
671 | adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); | |
672 | if (adev->dummy_page.page == NULL) | |
673 | return -ENOMEM; | |
674 | adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page, | |
675 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
676 | if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) { | |
677 | dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); | |
678 | __free_page(adev->dummy_page.page); | |
679 | adev->dummy_page.page = NULL; | |
680 | return -ENOMEM; | |
681 | } | |
682 | return 0; | |
683 | } | |
684 | ||
685 | /** | |
686 | * amdgpu_dummy_page_fini - free dummy page used by the driver | |
687 | * | |
688 | * @adev: amdgpu_device pointer | |
689 | * | |
690 | * Frees the dummy page used by the driver (all asics). | |
691 | */ | |
692 | void amdgpu_dummy_page_fini(struct amdgpu_device *adev) | |
693 | { | |
694 | if (adev->dummy_page.page == NULL) | |
695 | return; | |
696 | pci_unmap_page(adev->pdev, adev->dummy_page.addr, | |
697 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
698 | __free_page(adev->dummy_page.page); | |
699 | adev->dummy_page.page = NULL; | |
700 | } | |
701 | ||
702 | ||
703 | /* ATOM accessor methods */ | |
704 | /* | |
705 | * ATOM is an interpreted byte code stored in tables in the vbios. The | |
706 | * driver registers callbacks to access registers and the interpreter | |
707 | * in the driver parses the tables and executes then to program specific | |
708 | * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, | |
709 | * atombios.h, and atom.c | |
710 | */ | |
711 | ||
712 | /** | |
713 | * cail_pll_read - read PLL register | |
714 | * | |
715 | * @info: atom card_info pointer | |
716 | * @reg: PLL register offset | |
717 | * | |
718 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
719 | * Returns the value of the PLL register. | |
720 | */ | |
721 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) | |
722 | { | |
723 | return 0; | |
724 | } | |
725 | ||
726 | /** | |
727 | * cail_pll_write - write PLL register | |
728 | * | |
729 | * @info: atom card_info pointer | |
730 | * @reg: PLL register offset | |
731 | * @val: value to write to the pll register | |
732 | * | |
733 | * Provides a PLL register accessor for the atom interpreter (r4xx+). | |
734 | */ | |
735 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) | |
736 | { | |
737 | ||
738 | } | |
739 | ||
740 | /** | |
741 | * cail_mc_read - read MC (Memory Controller) register | |
742 | * | |
743 | * @info: atom card_info pointer | |
744 | * @reg: MC register offset | |
745 | * | |
746 | * Provides an MC register accessor for the atom interpreter (r4xx+). | |
747 | * Returns the value of the MC register. | |
748 | */ | |
749 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) | |
750 | { | |
751 | return 0; | |
752 | } | |
753 | ||
754 | /** | |
755 | * cail_mc_write - write MC (Memory Controller) register | |
756 | * | |
757 | * @info: atom card_info pointer | |
758 | * @reg: MC register offset | |
759 | * @val: value to write to the pll register | |
760 | * | |
761 | * Provides a MC register accessor for the atom interpreter (r4xx+). | |
762 | */ | |
763 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) | |
764 | { | |
765 | ||
766 | } | |
767 | ||
768 | /** | |
769 | * cail_reg_write - write MMIO register | |
770 | * | |
771 | * @info: atom card_info pointer | |
772 | * @reg: MMIO register offset | |
773 | * @val: value to write to the pll register | |
774 | * | |
775 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). | |
776 | */ | |
777 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
778 | { | |
779 | struct amdgpu_device *adev = info->dev->dev_private; | |
780 | ||
781 | WREG32(reg, val); | |
782 | } | |
783 | ||
784 | /** | |
785 | * cail_reg_read - read MMIO register | |
786 | * | |
787 | * @info: atom card_info pointer | |
788 | * @reg: MMIO register offset | |
789 | * | |
790 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). | |
791 | * Returns the value of the MMIO register. | |
792 | */ | |
793 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) | |
794 | { | |
795 | struct amdgpu_device *adev = info->dev->dev_private; | |
796 | uint32_t r; | |
797 | ||
798 | r = RREG32(reg); | |
799 | return r; | |
800 | } | |
801 | ||
802 | /** | |
803 | * cail_ioreg_write - write IO register | |
804 | * | |
805 | * @info: atom card_info pointer | |
806 | * @reg: IO register offset | |
807 | * @val: value to write to the pll register | |
808 | * | |
809 | * Provides a IO register accessor for the atom interpreter (r4xx+). | |
810 | */ | |
811 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) | |
812 | { | |
813 | struct amdgpu_device *adev = info->dev->dev_private; | |
814 | ||
815 | WREG32_IO(reg, val); | |
816 | } | |
817 | ||
818 | /** | |
819 | * cail_ioreg_read - read IO register | |
820 | * | |
821 | * @info: atom card_info pointer | |
822 | * @reg: IO register offset | |
823 | * | |
824 | * Provides an IO register accessor for the atom interpreter (r4xx+). | |
825 | * Returns the value of the IO register. | |
826 | */ | |
827 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) | |
828 | { | |
829 | struct amdgpu_device *adev = info->dev->dev_private; | |
830 | uint32_t r; | |
831 | ||
832 | r = RREG32_IO(reg); | |
833 | return r; | |
834 | } | |
835 | ||
836 | /** | |
837 | * amdgpu_atombios_fini - free the driver info and callbacks for atombios | |
838 | * | |
839 | * @adev: amdgpu_device pointer | |
840 | * | |
841 | * Frees the driver info and register access callbacks for the ATOM | |
842 | * interpreter (r4xx+). | |
843 | * Called at driver shutdown. | |
844 | */ | |
845 | static void amdgpu_atombios_fini(struct amdgpu_device *adev) | |
846 | { | |
847 | if (adev->mode_info.atom_context) | |
848 | kfree(adev->mode_info.atom_context->scratch); | |
849 | kfree(adev->mode_info.atom_context); | |
850 | adev->mode_info.atom_context = NULL; | |
851 | kfree(adev->mode_info.atom_card_info); | |
852 | adev->mode_info.atom_card_info = NULL; | |
853 | } | |
854 | ||
855 | /** | |
856 | * amdgpu_atombios_init - init the driver info and callbacks for atombios | |
857 | * | |
858 | * @adev: amdgpu_device pointer | |
859 | * | |
860 | * Initializes the driver info and register access callbacks for the | |
861 | * ATOM interpreter (r4xx+). | |
862 | * Returns 0 on sucess, -ENOMEM on failure. | |
863 | * Called at driver startup. | |
864 | */ | |
865 | static int amdgpu_atombios_init(struct amdgpu_device *adev) | |
866 | { | |
867 | struct card_info *atom_card_info = | |
868 | kzalloc(sizeof(struct card_info), GFP_KERNEL); | |
869 | ||
870 | if (!atom_card_info) | |
871 | return -ENOMEM; | |
872 | ||
873 | adev->mode_info.atom_card_info = atom_card_info; | |
874 | atom_card_info->dev = adev->ddev; | |
875 | atom_card_info->reg_read = cail_reg_read; | |
876 | atom_card_info->reg_write = cail_reg_write; | |
877 | /* needed for iio ops */ | |
878 | if (adev->rio_mem) { | |
879 | atom_card_info->ioreg_read = cail_ioreg_read; | |
880 | atom_card_info->ioreg_write = cail_ioreg_write; | |
881 | } else { | |
882 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); | |
883 | atom_card_info->ioreg_read = cail_reg_read; | |
884 | atom_card_info->ioreg_write = cail_reg_write; | |
885 | } | |
886 | atom_card_info->mc_read = cail_mc_read; | |
887 | atom_card_info->mc_write = cail_mc_write; | |
888 | atom_card_info->pll_read = cail_pll_read; | |
889 | atom_card_info->pll_write = cail_pll_write; | |
890 | ||
891 | adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); | |
892 | if (!adev->mode_info.atom_context) { | |
893 | amdgpu_atombios_fini(adev); | |
894 | return -ENOMEM; | |
895 | } | |
896 | ||
897 | mutex_init(&adev->mode_info.atom_context->mutex); | |
898 | amdgpu_atombios_scratch_regs_init(adev); | |
899 | amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context); | |
900 | return 0; | |
901 | } | |
902 | ||
903 | /* if we get transitioned to only one device, take VGA back */ | |
904 | /** | |
905 | * amdgpu_vga_set_decode - enable/disable vga decode | |
906 | * | |
907 | * @cookie: amdgpu_device pointer | |
908 | * @state: enable/disable vga decode | |
909 | * | |
910 | * Enable/disable vga decode (all asics). | |
911 | * Returns VGA resource flags. | |
912 | */ | |
913 | static unsigned int amdgpu_vga_set_decode(void *cookie, bool state) | |
914 | { | |
915 | struct amdgpu_device *adev = cookie; | |
916 | amdgpu_asic_set_vga_state(adev, state); | |
917 | if (state) | |
918 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
919 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
920 | else | |
921 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
922 | } | |
923 | ||
924 | /** | |
925 | * amdgpu_check_pot_argument - check that argument is a power of two | |
926 | * | |
927 | * @arg: value to check | |
928 | * | |
929 | * Validates that a certain argument is a power of two (all asics). | |
930 | * Returns true if argument is valid. | |
931 | */ | |
932 | static bool amdgpu_check_pot_argument(int arg) | |
933 | { | |
934 | return (arg & (arg - 1)) == 0; | |
935 | } | |
936 | ||
937 | /** | |
938 | * amdgpu_check_arguments - validate module params | |
939 | * | |
940 | * @adev: amdgpu_device pointer | |
941 | * | |
942 | * Validates certain module parameters and updates | |
943 | * the associated values used by the driver (all asics). | |
944 | */ | |
945 | static void amdgpu_check_arguments(struct amdgpu_device *adev) | |
946 | { | |
947 | /* vramlimit must be a power of two */ | |
948 | if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) { | |
949 | dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n", | |
950 | amdgpu_vram_limit); | |
951 | amdgpu_vram_limit = 0; | |
952 | } | |
953 | ||
954 | if (amdgpu_gart_size != -1) { | |
955 | /* gtt size must be power of two and greater or equal to 32M */ | |
956 | if (amdgpu_gart_size < 32) { | |
957 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
958 | amdgpu_gart_size); | |
959 | amdgpu_gart_size = -1; | |
960 | } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) { | |
961 | dev_warn(adev->dev, "gart size (%d) must be a power of 2\n", | |
962 | amdgpu_gart_size); | |
963 | amdgpu_gart_size = -1; | |
964 | } | |
965 | } | |
966 | ||
967 | if (!amdgpu_check_pot_argument(amdgpu_vm_size)) { | |
968 | dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", | |
969 | amdgpu_vm_size); | |
970 | amdgpu_vm_size = 4; | |
971 | } | |
972 | ||
973 | if (amdgpu_vm_size < 1) { | |
974 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
975 | amdgpu_vm_size); | |
976 | amdgpu_vm_size = 4; | |
977 | } | |
978 | ||
979 | /* | |
980 | * Max GPUVM size for Cayman, SI and CI are 40 bits. | |
981 | */ | |
982 | if (amdgpu_vm_size > 1024) { | |
983 | dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", | |
984 | amdgpu_vm_size); | |
985 | amdgpu_vm_size = 4; | |
986 | } | |
987 | ||
988 | /* defines number of bits in page table versus page directory, | |
989 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
990 | * page table and the remaining bits are in the page directory */ | |
991 | if (amdgpu_vm_block_size == -1) { | |
992 | ||
993 | /* Total bits covered by PD + PTs */ | |
994 | unsigned bits = ilog2(amdgpu_vm_size) + 18; | |
995 | ||
996 | /* Make sure the PD is 4K in size up to 8GB address space. | |
997 | Above that split equal between PD and PTs */ | |
998 | if (amdgpu_vm_size <= 8) | |
999 | amdgpu_vm_block_size = bits - 9; | |
1000 | else | |
1001 | amdgpu_vm_block_size = (bits + 3) / 2; | |
1002 | ||
1003 | } else if (amdgpu_vm_block_size < 9) { | |
1004 | dev_warn(adev->dev, "VM page table size (%d) too small\n", | |
1005 | amdgpu_vm_block_size); | |
1006 | amdgpu_vm_block_size = 9; | |
1007 | } | |
1008 | ||
1009 | if (amdgpu_vm_block_size > 24 || | |
1010 | (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { | |
1011 | dev_warn(adev->dev, "VM page table size (%d) too large\n", | |
1012 | amdgpu_vm_block_size); | |
1013 | amdgpu_vm_block_size = 9; | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | /** | |
1018 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1019 | * | |
1020 | * @pdev: pci dev pointer | |
1021 | * @state: vga switcheroo state | |
1022 | * | |
1023 | * Callback for the switcheroo driver. Suspends or resumes the | |
1024 | * the asics before or after it is powered up using ACPI methods. | |
1025 | */ | |
1026 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) | |
1027 | { | |
1028 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1029 | ||
1030 | if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF) | |
1031 | return; | |
1032 | ||
1033 | if (state == VGA_SWITCHEROO_ON) { | |
1034 | unsigned d3_delay = dev->pdev->d3_delay; | |
1035 | ||
1036 | printk(KERN_INFO "amdgpu: switched on\n"); | |
1037 | /* don't suspend or resume card normally */ | |
1038 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1039 | ||
1040 | amdgpu_resume_kms(dev, true, true); | |
1041 | ||
1042 | dev->pdev->d3_delay = d3_delay; | |
1043 | ||
1044 | dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
1045 | drm_kms_helper_poll_enable(dev); | |
1046 | } else { | |
1047 | printk(KERN_INFO "amdgpu: switched off\n"); | |
1048 | drm_kms_helper_poll_disable(dev); | |
1049 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1050 | amdgpu_suspend_kms(dev, true, true); | |
1051 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; | |
1052 | } | |
1053 | } | |
1054 | ||
1055 | /** | |
1056 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1057 | * | |
1058 | * @pdev: pci dev pointer | |
1059 | * | |
1060 | * Callback for the switcheroo driver. Check of the switcheroo | |
1061 | * state can be changed. | |
1062 | * Returns true if the state can be changed, false if not. | |
1063 | */ | |
1064 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1065 | { | |
1066 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1067 | ||
1068 | /* | |
1069 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1070 | * locking inversion with the driver load path. And the access here is | |
1071 | * completely racy anyway. So don't bother with locking for now. | |
1072 | */ | |
1073 | return dev->open_count == 0; | |
1074 | } | |
1075 | ||
1076 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1077 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1078 | .reprobe = NULL, | |
1079 | .can_switch = amdgpu_switcheroo_can_switch, | |
1080 | }; | |
1081 | ||
1082 | int amdgpu_set_clockgating_state(struct amdgpu_device *adev, | |
1083 | enum amdgpu_ip_block_type block_type, | |
1084 | enum amdgpu_clockgating_state state) | |
1085 | { | |
1086 | int i, r = 0; | |
1087 | ||
1088 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1089 | if (adev->ip_blocks[i].type == block_type) { | |
1090 | r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, | |
1091 | state); | |
1092 | if (r) | |
1093 | return r; | |
1094 | } | |
1095 | } | |
1096 | return r; | |
1097 | } | |
1098 | ||
1099 | int amdgpu_set_powergating_state(struct amdgpu_device *adev, | |
1100 | enum amdgpu_ip_block_type block_type, | |
1101 | enum amdgpu_powergating_state state) | |
1102 | { | |
1103 | int i, r = 0; | |
1104 | ||
1105 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1106 | if (adev->ip_blocks[i].type == block_type) { | |
1107 | r = adev->ip_blocks[i].funcs->set_powergating_state(adev, | |
1108 | state); | |
1109 | if (r) | |
1110 | return r; | |
1111 | } | |
1112 | } | |
1113 | return r; | |
1114 | } | |
1115 | ||
1116 | const struct amdgpu_ip_block_version * amdgpu_get_ip_block( | |
1117 | struct amdgpu_device *adev, | |
1118 | enum amdgpu_ip_block_type type) | |
1119 | { | |
1120 | int i; | |
1121 | ||
1122 | for (i = 0; i < adev->num_ip_blocks; i++) | |
1123 | if (adev->ip_blocks[i].type == type) | |
1124 | return &adev->ip_blocks[i]; | |
1125 | ||
1126 | return NULL; | |
1127 | } | |
1128 | ||
1129 | /** | |
1130 | * amdgpu_ip_block_version_cmp | |
1131 | * | |
1132 | * @adev: amdgpu_device pointer | |
1133 | * @type: enum amdgpu_ip_block_type | |
1134 | * @major: major version | |
1135 | * @minor: minor version | |
1136 | * | |
1137 | * return 0 if equal or greater | |
1138 | * return 1 if smaller or the ip_block doesn't exist | |
1139 | */ | |
1140 | int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, | |
1141 | enum amdgpu_ip_block_type type, | |
1142 | u32 major, u32 minor) | |
1143 | { | |
1144 | const struct amdgpu_ip_block_version *ip_block; | |
1145 | ip_block = amdgpu_get_ip_block(adev, type); | |
1146 | ||
1147 | if (ip_block && ((ip_block->major > major) || | |
1148 | ((ip_block->major == major) && | |
1149 | (ip_block->minor >= minor)))) | |
1150 | return 0; | |
1151 | ||
1152 | return 1; | |
1153 | } | |
1154 | ||
1155 | static int amdgpu_early_init(struct amdgpu_device *adev) | |
1156 | { | |
1157 | int i, r = -EINVAL; | |
1158 | ||
1159 | switch (adev->asic_type) { | |
a2e73f56 AD |
1160 | #ifdef CONFIG_DRM_AMDGPU_CIK |
1161 | case CHIP_BONAIRE: | |
1162 | case CHIP_HAWAII: | |
1163 | case CHIP_KAVERI: | |
1164 | case CHIP_KABINI: | |
1165 | case CHIP_MULLINS: | |
1166 | if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) | |
1167 | adev->family = AMDGPU_FAMILY_CI; | |
1168 | else | |
1169 | adev->family = AMDGPU_FAMILY_KV; | |
1170 | ||
1171 | r = cik_set_ip_blocks(adev); | |
1172 | if (r) | |
1173 | return r; | |
1174 | break; | |
1175 | #endif | |
d38ceaf9 AD |
1176 | default: |
1177 | /* FIXME: not supported yet */ | |
1178 | return -EINVAL; | |
1179 | } | |
1180 | ||
1181 | ||
1182 | ||
1183 | if (adev->ip_blocks == NULL) { | |
1184 | DRM_ERROR("No IP blocks found!\n"); | |
1185 | return r; | |
1186 | } | |
1187 | ||
1188 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1189 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
1190 | DRM_ERROR("disabled ip block: %d\n", i); | |
1191 | adev->ip_block_enabled[i] = false; | |
1192 | } else { | |
1193 | if (adev->ip_blocks[i].funcs->early_init) { | |
1194 | r = adev->ip_blocks[i].funcs->early_init(adev); | |
1195 | if (r) | |
1196 | return r; | |
1197 | } | |
1198 | adev->ip_block_enabled[i] = true; | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | return 0; | |
1203 | } | |
1204 | ||
1205 | static int amdgpu_init(struct amdgpu_device *adev) | |
1206 | { | |
1207 | int i, r; | |
1208 | ||
1209 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1210 | if (!adev->ip_block_enabled[i]) | |
1211 | continue; | |
1212 | r = adev->ip_blocks[i].funcs->sw_init(adev); | |
1213 | if (r) | |
1214 | return r; | |
1215 | /* need to do gmc hw init early so we can allocate gpu mem */ | |
1216 | if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) { | |
1217 | r = amdgpu_vram_scratch_init(adev); | |
1218 | if (r) | |
1219 | return r; | |
1220 | r = adev->ip_blocks[i].funcs->hw_init(adev); | |
1221 | if (r) | |
1222 | return r; | |
1223 | r = amdgpu_wb_init(adev); | |
1224 | if (r) | |
1225 | return r; | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1230 | if (!adev->ip_block_enabled[i]) | |
1231 | continue; | |
1232 | /* gmc hw init is done early */ | |
1233 | if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) | |
1234 | continue; | |
1235 | r = adev->ip_blocks[i].funcs->hw_init(adev); | |
1236 | if (r) | |
1237 | return r; | |
1238 | } | |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | static int amdgpu_late_init(struct amdgpu_device *adev) | |
1244 | { | |
1245 | int i = 0, r; | |
1246 | ||
1247 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1248 | if (!adev->ip_block_enabled[i]) | |
1249 | continue; | |
1250 | /* enable clockgating to save power */ | |
1251 | r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, | |
1252 | AMDGPU_CG_STATE_GATE); | |
1253 | if (r) | |
1254 | return r; | |
1255 | if (adev->ip_blocks[i].funcs->late_init) { | |
1256 | r = adev->ip_blocks[i].funcs->late_init(adev); | |
1257 | if (r) | |
1258 | return r; | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | static int amdgpu_fini(struct amdgpu_device *adev) | |
1266 | { | |
1267 | int i, r; | |
1268 | ||
1269 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
1270 | if (!adev->ip_block_enabled[i]) | |
1271 | continue; | |
1272 | if (adev->ip_blocks[i].type == AMDGPU_IP_BLOCK_TYPE_GMC) { | |
1273 | amdgpu_wb_fini(adev); | |
1274 | amdgpu_vram_scratch_fini(adev); | |
1275 | } | |
1276 | /* ungate blocks before hw fini so that we can shutdown the blocks safely */ | |
1277 | r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, | |
1278 | AMDGPU_CG_STATE_UNGATE); | |
1279 | if (r) | |
1280 | return r; | |
1281 | r = adev->ip_blocks[i].funcs->hw_fini(adev); | |
1282 | /* XXX handle errors */ | |
1283 | } | |
1284 | ||
1285 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
1286 | if (!adev->ip_block_enabled[i]) | |
1287 | continue; | |
1288 | r = adev->ip_blocks[i].funcs->sw_fini(adev); | |
1289 | /* XXX handle errors */ | |
1290 | adev->ip_block_enabled[i] = false; | |
1291 | } | |
1292 | ||
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | static int amdgpu_suspend(struct amdgpu_device *adev) | |
1297 | { | |
1298 | int i, r; | |
1299 | ||
1300 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { | |
1301 | if (!adev->ip_block_enabled[i]) | |
1302 | continue; | |
1303 | /* ungate blocks so that suspend can properly shut them down */ | |
1304 | r = adev->ip_blocks[i].funcs->set_clockgating_state(adev, | |
1305 | AMDGPU_CG_STATE_UNGATE); | |
1306 | /* XXX handle errors */ | |
1307 | r = adev->ip_blocks[i].funcs->suspend(adev); | |
1308 | /* XXX handle errors */ | |
1309 | } | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
1314 | static int amdgpu_resume(struct amdgpu_device *adev) | |
1315 | { | |
1316 | int i, r; | |
1317 | ||
1318 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1319 | if (!adev->ip_block_enabled[i]) | |
1320 | continue; | |
1321 | r = adev->ip_blocks[i].funcs->resume(adev); | |
1322 | if (r) | |
1323 | return r; | |
1324 | } | |
1325 | ||
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | /** | |
1330 | * amdgpu_device_init - initialize the driver | |
1331 | * | |
1332 | * @adev: amdgpu_device pointer | |
1333 | * @pdev: drm dev pointer | |
1334 | * @pdev: pci dev pointer | |
1335 | * @flags: driver flags | |
1336 | * | |
1337 | * Initializes the driver info and hw (all asics). | |
1338 | * Returns 0 for success or an error on failure. | |
1339 | * Called at driver startup. | |
1340 | */ | |
1341 | int amdgpu_device_init(struct amdgpu_device *adev, | |
1342 | struct drm_device *ddev, | |
1343 | struct pci_dev *pdev, | |
1344 | uint32_t flags) | |
1345 | { | |
1346 | int r, i; | |
1347 | bool runtime = false; | |
1348 | ||
1349 | adev->shutdown = false; | |
1350 | adev->dev = &pdev->dev; | |
1351 | adev->ddev = ddev; | |
1352 | adev->pdev = pdev; | |
1353 | adev->flags = flags; | |
1354 | adev->asic_type = flags & AMDGPU_ASIC_MASK; | |
1355 | adev->is_atom_bios = false; | |
1356 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; | |
1357 | adev->mc.gtt_size = 512 * 1024 * 1024; | |
1358 | adev->accel_working = false; | |
1359 | adev->num_rings = 0; | |
1360 | adev->mman.buffer_funcs = NULL; | |
1361 | adev->mman.buffer_funcs_ring = NULL; | |
1362 | adev->vm_manager.vm_pte_funcs = NULL; | |
1363 | adev->vm_manager.vm_pte_funcs_ring = NULL; | |
1364 | adev->gart.gart_funcs = NULL; | |
1365 | adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS); | |
1366 | ||
1367 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
1368 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
1369 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
1370 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
1371 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; | |
1372 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
1373 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
1374 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
1375 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; | |
1376 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
1377 | ||
1378 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", | |
1379 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
1380 | pdev->subsystem_vendor, pdev->subsystem_device); | |
1381 | ||
1382 | /* mutex initialization are all done here so we | |
1383 | * can recall function without having locking issues */ | |
1384 | mutex_init(&adev->ring_lock); | |
1385 | atomic_set(&adev->irq.ih.lock, 0); | |
1386 | mutex_init(&adev->gem.mutex); | |
1387 | mutex_init(&adev->pm.mutex); | |
1388 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
1389 | mutex_init(&adev->srbm_mutex); | |
1390 | mutex_init(&adev->grbm_idx_mutex); | |
1391 | init_rwsem(&adev->pm.mclk_lock); | |
1392 | init_rwsem(&adev->exclusive_lock); | |
1393 | mutex_init(&adev->mn_lock); | |
1394 | hash_init(adev->mn_hash); | |
1395 | ||
1396 | amdgpu_check_arguments(adev); | |
1397 | ||
1398 | /* Registers mapping */ | |
1399 | /* TODO: block userspace mapping of io register */ | |
1400 | spin_lock_init(&adev->mmio_idx_lock); | |
1401 | spin_lock_init(&adev->smc_idx_lock); | |
1402 | spin_lock_init(&adev->pcie_idx_lock); | |
1403 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
1404 | spin_lock_init(&adev->didt_idx_lock); | |
1405 | spin_lock_init(&adev->audio_endpt_idx_lock); | |
1406 | ||
1407 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
1408 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
1409 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); | |
1410 | if (adev->rmmio == NULL) { | |
1411 | return -ENOMEM; | |
1412 | } | |
1413 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
1414 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
1415 | ||
1416 | /* doorbell bar mapping */ | |
1417 | amdgpu_doorbell_init(adev); | |
1418 | ||
1419 | /* io port mapping */ | |
1420 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1421 | if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) { | |
1422 | adev->rio_mem_size = pci_resource_len(adev->pdev, i); | |
1423 | adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size); | |
1424 | break; | |
1425 | } | |
1426 | } | |
1427 | if (adev->rio_mem == NULL) | |
1428 | DRM_ERROR("Unable to find PCI I/O BAR\n"); | |
1429 | ||
1430 | /* early init functions */ | |
1431 | r = amdgpu_early_init(adev); | |
1432 | if (r) | |
1433 | return r; | |
1434 | ||
1435 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ | |
1436 | /* this will fail for cards that aren't VGA class devices, just | |
1437 | * ignore it */ | |
1438 | vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode); | |
1439 | ||
1440 | if (amdgpu_runtime_pm == 1) | |
1441 | runtime = true; | |
1442 | if (amdgpu_device_is_px(ddev)) | |
1443 | runtime = true; | |
1444 | vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime); | |
1445 | if (runtime) | |
1446 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
1447 | ||
1448 | /* Read BIOS */ | |
1449 | if (!amdgpu_get_bios(adev)) | |
1450 | return -EINVAL; | |
1451 | /* Must be an ATOMBIOS */ | |
1452 | if (!adev->is_atom_bios) { | |
1453 | dev_err(adev->dev, "Expecting atombios for GPU\n"); | |
1454 | return -EINVAL; | |
1455 | } | |
1456 | r = amdgpu_atombios_init(adev); | |
1457 | if (r) | |
1458 | return r; | |
1459 | ||
1460 | /* Post card if necessary */ | |
1461 | if (!amdgpu_card_posted(adev)) { | |
1462 | if (!adev->bios) { | |
1463 | dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n"); | |
1464 | return -EINVAL; | |
1465 | } | |
1466 | DRM_INFO("GPU not posted. posting now...\n"); | |
1467 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
1468 | } | |
1469 | ||
1470 | /* Initialize clocks */ | |
1471 | r = amdgpu_atombios_get_clock_info(adev); | |
1472 | if (r) | |
1473 | return r; | |
1474 | /* init i2c buses */ | |
1475 | amdgpu_atombios_i2c_init(adev); | |
1476 | ||
1477 | /* Fence driver */ | |
1478 | r = amdgpu_fence_driver_init(adev); | |
1479 | if (r) | |
1480 | return r; | |
1481 | ||
1482 | /* init the mode config */ | |
1483 | drm_mode_config_init(adev->ddev); | |
1484 | ||
1485 | r = amdgpu_init(adev); | |
1486 | if (r) { | |
1487 | amdgpu_fini(adev); | |
1488 | return r; | |
1489 | } | |
1490 | ||
1491 | adev->accel_working = true; | |
1492 | ||
1493 | amdgpu_fbdev_init(adev); | |
1494 | ||
1495 | r = amdgpu_ib_pool_init(adev); | |
1496 | if (r) { | |
1497 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
1498 | return r; | |
1499 | } | |
1500 | ||
1501 | r = amdgpu_ib_ring_tests(adev); | |
1502 | if (r) | |
1503 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1504 | ||
1505 | r = amdgpu_gem_debugfs_init(adev); | |
1506 | if (r) { | |
1507 | DRM_ERROR("registering gem debugfs failed (%d).\n", r); | |
1508 | } | |
1509 | ||
1510 | r = amdgpu_debugfs_regs_init(adev); | |
1511 | if (r) { | |
1512 | DRM_ERROR("registering register debugfs failed (%d).\n", r); | |
1513 | } | |
1514 | ||
1515 | if ((amdgpu_testing & 1)) { | |
1516 | if (adev->accel_working) | |
1517 | amdgpu_test_moves(adev); | |
1518 | else | |
1519 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
1520 | } | |
1521 | if ((amdgpu_testing & 2)) { | |
1522 | if (adev->accel_working) | |
1523 | amdgpu_test_syncing(adev); | |
1524 | else | |
1525 | DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n"); | |
1526 | } | |
1527 | if (amdgpu_benchmarking) { | |
1528 | if (adev->accel_working) | |
1529 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
1530 | else | |
1531 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
1532 | } | |
1533 | ||
1534 | /* enable clockgating, etc. after ib tests, etc. since some blocks require | |
1535 | * explicit gating rather than handling it automatically. | |
1536 | */ | |
1537 | r = amdgpu_late_init(adev); | |
1538 | if (r) | |
1539 | return r; | |
1540 | ||
1541 | return 0; | |
1542 | } | |
1543 | ||
1544 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev); | |
1545 | ||
1546 | /** | |
1547 | * amdgpu_device_fini - tear down the driver | |
1548 | * | |
1549 | * @adev: amdgpu_device pointer | |
1550 | * | |
1551 | * Tear down the driver info (all asics). | |
1552 | * Called at driver shutdown. | |
1553 | */ | |
1554 | void amdgpu_device_fini(struct amdgpu_device *adev) | |
1555 | { | |
1556 | int r; | |
1557 | ||
1558 | DRM_INFO("amdgpu: finishing device.\n"); | |
1559 | adev->shutdown = true; | |
1560 | /* evict vram memory */ | |
1561 | amdgpu_bo_evict_vram(adev); | |
1562 | amdgpu_ib_pool_fini(adev); | |
1563 | amdgpu_fence_driver_fini(adev); | |
1564 | amdgpu_fbdev_fini(adev); | |
1565 | r = amdgpu_fini(adev); | |
1566 | if (adev->ip_block_enabled) | |
1567 | kfree(adev->ip_block_enabled); | |
1568 | adev->ip_block_enabled = NULL; | |
1569 | adev->accel_working = false; | |
1570 | /* free i2c buses */ | |
1571 | amdgpu_i2c_fini(adev); | |
1572 | amdgpu_atombios_fini(adev); | |
1573 | kfree(adev->bios); | |
1574 | adev->bios = NULL; | |
1575 | vga_switcheroo_unregister_client(adev->pdev); | |
1576 | vga_client_register(adev->pdev, NULL, NULL, NULL); | |
1577 | if (adev->rio_mem) | |
1578 | pci_iounmap(adev->pdev, adev->rio_mem); | |
1579 | adev->rio_mem = NULL; | |
1580 | iounmap(adev->rmmio); | |
1581 | adev->rmmio = NULL; | |
1582 | amdgpu_doorbell_fini(adev); | |
1583 | amdgpu_debugfs_regs_cleanup(adev); | |
1584 | amdgpu_debugfs_remove_files(adev); | |
1585 | } | |
1586 | ||
1587 | ||
1588 | /* | |
1589 | * Suspend & resume. | |
1590 | */ | |
1591 | /** | |
1592 | * amdgpu_suspend_kms - initiate device suspend | |
1593 | * | |
1594 | * @pdev: drm dev pointer | |
1595 | * @state: suspend state | |
1596 | * | |
1597 | * Puts the hw in the suspend state (all asics). | |
1598 | * Returns 0 for success or an error on failure. | |
1599 | * Called at driver suspend. | |
1600 | */ | |
1601 | int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) | |
1602 | { | |
1603 | struct amdgpu_device *adev; | |
1604 | struct drm_crtc *crtc; | |
1605 | struct drm_connector *connector; | |
1606 | int i, r; | |
1607 | bool force_completion = false; | |
1608 | ||
1609 | if (dev == NULL || dev->dev_private == NULL) { | |
1610 | return -ENODEV; | |
1611 | } | |
1612 | ||
1613 | adev = dev->dev_private; | |
1614 | ||
1615 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1616 | return 0; | |
1617 | ||
1618 | drm_kms_helper_poll_disable(dev); | |
1619 | ||
1620 | /* turn off display hw */ | |
1621 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1622 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); | |
1623 | } | |
1624 | ||
1625 | /* unpin the front buffers */ | |
1626 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
1627 | struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); | |
1628 | struct amdgpu_bo *robj; | |
1629 | ||
1630 | if (rfb == NULL || rfb->obj == NULL) { | |
1631 | continue; | |
1632 | } | |
1633 | robj = gem_to_amdgpu_bo(rfb->obj); | |
1634 | /* don't unpin kernel fb objects */ | |
1635 | if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { | |
1636 | r = amdgpu_bo_reserve(robj, false); | |
1637 | if (r == 0) { | |
1638 | amdgpu_bo_unpin(robj); | |
1639 | amdgpu_bo_unreserve(robj); | |
1640 | } | |
1641 | } | |
1642 | } | |
1643 | /* evict vram memory */ | |
1644 | amdgpu_bo_evict_vram(adev); | |
1645 | ||
1646 | /* wait for gpu to finish processing current batch */ | |
1647 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
1648 | struct amdgpu_ring *ring = adev->rings[i]; | |
1649 | if (!ring) | |
1650 | continue; | |
1651 | ||
1652 | r = amdgpu_fence_wait_empty(ring); | |
1653 | if (r) { | |
1654 | /* delay GPU reset to resume */ | |
1655 | force_completion = true; | |
1656 | } | |
1657 | } | |
1658 | if (force_completion) { | |
1659 | amdgpu_fence_driver_force_completion(adev); | |
1660 | } | |
1661 | ||
1662 | r = amdgpu_suspend(adev); | |
1663 | ||
1664 | /* evict remaining vram memory */ | |
1665 | amdgpu_bo_evict_vram(adev); | |
1666 | ||
1667 | pci_save_state(dev->pdev); | |
1668 | if (suspend) { | |
1669 | /* Shut down the device */ | |
1670 | pci_disable_device(dev->pdev); | |
1671 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
1672 | } | |
1673 | ||
1674 | if (fbcon) { | |
1675 | console_lock(); | |
1676 | amdgpu_fbdev_set_suspend(adev, 1); | |
1677 | console_unlock(); | |
1678 | } | |
1679 | return 0; | |
1680 | } | |
1681 | ||
1682 | /** | |
1683 | * amdgpu_resume_kms - initiate device resume | |
1684 | * | |
1685 | * @pdev: drm dev pointer | |
1686 | * | |
1687 | * Bring the hw back to operating state (all asics). | |
1688 | * Returns 0 for success or an error on failure. | |
1689 | * Called at driver resume. | |
1690 | */ | |
1691 | int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon) | |
1692 | { | |
1693 | struct drm_connector *connector; | |
1694 | struct amdgpu_device *adev = dev->dev_private; | |
1695 | int r; | |
1696 | ||
1697 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
1698 | return 0; | |
1699 | ||
1700 | if (fbcon) { | |
1701 | console_lock(); | |
1702 | } | |
1703 | if (resume) { | |
1704 | pci_set_power_state(dev->pdev, PCI_D0); | |
1705 | pci_restore_state(dev->pdev); | |
1706 | if (pci_enable_device(dev->pdev)) { | |
1707 | if (fbcon) | |
1708 | console_unlock(); | |
1709 | return -1; | |
1710 | } | |
1711 | } | |
1712 | ||
1713 | /* post card */ | |
1714 | amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
1715 | ||
1716 | r = amdgpu_resume(adev); | |
1717 | ||
1718 | r = amdgpu_ib_ring_tests(adev); | |
1719 | if (r) | |
1720 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
1721 | ||
1722 | r = amdgpu_late_init(adev); | |
1723 | if (r) | |
1724 | return r; | |
1725 | ||
1726 | /* blat the mode back in */ | |
1727 | if (fbcon) { | |
1728 | drm_helper_resume_force_mode(dev); | |
1729 | /* turn on display hw */ | |
1730 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1731 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | drm_kms_helper_poll_enable(dev); | |
1736 | ||
1737 | if (fbcon) { | |
1738 | amdgpu_fbdev_set_suspend(adev, 0); | |
1739 | console_unlock(); | |
1740 | } | |
1741 | ||
1742 | return 0; | |
1743 | } | |
1744 | ||
1745 | /** | |
1746 | * amdgpu_gpu_reset - reset the asic | |
1747 | * | |
1748 | * @adev: amdgpu device pointer | |
1749 | * | |
1750 | * Attempt the reset the GPU if it has hung (all asics). | |
1751 | * Returns 0 for success or an error on failure. | |
1752 | */ | |
1753 | int amdgpu_gpu_reset(struct amdgpu_device *adev) | |
1754 | { | |
1755 | unsigned ring_sizes[AMDGPU_MAX_RINGS]; | |
1756 | uint32_t *ring_data[AMDGPU_MAX_RINGS]; | |
1757 | ||
1758 | bool saved = false; | |
1759 | ||
1760 | int i, r; | |
1761 | int resched; | |
1762 | ||
1763 | down_write(&adev->exclusive_lock); | |
1764 | ||
1765 | if (!adev->needs_reset) { | |
1766 | up_write(&adev->exclusive_lock); | |
1767 | return 0; | |
1768 | } | |
1769 | ||
1770 | adev->needs_reset = false; | |
1771 | ||
1772 | /* block TTM */ | |
1773 | resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); | |
1774 | ||
1775 | r = amdgpu_suspend(adev); | |
1776 | ||
1777 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1778 | struct amdgpu_ring *ring = adev->rings[i]; | |
1779 | if (!ring) | |
1780 | continue; | |
1781 | ||
1782 | ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]); | |
1783 | if (ring_sizes[i]) { | |
1784 | saved = true; | |
1785 | dev_info(adev->dev, "Saved %d dwords of commands " | |
1786 | "on ring %d.\n", ring_sizes[i], i); | |
1787 | } | |
1788 | } | |
1789 | ||
1790 | retry: | |
1791 | r = amdgpu_asic_reset(adev); | |
1792 | if (!r) { | |
1793 | dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); | |
1794 | r = amdgpu_resume(adev); | |
1795 | } | |
1796 | ||
1797 | if (!r) { | |
1798 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1799 | struct amdgpu_ring *ring = adev->rings[i]; | |
1800 | if (!ring) | |
1801 | continue; | |
1802 | ||
1803 | amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]); | |
1804 | ring_sizes[i] = 0; | |
1805 | ring_data[i] = NULL; | |
1806 | } | |
1807 | ||
1808 | r = amdgpu_ib_ring_tests(adev); | |
1809 | if (r) { | |
1810 | dev_err(adev->dev, "ib ring test failed (%d).\n", r); | |
1811 | if (saved) { | |
1812 | saved = false; | |
1813 | r = amdgpu_suspend(adev); | |
1814 | goto retry; | |
1815 | } | |
1816 | } | |
1817 | } else { | |
1818 | amdgpu_fence_driver_force_completion(adev); | |
1819 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
1820 | if (adev->rings[i]) | |
1821 | kfree(ring_data[i]); | |
1822 | } | |
1823 | } | |
1824 | ||
1825 | drm_helper_resume_force_mode(adev->ddev); | |
1826 | ||
1827 | ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); | |
1828 | if (r) { | |
1829 | /* bad news, how to tell it to userspace ? */ | |
1830 | dev_info(adev->dev, "GPU reset failed\n"); | |
1831 | } | |
1832 | ||
1833 | up_write(&adev->exclusive_lock); | |
1834 | return r; | |
1835 | } | |
1836 | ||
1837 | ||
1838 | /* | |
1839 | * Debugfs | |
1840 | */ | |
1841 | int amdgpu_debugfs_add_files(struct amdgpu_device *adev, | |
1842 | struct drm_info_list *files, | |
1843 | unsigned nfiles) | |
1844 | { | |
1845 | unsigned i; | |
1846 | ||
1847 | for (i = 0; i < adev->debugfs_count; i++) { | |
1848 | if (adev->debugfs[i].files == files) { | |
1849 | /* Already registered */ | |
1850 | return 0; | |
1851 | } | |
1852 | } | |
1853 | ||
1854 | i = adev->debugfs_count + 1; | |
1855 | if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { | |
1856 | DRM_ERROR("Reached maximum number of debugfs components.\n"); | |
1857 | DRM_ERROR("Report so we increase " | |
1858 | "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); | |
1859 | return -EINVAL; | |
1860 | } | |
1861 | adev->debugfs[adev->debugfs_count].files = files; | |
1862 | adev->debugfs[adev->debugfs_count].num_files = nfiles; | |
1863 | adev->debugfs_count = i; | |
1864 | #if defined(CONFIG_DEBUG_FS) | |
1865 | drm_debugfs_create_files(files, nfiles, | |
1866 | adev->ddev->control->debugfs_root, | |
1867 | adev->ddev->control); | |
1868 | drm_debugfs_create_files(files, nfiles, | |
1869 | adev->ddev->primary->debugfs_root, | |
1870 | adev->ddev->primary); | |
1871 | #endif | |
1872 | return 0; | |
1873 | } | |
1874 | ||
1875 | static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev) | |
1876 | { | |
1877 | #if defined(CONFIG_DEBUG_FS) | |
1878 | unsigned i; | |
1879 | ||
1880 | for (i = 0; i < adev->debugfs_count; i++) { | |
1881 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
1882 | adev->debugfs[i].num_files, | |
1883 | adev->ddev->control); | |
1884 | drm_debugfs_remove_files(adev->debugfs[i].files, | |
1885 | adev->debugfs[i].num_files, | |
1886 | adev->ddev->primary); | |
1887 | } | |
1888 | #endif | |
1889 | } | |
1890 | ||
1891 | #if defined(CONFIG_DEBUG_FS) | |
1892 | ||
1893 | static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, | |
1894 | size_t size, loff_t *pos) | |
1895 | { | |
1896 | struct amdgpu_device *adev = f->f_inode->i_private; | |
1897 | ssize_t result = 0; | |
1898 | int r; | |
1899 | ||
1900 | if (size & 0x3 || *pos & 0x3) | |
1901 | return -EINVAL; | |
1902 | ||
1903 | while (size) { | |
1904 | uint32_t value; | |
1905 | ||
1906 | if (*pos > adev->rmmio_size) | |
1907 | return result; | |
1908 | ||
1909 | value = RREG32(*pos >> 2); | |
1910 | r = put_user(value, (uint32_t *)buf); | |
1911 | if (r) | |
1912 | return r; | |
1913 | ||
1914 | result += 4; | |
1915 | buf += 4; | |
1916 | *pos += 4; | |
1917 | size -= 4; | |
1918 | } | |
1919 | ||
1920 | return result; | |
1921 | } | |
1922 | ||
1923 | static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, | |
1924 | size_t size, loff_t *pos) | |
1925 | { | |
1926 | struct amdgpu_device *adev = f->f_inode->i_private; | |
1927 | ssize_t result = 0; | |
1928 | int r; | |
1929 | ||
1930 | if (size & 0x3 || *pos & 0x3) | |
1931 | return -EINVAL; | |
1932 | ||
1933 | while (size) { | |
1934 | uint32_t value; | |
1935 | ||
1936 | if (*pos > adev->rmmio_size) | |
1937 | return result; | |
1938 | ||
1939 | r = get_user(value, (uint32_t *)buf); | |
1940 | if (r) | |
1941 | return r; | |
1942 | ||
1943 | WREG32(*pos >> 2, value); | |
1944 | ||
1945 | result += 4; | |
1946 | buf += 4; | |
1947 | *pos += 4; | |
1948 | size -= 4; | |
1949 | } | |
1950 | ||
1951 | return result; | |
1952 | } | |
1953 | ||
1954 | static const struct file_operations amdgpu_debugfs_regs_fops = { | |
1955 | .owner = THIS_MODULE, | |
1956 | .read = amdgpu_debugfs_regs_read, | |
1957 | .write = amdgpu_debugfs_regs_write, | |
1958 | .llseek = default_llseek | |
1959 | }; | |
1960 | ||
1961 | static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) | |
1962 | { | |
1963 | struct drm_minor *minor = adev->ddev->primary; | |
1964 | struct dentry *ent, *root = minor->debugfs_root; | |
1965 | ||
1966 | ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root, | |
1967 | adev, &amdgpu_debugfs_regs_fops); | |
1968 | if (IS_ERR(ent)) | |
1969 | return PTR_ERR(ent); | |
1970 | i_size_write(ent->d_inode, adev->rmmio_size); | |
1971 | adev->debugfs_regs = ent; | |
1972 | ||
1973 | return 0; | |
1974 | } | |
1975 | ||
1976 | static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) | |
1977 | { | |
1978 | debugfs_remove(adev->debugfs_regs); | |
1979 | adev->debugfs_regs = NULL; | |
1980 | } | |
1981 | ||
1982 | int amdgpu_debugfs_init(struct drm_minor *minor) | |
1983 | { | |
1984 | return 0; | |
1985 | } | |
1986 | ||
1987 | void amdgpu_debugfs_cleanup(struct drm_minor *minor) | |
1988 | { | |
1989 | } | |
1990 | #endif |