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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
b1ddf548 | 28 | #include <linux/power_supply.h> |
0875dc9e | 29 | #include <linux/kthread.h> |
fdf2f6c5 | 30 | #include <linux/module.h> |
d38ceaf9 AD |
31 | #include <linux/console.h> |
32 | #include <linux/slab.h> | |
c5452d42 | 33 | #include <linux/pci.h> |
fdf2f6c5 | 34 | |
4562236b | 35 | #include <drm/drm_atomic_helper.h> |
fcd70cd3 | 36 | #include <drm/drm_probe_helper.h> |
d38ceaf9 AD |
37 | #include <drm/amdgpu_drm.h> |
38 | #include <linux/vgaarb.h> | |
39 | #include <linux/vga_switcheroo.h> | |
40 | #include <linux/efi.h> | |
41 | #include "amdgpu.h" | |
f4b373f4 | 42 | #include "amdgpu_trace.h" |
d38ceaf9 AD |
43 | #include "amdgpu_i2c.h" |
44 | #include "atom.h" | |
45 | #include "amdgpu_atombios.h" | |
a5bde2f9 | 46 | #include "amdgpu_atomfirmware.h" |
d0dd7f0c | 47 | #include "amd_pcie.h" |
33f34802 KW |
48 | #ifdef CONFIG_DRM_AMDGPU_SI |
49 | #include "si.h" | |
50 | #endif | |
a2e73f56 AD |
51 | #ifdef CONFIG_DRM_AMDGPU_CIK |
52 | #include "cik.h" | |
53 | #endif | |
aaa36a97 | 54 | #include "vi.h" |
460826e6 | 55 | #include "soc15.h" |
0a5b8c7b | 56 | #include "nv.h" |
d38ceaf9 | 57 | #include "bif/bif_4_1_d.h" |
9accf2fd | 58 | #include <linux/pci.h> |
bec86378 | 59 | #include <linux/firmware.h> |
89041940 | 60 | #include "amdgpu_vf_error.h" |
d38ceaf9 | 61 | |
ba997709 | 62 | #include "amdgpu_amdkfd.h" |
d2f52ac8 | 63 | #include "amdgpu_pm.h" |
d38ceaf9 | 64 | |
5183411b | 65 | #include "amdgpu_xgmi.h" |
c030f2e4 | 66 | #include "amdgpu_ras.h" |
9c7c85f7 | 67 | #include "amdgpu_pmu.h" |
bd607166 | 68 | #include "amdgpu_fru_eeprom.h" |
04442bf7 | 69 | #include "amdgpu_reset.h" |
5183411b | 70 | |
d5ea093e | 71 | #include <linux/suspend.h> |
c6a6e2db | 72 | #include <drm/task_barrier.h> |
3f12acc8 | 73 | #include <linux/pm_runtime.h> |
d5ea093e | 74 | |
f89f8c6b AG |
75 | #include <drm/drm_drv.h> |
76 | ||
e2a75f88 | 77 | MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin"); |
3f76dced | 78 | MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin"); |
2d2e5e7e | 79 | MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin"); |
ad5a67a7 | 80 | MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); |
54c4d17e | 81 | MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); |
65e60f6e | 82 | MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); |
b51a26a0 | 83 | MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin"); |
23c6268e | 84 | MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin"); |
ed42cfe1 | 85 | MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin"); |
42b325e5 | 86 | MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); |
4e52a9f8 | 87 | MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin"); |
8bf84f60 | 88 | MODULE_FIRMWARE("amdgpu/yellow_carp_gpu_info.bin"); |
e2a75f88 | 89 | |
2dc80b00 S |
90 | #define AMDGPU_RESUME_MS 2000 |
91 | ||
050091ab | 92 | const char *amdgpu_asic_name[] = { |
da69c161 KW |
93 | "TAHITI", |
94 | "PITCAIRN", | |
95 | "VERDE", | |
96 | "OLAND", | |
97 | "HAINAN", | |
d38ceaf9 AD |
98 | "BONAIRE", |
99 | "KAVERI", | |
100 | "KABINI", | |
101 | "HAWAII", | |
102 | "MULLINS", | |
103 | "TOPAZ", | |
104 | "TONGA", | |
48299f95 | 105 | "FIJI", |
d38ceaf9 | 106 | "CARRIZO", |
139f4917 | 107 | "STONEY", |
2cc0c0b5 FC |
108 | "POLARIS10", |
109 | "POLARIS11", | |
c4642a47 | 110 | "POLARIS12", |
48ff108d | 111 | "VEGAM", |
d4196f01 | 112 | "VEGA10", |
8fab806a | 113 | "VEGA12", |
956fcddc | 114 | "VEGA20", |
2ca8a5d2 | 115 | "RAVEN", |
d6c3b24e | 116 | "ARCTURUS", |
1eee4228 | 117 | "RENOIR", |
d46b417a | 118 | "ALDEBARAN", |
852a6626 | 119 | "NAVI10", |
d0f56dc2 | 120 | "CYAN_SKILLFISH", |
87dbad02 | 121 | "NAVI14", |
9802f5d7 | 122 | "NAVI12", |
ccaf72d3 | 123 | "SIENNA_CICHLID", |
ddd8fbe7 | 124 | "NAVY_FLOUNDER", |
4f1e9a76 | 125 | "VANGOGH", |
a2468e04 | 126 | "DIMGREY_CAVEFISH", |
6f169591 | 127 | "BEIGE_GOBY", |
ee9236b7 | 128 | "YELLOW_CARP", |
d38ceaf9 AD |
129 | "LAST", |
130 | }; | |
131 | ||
dcea6e65 KR |
132 | /** |
133 | * DOC: pcie_replay_count | |
134 | * | |
135 | * The amdgpu driver provides a sysfs API for reporting the total number | |
136 | * of PCIe replays (NAKs) | |
137 | * The file pcie_replay_count is used for this and returns the total | |
138 | * number of replays as a sum of the NAKs generated and NAKs received | |
139 | */ | |
140 | ||
141 | static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev, | |
142 | struct device_attribute *attr, char *buf) | |
143 | { | |
144 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 145 | struct amdgpu_device *adev = drm_to_adev(ddev); |
dcea6e65 KR |
146 | uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); |
147 | ||
36000c7a | 148 | return sysfs_emit(buf, "%llu\n", cnt); |
dcea6e65 KR |
149 | } |
150 | ||
151 | static DEVICE_ATTR(pcie_replay_count, S_IRUGO, | |
152 | amdgpu_device_get_pcie_replay_count, NULL); | |
153 | ||
5494d864 AD |
154 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); |
155 | ||
bd607166 KR |
156 | /** |
157 | * DOC: product_name | |
158 | * | |
159 | * The amdgpu driver provides a sysfs API for reporting the product name | |
160 | * for the device | |
161 | * The file serial_number is used for this and returns the product name | |
162 | * as returned from the FRU. | |
163 | * NOTE: This is only available for certain server cards | |
164 | */ | |
165 | ||
166 | static ssize_t amdgpu_device_get_product_name(struct device *dev, | |
167 | struct device_attribute *attr, char *buf) | |
168 | { | |
169 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 170 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 171 | |
36000c7a | 172 | return sysfs_emit(buf, "%s\n", adev->product_name); |
bd607166 KR |
173 | } |
174 | ||
175 | static DEVICE_ATTR(product_name, S_IRUGO, | |
176 | amdgpu_device_get_product_name, NULL); | |
177 | ||
178 | /** | |
179 | * DOC: product_number | |
180 | * | |
181 | * The amdgpu driver provides a sysfs API for reporting the part number | |
182 | * for the device | |
183 | * The file serial_number is used for this and returns the part number | |
184 | * as returned from the FRU. | |
185 | * NOTE: This is only available for certain server cards | |
186 | */ | |
187 | ||
188 | static ssize_t amdgpu_device_get_product_number(struct device *dev, | |
189 | struct device_attribute *attr, char *buf) | |
190 | { | |
191 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 192 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 193 | |
36000c7a | 194 | return sysfs_emit(buf, "%s\n", adev->product_number); |
bd607166 KR |
195 | } |
196 | ||
197 | static DEVICE_ATTR(product_number, S_IRUGO, | |
198 | amdgpu_device_get_product_number, NULL); | |
199 | ||
200 | /** | |
201 | * DOC: serial_number | |
202 | * | |
203 | * The amdgpu driver provides a sysfs API for reporting the serial number | |
204 | * for the device | |
205 | * The file serial_number is used for this and returns the serial number | |
206 | * as returned from the FRU. | |
207 | * NOTE: This is only available for certain server cards | |
208 | */ | |
209 | ||
210 | static ssize_t amdgpu_device_get_serial_number(struct device *dev, | |
211 | struct device_attribute *attr, char *buf) | |
212 | { | |
213 | struct drm_device *ddev = dev_get_drvdata(dev); | |
1348969a | 214 | struct amdgpu_device *adev = drm_to_adev(ddev); |
bd607166 | 215 | |
36000c7a | 216 | return sysfs_emit(buf, "%s\n", adev->serial); |
bd607166 KR |
217 | } |
218 | ||
219 | static DEVICE_ATTR(serial_number, S_IRUGO, | |
220 | amdgpu_device_get_serial_number, NULL); | |
221 | ||
fd496ca8 | 222 | /** |
b98c6299 | 223 | * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control |
fd496ca8 AD |
224 | * |
225 | * @dev: drm_device pointer | |
226 | * | |
b98c6299 | 227 | * Returns true if the device is a dGPU with ATPX power control, |
fd496ca8 AD |
228 | * otherwise return false. |
229 | */ | |
b98c6299 | 230 | bool amdgpu_device_supports_px(struct drm_device *dev) |
fd496ca8 AD |
231 | { |
232 | struct amdgpu_device *adev = drm_to_adev(dev); | |
233 | ||
b98c6299 | 234 | if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid()) |
fd496ca8 AD |
235 | return true; |
236 | return false; | |
237 | } | |
238 | ||
e3ecdffa | 239 | /** |
0330b848 | 240 | * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources |
e3ecdffa AD |
241 | * |
242 | * @dev: drm_device pointer | |
243 | * | |
b98c6299 | 244 | * Returns true if the device is a dGPU with ACPI power control, |
e3ecdffa AD |
245 | * otherwise return false. |
246 | */ | |
31af062a | 247 | bool amdgpu_device_supports_boco(struct drm_device *dev) |
d38ceaf9 | 248 | { |
1348969a | 249 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 250 | |
b98c6299 AD |
251 | if (adev->has_pr3 || |
252 | ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid())) | |
d38ceaf9 AD |
253 | return true; |
254 | return false; | |
255 | } | |
256 | ||
a69cba42 AD |
257 | /** |
258 | * amdgpu_device_supports_baco - Does the device support BACO | |
259 | * | |
260 | * @dev: drm_device pointer | |
261 | * | |
262 | * Returns true if the device supporte BACO, | |
263 | * otherwise return false. | |
264 | */ | |
265 | bool amdgpu_device_supports_baco(struct drm_device *dev) | |
266 | { | |
1348969a | 267 | struct amdgpu_device *adev = drm_to_adev(dev); |
a69cba42 AD |
268 | |
269 | return amdgpu_asic_supports_baco(adev); | |
270 | } | |
271 | ||
3fa8f89d S |
272 | /** |
273 | * amdgpu_device_supports_smart_shift - Is the device dGPU with | |
274 | * smart shift support | |
275 | * | |
276 | * @dev: drm_device pointer | |
277 | * | |
278 | * Returns true if the device is a dGPU with Smart Shift support, | |
279 | * otherwise returns false. | |
280 | */ | |
281 | bool amdgpu_device_supports_smart_shift(struct drm_device *dev) | |
282 | { | |
283 | return (amdgpu_device_supports_boco(dev) && | |
284 | amdgpu_acpi_is_power_shift_control_supported()); | |
285 | } | |
286 | ||
6e3cd2a9 MCC |
287 | /* |
288 | * VRAM access helper functions | |
289 | */ | |
290 | ||
e35e2b11 | 291 | /** |
048af66b | 292 | * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA |
e35e2b11 TY |
293 | * |
294 | * @adev: amdgpu_device pointer | |
295 | * @pos: offset of the buffer in vram | |
296 | * @buf: virtual address of the buffer in system memory | |
297 | * @size: read/write size, sizeof(@buf) must > @size | |
298 | * @write: true - write to vram, otherwise - read from vram | |
299 | */ | |
048af66b KW |
300 | void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, |
301 | void *buf, size_t size, bool write) | |
e35e2b11 | 302 | { |
e35e2b11 | 303 | unsigned long flags; |
048af66b KW |
304 | uint32_t hi = ~0, tmp = 0; |
305 | uint32_t *data = buf; | |
ce05ac56 | 306 | uint64_t last; |
f89f8c6b | 307 | int idx; |
ce05ac56 | 308 | |
f89f8c6b AG |
309 | if (!drm_dev_enter(&adev->ddev, &idx)) |
310 | return; | |
9d11eb0d | 311 | |
048af66b KW |
312 | BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4)); |
313 | ||
314 | spin_lock_irqsave(&adev->mmio_idx_lock, flags); | |
315 | for (last = pos + size; pos < last; pos += 4) { | |
316 | tmp = pos >> 31; | |
317 | ||
318 | WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); | |
319 | if (tmp != hi) { | |
320 | WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); | |
321 | hi = tmp; | |
322 | } | |
323 | if (write) | |
324 | WREG32_NO_KIQ(mmMM_DATA, *data++); | |
325 | else | |
326 | *data++ = RREG32_NO_KIQ(mmMM_DATA); | |
327 | } | |
328 | ||
329 | spin_unlock_irqrestore(&adev->mmio_idx_lock, flags); | |
330 | drm_dev_exit(idx); | |
331 | } | |
332 | ||
333 | /** | |
334 | * amdgpu_device_vram_access - access vram by vram aperature | |
335 | * | |
336 | * @adev: amdgpu_device pointer | |
337 | * @pos: offset of the buffer in vram | |
338 | * @buf: virtual address of the buffer in system memory | |
339 | * @size: read/write size, sizeof(@buf) must > @size | |
340 | * @write: true - write to vram, otherwise - read from vram | |
341 | * | |
342 | * The return value means how many bytes have been transferred. | |
343 | */ | |
344 | size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, | |
345 | void *buf, size_t size, bool write) | |
346 | { | |
9d11eb0d | 347 | #ifdef CONFIG_64BIT |
048af66b KW |
348 | void __iomem *addr; |
349 | size_t count = 0; | |
350 | uint64_t last; | |
351 | ||
352 | if (!adev->mman.aper_base_kaddr) | |
353 | return 0; | |
354 | ||
9d11eb0d CK |
355 | last = min(pos + size, adev->gmc.visible_vram_size); |
356 | if (last > pos) { | |
048af66b KW |
357 | addr = adev->mman.aper_base_kaddr + pos; |
358 | count = last - pos; | |
9d11eb0d CK |
359 | |
360 | if (write) { | |
361 | memcpy_toio(addr, buf, count); | |
362 | mb(); | |
810085dd | 363 | amdgpu_device_flush_hdp(adev, NULL); |
9d11eb0d | 364 | } else { |
810085dd | 365 | amdgpu_device_invalidate_hdp(adev, NULL); |
9d11eb0d CK |
366 | mb(); |
367 | memcpy_fromio(buf, addr, count); | |
368 | } | |
369 | ||
9d11eb0d | 370 | } |
048af66b KW |
371 | |
372 | return count; | |
373 | #else | |
374 | return 0; | |
9d11eb0d | 375 | #endif |
048af66b | 376 | } |
9d11eb0d | 377 | |
048af66b KW |
378 | /** |
379 | * amdgpu_device_vram_access - read/write a buffer in vram | |
380 | * | |
381 | * @adev: amdgpu_device pointer | |
382 | * @pos: offset of the buffer in vram | |
383 | * @buf: virtual address of the buffer in system memory | |
384 | * @size: read/write size, sizeof(@buf) must > @size | |
385 | * @write: true - write to vram, otherwise - read from vram | |
386 | */ | |
387 | void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, | |
388 | void *buf, size_t size, bool write) | |
389 | { | |
390 | size_t count; | |
e35e2b11 | 391 | |
048af66b KW |
392 | /* try to using vram apreature to access vram first */ |
393 | count = amdgpu_device_aper_access(adev, pos, buf, size, write); | |
394 | size -= count; | |
395 | if (size) { | |
396 | /* using MM to access rest vram */ | |
397 | pos += count; | |
398 | buf += count; | |
399 | amdgpu_device_mm_access(adev, pos, buf, size, write); | |
e35e2b11 TY |
400 | } |
401 | } | |
402 | ||
d38ceaf9 | 403 | /* |
f7ee1874 | 404 | * register access helper functions. |
d38ceaf9 | 405 | */ |
56b53c0b DL |
406 | |
407 | /* Check if hw access should be skipped because of hotplug or device error */ | |
408 | bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) | |
409 | { | |
7afefb81 | 410 | if (adev->no_hw_access) |
56b53c0b DL |
411 | return true; |
412 | ||
413 | #ifdef CONFIG_LOCKDEP | |
414 | /* | |
415 | * This is a bit complicated to understand, so worth a comment. What we assert | |
416 | * here is that the GPU reset is not running on another thread in parallel. | |
417 | * | |
418 | * For this we trylock the read side of the reset semaphore, if that succeeds | |
419 | * we know that the reset is not running in paralell. | |
420 | * | |
421 | * If the trylock fails we assert that we are either already holding the read | |
422 | * side of the lock or are the reset thread itself and hold the write side of | |
423 | * the lock. | |
424 | */ | |
425 | if (in_task()) { | |
426 | if (down_read_trylock(&adev->reset_sem)) | |
427 | up_read(&adev->reset_sem); | |
428 | else | |
429 | lockdep_assert_held(&adev->reset_sem); | |
430 | } | |
431 | #endif | |
432 | return false; | |
433 | } | |
434 | ||
e3ecdffa | 435 | /** |
f7ee1874 | 436 | * amdgpu_device_rreg - read a memory mapped IO or indirect register |
e3ecdffa AD |
437 | * |
438 | * @adev: amdgpu_device pointer | |
439 | * @reg: dword aligned register offset | |
440 | * @acc_flags: access flags which require special behavior | |
441 | * | |
442 | * Returns the 32 bit value from the offset specified. | |
443 | */ | |
f7ee1874 HZ |
444 | uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, |
445 | uint32_t reg, uint32_t acc_flags) | |
d38ceaf9 | 446 | { |
f4b373f4 TSD |
447 | uint32_t ret; |
448 | ||
56b53c0b | 449 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
450 | return 0; |
451 | ||
f7ee1874 HZ |
452 | if ((reg * 4) < adev->rmmio_size) { |
453 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
454 | amdgpu_sriov_runtime(adev) && | |
455 | down_read_trylock(&adev->reset_sem)) { | |
456 | ret = amdgpu_kiq_rreg(adev, reg); | |
457 | up_read(&adev->reset_sem); | |
458 | } else { | |
459 | ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); | |
460 | } | |
461 | } else { | |
462 | ret = adev->pcie_rreg(adev, reg * 4); | |
81202807 | 463 | } |
bc992ba5 | 464 | |
f7ee1874 | 465 | trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); |
e78b579d | 466 | |
f4b373f4 | 467 | return ret; |
d38ceaf9 AD |
468 | } |
469 | ||
421a2a30 ML |
470 | /* |
471 | * MMIO register read with bytes helper functions | |
472 | * @offset:bytes offset from MMIO start | |
473 | * | |
474 | */ | |
475 | ||
e3ecdffa AD |
476 | /** |
477 | * amdgpu_mm_rreg8 - read a memory mapped IO register | |
478 | * | |
479 | * @adev: amdgpu_device pointer | |
480 | * @offset: byte aligned register offset | |
481 | * | |
482 | * Returns the 8 bit value from the offset specified. | |
483 | */ | |
7cbbc745 AG |
484 | uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) |
485 | { | |
56b53c0b | 486 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
487 | return 0; |
488 | ||
421a2a30 ML |
489 | if (offset < adev->rmmio_size) |
490 | return (readb(adev->rmmio + offset)); | |
491 | BUG(); | |
492 | } | |
493 | ||
494 | /* | |
495 | * MMIO register write with bytes helper functions | |
496 | * @offset:bytes offset from MMIO start | |
497 | * @value: the value want to be written to the register | |
498 | * | |
499 | */ | |
e3ecdffa AD |
500 | /** |
501 | * amdgpu_mm_wreg8 - read a memory mapped IO register | |
502 | * | |
503 | * @adev: amdgpu_device pointer | |
504 | * @offset: byte aligned register offset | |
505 | * @value: 8 bit value to write | |
506 | * | |
507 | * Writes the value specified to the offset specified. | |
508 | */ | |
7cbbc745 AG |
509 | void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) |
510 | { | |
56b53c0b | 511 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
512 | return; |
513 | ||
421a2a30 ML |
514 | if (offset < adev->rmmio_size) |
515 | writeb(value, adev->rmmio + offset); | |
516 | else | |
517 | BUG(); | |
518 | } | |
519 | ||
e3ecdffa | 520 | /** |
f7ee1874 | 521 | * amdgpu_device_wreg - write to a memory mapped IO or indirect register |
e3ecdffa AD |
522 | * |
523 | * @adev: amdgpu_device pointer | |
524 | * @reg: dword aligned register offset | |
525 | * @v: 32 bit value to write to the register | |
526 | * @acc_flags: access flags which require special behavior | |
527 | * | |
528 | * Writes the value specified to the offset specified. | |
529 | */ | |
f7ee1874 HZ |
530 | void amdgpu_device_wreg(struct amdgpu_device *adev, |
531 | uint32_t reg, uint32_t v, | |
532 | uint32_t acc_flags) | |
d38ceaf9 | 533 | { |
56b53c0b | 534 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
535 | return; |
536 | ||
f7ee1874 HZ |
537 | if ((reg * 4) < adev->rmmio_size) { |
538 | if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && | |
539 | amdgpu_sriov_runtime(adev) && | |
540 | down_read_trylock(&adev->reset_sem)) { | |
541 | amdgpu_kiq_wreg(adev, reg, v); | |
542 | up_read(&adev->reset_sem); | |
543 | } else { | |
544 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
545 | } | |
546 | } else { | |
547 | adev->pcie_wreg(adev, reg * 4, v); | |
81202807 | 548 | } |
bc992ba5 | 549 | |
f7ee1874 | 550 | trace_amdgpu_device_wreg(adev->pdev->device, reg, v); |
2e0cc4d4 | 551 | } |
d38ceaf9 | 552 | |
2e0cc4d4 ML |
553 | /* |
554 | * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range | |
555 | * | |
556 | * this function is invoked only the debugfs register access | |
557 | * */ | |
f7ee1874 HZ |
558 | void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, |
559 | uint32_t reg, uint32_t v) | |
2e0cc4d4 | 560 | { |
56b53c0b | 561 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
562 | return; |
563 | ||
2e0cc4d4 | 564 | if (amdgpu_sriov_fullaccess(adev) && |
f7ee1874 HZ |
565 | adev->gfx.rlc.funcs && |
566 | adev->gfx.rlc.funcs->is_rlcg_access_range) { | |
2e0cc4d4 | 567 | if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) |
1a4772d9 | 568 | return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v, 0, 0); |
f7ee1874 HZ |
569 | } else { |
570 | writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); | |
47ed4e1c | 571 | } |
d38ceaf9 AD |
572 | } |
573 | ||
d38ceaf9 AD |
574 | /** |
575 | * amdgpu_mm_rdoorbell - read a doorbell dword | |
576 | * | |
577 | * @adev: amdgpu_device pointer | |
578 | * @index: doorbell index | |
579 | * | |
580 | * Returns the value in the doorbell aperture at the | |
581 | * requested doorbell index (CIK). | |
582 | */ | |
583 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index) | |
584 | { | |
56b53c0b | 585 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
586 | return 0; |
587 | ||
d38ceaf9 AD |
588 | if (index < adev->doorbell.num_doorbells) { |
589 | return readl(adev->doorbell.ptr + index); | |
590 | } else { | |
591 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
592 | return 0; | |
593 | } | |
594 | } | |
595 | ||
596 | /** | |
597 | * amdgpu_mm_wdoorbell - write a doorbell dword | |
598 | * | |
599 | * @adev: amdgpu_device pointer | |
600 | * @index: doorbell index | |
601 | * @v: value to write | |
602 | * | |
603 | * Writes @v to the doorbell aperture at the | |
604 | * requested doorbell index (CIK). | |
605 | */ | |
606 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v) | |
607 | { | |
56b53c0b | 608 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
609 | return; |
610 | ||
d38ceaf9 AD |
611 | if (index < adev->doorbell.num_doorbells) { |
612 | writel(v, adev->doorbell.ptr + index); | |
613 | } else { | |
614 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
615 | } | |
616 | } | |
617 | ||
832be404 KW |
618 | /** |
619 | * amdgpu_mm_rdoorbell64 - read a doorbell Qword | |
620 | * | |
621 | * @adev: amdgpu_device pointer | |
622 | * @index: doorbell index | |
623 | * | |
624 | * Returns the value in the doorbell aperture at the | |
625 | * requested doorbell index (VEGA10+). | |
626 | */ | |
627 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index) | |
628 | { | |
56b53c0b | 629 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
630 | return 0; |
631 | ||
832be404 KW |
632 | if (index < adev->doorbell.num_doorbells) { |
633 | return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index)); | |
634 | } else { | |
635 | DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index); | |
636 | return 0; | |
637 | } | |
638 | } | |
639 | ||
640 | /** | |
641 | * amdgpu_mm_wdoorbell64 - write a doorbell Qword | |
642 | * | |
643 | * @adev: amdgpu_device pointer | |
644 | * @index: doorbell index | |
645 | * @v: value to write | |
646 | * | |
647 | * Writes @v to the doorbell aperture at the | |
648 | * requested doorbell index (VEGA10+). | |
649 | */ | |
650 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v) | |
651 | { | |
56b53c0b | 652 | if (amdgpu_device_skip_hw_access(adev)) |
bf36b52e AG |
653 | return; |
654 | ||
832be404 KW |
655 | if (index < adev->doorbell.num_doorbells) { |
656 | atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v); | |
657 | } else { | |
658 | DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index); | |
659 | } | |
660 | } | |
661 | ||
1bba3683 HZ |
662 | /** |
663 | * amdgpu_device_indirect_rreg - read an indirect register | |
664 | * | |
665 | * @adev: amdgpu_device pointer | |
666 | * @pcie_index: mmio register offset | |
667 | * @pcie_data: mmio register offset | |
22f453fb | 668 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
669 | * |
670 | * Returns the value of indirect register @reg_addr | |
671 | */ | |
672 | u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, | |
673 | u32 pcie_index, u32 pcie_data, | |
674 | u32 reg_addr) | |
675 | { | |
676 | unsigned long flags; | |
677 | u32 r; | |
678 | void __iomem *pcie_index_offset; | |
679 | void __iomem *pcie_data_offset; | |
680 | ||
681 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
682 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
683 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
684 | ||
685 | writel(reg_addr, pcie_index_offset); | |
686 | readl(pcie_index_offset); | |
687 | r = readl(pcie_data_offset); | |
688 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
689 | ||
690 | return r; | |
691 | } | |
692 | ||
693 | /** | |
694 | * amdgpu_device_indirect_rreg64 - read a 64bits indirect register | |
695 | * | |
696 | * @adev: amdgpu_device pointer | |
697 | * @pcie_index: mmio register offset | |
698 | * @pcie_data: mmio register offset | |
22f453fb | 699 | * @reg_addr: indirect register address to read from |
1bba3683 HZ |
700 | * |
701 | * Returns the value of indirect register @reg_addr | |
702 | */ | |
703 | u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, | |
704 | u32 pcie_index, u32 pcie_data, | |
705 | u32 reg_addr) | |
706 | { | |
707 | unsigned long flags; | |
708 | u64 r; | |
709 | void __iomem *pcie_index_offset; | |
710 | void __iomem *pcie_data_offset; | |
711 | ||
712 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
713 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
714 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
715 | ||
716 | /* read low 32 bits */ | |
717 | writel(reg_addr, pcie_index_offset); | |
718 | readl(pcie_index_offset); | |
719 | r = readl(pcie_data_offset); | |
720 | /* read high 32 bits */ | |
721 | writel(reg_addr + 4, pcie_index_offset); | |
722 | readl(pcie_index_offset); | |
723 | r |= ((u64)readl(pcie_data_offset) << 32); | |
724 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
725 | ||
726 | return r; | |
727 | } | |
728 | ||
729 | /** | |
730 | * amdgpu_device_indirect_wreg - write an indirect register address | |
731 | * | |
732 | * @adev: amdgpu_device pointer | |
733 | * @pcie_index: mmio register offset | |
734 | * @pcie_data: mmio register offset | |
735 | * @reg_addr: indirect register offset | |
736 | * @reg_data: indirect register data | |
737 | * | |
738 | */ | |
739 | void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, | |
740 | u32 pcie_index, u32 pcie_data, | |
741 | u32 reg_addr, u32 reg_data) | |
742 | { | |
743 | unsigned long flags; | |
744 | void __iomem *pcie_index_offset; | |
745 | void __iomem *pcie_data_offset; | |
746 | ||
747 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
748 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
749 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
750 | ||
751 | writel(reg_addr, pcie_index_offset); | |
752 | readl(pcie_index_offset); | |
753 | writel(reg_data, pcie_data_offset); | |
754 | readl(pcie_data_offset); | |
755 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
756 | } | |
757 | ||
758 | /** | |
759 | * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address | |
760 | * | |
761 | * @adev: amdgpu_device pointer | |
762 | * @pcie_index: mmio register offset | |
763 | * @pcie_data: mmio register offset | |
764 | * @reg_addr: indirect register offset | |
765 | * @reg_data: indirect register data | |
766 | * | |
767 | */ | |
768 | void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, | |
769 | u32 pcie_index, u32 pcie_data, | |
770 | u32 reg_addr, u64 reg_data) | |
771 | { | |
772 | unsigned long flags; | |
773 | void __iomem *pcie_index_offset; | |
774 | void __iomem *pcie_data_offset; | |
775 | ||
776 | spin_lock_irqsave(&adev->pcie_idx_lock, flags); | |
777 | pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; | |
778 | pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; | |
779 | ||
780 | /* write low 32 bits */ | |
781 | writel(reg_addr, pcie_index_offset); | |
782 | readl(pcie_index_offset); | |
783 | writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); | |
784 | readl(pcie_data_offset); | |
785 | /* write high 32 bits */ | |
786 | writel(reg_addr + 4, pcie_index_offset); | |
787 | readl(pcie_index_offset); | |
788 | writel((u32)(reg_data >> 32), pcie_data_offset); | |
789 | readl(pcie_data_offset); | |
790 | spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); | |
791 | } | |
792 | ||
d38ceaf9 AD |
793 | /** |
794 | * amdgpu_invalid_rreg - dummy reg read function | |
795 | * | |
982a820b | 796 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
797 | * @reg: offset of register |
798 | * | |
799 | * Dummy register read function. Used for register blocks | |
800 | * that certain asics don't have (all asics). | |
801 | * Returns the value in the register. | |
802 | */ | |
803 | static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) | |
804 | { | |
805 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
806 | BUG(); | |
807 | return 0; | |
808 | } | |
809 | ||
810 | /** | |
811 | * amdgpu_invalid_wreg - dummy reg write function | |
812 | * | |
982a820b | 813 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
814 | * @reg: offset of register |
815 | * @v: value to write to the register | |
816 | * | |
817 | * Dummy register read function. Used for register blocks | |
818 | * that certain asics don't have (all asics). | |
819 | */ | |
820 | static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) | |
821 | { | |
822 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
823 | reg, v); | |
824 | BUG(); | |
825 | } | |
826 | ||
4fa1c6a6 TZ |
827 | /** |
828 | * amdgpu_invalid_rreg64 - dummy 64 bit reg read function | |
829 | * | |
982a820b | 830 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
831 | * @reg: offset of register |
832 | * | |
833 | * Dummy register read function. Used for register blocks | |
834 | * that certain asics don't have (all asics). | |
835 | * Returns the value in the register. | |
836 | */ | |
837 | static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) | |
838 | { | |
839 | DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg); | |
840 | BUG(); | |
841 | return 0; | |
842 | } | |
843 | ||
844 | /** | |
845 | * amdgpu_invalid_wreg64 - dummy reg write function | |
846 | * | |
982a820b | 847 | * @adev: amdgpu_device pointer |
4fa1c6a6 TZ |
848 | * @reg: offset of register |
849 | * @v: value to write to the register | |
850 | * | |
851 | * Dummy register read function. Used for register blocks | |
852 | * that certain asics don't have (all asics). | |
853 | */ | |
854 | static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) | |
855 | { | |
856 | DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", | |
857 | reg, v); | |
858 | BUG(); | |
859 | } | |
860 | ||
d38ceaf9 AD |
861 | /** |
862 | * amdgpu_block_invalid_rreg - dummy reg read function | |
863 | * | |
982a820b | 864 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
865 | * @block: offset of instance |
866 | * @reg: offset of register | |
867 | * | |
868 | * Dummy register read function. Used for register blocks | |
869 | * that certain asics don't have (all asics). | |
870 | * Returns the value in the register. | |
871 | */ | |
872 | static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, | |
873 | uint32_t block, uint32_t reg) | |
874 | { | |
875 | DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n", | |
876 | reg, block); | |
877 | BUG(); | |
878 | return 0; | |
879 | } | |
880 | ||
881 | /** | |
882 | * amdgpu_block_invalid_wreg - dummy reg write function | |
883 | * | |
982a820b | 884 | * @adev: amdgpu_device pointer |
d38ceaf9 AD |
885 | * @block: offset of instance |
886 | * @reg: offset of register | |
887 | * @v: value to write to the register | |
888 | * | |
889 | * Dummy register read function. Used for register blocks | |
890 | * that certain asics don't have (all asics). | |
891 | */ | |
892 | static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, | |
893 | uint32_t block, | |
894 | uint32_t reg, uint32_t v) | |
895 | { | |
896 | DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", | |
897 | reg, block, v); | |
898 | BUG(); | |
899 | } | |
900 | ||
4d2997ab AD |
901 | /** |
902 | * amdgpu_device_asic_init - Wrapper for atom asic_init | |
903 | * | |
982a820b | 904 | * @adev: amdgpu_device pointer |
4d2997ab AD |
905 | * |
906 | * Does any asic specific work and then calls atom asic init. | |
907 | */ | |
908 | static int amdgpu_device_asic_init(struct amdgpu_device *adev) | |
909 | { | |
910 | amdgpu_asic_pre_asic_init(adev); | |
911 | ||
912 | return amdgpu_atom_asic_init(adev->mode_info.atom_context); | |
913 | } | |
914 | ||
e3ecdffa AD |
915 | /** |
916 | * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page | |
917 | * | |
982a820b | 918 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
919 | * |
920 | * Allocates a scratch page of VRAM for use by various things in the | |
921 | * driver. | |
922 | */ | |
06ec9070 | 923 | static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev) |
d38ceaf9 | 924 | { |
a4a02777 CK |
925 | return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, |
926 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, | |
927 | &adev->vram_scratch.robj, | |
928 | &adev->vram_scratch.gpu_addr, | |
929 | (void **)&adev->vram_scratch.ptr); | |
d38ceaf9 AD |
930 | } |
931 | ||
e3ecdffa AD |
932 | /** |
933 | * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page | |
934 | * | |
982a820b | 935 | * @adev: amdgpu_device pointer |
e3ecdffa AD |
936 | * |
937 | * Frees the VRAM scratch page. | |
938 | */ | |
06ec9070 | 939 | static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) |
d38ceaf9 | 940 | { |
078af1a3 | 941 | amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL); |
d38ceaf9 AD |
942 | } |
943 | ||
944 | /** | |
9c3f2b54 | 945 | * amdgpu_device_program_register_sequence - program an array of registers. |
d38ceaf9 AD |
946 | * |
947 | * @adev: amdgpu_device pointer | |
948 | * @registers: pointer to the register array | |
949 | * @array_size: size of the register array | |
950 | * | |
951 | * Programs an array or registers with and and or masks. | |
952 | * This is a helper for setting golden registers. | |
953 | */ | |
9c3f2b54 AD |
954 | void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, |
955 | const u32 *registers, | |
956 | const u32 array_size) | |
d38ceaf9 AD |
957 | { |
958 | u32 tmp, reg, and_mask, or_mask; | |
959 | int i; | |
960 | ||
961 | if (array_size % 3) | |
962 | return; | |
963 | ||
964 | for (i = 0; i < array_size; i +=3) { | |
965 | reg = registers[i + 0]; | |
966 | and_mask = registers[i + 1]; | |
967 | or_mask = registers[i + 2]; | |
968 | ||
969 | if (and_mask == 0xffffffff) { | |
970 | tmp = or_mask; | |
971 | } else { | |
972 | tmp = RREG32(reg); | |
973 | tmp &= ~and_mask; | |
e0d07657 HZ |
974 | if (adev->family >= AMDGPU_FAMILY_AI) |
975 | tmp |= (or_mask & and_mask); | |
976 | else | |
977 | tmp |= or_mask; | |
d38ceaf9 AD |
978 | } |
979 | WREG32(reg, tmp); | |
980 | } | |
981 | } | |
982 | ||
e3ecdffa AD |
983 | /** |
984 | * amdgpu_device_pci_config_reset - reset the GPU | |
985 | * | |
986 | * @adev: amdgpu_device pointer | |
987 | * | |
988 | * Resets the GPU using the pci config reset sequence. | |
989 | * Only applicable to asics prior to vega10. | |
990 | */ | |
8111c387 | 991 | void amdgpu_device_pci_config_reset(struct amdgpu_device *adev) |
d38ceaf9 AD |
992 | { |
993 | pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA); | |
994 | } | |
995 | ||
af484df8 AD |
996 | /** |
997 | * amdgpu_device_pci_reset - reset the GPU using generic PCI means | |
998 | * | |
999 | * @adev: amdgpu_device pointer | |
1000 | * | |
1001 | * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.). | |
1002 | */ | |
1003 | int amdgpu_device_pci_reset(struct amdgpu_device *adev) | |
1004 | { | |
1005 | return pci_reset_function(adev->pdev); | |
1006 | } | |
1007 | ||
d38ceaf9 AD |
1008 | /* |
1009 | * GPU doorbell aperture helpers function. | |
1010 | */ | |
1011 | /** | |
06ec9070 | 1012 | * amdgpu_device_doorbell_init - Init doorbell driver information. |
d38ceaf9 AD |
1013 | * |
1014 | * @adev: amdgpu_device pointer | |
1015 | * | |
1016 | * Init doorbell driver information (CIK) | |
1017 | * Returns 0 on success, error on failure. | |
1018 | */ | |
06ec9070 | 1019 | static int amdgpu_device_doorbell_init(struct amdgpu_device *adev) |
d38ceaf9 | 1020 | { |
6585661d | 1021 | |
705e519e CK |
1022 | /* No doorbell on SI hardware generation */ |
1023 | if (adev->asic_type < CHIP_BONAIRE) { | |
1024 | adev->doorbell.base = 0; | |
1025 | adev->doorbell.size = 0; | |
1026 | adev->doorbell.num_doorbells = 0; | |
1027 | adev->doorbell.ptr = NULL; | |
1028 | return 0; | |
1029 | } | |
1030 | ||
d6895ad3 CK |
1031 | if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) |
1032 | return -EINVAL; | |
1033 | ||
22357775 AD |
1034 | amdgpu_asic_init_doorbell_index(adev); |
1035 | ||
d38ceaf9 AD |
1036 | /* doorbell bar mapping */ |
1037 | adev->doorbell.base = pci_resource_start(adev->pdev, 2); | |
1038 | adev->doorbell.size = pci_resource_len(adev->pdev, 2); | |
1039 | ||
edf600da | 1040 | adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32), |
9564f192 | 1041 | adev->doorbell_index.max_assignment+1); |
d38ceaf9 AD |
1042 | if (adev->doorbell.num_doorbells == 0) |
1043 | return -EINVAL; | |
1044 | ||
ec3db8a6 | 1045 | /* For Vega, reserve and map two pages on doorbell BAR since SDMA |
88dc26e4 OZ |
1046 | * paging queue doorbell use the second page. The |
1047 | * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the | |
1048 | * doorbells are in the first page. So with paging queue enabled, | |
1049 | * the max num_doorbells should + 1 page (0x400 in dword) | |
ec3db8a6 PY |
1050 | */ |
1051 | if (adev->asic_type >= CHIP_VEGA10) | |
88dc26e4 | 1052 | adev->doorbell.num_doorbells += 0x400; |
ec3db8a6 | 1053 | |
8972e5d2 CK |
1054 | adev->doorbell.ptr = ioremap(adev->doorbell.base, |
1055 | adev->doorbell.num_doorbells * | |
1056 | sizeof(u32)); | |
1057 | if (adev->doorbell.ptr == NULL) | |
d38ceaf9 | 1058 | return -ENOMEM; |
d38ceaf9 AD |
1059 | |
1060 | return 0; | |
1061 | } | |
1062 | ||
1063 | /** | |
06ec9070 | 1064 | * amdgpu_device_doorbell_fini - Tear down doorbell driver information. |
d38ceaf9 AD |
1065 | * |
1066 | * @adev: amdgpu_device pointer | |
1067 | * | |
1068 | * Tear down doorbell driver information (CIK) | |
1069 | */ | |
06ec9070 | 1070 | static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1071 | { |
1072 | iounmap(adev->doorbell.ptr); | |
1073 | adev->doorbell.ptr = NULL; | |
1074 | } | |
1075 | ||
22cb0164 | 1076 | |
d38ceaf9 AD |
1077 | |
1078 | /* | |
06ec9070 | 1079 | * amdgpu_device_wb_*() |
455a7bc2 | 1080 | * Writeback is the method by which the GPU updates special pages in memory |
ea81a173 | 1081 | * with the status of certain GPU events (fences, ring pointers,etc.). |
d38ceaf9 AD |
1082 | */ |
1083 | ||
1084 | /** | |
06ec9070 | 1085 | * amdgpu_device_wb_fini - Disable Writeback and free memory |
d38ceaf9 AD |
1086 | * |
1087 | * @adev: amdgpu_device pointer | |
1088 | * | |
1089 | * Disables Writeback and frees the Writeback memory (all asics). | |
1090 | * Used at driver shutdown. | |
1091 | */ | |
06ec9070 | 1092 | static void amdgpu_device_wb_fini(struct amdgpu_device *adev) |
d38ceaf9 AD |
1093 | { |
1094 | if (adev->wb.wb_obj) { | |
a76ed485 AD |
1095 | amdgpu_bo_free_kernel(&adev->wb.wb_obj, |
1096 | &adev->wb.gpu_addr, | |
1097 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1098 | adev->wb.wb_obj = NULL; |
1099 | } | |
1100 | } | |
1101 | ||
1102 | /** | |
06ec9070 | 1103 | * amdgpu_device_wb_init- Init Writeback driver info and allocate memory |
d38ceaf9 AD |
1104 | * |
1105 | * @adev: amdgpu_device pointer | |
1106 | * | |
455a7bc2 | 1107 | * Initializes writeback and allocates writeback memory (all asics). |
d38ceaf9 AD |
1108 | * Used at driver startup. |
1109 | * Returns 0 on success or an -error on failure. | |
1110 | */ | |
06ec9070 | 1111 | static int amdgpu_device_wb_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
1112 | { |
1113 | int r; | |
1114 | ||
1115 | if (adev->wb.wb_obj == NULL) { | |
97407b63 AD |
1116 | /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */ |
1117 | r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8, | |
a76ed485 AD |
1118 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, |
1119 | &adev->wb.wb_obj, &adev->wb.gpu_addr, | |
1120 | (void **)&adev->wb.wb); | |
d38ceaf9 AD |
1121 | if (r) { |
1122 | dev_warn(adev->dev, "(%d) create WB bo failed\n", r); | |
1123 | return r; | |
1124 | } | |
d38ceaf9 AD |
1125 | |
1126 | adev->wb.num_wb = AMDGPU_MAX_WB; | |
1127 | memset(&adev->wb.used, 0, sizeof(adev->wb.used)); | |
1128 | ||
1129 | /* clear wb memory */ | |
73469585 | 1130 | memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8); |
d38ceaf9 AD |
1131 | } |
1132 | ||
1133 | return 0; | |
1134 | } | |
1135 | ||
1136 | /** | |
131b4b36 | 1137 | * amdgpu_device_wb_get - Allocate a wb entry |
d38ceaf9 AD |
1138 | * |
1139 | * @adev: amdgpu_device pointer | |
1140 | * @wb: wb index | |
1141 | * | |
1142 | * Allocate a wb slot for use by the driver (all asics). | |
1143 | * Returns 0 on success or -EINVAL on failure. | |
1144 | */ | |
131b4b36 | 1145 | int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) |
d38ceaf9 AD |
1146 | { |
1147 | unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); | |
d38ceaf9 | 1148 | |
97407b63 | 1149 | if (offset < adev->wb.num_wb) { |
7014285a | 1150 | __set_bit(offset, adev->wb.used); |
63ae07ca | 1151 | *wb = offset << 3; /* convert to dw offset */ |
0915fdbc ML |
1152 | return 0; |
1153 | } else { | |
1154 | return -EINVAL; | |
1155 | } | |
1156 | } | |
1157 | ||
d38ceaf9 | 1158 | /** |
131b4b36 | 1159 | * amdgpu_device_wb_free - Free a wb entry |
d38ceaf9 AD |
1160 | * |
1161 | * @adev: amdgpu_device pointer | |
1162 | * @wb: wb index | |
1163 | * | |
1164 | * Free a wb slot allocated for use by the driver (all asics) | |
1165 | */ | |
131b4b36 | 1166 | void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) |
d38ceaf9 | 1167 | { |
73469585 | 1168 | wb >>= 3; |
d38ceaf9 | 1169 | if (wb < adev->wb.num_wb) |
73469585 | 1170 | __clear_bit(wb, adev->wb.used); |
d38ceaf9 AD |
1171 | } |
1172 | ||
d6895ad3 CK |
1173 | /** |
1174 | * amdgpu_device_resize_fb_bar - try to resize FB BAR | |
1175 | * | |
1176 | * @adev: amdgpu_device pointer | |
1177 | * | |
1178 | * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not | |
1179 | * to fail, but if any of the BARs is not accessible after the size we abort | |
1180 | * driver loading by returning -ENODEV. | |
1181 | */ | |
1182 | int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) | |
1183 | { | |
453f617a | 1184 | int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size); |
31b8adab CK |
1185 | struct pci_bus *root; |
1186 | struct resource *res; | |
1187 | unsigned i; | |
d6895ad3 CK |
1188 | u16 cmd; |
1189 | int r; | |
1190 | ||
0c03b912 | 1191 | /* Bypass for VF */ |
1192 | if (amdgpu_sriov_vf(adev)) | |
1193 | return 0; | |
1194 | ||
b7221f2b AD |
1195 | /* skip if the bios has already enabled large BAR */ |
1196 | if (adev->gmc.real_vram_size && | |
1197 | (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size)) | |
1198 | return 0; | |
1199 | ||
31b8adab CK |
1200 | /* Check if the root BUS has 64bit memory resources */ |
1201 | root = adev->pdev->bus; | |
1202 | while (root->parent) | |
1203 | root = root->parent; | |
1204 | ||
1205 | pci_bus_for_each_resource(root, res, i) { | |
0ebb7c54 | 1206 | if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) && |
31b8adab CK |
1207 | res->start > 0x100000000ull) |
1208 | break; | |
1209 | } | |
1210 | ||
1211 | /* Trying to resize is pointless without a root hub window above 4GB */ | |
1212 | if (!res) | |
1213 | return 0; | |
1214 | ||
453f617a ND |
1215 | /* Limit the BAR size to what is available */ |
1216 | rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, | |
1217 | rbar_size); | |
1218 | ||
d6895ad3 CK |
1219 | /* Disable memory decoding while we change the BAR addresses and size */ |
1220 | pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); | |
1221 | pci_write_config_word(adev->pdev, PCI_COMMAND, | |
1222 | cmd & ~PCI_COMMAND_MEMORY); | |
1223 | ||
1224 | /* Free the VRAM and doorbell BAR, we most likely need to move both. */ | |
06ec9070 | 1225 | amdgpu_device_doorbell_fini(adev); |
d6895ad3 CK |
1226 | if (adev->asic_type >= CHIP_BONAIRE) |
1227 | pci_release_resource(adev->pdev, 2); | |
1228 | ||
1229 | pci_release_resource(adev->pdev, 0); | |
1230 | ||
1231 | r = pci_resize_resource(adev->pdev, 0, rbar_size); | |
1232 | if (r == -ENOSPC) | |
1233 | DRM_INFO("Not enough PCI address space for a large BAR."); | |
1234 | else if (r && r != -ENOTSUPP) | |
1235 | DRM_ERROR("Problem resizing BAR0 (%d).", r); | |
1236 | ||
1237 | pci_assign_unassigned_bus_resources(adev->pdev->bus); | |
1238 | ||
1239 | /* When the doorbell or fb BAR isn't available we have no chance of | |
1240 | * using the device. | |
1241 | */ | |
06ec9070 | 1242 | r = amdgpu_device_doorbell_init(adev); |
d6895ad3 CK |
1243 | if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) |
1244 | return -ENODEV; | |
1245 | ||
1246 | pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); | |
1247 | ||
1248 | return 0; | |
1249 | } | |
a05502e5 | 1250 | |
d38ceaf9 AD |
1251 | /* |
1252 | * GPU helpers function. | |
1253 | */ | |
1254 | /** | |
39c640c0 | 1255 | * amdgpu_device_need_post - check if the hw need post or not |
d38ceaf9 AD |
1256 | * |
1257 | * @adev: amdgpu_device pointer | |
1258 | * | |
c836fec5 JQ |
1259 | * Check if the asic has been initialized (all asics) at driver startup |
1260 | * or post is needed if hw reset is performed. | |
1261 | * Returns true if need or false if not. | |
d38ceaf9 | 1262 | */ |
39c640c0 | 1263 | bool amdgpu_device_need_post(struct amdgpu_device *adev) |
d38ceaf9 AD |
1264 | { |
1265 | uint32_t reg; | |
1266 | ||
bec86378 ML |
1267 | if (amdgpu_sriov_vf(adev)) |
1268 | return false; | |
1269 | ||
1270 | if (amdgpu_passthrough(adev)) { | |
1da2c326 ML |
1271 | /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot |
1272 | * some old smc fw still need driver do vPost otherwise gpu hang, while | |
1273 | * those smc fw version above 22.15 doesn't have this flaw, so we force | |
1274 | * vpost executed for smc version below 22.15 | |
bec86378 ML |
1275 | */ |
1276 | if (adev->asic_type == CHIP_FIJI) { | |
1277 | int err; | |
1278 | uint32_t fw_ver; | |
1279 | err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev); | |
1280 | /* force vPost if error occured */ | |
1281 | if (err) | |
1282 | return true; | |
1283 | ||
1284 | fw_ver = *((uint32_t *)adev->pm.fw->data + 69); | |
1da2c326 ML |
1285 | if (fw_ver < 0x00160e00) |
1286 | return true; | |
bec86378 | 1287 | } |
bec86378 | 1288 | } |
91fe77eb | 1289 | |
e3c1b071 | 1290 | /* Don't post if we need to reset whole hive on init */ |
1291 | if (adev->gmc.xgmi.pending_reset) | |
1292 | return false; | |
1293 | ||
91fe77eb | 1294 | if (adev->has_hw_reset) { |
1295 | adev->has_hw_reset = false; | |
1296 | return true; | |
1297 | } | |
1298 | ||
1299 | /* bios scratch used on CIK+ */ | |
1300 | if (adev->asic_type >= CHIP_BONAIRE) | |
1301 | return amdgpu_atombios_scratch_need_asic_init(adev); | |
1302 | ||
1303 | /* check MEM_SIZE for older asics */ | |
1304 | reg = amdgpu_asic_get_config_memsize(adev); | |
1305 | ||
1306 | if ((reg != 0) && (reg != 0xffffffff)) | |
1307 | return false; | |
1308 | ||
1309 | return true; | |
bec86378 ML |
1310 | } |
1311 | ||
d38ceaf9 AD |
1312 | /* if we get transitioned to only one device, take VGA back */ |
1313 | /** | |
06ec9070 | 1314 | * amdgpu_device_vga_set_decode - enable/disable vga decode |
d38ceaf9 | 1315 | * |
bf44e8ce | 1316 | * @pdev: PCI device pointer |
d38ceaf9 AD |
1317 | * @state: enable/disable vga decode |
1318 | * | |
1319 | * Enable/disable vga decode (all asics). | |
1320 | * Returns VGA resource flags. | |
1321 | */ | |
bf44e8ce CH |
1322 | static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev, |
1323 | bool state) | |
d38ceaf9 | 1324 | { |
bf44e8ce | 1325 | struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev)); |
d38ceaf9 AD |
1326 | amdgpu_asic_set_vga_state(adev, state); |
1327 | if (state) | |
1328 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
1329 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1330 | else | |
1331 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
1332 | } | |
1333 | ||
e3ecdffa AD |
1334 | /** |
1335 | * amdgpu_device_check_block_size - validate the vm block size | |
1336 | * | |
1337 | * @adev: amdgpu_device pointer | |
1338 | * | |
1339 | * Validates the vm block size specified via module parameter. | |
1340 | * The vm block size defines number of bits in page table versus page directory, | |
1341 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1342 | * page table and the remaining bits are in the page directory. | |
1343 | */ | |
06ec9070 | 1344 | static void amdgpu_device_check_block_size(struct amdgpu_device *adev) |
a1adf8be CZ |
1345 | { |
1346 | /* defines number of bits in page table versus page directory, | |
1347 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the | |
1348 | * page table and the remaining bits are in the page directory */ | |
bab4fee7 JZ |
1349 | if (amdgpu_vm_block_size == -1) |
1350 | return; | |
a1adf8be | 1351 | |
bab4fee7 | 1352 | if (amdgpu_vm_block_size < 9) { |
a1adf8be CZ |
1353 | dev_warn(adev->dev, "VM page table size (%d) too small\n", |
1354 | amdgpu_vm_block_size); | |
97489129 | 1355 | amdgpu_vm_block_size = -1; |
a1adf8be | 1356 | } |
a1adf8be CZ |
1357 | } |
1358 | ||
e3ecdffa AD |
1359 | /** |
1360 | * amdgpu_device_check_vm_size - validate the vm size | |
1361 | * | |
1362 | * @adev: amdgpu_device pointer | |
1363 | * | |
1364 | * Validates the vm size in GB specified via module parameter. | |
1365 | * The VM size is the size of the GPU virtual memory space in GB. | |
1366 | */ | |
06ec9070 | 1367 | static void amdgpu_device_check_vm_size(struct amdgpu_device *adev) |
83ca145d | 1368 | { |
64dab074 AD |
1369 | /* no need to check the default value */ |
1370 | if (amdgpu_vm_size == -1) | |
1371 | return; | |
1372 | ||
83ca145d ZJ |
1373 | if (amdgpu_vm_size < 1) { |
1374 | dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", | |
1375 | amdgpu_vm_size); | |
f3368128 | 1376 | amdgpu_vm_size = -1; |
83ca145d | 1377 | } |
83ca145d ZJ |
1378 | } |
1379 | ||
7951e376 RZ |
1380 | static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev) |
1381 | { | |
1382 | struct sysinfo si; | |
a9d4fe2f | 1383 | bool is_os_64 = (sizeof(void *) == 8); |
7951e376 RZ |
1384 | uint64_t total_memory; |
1385 | uint64_t dram_size_seven_GB = 0x1B8000000; | |
1386 | uint64_t dram_size_three_GB = 0xB8000000; | |
1387 | ||
1388 | if (amdgpu_smu_memory_pool_size == 0) | |
1389 | return; | |
1390 | ||
1391 | if (!is_os_64) { | |
1392 | DRM_WARN("Not 64-bit OS, feature not supported\n"); | |
1393 | goto def_value; | |
1394 | } | |
1395 | si_meminfo(&si); | |
1396 | total_memory = (uint64_t)si.totalram * si.mem_unit; | |
1397 | ||
1398 | if ((amdgpu_smu_memory_pool_size == 1) || | |
1399 | (amdgpu_smu_memory_pool_size == 2)) { | |
1400 | if (total_memory < dram_size_three_GB) | |
1401 | goto def_value1; | |
1402 | } else if ((amdgpu_smu_memory_pool_size == 4) || | |
1403 | (amdgpu_smu_memory_pool_size == 8)) { | |
1404 | if (total_memory < dram_size_seven_GB) | |
1405 | goto def_value1; | |
1406 | } else { | |
1407 | DRM_WARN("Smu memory pool size not supported\n"); | |
1408 | goto def_value; | |
1409 | } | |
1410 | adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28; | |
1411 | ||
1412 | return; | |
1413 | ||
1414 | def_value1: | |
1415 | DRM_WARN("No enough system memory\n"); | |
1416 | def_value: | |
1417 | adev->pm.smu_prv_buffer_size = 0; | |
1418 | } | |
1419 | ||
9f6a7857 HR |
1420 | static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev) |
1421 | { | |
1422 | if (!(adev->flags & AMD_IS_APU) || | |
1423 | adev->asic_type < CHIP_RAVEN) | |
1424 | return 0; | |
1425 | ||
1426 | switch (adev->asic_type) { | |
1427 | case CHIP_RAVEN: | |
1428 | if (adev->pdev->device == 0x15dd) | |
1429 | adev->apu_flags |= AMD_APU_IS_RAVEN; | |
1430 | if (adev->pdev->device == 0x15d8) | |
1431 | adev->apu_flags |= AMD_APU_IS_PICASSO; | |
1432 | break; | |
1433 | case CHIP_RENOIR: | |
1434 | if ((adev->pdev->device == 0x1636) || | |
1435 | (adev->pdev->device == 0x164c)) | |
1436 | adev->apu_flags |= AMD_APU_IS_RENOIR; | |
1437 | else | |
1438 | adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE; | |
1439 | break; | |
1440 | case CHIP_VANGOGH: | |
1441 | adev->apu_flags |= AMD_APU_IS_VANGOGH; | |
1442 | break; | |
1443 | case CHIP_YELLOW_CARP: | |
1444 | break; | |
d0f56dc2 TZ |
1445 | case CHIP_CYAN_SKILLFISH: |
1446 | if (adev->pdev->device == 0x13FE) | |
1447 | adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2; | |
1448 | break; | |
9f6a7857 HR |
1449 | default: |
1450 | return -EINVAL; | |
1451 | } | |
1452 | ||
1453 | return 0; | |
1454 | } | |
1455 | ||
d38ceaf9 | 1456 | /** |
06ec9070 | 1457 | * amdgpu_device_check_arguments - validate module params |
d38ceaf9 AD |
1458 | * |
1459 | * @adev: amdgpu_device pointer | |
1460 | * | |
1461 | * Validates certain module parameters and updates | |
1462 | * the associated values used by the driver (all asics). | |
1463 | */ | |
912dfc84 | 1464 | static int amdgpu_device_check_arguments(struct amdgpu_device *adev) |
d38ceaf9 | 1465 | { |
5b011235 CZ |
1466 | if (amdgpu_sched_jobs < 4) { |
1467 | dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", | |
1468 | amdgpu_sched_jobs); | |
1469 | amdgpu_sched_jobs = 4; | |
76117507 | 1470 | } else if (!is_power_of_2(amdgpu_sched_jobs)){ |
5b011235 CZ |
1471 | dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", |
1472 | amdgpu_sched_jobs); | |
1473 | amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs); | |
1474 | } | |
d38ceaf9 | 1475 | |
83e74db6 | 1476 | if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) { |
f9321cc4 CK |
1477 | /* gart size must be greater or equal to 32M */ |
1478 | dev_warn(adev->dev, "gart size (%d) too small\n", | |
1479 | amdgpu_gart_size); | |
83e74db6 | 1480 | amdgpu_gart_size = -1; |
d38ceaf9 AD |
1481 | } |
1482 | ||
36d38372 | 1483 | if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) { |
c4e1a13a | 1484 | /* gtt size must be greater or equal to 32M */ |
36d38372 CK |
1485 | dev_warn(adev->dev, "gtt size (%d) too small\n", |
1486 | amdgpu_gtt_size); | |
1487 | amdgpu_gtt_size = -1; | |
d38ceaf9 AD |
1488 | } |
1489 | ||
d07f14be RH |
1490 | /* valid range is between 4 and 9 inclusive */ |
1491 | if (amdgpu_vm_fragment_size != -1 && | |
1492 | (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { | |
1493 | dev_warn(adev->dev, "valid range is between 4 and 9\n"); | |
1494 | amdgpu_vm_fragment_size = -1; | |
1495 | } | |
1496 | ||
5d5bd5e3 KW |
1497 | if (amdgpu_sched_hw_submission < 2) { |
1498 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", | |
1499 | amdgpu_sched_hw_submission); | |
1500 | amdgpu_sched_hw_submission = 2; | |
1501 | } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { | |
1502 | dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", | |
1503 | amdgpu_sched_hw_submission); | |
1504 | amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); | |
1505 | } | |
1506 | ||
7951e376 RZ |
1507 | amdgpu_device_check_smu_prv_buffer_size(adev); |
1508 | ||
06ec9070 | 1509 | amdgpu_device_check_vm_size(adev); |
d38ceaf9 | 1510 | |
06ec9070 | 1511 | amdgpu_device_check_block_size(adev); |
6a7f76e7 | 1512 | |
19aede77 | 1513 | adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); |
912dfc84 | 1514 | |
c6252390 | 1515 | amdgpu_gmc_tmz_set(adev); |
01a8dcec | 1516 | |
9b498efa AD |
1517 | amdgpu_gmc_noretry_set(adev); |
1518 | ||
e3c00faa | 1519 | return 0; |
d38ceaf9 AD |
1520 | } |
1521 | ||
1522 | /** | |
1523 | * amdgpu_switcheroo_set_state - set switcheroo state | |
1524 | * | |
1525 | * @pdev: pci dev pointer | |
1694467b | 1526 | * @state: vga_switcheroo state |
d38ceaf9 AD |
1527 | * |
1528 | * Callback for the switcheroo driver. Suspends or resumes the | |
1529 | * the asics before or after it is powered up using ACPI methods. | |
1530 | */ | |
8aba21b7 LT |
1531 | static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, |
1532 | enum vga_switcheroo_state state) | |
d38ceaf9 AD |
1533 | { |
1534 | struct drm_device *dev = pci_get_drvdata(pdev); | |
de185019 | 1535 | int r; |
d38ceaf9 | 1536 | |
b98c6299 | 1537 | if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF) |
d38ceaf9 AD |
1538 | return; |
1539 | ||
1540 | if (state == VGA_SWITCHEROO_ON) { | |
dd4fa6c1 | 1541 | pr_info("switched on\n"); |
d38ceaf9 AD |
1542 | /* don't suspend or resume card normally */ |
1543 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1544 | ||
8f66090b TZ |
1545 | pci_set_power_state(pdev, PCI_D0); |
1546 | amdgpu_device_load_pci_state(pdev); | |
1547 | r = pci_enable_device(pdev); | |
de185019 AD |
1548 | if (r) |
1549 | DRM_WARN("pci_enable_device failed (%d)\n", r); | |
1550 | amdgpu_device_resume(dev, true); | |
d38ceaf9 | 1551 | |
d38ceaf9 | 1552 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
d38ceaf9 | 1553 | } else { |
dd4fa6c1 | 1554 | pr_info("switched off\n"); |
d38ceaf9 | 1555 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
de185019 | 1556 | amdgpu_device_suspend(dev, true); |
8f66090b | 1557 | amdgpu_device_cache_pci_state(pdev); |
de185019 | 1558 | /* Shut down the device */ |
8f66090b TZ |
1559 | pci_disable_device(pdev); |
1560 | pci_set_power_state(pdev, PCI_D3cold); | |
d38ceaf9 AD |
1561 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
1562 | } | |
1563 | } | |
1564 | ||
1565 | /** | |
1566 | * amdgpu_switcheroo_can_switch - see if switcheroo state can change | |
1567 | * | |
1568 | * @pdev: pci dev pointer | |
1569 | * | |
1570 | * Callback for the switcheroo driver. Check of the switcheroo | |
1571 | * state can be changed. | |
1572 | * Returns true if the state can be changed, false if not. | |
1573 | */ | |
1574 | static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) | |
1575 | { | |
1576 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1577 | ||
1578 | /* | |
1579 | * FIXME: open_count is protected by drm_global_mutex but that would lead to | |
1580 | * locking inversion with the driver load path. And the access here is | |
1581 | * completely racy anyway. So don't bother with locking for now. | |
1582 | */ | |
7e13ad89 | 1583 | return atomic_read(&dev->open_count) == 0; |
d38ceaf9 AD |
1584 | } |
1585 | ||
1586 | static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { | |
1587 | .set_gpu_state = amdgpu_switcheroo_set_state, | |
1588 | .reprobe = NULL, | |
1589 | .can_switch = amdgpu_switcheroo_can_switch, | |
1590 | }; | |
1591 | ||
e3ecdffa AD |
1592 | /** |
1593 | * amdgpu_device_ip_set_clockgating_state - set the CG state | |
1594 | * | |
87e3f136 | 1595 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1596 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1597 | * @state: clockgating state (gate or ungate) | |
1598 | * | |
1599 | * Sets the requested clockgating state for all instances of | |
1600 | * the hardware IP specified. | |
1601 | * Returns the error code from the last instance. | |
1602 | */ | |
43fa561f | 1603 | int amdgpu_device_ip_set_clockgating_state(void *dev, |
2990a1fc AD |
1604 | enum amd_ip_block_type block_type, |
1605 | enum amd_clockgating_state state) | |
d38ceaf9 | 1606 | { |
43fa561f | 1607 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1608 | int i, r = 0; |
1609 | ||
1610 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1611 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1612 | continue; |
c722865a RZ |
1613 | if (adev->ip_blocks[i].version->type != block_type) |
1614 | continue; | |
1615 | if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) | |
1616 | continue; | |
1617 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state( | |
1618 | (void *)adev, state); | |
1619 | if (r) | |
1620 | DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n", | |
1621 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1622 | } |
1623 | return r; | |
1624 | } | |
1625 | ||
e3ecdffa AD |
1626 | /** |
1627 | * amdgpu_device_ip_set_powergating_state - set the PG state | |
1628 | * | |
87e3f136 | 1629 | * @dev: amdgpu_device pointer |
e3ecdffa AD |
1630 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) |
1631 | * @state: powergating state (gate or ungate) | |
1632 | * | |
1633 | * Sets the requested powergating state for all instances of | |
1634 | * the hardware IP specified. | |
1635 | * Returns the error code from the last instance. | |
1636 | */ | |
43fa561f | 1637 | int amdgpu_device_ip_set_powergating_state(void *dev, |
2990a1fc AD |
1638 | enum amd_ip_block_type block_type, |
1639 | enum amd_powergating_state state) | |
d38ceaf9 | 1640 | { |
43fa561f | 1641 | struct amdgpu_device *adev = dev; |
d38ceaf9 AD |
1642 | int i, r = 0; |
1643 | ||
1644 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1645 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1646 | continue; |
c722865a RZ |
1647 | if (adev->ip_blocks[i].version->type != block_type) |
1648 | continue; | |
1649 | if (!adev->ip_blocks[i].version->funcs->set_powergating_state) | |
1650 | continue; | |
1651 | r = adev->ip_blocks[i].version->funcs->set_powergating_state( | |
1652 | (void *)adev, state); | |
1653 | if (r) | |
1654 | DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n", | |
1655 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 AD |
1656 | } |
1657 | return r; | |
1658 | } | |
1659 | ||
e3ecdffa AD |
1660 | /** |
1661 | * amdgpu_device_ip_get_clockgating_state - get the CG state | |
1662 | * | |
1663 | * @adev: amdgpu_device pointer | |
1664 | * @flags: clockgating feature flags | |
1665 | * | |
1666 | * Walks the list of IPs on the device and updates the clockgating | |
1667 | * flags for each IP. | |
1668 | * Updates @flags with the feature flags for each hardware IP where | |
1669 | * clockgating is enabled. | |
1670 | */ | |
2990a1fc AD |
1671 | void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, |
1672 | u32 *flags) | |
6cb2d4e4 HR |
1673 | { |
1674 | int i; | |
1675 | ||
1676 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
1677 | if (!adev->ip_blocks[i].status.valid) | |
1678 | continue; | |
1679 | if (adev->ip_blocks[i].version->funcs->get_clockgating_state) | |
1680 | adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags); | |
1681 | } | |
1682 | } | |
1683 | ||
e3ecdffa AD |
1684 | /** |
1685 | * amdgpu_device_ip_wait_for_idle - wait for idle | |
1686 | * | |
1687 | * @adev: amdgpu_device pointer | |
1688 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1689 | * | |
1690 | * Waits for the request hardware IP to be idle. | |
1691 | * Returns 0 for success or a negative error code on failure. | |
1692 | */ | |
2990a1fc AD |
1693 | int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, |
1694 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1695 | { |
1696 | int i, r; | |
1697 | ||
1698 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1699 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1700 | continue; |
a1255107 AD |
1701 | if (adev->ip_blocks[i].version->type == block_type) { |
1702 | r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); | |
5dbbb60b AD |
1703 | if (r) |
1704 | return r; | |
1705 | break; | |
1706 | } | |
1707 | } | |
1708 | return 0; | |
1709 | ||
1710 | } | |
1711 | ||
e3ecdffa AD |
1712 | /** |
1713 | * amdgpu_device_ip_is_idle - is the hardware IP idle | |
1714 | * | |
1715 | * @adev: amdgpu_device pointer | |
1716 | * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) | |
1717 | * | |
1718 | * Check if the hardware IP is idle or not. | |
1719 | * Returns true if it the IP is idle, false if not. | |
1720 | */ | |
2990a1fc AD |
1721 | bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, |
1722 | enum amd_ip_block_type block_type) | |
5dbbb60b AD |
1723 | { |
1724 | int i; | |
1725 | ||
1726 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 1727 | if (!adev->ip_blocks[i].status.valid) |
9ecbe7f5 | 1728 | continue; |
a1255107 AD |
1729 | if (adev->ip_blocks[i].version->type == block_type) |
1730 | return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); | |
5dbbb60b AD |
1731 | } |
1732 | return true; | |
1733 | ||
1734 | } | |
1735 | ||
e3ecdffa AD |
1736 | /** |
1737 | * amdgpu_device_ip_get_ip_block - get a hw IP pointer | |
1738 | * | |
1739 | * @adev: amdgpu_device pointer | |
87e3f136 | 1740 | * @type: Type of hardware IP (SMU, GFX, UVD, etc.) |
e3ecdffa AD |
1741 | * |
1742 | * Returns a pointer to the hardware IP block structure | |
1743 | * if it exists for the asic, otherwise NULL. | |
1744 | */ | |
2990a1fc AD |
1745 | struct amdgpu_ip_block * |
1746 | amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, | |
1747 | enum amd_ip_block_type type) | |
d38ceaf9 AD |
1748 | { |
1749 | int i; | |
1750 | ||
1751 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 | 1752 | if (adev->ip_blocks[i].version->type == type) |
d38ceaf9 AD |
1753 | return &adev->ip_blocks[i]; |
1754 | ||
1755 | return NULL; | |
1756 | } | |
1757 | ||
1758 | /** | |
2990a1fc | 1759 | * amdgpu_device_ip_block_version_cmp |
d38ceaf9 AD |
1760 | * |
1761 | * @adev: amdgpu_device pointer | |
5fc3aeeb | 1762 | * @type: enum amd_ip_block_type |
d38ceaf9 AD |
1763 | * @major: major version |
1764 | * @minor: minor version | |
1765 | * | |
1766 | * return 0 if equal or greater | |
1767 | * return 1 if smaller or the ip_block doesn't exist | |
1768 | */ | |
2990a1fc AD |
1769 | int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, |
1770 | enum amd_ip_block_type type, | |
1771 | u32 major, u32 minor) | |
d38ceaf9 | 1772 | { |
2990a1fc | 1773 | struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); |
d38ceaf9 | 1774 | |
a1255107 AD |
1775 | if (ip_block && ((ip_block->version->major > major) || |
1776 | ((ip_block->version->major == major) && | |
1777 | (ip_block->version->minor >= minor)))) | |
d38ceaf9 AD |
1778 | return 0; |
1779 | ||
1780 | return 1; | |
1781 | } | |
1782 | ||
a1255107 | 1783 | /** |
2990a1fc | 1784 | * amdgpu_device_ip_block_add |
a1255107 AD |
1785 | * |
1786 | * @adev: amdgpu_device pointer | |
1787 | * @ip_block_version: pointer to the IP to add | |
1788 | * | |
1789 | * Adds the IP block driver information to the collection of IPs | |
1790 | * on the asic. | |
1791 | */ | |
2990a1fc AD |
1792 | int amdgpu_device_ip_block_add(struct amdgpu_device *adev, |
1793 | const struct amdgpu_ip_block_version *ip_block_version) | |
a1255107 AD |
1794 | { |
1795 | if (!ip_block_version) | |
1796 | return -EINVAL; | |
1797 | ||
7bd939d0 LG |
1798 | switch (ip_block_version->type) { |
1799 | case AMD_IP_BLOCK_TYPE_VCN: | |
1800 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) | |
1801 | return 0; | |
1802 | break; | |
1803 | case AMD_IP_BLOCK_TYPE_JPEG: | |
1804 | if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) | |
1805 | return 0; | |
1806 | break; | |
1807 | default: | |
1808 | break; | |
1809 | } | |
1810 | ||
e966a725 | 1811 | DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, |
a0bae357 HR |
1812 | ip_block_version->funcs->name); |
1813 | ||
a1255107 AD |
1814 | adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; |
1815 | ||
1816 | return 0; | |
1817 | } | |
1818 | ||
e3ecdffa AD |
1819 | /** |
1820 | * amdgpu_device_enable_virtual_display - enable virtual display feature | |
1821 | * | |
1822 | * @adev: amdgpu_device pointer | |
1823 | * | |
1824 | * Enabled the virtual display feature if the user has enabled it via | |
1825 | * the module parameter virtual_display. This feature provides a virtual | |
1826 | * display hardware on headless boards or in virtualized environments. | |
1827 | * This function parses and validates the configuration string specified by | |
1828 | * the user and configues the virtual display configuration (number of | |
1829 | * virtual connectors, crtcs, etc.) specified. | |
1830 | */ | |
483ef985 | 1831 | static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev) |
9accf2fd ED |
1832 | { |
1833 | adev->enable_virtual_display = false; | |
1834 | ||
1835 | if (amdgpu_virtual_display) { | |
8f66090b | 1836 | const char *pci_address_name = pci_name(adev->pdev); |
0f66356d | 1837 | char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname; |
9accf2fd ED |
1838 | |
1839 | pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL); | |
1840 | pciaddstr_tmp = pciaddstr; | |
0f66356d ED |
1841 | while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) { |
1842 | pciaddname = strsep(&pciaddname_tmp, ","); | |
967de2a9 YT |
1843 | if (!strcmp("all", pciaddname) |
1844 | || !strcmp(pci_address_name, pciaddname)) { | |
0f66356d ED |
1845 | long num_crtc; |
1846 | int res = -1; | |
1847 | ||
9accf2fd | 1848 | adev->enable_virtual_display = true; |
0f66356d ED |
1849 | |
1850 | if (pciaddname_tmp) | |
1851 | res = kstrtol(pciaddname_tmp, 10, | |
1852 | &num_crtc); | |
1853 | ||
1854 | if (!res) { | |
1855 | if (num_crtc < 1) | |
1856 | num_crtc = 1; | |
1857 | if (num_crtc > 6) | |
1858 | num_crtc = 6; | |
1859 | adev->mode_info.num_crtc = num_crtc; | |
1860 | } else { | |
1861 | adev->mode_info.num_crtc = 1; | |
1862 | } | |
9accf2fd ED |
1863 | break; |
1864 | } | |
1865 | } | |
1866 | ||
0f66356d ED |
1867 | DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n", |
1868 | amdgpu_virtual_display, pci_address_name, | |
1869 | adev->enable_virtual_display, adev->mode_info.num_crtc); | |
9accf2fd ED |
1870 | |
1871 | kfree(pciaddstr); | |
1872 | } | |
1873 | } | |
1874 | ||
e3ecdffa AD |
1875 | /** |
1876 | * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware | |
1877 | * | |
1878 | * @adev: amdgpu_device pointer | |
1879 | * | |
1880 | * Parses the asic configuration parameters specified in the gpu info | |
1881 | * firmware and makes them availale to the driver for use in configuring | |
1882 | * the asic. | |
1883 | * Returns 0 on success, -EINVAL on failure. | |
1884 | */ | |
e2a75f88 AD |
1885 | static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) |
1886 | { | |
e2a75f88 | 1887 | const char *chip_name; |
c0a43457 | 1888 | char fw_name[40]; |
e2a75f88 AD |
1889 | int err; |
1890 | const struct gpu_info_firmware_header_v1_0 *hdr; | |
1891 | ||
ab4fe3e1 HR |
1892 | adev->firmware.gpu_info_fw = NULL; |
1893 | ||
72de33f8 | 1894 | if (adev->mman.discovery_bin) { |
258620d0 | 1895 | amdgpu_discovery_get_gfx_info(adev); |
cc375d8c TY |
1896 | |
1897 | /* | |
1898 | * FIXME: The bounding box is still needed by Navi12, so | |
1899 | * temporarily read it from gpu_info firmware. Should be droped | |
1900 | * when DAL no longer needs it. | |
1901 | */ | |
1902 | if (adev->asic_type != CHIP_NAVI12) | |
1903 | return 0; | |
258620d0 AD |
1904 | } |
1905 | ||
e2a75f88 | 1906 | switch (adev->asic_type) { |
e2a75f88 AD |
1907 | #ifdef CONFIG_DRM_AMDGPU_SI |
1908 | case CHIP_VERDE: | |
1909 | case CHIP_TAHITI: | |
1910 | case CHIP_PITCAIRN: | |
1911 | case CHIP_OLAND: | |
1912 | case CHIP_HAINAN: | |
1913 | #endif | |
1914 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1915 | case CHIP_BONAIRE: | |
1916 | case CHIP_HAWAII: | |
1917 | case CHIP_KAVERI: | |
1918 | case CHIP_KABINI: | |
1919 | case CHIP_MULLINS: | |
1920 | #endif | |
da87c30b AD |
1921 | case CHIP_TOPAZ: |
1922 | case CHIP_TONGA: | |
1923 | case CHIP_FIJI: | |
1924 | case CHIP_POLARIS10: | |
1925 | case CHIP_POLARIS11: | |
1926 | case CHIP_POLARIS12: | |
1927 | case CHIP_VEGAM: | |
1928 | case CHIP_CARRIZO: | |
1929 | case CHIP_STONEY: | |
27c0bc71 | 1930 | case CHIP_VEGA20: |
44b3253a | 1931 | case CHIP_ALDEBARAN: |
84d244a3 JC |
1932 | case CHIP_SIENNA_CICHLID: |
1933 | case CHIP_NAVY_FLOUNDER: | |
eac88a5f | 1934 | case CHIP_DIMGREY_CAVEFISH: |
0e5f4b09 | 1935 | case CHIP_BEIGE_GOBY: |
e2a75f88 AD |
1936 | default: |
1937 | return 0; | |
1938 | case CHIP_VEGA10: | |
1939 | chip_name = "vega10"; | |
1940 | break; | |
3f76dced AD |
1941 | case CHIP_VEGA12: |
1942 | chip_name = "vega12"; | |
1943 | break; | |
2d2e5e7e | 1944 | case CHIP_RAVEN: |
54f78a76 | 1945 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
54c4d17e | 1946 | chip_name = "raven2"; |
54f78a76 | 1947 | else if (adev->apu_flags & AMD_APU_IS_PICASSO) |
741deade | 1948 | chip_name = "picasso"; |
54c4d17e FX |
1949 | else |
1950 | chip_name = "raven"; | |
2d2e5e7e | 1951 | break; |
65e60f6e LM |
1952 | case CHIP_ARCTURUS: |
1953 | chip_name = "arcturus"; | |
1954 | break; | |
b51a26a0 | 1955 | case CHIP_RENOIR: |
2e62f0b5 PL |
1956 | if (adev->apu_flags & AMD_APU_IS_RENOIR) |
1957 | chip_name = "renoir"; | |
1958 | else | |
1959 | chip_name = "green_sardine"; | |
b51a26a0 | 1960 | break; |
23c6268e HR |
1961 | case CHIP_NAVI10: |
1962 | chip_name = "navi10"; | |
1963 | break; | |
ed42cfe1 XY |
1964 | case CHIP_NAVI14: |
1965 | chip_name = "navi14"; | |
1966 | break; | |
42b325e5 XY |
1967 | case CHIP_NAVI12: |
1968 | chip_name = "navi12"; | |
1969 | break; | |
4e52a9f8 HR |
1970 | case CHIP_VANGOGH: |
1971 | chip_name = "vangogh"; | |
1972 | break; | |
8bf84f60 AL |
1973 | case CHIP_YELLOW_CARP: |
1974 | chip_name = "yellow_carp"; | |
1975 | break; | |
e2a75f88 AD |
1976 | } |
1977 | ||
1978 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); | |
ab4fe3e1 | 1979 | err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev); |
e2a75f88 AD |
1980 | if (err) { |
1981 | dev_err(adev->dev, | |
1982 | "Failed to load gpu_info firmware \"%s\"\n", | |
1983 | fw_name); | |
1984 | goto out; | |
1985 | } | |
ab4fe3e1 | 1986 | err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw); |
e2a75f88 AD |
1987 | if (err) { |
1988 | dev_err(adev->dev, | |
1989 | "Failed to validate gpu_info firmware \"%s\"\n", | |
1990 | fw_name); | |
1991 | goto out; | |
1992 | } | |
1993 | ||
ab4fe3e1 | 1994 | hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data; |
e2a75f88 AD |
1995 | amdgpu_ucode_print_gpu_info_hdr(&hdr->header); |
1996 | ||
1997 | switch (hdr->version_major) { | |
1998 | case 1: | |
1999 | { | |
2000 | const struct gpu_info_firmware_v1_0 *gpu_info_fw = | |
ab4fe3e1 | 2001 | (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data + |
e2a75f88 AD |
2002 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); |
2003 | ||
cc375d8c TY |
2004 | /* |
2005 | * Should be droped when DAL no longer needs it. | |
2006 | */ | |
2007 | if (adev->asic_type == CHIP_NAVI12) | |
ec51d3fa XY |
2008 | goto parse_soc_bounding_box; |
2009 | ||
b5ab16bf AD |
2010 | adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se); |
2011 | adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh); | |
2012 | adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); | |
2013 | adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se); | |
e2a75f88 | 2014 | adev->gfx.config.max_texture_channel_caches = |
b5ab16bf AD |
2015 | le32_to_cpu(gpu_info_fw->gc_num_tccs); |
2016 | adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs); | |
2017 | adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds); | |
2018 | adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth); | |
2019 | adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth); | |
e2a75f88 | 2020 | adev->gfx.config.double_offchip_lds_buf = |
b5ab16bf AD |
2021 | le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer); |
2022 | adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size); | |
51fd0370 HZ |
2023 | adev->gfx.cu_info.max_waves_per_simd = |
2024 | le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd); | |
2025 | adev->gfx.cu_info.max_scratch_slots_per_cu = | |
2026 | le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); | |
2027 | adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); | |
48321c3d | 2028 | if (hdr->version_minor >= 1) { |
35c2e910 HZ |
2029 | const struct gpu_info_firmware_v1_1 *gpu_info_fw = |
2030 | (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + | |
2031 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2032 | adev->gfx.config.num_sc_per_sh = | |
2033 | le32_to_cpu(gpu_info_fw->num_sc_per_sh); | |
2034 | adev->gfx.config.num_packer_per_sc = | |
2035 | le32_to_cpu(gpu_info_fw->num_packer_per_sc); | |
2036 | } | |
ec51d3fa XY |
2037 | |
2038 | parse_soc_bounding_box: | |
ec51d3fa XY |
2039 | /* |
2040 | * soc bounding box info is not integrated in disocovery table, | |
258620d0 | 2041 | * we always need to parse it from gpu info firmware if needed. |
ec51d3fa | 2042 | */ |
48321c3d HW |
2043 | if (hdr->version_minor == 2) { |
2044 | const struct gpu_info_firmware_v1_2 *gpu_info_fw = | |
2045 | (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + | |
2046 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
2047 | adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; | |
2048 | } | |
e2a75f88 AD |
2049 | break; |
2050 | } | |
2051 | default: | |
2052 | dev_err(adev->dev, | |
2053 | "Unsupported gpu_info table %d\n", hdr->header.ucode_version); | |
2054 | err = -EINVAL; | |
2055 | goto out; | |
2056 | } | |
2057 | out: | |
e2a75f88 AD |
2058 | return err; |
2059 | } | |
2060 | ||
e3ecdffa AD |
2061 | /** |
2062 | * amdgpu_device_ip_early_init - run early init for hardware IPs | |
2063 | * | |
2064 | * @adev: amdgpu_device pointer | |
2065 | * | |
2066 | * Early initialization pass for hardware IPs. The hardware IPs that make | |
2067 | * up each asic are discovered each IP's early_init callback is run. This | |
2068 | * is the first stage in initializing the asic. | |
2069 | * Returns 0 on success, negative error code on failure. | |
2070 | */ | |
06ec9070 | 2071 | static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) |
d38ceaf9 | 2072 | { |
c5452d42 AD |
2073 | struct drm_device *dev = adev_to_drm(adev); |
2074 | struct pci_dev *parent; | |
aaa36a97 | 2075 | int i, r; |
d38ceaf9 | 2076 | |
483ef985 | 2077 | amdgpu_device_enable_virtual_display(adev); |
a6be7570 | 2078 | |
00a979f3 | 2079 | if (amdgpu_sriov_vf(adev)) { |
00a979f3 | 2080 | r = amdgpu_virt_request_full_gpu(adev, true); |
aaa36a97 AD |
2081 | if (r) |
2082 | return r; | |
00a979f3 WS |
2083 | } |
2084 | ||
d38ceaf9 | 2085 | switch (adev->asic_type) { |
33f34802 KW |
2086 | #ifdef CONFIG_DRM_AMDGPU_SI |
2087 | case CHIP_VERDE: | |
2088 | case CHIP_TAHITI: | |
2089 | case CHIP_PITCAIRN: | |
2090 | case CHIP_OLAND: | |
2091 | case CHIP_HAINAN: | |
295d0daf | 2092 | adev->family = AMDGPU_FAMILY_SI; |
33f34802 KW |
2093 | r = si_set_ip_blocks(adev); |
2094 | if (r) | |
2095 | return r; | |
2096 | break; | |
2097 | #endif | |
a2e73f56 AD |
2098 | #ifdef CONFIG_DRM_AMDGPU_CIK |
2099 | case CHIP_BONAIRE: | |
2100 | case CHIP_HAWAII: | |
2101 | case CHIP_KAVERI: | |
2102 | case CHIP_KABINI: | |
2103 | case CHIP_MULLINS: | |
e1ad2d53 | 2104 | if (adev->flags & AMD_IS_APU) |
a2e73f56 | 2105 | adev->family = AMDGPU_FAMILY_KV; |
e1ad2d53 AD |
2106 | else |
2107 | adev->family = AMDGPU_FAMILY_CI; | |
a2e73f56 AD |
2108 | |
2109 | r = cik_set_ip_blocks(adev); | |
2110 | if (r) | |
2111 | return r; | |
2112 | break; | |
2113 | #endif | |
da87c30b AD |
2114 | case CHIP_TOPAZ: |
2115 | case CHIP_TONGA: | |
2116 | case CHIP_FIJI: | |
2117 | case CHIP_POLARIS10: | |
2118 | case CHIP_POLARIS11: | |
2119 | case CHIP_POLARIS12: | |
2120 | case CHIP_VEGAM: | |
2121 | case CHIP_CARRIZO: | |
2122 | case CHIP_STONEY: | |
2123 | if (adev->flags & AMD_IS_APU) | |
2124 | adev->family = AMDGPU_FAMILY_CZ; | |
2125 | else | |
2126 | adev->family = AMDGPU_FAMILY_VI; | |
2127 | ||
2128 | r = vi_set_ip_blocks(adev); | |
2129 | if (r) | |
2130 | return r; | |
2131 | break; | |
e48a3cd9 AD |
2132 | case CHIP_VEGA10: |
2133 | case CHIP_VEGA12: | |
e4bd8170 | 2134 | case CHIP_VEGA20: |
e48a3cd9 | 2135 | case CHIP_RAVEN: |
61cf44c1 | 2136 | case CHIP_ARCTURUS: |
b51a26a0 | 2137 | case CHIP_RENOIR: |
c00a18ec | 2138 | case CHIP_ALDEBARAN: |
70534d1e | 2139 | if (adev->flags & AMD_IS_APU) |
2ca8a5d2 CZ |
2140 | adev->family = AMDGPU_FAMILY_RV; |
2141 | else | |
2142 | adev->family = AMDGPU_FAMILY_AI; | |
460826e6 KW |
2143 | |
2144 | r = soc15_set_ip_blocks(adev); | |
2145 | if (r) | |
2146 | return r; | |
2147 | break; | |
0a5b8c7b | 2148 | case CHIP_NAVI10: |
7ecb5cd4 | 2149 | case CHIP_NAVI14: |
4808cf9c | 2150 | case CHIP_NAVI12: |
11e8aef5 | 2151 | case CHIP_SIENNA_CICHLID: |
41f446bf | 2152 | case CHIP_NAVY_FLOUNDER: |
144722fa | 2153 | case CHIP_DIMGREY_CAVEFISH: |
b41f5b7a | 2154 | case CHIP_BEIGE_GOBY: |
4e52a9f8 | 2155 | case CHIP_VANGOGH: |
8bf84f60 | 2156 | case CHIP_YELLOW_CARP: |
6e80eacd | 2157 | case CHIP_CYAN_SKILLFISH: |
4e52a9f8 HR |
2158 | if (adev->asic_type == CHIP_VANGOGH) |
2159 | adev->family = AMDGPU_FAMILY_VGH; | |
8bf84f60 AL |
2160 | else if (adev->asic_type == CHIP_YELLOW_CARP) |
2161 | adev->family = AMDGPU_FAMILY_YC; | |
4e52a9f8 HR |
2162 | else |
2163 | adev->family = AMDGPU_FAMILY_NV; | |
0a5b8c7b HR |
2164 | |
2165 | r = nv_set_ip_blocks(adev); | |
2166 | if (r) | |
2167 | return r; | |
2168 | break; | |
d38ceaf9 AD |
2169 | default: |
2170 | /* FIXME: not supported yet */ | |
2171 | return -EINVAL; | |
2172 | } | |
2173 | ||
c5452d42 AD |
2174 | if (amdgpu_has_atpx() && |
2175 | (amdgpu_is_atpx_hybrid() || | |
2176 | amdgpu_has_atpx_dgpu_power_cntl()) && | |
2177 | ((adev->flags & AMD_IS_APU) == 0) && | |
2178 | !pci_is_thunderbolt_attached(to_pci_dev(dev->dev))) | |
2179 | adev->flags |= AMD_IS_PX; | |
2180 | ||
d1ab966b AD |
2181 | if (!(adev->flags & AMD_IS_APU)) { |
2182 | parent = pci_upstream_bridge(adev->pdev); | |
2183 | adev->has_pr3 = parent ? pci_pr3_present(parent) : false; | |
2184 | } | |
c5452d42 | 2185 | |
1884734a | 2186 | amdgpu_amdkfd_device_probe(adev); |
2187 | ||
3b94fb10 | 2188 | adev->pm.pp_feature = amdgpu_pp_feature_mask; |
a35ad98b | 2189 | if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) |
00544006 | 2190 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
4215a119 HC |
2191 | if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) |
2192 | adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK; | |
00f54b97 | 2193 | |
d38ceaf9 AD |
2194 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2195 | if ((amdgpu_ip_block_mask & (1 << i)) == 0) { | |
ed8cf00c HR |
2196 | DRM_ERROR("disabled ip block: %d <%s>\n", |
2197 | i, adev->ip_blocks[i].version->funcs->name); | |
a1255107 | 2198 | adev->ip_blocks[i].status.valid = false; |
d38ceaf9 | 2199 | } else { |
a1255107 AD |
2200 | if (adev->ip_blocks[i].version->funcs->early_init) { |
2201 | r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); | |
2c1a2784 | 2202 | if (r == -ENOENT) { |
a1255107 | 2203 | adev->ip_blocks[i].status.valid = false; |
2c1a2784 | 2204 | } else if (r) { |
a1255107 AD |
2205 | DRM_ERROR("early_init of IP block <%s> failed %d\n", |
2206 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 2207 | return r; |
2c1a2784 | 2208 | } else { |
a1255107 | 2209 | adev->ip_blocks[i].status.valid = true; |
2c1a2784 | 2210 | } |
974e6b64 | 2211 | } else { |
a1255107 | 2212 | adev->ip_blocks[i].status.valid = true; |
d38ceaf9 | 2213 | } |
d38ceaf9 | 2214 | } |
21a249ca AD |
2215 | /* get the vbios after the asic_funcs are set up */ |
2216 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { | |
6e29c227 AD |
2217 | r = amdgpu_device_parse_gpu_info_fw(adev); |
2218 | if (r) | |
2219 | return r; | |
2220 | ||
21a249ca AD |
2221 | /* Read BIOS */ |
2222 | if (!amdgpu_get_bios(adev)) | |
2223 | return -EINVAL; | |
2224 | ||
2225 | r = amdgpu_atombios_init(adev); | |
2226 | if (r) { | |
2227 | dev_err(adev->dev, "amdgpu_atombios_init failed\n"); | |
2228 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0); | |
2229 | return r; | |
2230 | } | |
77eabc6f PJZ |
2231 | |
2232 | /*get pf2vf msg info at it's earliest time*/ | |
2233 | if (amdgpu_sriov_vf(adev)) | |
2234 | amdgpu_virt_init_data_exchange(adev); | |
2235 | ||
21a249ca | 2236 | } |
d38ceaf9 AD |
2237 | } |
2238 | ||
395d1fb9 NH |
2239 | adev->cg_flags &= amdgpu_cg_mask; |
2240 | adev->pg_flags &= amdgpu_pg_mask; | |
2241 | ||
d38ceaf9 AD |
2242 | return 0; |
2243 | } | |
2244 | ||
0a4f2520 RZ |
2245 | static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) |
2246 | { | |
2247 | int i, r; | |
2248 | ||
2249 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2250 | if (!adev->ip_blocks[i].status.sw) | |
2251 | continue; | |
2252 | if (adev->ip_blocks[i].status.hw) | |
2253 | continue; | |
2254 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2d11fd3f | 2255 | (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || |
0a4f2520 RZ |
2256 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { |
2257 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2258 | if (r) { | |
2259 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2260 | adev->ip_blocks[i].version->funcs->name, r); | |
2261 | return r; | |
2262 | } | |
2263 | adev->ip_blocks[i].status.hw = true; | |
2264 | } | |
2265 | } | |
2266 | ||
2267 | return 0; | |
2268 | } | |
2269 | ||
2270 | static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) | |
2271 | { | |
2272 | int i, r; | |
2273 | ||
2274 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
2275 | if (!adev->ip_blocks[i].status.sw) | |
2276 | continue; | |
2277 | if (adev->ip_blocks[i].status.hw) | |
2278 | continue; | |
2279 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2280 | if (r) { | |
2281 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2282 | adev->ip_blocks[i].version->funcs->name, r); | |
2283 | return r; | |
2284 | } | |
2285 | adev->ip_blocks[i].status.hw = true; | |
2286 | } | |
2287 | ||
2288 | return 0; | |
2289 | } | |
2290 | ||
7a3e0bb2 RZ |
2291 | static int amdgpu_device_fw_loading(struct amdgpu_device *adev) |
2292 | { | |
2293 | int r = 0; | |
2294 | int i; | |
80f41f84 | 2295 | uint32_t smu_version; |
7a3e0bb2 RZ |
2296 | |
2297 | if (adev->asic_type >= CHIP_VEGA10) { | |
2298 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 ML |
2299 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) |
2300 | continue; | |
2301 | ||
e3c1b071 | 2302 | if (!adev->ip_blocks[i].status.sw) |
2303 | continue; | |
2304 | ||
482f0e53 ML |
2305 | /* no need to do the fw loading again if already done*/ |
2306 | if (adev->ip_blocks[i].status.hw == true) | |
2307 | break; | |
2308 | ||
53b3f8f4 | 2309 | if (amdgpu_in_reset(adev) || adev->in_suspend) { |
482f0e53 ML |
2310 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2311 | if (r) { | |
2312 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
7a3e0bb2 | 2313 | adev->ip_blocks[i].version->funcs->name, r); |
482f0e53 ML |
2314 | return r; |
2315 | } | |
2316 | } else { | |
2317 | r = adev->ip_blocks[i].version->funcs->hw_init(adev); | |
2318 | if (r) { | |
2319 | DRM_ERROR("hw_init of IP block <%s> failed %d\n", | |
2320 | adev->ip_blocks[i].version->funcs->name, r); | |
2321 | return r; | |
7a3e0bb2 | 2322 | } |
7a3e0bb2 | 2323 | } |
482f0e53 ML |
2324 | |
2325 | adev->ip_blocks[i].status.hw = true; | |
2326 | break; | |
7a3e0bb2 RZ |
2327 | } |
2328 | } | |
482f0e53 | 2329 | |
8973d9ec ED |
2330 | if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) |
2331 | r = amdgpu_pm_load_smu_firmware(adev, &smu_version); | |
7a3e0bb2 | 2332 | |
80f41f84 | 2333 | return r; |
7a3e0bb2 RZ |
2334 | } |
2335 | ||
e3ecdffa AD |
2336 | /** |
2337 | * amdgpu_device_ip_init - run init for hardware IPs | |
2338 | * | |
2339 | * @adev: amdgpu_device pointer | |
2340 | * | |
2341 | * Main initialization pass for hardware IPs. The list of all the hardware | |
2342 | * IPs that make up the asic is walked and the sw_init and hw_init callbacks | |
2343 | * are run. sw_init initializes the software state associated with each IP | |
2344 | * and hw_init initializes the hardware associated with each IP. | |
2345 | * Returns 0 on success, negative error code on failure. | |
2346 | */ | |
06ec9070 | 2347 | static int amdgpu_device_ip_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
2348 | { |
2349 | int i, r; | |
2350 | ||
c030f2e4 | 2351 | r = amdgpu_ras_init(adev); |
2352 | if (r) | |
2353 | return r; | |
2354 | ||
d38ceaf9 | 2355 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 2356 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2357 | continue; |
a1255107 | 2358 | r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); |
2c1a2784 | 2359 | if (r) { |
a1255107 AD |
2360 | DRM_ERROR("sw_init of IP block <%s> failed %d\n", |
2361 | adev->ip_blocks[i].version->funcs->name, r); | |
72d3f592 | 2362 | goto init_failed; |
2c1a2784 | 2363 | } |
a1255107 | 2364 | adev->ip_blocks[i].status.sw = true; |
bfca0289 | 2365 | |
d38ceaf9 | 2366 | /* need to do gmc hw init early so we can allocate gpu mem */ |
a1255107 | 2367 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { |
06ec9070 | 2368 | r = amdgpu_device_vram_scratch_init(adev); |
2c1a2784 AD |
2369 | if (r) { |
2370 | DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r); | |
72d3f592 | 2371 | goto init_failed; |
2c1a2784 | 2372 | } |
a1255107 | 2373 | r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); |
2c1a2784 AD |
2374 | if (r) { |
2375 | DRM_ERROR("hw_init %d failed %d\n", i, r); | |
72d3f592 | 2376 | goto init_failed; |
2c1a2784 | 2377 | } |
06ec9070 | 2378 | r = amdgpu_device_wb_init(adev); |
2c1a2784 | 2379 | if (r) { |
06ec9070 | 2380 | DRM_ERROR("amdgpu_device_wb_init failed %d\n", r); |
72d3f592 | 2381 | goto init_failed; |
2c1a2784 | 2382 | } |
a1255107 | 2383 | adev->ip_blocks[i].status.hw = true; |
2493664f ML |
2384 | |
2385 | /* right after GMC hw init, we create CSA */ | |
f92d5c61 | 2386 | if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { |
1e256e27 RZ |
2387 | r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj, |
2388 | AMDGPU_GEM_DOMAIN_VRAM, | |
2389 | AMDGPU_CSA_SIZE); | |
2493664f ML |
2390 | if (r) { |
2391 | DRM_ERROR("allocate CSA failed %d\n", r); | |
72d3f592 | 2392 | goto init_failed; |
2493664f ML |
2393 | } |
2394 | } | |
d38ceaf9 AD |
2395 | } |
2396 | } | |
2397 | ||
c9ffa427 YT |
2398 | if (amdgpu_sriov_vf(adev)) |
2399 | amdgpu_virt_init_data_exchange(adev); | |
2400 | ||
533aed27 AG |
2401 | r = amdgpu_ib_pool_init(adev); |
2402 | if (r) { | |
2403 | dev_err(adev->dev, "IB initialization failed (%d).\n", r); | |
2404 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r); | |
2405 | goto init_failed; | |
2406 | } | |
2407 | ||
c8963ea4 RZ |
2408 | r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ |
2409 | if (r) | |
72d3f592 | 2410 | goto init_failed; |
0a4f2520 | 2411 | |
c482aa2c JZ |
2412 | r = amdgpu_amdkfd_resume_iommu(adev); |
2413 | if (r) | |
2414 | goto init_failed; | |
2415 | ||
0a4f2520 RZ |
2416 | r = amdgpu_device_ip_hw_init_phase1(adev); |
2417 | if (r) | |
72d3f592 | 2418 | goto init_failed; |
0a4f2520 | 2419 | |
7a3e0bb2 RZ |
2420 | r = amdgpu_device_fw_loading(adev); |
2421 | if (r) | |
72d3f592 | 2422 | goto init_failed; |
7a3e0bb2 | 2423 | |
0a4f2520 RZ |
2424 | r = amdgpu_device_ip_hw_init_phase2(adev); |
2425 | if (r) | |
72d3f592 | 2426 | goto init_failed; |
d38ceaf9 | 2427 | |
121a2bc6 AG |
2428 | /* |
2429 | * retired pages will be loaded from eeprom and reserved here, | |
2430 | * it should be called after amdgpu_device_ip_hw_init_phase2 since | |
2431 | * for some ASICs the RAS EEPROM code relies on SMU fully functioning | |
2432 | * for I2C communication which only true at this point. | |
b82e65a9 GC |
2433 | * |
2434 | * amdgpu_ras_recovery_init may fail, but the upper only cares the | |
2435 | * failure from bad gpu situation and stop amdgpu init process | |
2436 | * accordingly. For other failed cases, it will still release all | |
2437 | * the resource and print error message, rather than returning one | |
2438 | * negative value to upper level. | |
121a2bc6 AG |
2439 | * |
2440 | * Note: theoretically, this should be called before all vram allocations | |
2441 | * to protect retired page from abusing | |
2442 | */ | |
b82e65a9 GC |
2443 | r = amdgpu_ras_recovery_init(adev); |
2444 | if (r) | |
2445 | goto init_failed; | |
121a2bc6 | 2446 | |
3e2e2ab5 HZ |
2447 | if (adev->gmc.xgmi.num_physical_nodes > 1) |
2448 | amdgpu_xgmi_add_device(adev); | |
e3c1b071 | 2449 | |
2450 | /* Don't init kfd if whole hive need to be reset during init */ | |
2451 | if (!adev->gmc.xgmi.pending_reset) | |
2452 | amdgpu_amdkfd_device_init(adev); | |
c6332b97 | 2453 | |
bd607166 KR |
2454 | amdgpu_fru_get_product_info(adev); |
2455 | ||
72d3f592 | 2456 | init_failed: |
c9ffa427 | 2457 | if (amdgpu_sriov_vf(adev)) |
c6332b97 | 2458 | amdgpu_virt_release_full_gpu(adev, true); |
2459 | ||
72d3f592 | 2460 | return r; |
d38ceaf9 AD |
2461 | } |
2462 | ||
e3ecdffa AD |
2463 | /** |
2464 | * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer | |
2465 | * | |
2466 | * @adev: amdgpu_device pointer | |
2467 | * | |
2468 | * Writes a reset magic value to the gart pointer in VRAM. The driver calls | |
2469 | * this function before a GPU reset. If the value is retained after a | |
2470 | * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents. | |
2471 | */ | |
06ec9070 | 2472 | static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev) |
0c49e0b8 CZ |
2473 | { |
2474 | memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); | |
2475 | } | |
2476 | ||
e3ecdffa AD |
2477 | /** |
2478 | * amdgpu_device_check_vram_lost - check if vram is valid | |
2479 | * | |
2480 | * @adev: amdgpu_device pointer | |
2481 | * | |
2482 | * Checks the reset magic value written to the gart pointer in VRAM. | |
2483 | * The driver calls this after a GPU reset to see if the contents of | |
2484 | * VRAM is lost or now. | |
2485 | * returns true if vram is lost, false if not. | |
2486 | */ | |
06ec9070 | 2487 | static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) |
0c49e0b8 | 2488 | { |
dadce777 EQ |
2489 | if (memcmp(adev->gart.ptr, adev->reset_magic, |
2490 | AMDGPU_RESET_MAGIC_NUM)) | |
2491 | return true; | |
2492 | ||
53b3f8f4 | 2493 | if (!amdgpu_in_reset(adev)) |
dadce777 EQ |
2494 | return false; |
2495 | ||
2496 | /* | |
2497 | * For all ASICs with baco/mode1 reset, the VRAM is | |
2498 | * always assumed to be lost. | |
2499 | */ | |
2500 | switch (amdgpu_asic_reset_method(adev)) { | |
2501 | case AMD_RESET_METHOD_BACO: | |
2502 | case AMD_RESET_METHOD_MODE1: | |
2503 | return true; | |
2504 | default: | |
2505 | return false; | |
2506 | } | |
0c49e0b8 CZ |
2507 | } |
2508 | ||
e3ecdffa | 2509 | /** |
1112a46b | 2510 | * amdgpu_device_set_cg_state - set clockgating for amdgpu device |
e3ecdffa AD |
2511 | * |
2512 | * @adev: amdgpu_device pointer | |
b8b72130 | 2513 | * @state: clockgating state (gate or ungate) |
e3ecdffa | 2514 | * |
e3ecdffa | 2515 | * The list of all the hardware IPs that make up the asic is walked and the |
1112a46b RZ |
2516 | * set_clockgating_state callbacks are run. |
2517 | * Late initialization pass enabling clockgating for hardware IPs. | |
2518 | * Fini or suspend, pass disabling clockgating for hardware IPs. | |
e3ecdffa AD |
2519 | * Returns 0 on success, negative error code on failure. |
2520 | */ | |
fdd34271 | 2521 | |
5d89bb2d LL |
2522 | int amdgpu_device_set_cg_state(struct amdgpu_device *adev, |
2523 | enum amd_clockgating_state state) | |
d38ceaf9 | 2524 | { |
1112a46b | 2525 | int i, j, r; |
d38ceaf9 | 2526 | |
4a2ba394 SL |
2527 | if (amdgpu_emu_mode == 1) |
2528 | return 0; | |
2529 | ||
1112a46b RZ |
2530 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2531 | i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2532 | if (!adev->ip_blocks[i].status.late_initialized) |
d38ceaf9 | 2533 | continue; |
5d70a549 PV |
2534 | /* skip CG for GFX on S0ix */ |
2535 | if (adev->in_s0ix && | |
2536 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) | |
2537 | continue; | |
4a446d55 | 2538 | /* skip CG for VCE/UVD, it's handled specially */ |
a1255107 | 2539 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && |
57716327 | 2540 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && |
34319b32 | 2541 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && |
52f2e779 | 2542 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
57716327 | 2543 | adev->ip_blocks[i].version->funcs->set_clockgating_state) { |
4a446d55 | 2544 | /* enable clockgating to save power */ |
a1255107 | 2545 | r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, |
1112a46b | 2546 | state); |
4a446d55 AD |
2547 | if (r) { |
2548 | DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", | |
a1255107 | 2549 | adev->ip_blocks[i].version->funcs->name, r); |
4a446d55 AD |
2550 | return r; |
2551 | } | |
b0b00ff1 | 2552 | } |
d38ceaf9 | 2553 | } |
06b18f61 | 2554 | |
c9f96fd5 RZ |
2555 | return 0; |
2556 | } | |
2557 | ||
5d89bb2d LL |
2558 | int amdgpu_device_set_pg_state(struct amdgpu_device *adev, |
2559 | enum amd_powergating_state state) | |
c9f96fd5 | 2560 | { |
1112a46b | 2561 | int i, j, r; |
06b18f61 | 2562 | |
c9f96fd5 RZ |
2563 | if (amdgpu_emu_mode == 1) |
2564 | return 0; | |
2565 | ||
1112a46b RZ |
2566 | for (j = 0; j < adev->num_ip_blocks; j++) { |
2567 | i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; | |
a2d31dc3 | 2568 | if (!adev->ip_blocks[i].status.late_initialized) |
c9f96fd5 | 2569 | continue; |
5d70a549 PV |
2570 | /* skip PG for GFX on S0ix */ |
2571 | if (adev->in_s0ix && | |
2572 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX) | |
2573 | continue; | |
c9f96fd5 RZ |
2574 | /* skip CG for VCE/UVD, it's handled specially */ |
2575 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && | |
2576 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && | |
2577 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && | |
52f2e779 | 2578 | adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && |
c9f96fd5 RZ |
2579 | adev->ip_blocks[i].version->funcs->set_powergating_state) { |
2580 | /* enable powergating to save power */ | |
2581 | r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev, | |
1112a46b | 2582 | state); |
c9f96fd5 RZ |
2583 | if (r) { |
2584 | DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n", | |
2585 | adev->ip_blocks[i].version->funcs->name, r); | |
2586 | return r; | |
2587 | } | |
2588 | } | |
2589 | } | |
2dc80b00 S |
2590 | return 0; |
2591 | } | |
2592 | ||
beff74bc AD |
2593 | static int amdgpu_device_enable_mgpu_fan_boost(void) |
2594 | { | |
2595 | struct amdgpu_gpu_instance *gpu_ins; | |
2596 | struct amdgpu_device *adev; | |
2597 | int i, ret = 0; | |
2598 | ||
2599 | mutex_lock(&mgpu_info.mutex); | |
2600 | ||
2601 | /* | |
2602 | * MGPU fan boost feature should be enabled | |
2603 | * only when there are two or more dGPUs in | |
2604 | * the system | |
2605 | */ | |
2606 | if (mgpu_info.num_dgpu < 2) | |
2607 | goto out; | |
2608 | ||
2609 | for (i = 0; i < mgpu_info.num_dgpu; i++) { | |
2610 | gpu_ins = &(mgpu_info.gpu_ins[i]); | |
2611 | adev = gpu_ins->adev; | |
2612 | if (!(adev->flags & AMD_IS_APU) && | |
f10bb940 | 2613 | !gpu_ins->mgpu_fan_enabled) { |
beff74bc AD |
2614 | ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); |
2615 | if (ret) | |
2616 | break; | |
2617 | ||
2618 | gpu_ins->mgpu_fan_enabled = 1; | |
2619 | } | |
2620 | } | |
2621 | ||
2622 | out: | |
2623 | mutex_unlock(&mgpu_info.mutex); | |
2624 | ||
2625 | return ret; | |
2626 | } | |
2627 | ||
e3ecdffa AD |
2628 | /** |
2629 | * amdgpu_device_ip_late_init - run late init for hardware IPs | |
2630 | * | |
2631 | * @adev: amdgpu_device pointer | |
2632 | * | |
2633 | * Late initialization pass for hardware IPs. The list of all the hardware | |
2634 | * IPs that make up the asic is walked and the late_init callbacks are run. | |
2635 | * late_init covers any special initialization that an IP requires | |
2636 | * after all of the have been initialized or something that needs to happen | |
2637 | * late in the init process. | |
2638 | * Returns 0 on success, negative error code on failure. | |
2639 | */ | |
06ec9070 | 2640 | static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) |
2dc80b00 | 2641 | { |
60599a03 | 2642 | struct amdgpu_gpu_instance *gpu_instance; |
2dc80b00 S |
2643 | int i = 0, r; |
2644 | ||
2645 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
73f847db | 2646 | if (!adev->ip_blocks[i].status.hw) |
2dc80b00 S |
2647 | continue; |
2648 | if (adev->ip_blocks[i].version->funcs->late_init) { | |
2649 | r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); | |
2650 | if (r) { | |
2651 | DRM_ERROR("late_init of IP block <%s> failed %d\n", | |
2652 | adev->ip_blocks[i].version->funcs->name, r); | |
2653 | return r; | |
2654 | } | |
2dc80b00 | 2655 | } |
73f847db | 2656 | adev->ip_blocks[i].status.late_initialized = true; |
2dc80b00 S |
2657 | } |
2658 | ||
a891d239 DL |
2659 | amdgpu_ras_set_error_query_ready(adev, true); |
2660 | ||
1112a46b RZ |
2661 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
2662 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); | |
916ac57f | 2663 | |
06ec9070 | 2664 | amdgpu_device_fill_reset_magic(adev); |
d38ceaf9 | 2665 | |
beff74bc AD |
2666 | r = amdgpu_device_enable_mgpu_fan_boost(); |
2667 | if (r) | |
2668 | DRM_ERROR("enable mgpu fan boost failed (%d).\n", r); | |
2669 | ||
2d02893f | 2670 | /* For XGMI + passthrough configuration on arcturus, enable light SBR */ |
2671 | if (adev->asic_type == CHIP_ARCTURUS && | |
2672 | amdgpu_passthrough(adev) && | |
2673 | adev->gmc.xgmi.num_physical_nodes > 1) | |
2674 | smu_set_light_sbr(&adev->smu, true); | |
60599a03 EQ |
2675 | |
2676 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
2677 | mutex_lock(&mgpu_info.mutex); | |
2678 | ||
2679 | /* | |
2680 | * Reset device p-state to low as this was booted with high. | |
2681 | * | |
2682 | * This should be performed only after all devices from the same | |
2683 | * hive get initialized. | |
2684 | * | |
2685 | * However, it's unknown how many device in the hive in advance. | |
2686 | * As this is counted one by one during devices initializations. | |
2687 | * | |
2688 | * So, we wait for all XGMI interlinked devices initialized. | |
2689 | * This may bring some delays as those devices may come from | |
2690 | * different hives. But that should be OK. | |
2691 | */ | |
2692 | if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) { | |
2693 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
2694 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
2695 | if (gpu_instance->adev->flags & AMD_IS_APU) | |
2696 | continue; | |
2697 | ||
d84a430d JK |
2698 | r = amdgpu_xgmi_set_pstate(gpu_instance->adev, |
2699 | AMDGPU_XGMI_PSTATE_MIN); | |
60599a03 EQ |
2700 | if (r) { |
2701 | DRM_ERROR("pstate setting failed (%d).\n", r); | |
2702 | break; | |
2703 | } | |
2704 | } | |
2705 | } | |
2706 | ||
2707 | mutex_unlock(&mgpu_info.mutex); | |
2708 | } | |
2709 | ||
d38ceaf9 AD |
2710 | return 0; |
2711 | } | |
2712 | ||
e9669fb7 | 2713 | static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) |
d38ceaf9 AD |
2714 | { |
2715 | int i, r; | |
2716 | ||
e9669fb7 AG |
2717 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2718 | if (!adev->ip_blocks[i].version->funcs->early_fini) | |
2719 | continue; | |
5278a159 | 2720 | |
e9669fb7 AG |
2721 | r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev); |
2722 | if (r) { | |
2723 | DRM_DEBUG("early_fini of IP block <%s> failed %d\n", | |
2724 | adev->ip_blocks[i].version->funcs->name, r); | |
2725 | } | |
2726 | } | |
c030f2e4 | 2727 | |
e9669fb7 | 2728 | amdgpu_amdkfd_suspend(adev, false); |
a82400b5 | 2729 | |
05df1f01 | 2730 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
fdd34271 RZ |
2731 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
2732 | ||
3e96dbfd AD |
2733 | /* need to disable SMC first */ |
2734 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 2735 | if (!adev->ip_blocks[i].status.hw) |
3e96dbfd | 2736 | continue; |
fdd34271 | 2737 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { |
a1255107 | 2738 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
3e96dbfd AD |
2739 | /* XXX handle errors */ |
2740 | if (r) { | |
2741 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", | |
a1255107 | 2742 | adev->ip_blocks[i].version->funcs->name, r); |
3e96dbfd | 2743 | } |
a1255107 | 2744 | adev->ip_blocks[i].status.hw = false; |
3e96dbfd AD |
2745 | break; |
2746 | } | |
2747 | } | |
2748 | ||
d38ceaf9 | 2749 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2750 | if (!adev->ip_blocks[i].status.hw) |
d38ceaf9 | 2751 | continue; |
8201a67a | 2752 | |
a1255107 | 2753 | r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); |
d38ceaf9 | 2754 | /* XXX handle errors */ |
2c1a2784 | 2755 | if (r) { |
a1255107 AD |
2756 | DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", |
2757 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2758 | } |
8201a67a | 2759 | |
a1255107 | 2760 | adev->ip_blocks[i].status.hw = false; |
d38ceaf9 AD |
2761 | } |
2762 | ||
75d680ca GC |
2763 | if (amdgpu_sriov_vf(adev)) { |
2764 | if (amdgpu_virt_release_full_gpu(adev, false)) | |
2765 | DRM_ERROR("failed to release exclusive mode on fini\n"); | |
2766 | } | |
2767 | ||
e9669fb7 AG |
2768 | return 0; |
2769 | } | |
2770 | ||
2771 | /** | |
2772 | * amdgpu_device_ip_fini - run fini for hardware IPs | |
2773 | * | |
2774 | * @adev: amdgpu_device pointer | |
2775 | * | |
2776 | * Main teardown pass for hardware IPs. The list of all the hardware | |
2777 | * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks | |
2778 | * are run. hw_fini tears down the hardware associated with each IP | |
2779 | * and sw_fini tears down any software state associated with each IP. | |
2780 | * Returns 0 on success, negative error code on failure. | |
2781 | */ | |
2782 | static int amdgpu_device_ip_fini(struct amdgpu_device *adev) | |
2783 | { | |
2784 | int i, r; | |
2785 | ||
2786 | if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done) | |
2787 | amdgpu_virt_release_ras_err_handler_data(adev); | |
2788 | ||
2789 | amdgpu_ras_pre_fini(adev); | |
2790 | ||
2791 | if (adev->gmc.xgmi.num_physical_nodes > 1) | |
2792 | amdgpu_xgmi_remove_device(adev); | |
2793 | ||
2794 | amdgpu_amdkfd_device_fini_sw(adev); | |
9950cda2 | 2795 | |
d38ceaf9 | 2796 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2797 | if (!adev->ip_blocks[i].status.sw) |
d38ceaf9 | 2798 | continue; |
c12aba3a ML |
2799 | |
2800 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { | |
c8963ea4 | 2801 | amdgpu_ucode_free_bo(adev); |
1e256e27 | 2802 | amdgpu_free_static_csa(&adev->virt.csa_obj); |
c12aba3a ML |
2803 | amdgpu_device_wb_fini(adev); |
2804 | amdgpu_device_vram_scratch_fini(adev); | |
533aed27 | 2805 | amdgpu_ib_pool_fini(adev); |
c12aba3a ML |
2806 | } |
2807 | ||
a1255107 | 2808 | r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); |
d38ceaf9 | 2809 | /* XXX handle errors */ |
2c1a2784 | 2810 | if (r) { |
a1255107 AD |
2811 | DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", |
2812 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2813 | } |
a1255107 AD |
2814 | adev->ip_blocks[i].status.sw = false; |
2815 | adev->ip_blocks[i].status.valid = false; | |
d38ceaf9 AD |
2816 | } |
2817 | ||
a6dcfd9c | 2818 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2819 | if (!adev->ip_blocks[i].status.late_initialized) |
8a2eef1d | 2820 | continue; |
a1255107 AD |
2821 | if (adev->ip_blocks[i].version->funcs->late_fini) |
2822 | adev->ip_blocks[i].version->funcs->late_fini((void *)adev); | |
2823 | adev->ip_blocks[i].status.late_initialized = false; | |
a6dcfd9c ML |
2824 | } |
2825 | ||
c030f2e4 | 2826 | amdgpu_ras_fini(adev); |
2827 | ||
d38ceaf9 AD |
2828 | return 0; |
2829 | } | |
2830 | ||
e3ecdffa | 2831 | /** |
beff74bc | 2832 | * amdgpu_device_delayed_init_work_handler - work handler for IB tests |
e3ecdffa | 2833 | * |
1112a46b | 2834 | * @work: work_struct. |
e3ecdffa | 2835 | */ |
beff74bc | 2836 | static void amdgpu_device_delayed_init_work_handler(struct work_struct *work) |
2dc80b00 S |
2837 | { |
2838 | struct amdgpu_device *adev = | |
beff74bc | 2839 | container_of(work, struct amdgpu_device, delayed_init_work.work); |
916ac57f RZ |
2840 | int r; |
2841 | ||
2842 | r = amdgpu_ib_ring_tests(adev); | |
2843 | if (r) | |
2844 | DRM_ERROR("ib ring test failed (%d).\n", r); | |
2dc80b00 S |
2845 | } |
2846 | ||
1e317b99 RZ |
2847 | static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) |
2848 | { | |
2849 | struct amdgpu_device *adev = | |
2850 | container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); | |
2851 | ||
90a92662 MD |
2852 | WARN_ON_ONCE(adev->gfx.gfx_off_state); |
2853 | WARN_ON_ONCE(adev->gfx.gfx_off_req_count); | |
2854 | ||
2855 | if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) | |
2856 | adev->gfx.gfx_off_state = true; | |
1e317b99 RZ |
2857 | } |
2858 | ||
e3ecdffa | 2859 | /** |
e7854a03 | 2860 | * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) |
e3ecdffa AD |
2861 | * |
2862 | * @adev: amdgpu_device pointer | |
2863 | * | |
2864 | * Main suspend function for hardware IPs. The list of all the hardware | |
2865 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2866 | * suspend callbacks are run. suspend puts the hardware and software state | |
2867 | * in each IP into a state suitable for suspend. | |
2868 | * Returns 0 on success, negative error code on failure. | |
2869 | */ | |
e7854a03 AD |
2870 | static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) |
2871 | { | |
2872 | int i, r; | |
2873 | ||
50ec83f0 AD |
2874 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
2875 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); | |
05df1f01 | 2876 | |
e7854a03 AD |
2877 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
2878 | if (!adev->ip_blocks[i].status.valid) | |
2879 | continue; | |
2b9f7848 | 2880 | |
e7854a03 | 2881 | /* displays are handled separately */ |
2b9f7848 ND |
2882 | if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) |
2883 | continue; | |
2884 | ||
2885 | /* XXX handle errors */ | |
2886 | r = adev->ip_blocks[i].version->funcs->suspend(adev); | |
2887 | /* XXX handle errors */ | |
2888 | if (r) { | |
2889 | DRM_ERROR("suspend of IP block <%s> failed %d\n", | |
2890 | adev->ip_blocks[i].version->funcs->name, r); | |
2891 | return r; | |
e7854a03 | 2892 | } |
2b9f7848 ND |
2893 | |
2894 | adev->ip_blocks[i].status.hw = false; | |
e7854a03 AD |
2895 | } |
2896 | ||
e7854a03 AD |
2897 | return 0; |
2898 | } | |
2899 | ||
2900 | /** | |
2901 | * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2) | |
2902 | * | |
2903 | * @adev: amdgpu_device pointer | |
2904 | * | |
2905 | * Main suspend function for hardware IPs. The list of all the hardware | |
2906 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2907 | * suspend callbacks are run. suspend puts the hardware and software state | |
2908 | * in each IP into a state suitable for suspend. | |
2909 | * Returns 0 on success, negative error code on failure. | |
2910 | */ | |
2911 | static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) | |
d38ceaf9 AD |
2912 | { |
2913 | int i, r; | |
2914 | ||
557f42a2 | 2915 | if (adev->in_s0ix) |
34416931 | 2916 | amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry); |
34416931 | 2917 | |
d38ceaf9 | 2918 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
a1255107 | 2919 | if (!adev->ip_blocks[i].status.valid) |
d38ceaf9 | 2920 | continue; |
e7854a03 AD |
2921 | /* displays are handled in phase1 */ |
2922 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) | |
2923 | continue; | |
bff77e86 LM |
2924 | /* PSP lost connection when err_event_athub occurs */ |
2925 | if (amdgpu_ras_intr_triggered() && | |
2926 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
2927 | adev->ip_blocks[i].status.hw = false; | |
2928 | continue; | |
2929 | } | |
e3c1b071 | 2930 | |
2931 | /* skip unnecessary suspend if we do not initialize them yet */ | |
2932 | if (adev->gmc.xgmi.pending_reset && | |
2933 | !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
2934 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC || | |
2935 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
2936 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) { | |
2937 | adev->ip_blocks[i].status.hw = false; | |
2938 | continue; | |
2939 | } | |
557f42a2 | 2940 | |
32ff160d AD |
2941 | /* skip suspend of gfx and psp for S0ix |
2942 | * gfx is in gfxoff state, so on resume it will exit gfxoff just | |
2943 | * like at runtime. PSP is also part of the always on hardware | |
2944 | * so no need to suspend it. | |
2945 | */ | |
557f42a2 | 2946 | if (adev->in_s0ix && |
32ff160d AD |
2947 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP || |
2948 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)) | |
557f42a2 AD |
2949 | continue; |
2950 | ||
d38ceaf9 | 2951 | /* XXX handle errors */ |
a1255107 | 2952 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
d38ceaf9 | 2953 | /* XXX handle errors */ |
2c1a2784 | 2954 | if (r) { |
a1255107 AD |
2955 | DRM_ERROR("suspend of IP block <%s> failed %d\n", |
2956 | adev->ip_blocks[i].version->funcs->name, r); | |
2c1a2784 | 2957 | } |
876923fb | 2958 | adev->ip_blocks[i].status.hw = false; |
a3a09142 | 2959 | /* handle putting the SMC in the appropriate state */ |
86b93fd6 JZ |
2960 | if(!amdgpu_sriov_vf(adev)){ |
2961 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { | |
2962 | r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state); | |
2963 | if (r) { | |
2964 | DRM_ERROR("SMC failed to set mp1 state %d, %d\n", | |
2965 | adev->mp1_state, r); | |
2966 | return r; | |
2967 | } | |
a3a09142 AD |
2968 | } |
2969 | } | |
d38ceaf9 AD |
2970 | } |
2971 | ||
2972 | return 0; | |
2973 | } | |
2974 | ||
e7854a03 AD |
2975 | /** |
2976 | * amdgpu_device_ip_suspend - run suspend for hardware IPs | |
2977 | * | |
2978 | * @adev: amdgpu_device pointer | |
2979 | * | |
2980 | * Main suspend function for hardware IPs. The list of all the hardware | |
2981 | * IPs that make up the asic is walked, clockgating is disabled and the | |
2982 | * suspend callbacks are run. suspend puts the hardware and software state | |
2983 | * in each IP into a state suitable for suspend. | |
2984 | * Returns 0 on success, negative error code on failure. | |
2985 | */ | |
2986 | int amdgpu_device_ip_suspend(struct amdgpu_device *adev) | |
2987 | { | |
2988 | int r; | |
2989 | ||
3c73683c JC |
2990 | if (amdgpu_sriov_vf(adev)) { |
2991 | amdgpu_virt_fini_data_exchange(adev); | |
e7819644 | 2992 | amdgpu_virt_request_full_gpu(adev, false); |
3c73683c | 2993 | } |
e7819644 | 2994 | |
e7854a03 AD |
2995 | r = amdgpu_device_ip_suspend_phase1(adev); |
2996 | if (r) | |
2997 | return r; | |
2998 | r = amdgpu_device_ip_suspend_phase2(adev); | |
2999 | ||
e7819644 YT |
3000 | if (amdgpu_sriov_vf(adev)) |
3001 | amdgpu_virt_release_full_gpu(adev, false); | |
3002 | ||
e7854a03 AD |
3003 | return r; |
3004 | } | |
3005 | ||
06ec9070 | 3006 | static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
3007 | { |
3008 | int i, r; | |
3009 | ||
2cb681b6 ML |
3010 | static enum amd_ip_block_type ip_order[] = { |
3011 | AMD_IP_BLOCK_TYPE_GMC, | |
3012 | AMD_IP_BLOCK_TYPE_COMMON, | |
39186aef | 3013 | AMD_IP_BLOCK_TYPE_PSP, |
2cb681b6 ML |
3014 | AMD_IP_BLOCK_TYPE_IH, |
3015 | }; | |
a90ad3c2 | 3016 | |
95ea3dbc | 3017 | for (i = 0; i < adev->num_ip_blocks; i++) { |
2cb681b6 ML |
3018 | int j; |
3019 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3020 | |
4cd2a96d J |
3021 | block = &adev->ip_blocks[i]; |
3022 | block->status.hw = false; | |
2cb681b6 | 3023 | |
4cd2a96d | 3024 | for (j = 0; j < ARRAY_SIZE(ip_order); j++) { |
2cb681b6 | 3025 | |
4cd2a96d | 3026 | if (block->version->type != ip_order[j] || |
2cb681b6 ML |
3027 | !block->status.valid) |
3028 | continue; | |
3029 | ||
3030 | r = block->version->funcs->hw_init(adev); | |
0aaeefcc | 3031 | DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3032 | if (r) |
3033 | return r; | |
482f0e53 | 3034 | block->status.hw = true; |
a90ad3c2 ML |
3035 | } |
3036 | } | |
3037 | ||
3038 | return 0; | |
3039 | } | |
3040 | ||
06ec9070 | 3041 | static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) |
a90ad3c2 ML |
3042 | { |
3043 | int i, r; | |
3044 | ||
2cb681b6 ML |
3045 | static enum amd_ip_block_type ip_order[] = { |
3046 | AMD_IP_BLOCK_TYPE_SMC, | |
3047 | AMD_IP_BLOCK_TYPE_DCE, | |
3048 | AMD_IP_BLOCK_TYPE_GFX, | |
3049 | AMD_IP_BLOCK_TYPE_SDMA, | |
257deb8c | 3050 | AMD_IP_BLOCK_TYPE_UVD, |
d83c7a07 JJ |
3051 | AMD_IP_BLOCK_TYPE_VCE, |
3052 | AMD_IP_BLOCK_TYPE_VCN | |
2cb681b6 | 3053 | }; |
a90ad3c2 | 3054 | |
2cb681b6 ML |
3055 | for (i = 0; i < ARRAY_SIZE(ip_order); i++) { |
3056 | int j; | |
3057 | struct amdgpu_ip_block *block; | |
a90ad3c2 | 3058 | |
2cb681b6 ML |
3059 | for (j = 0; j < adev->num_ip_blocks; j++) { |
3060 | block = &adev->ip_blocks[j]; | |
3061 | ||
3062 | if (block->version->type != ip_order[i] || | |
482f0e53 ML |
3063 | !block->status.valid || |
3064 | block->status.hw) | |
2cb681b6 ML |
3065 | continue; |
3066 | ||
895bd048 JZ |
3067 | if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) |
3068 | r = block->version->funcs->resume(adev); | |
3069 | else | |
3070 | r = block->version->funcs->hw_init(adev); | |
3071 | ||
0aaeefcc | 3072 | DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); |
c41d1cf6 ML |
3073 | if (r) |
3074 | return r; | |
482f0e53 | 3075 | block->status.hw = true; |
a90ad3c2 ML |
3076 | } |
3077 | } | |
3078 | ||
3079 | return 0; | |
3080 | } | |
3081 | ||
e3ecdffa AD |
3082 | /** |
3083 | * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs | |
3084 | * | |
3085 | * @adev: amdgpu_device pointer | |
3086 | * | |
3087 | * First resume function for hardware IPs. The list of all the hardware | |
3088 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3089 | * COMMON, GMC, and IH. resume puts the hardware into a functional state | |
3090 | * after a suspend and updates the software state as necessary. This | |
3091 | * function is also used for restoring the GPU after a GPU reset. | |
3092 | * Returns 0 on success, negative error code on failure. | |
3093 | */ | |
06ec9070 | 3094 | static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) |
d38ceaf9 AD |
3095 | { |
3096 | int i, r; | |
3097 | ||
a90ad3c2 | 3098 | for (i = 0; i < adev->num_ip_blocks; i++) { |
482f0e53 | 3099 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
a90ad3c2 | 3100 | continue; |
a90ad3c2 | 3101 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa AD |
3102 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
3103 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { | |
482f0e53 | 3104 | |
fcf0649f CZ |
3105 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
3106 | if (r) { | |
3107 | DRM_ERROR("resume of IP block <%s> failed %d\n", | |
3108 | adev->ip_blocks[i].version->funcs->name, r); | |
3109 | return r; | |
3110 | } | |
482f0e53 | 3111 | adev->ip_blocks[i].status.hw = true; |
a90ad3c2 ML |
3112 | } |
3113 | } | |
3114 | ||
3115 | return 0; | |
3116 | } | |
3117 | ||
e3ecdffa AD |
3118 | /** |
3119 | * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs | |
3120 | * | |
3121 | * @adev: amdgpu_device pointer | |
3122 | * | |
3123 | * First resume function for hardware IPs. The list of all the hardware | |
3124 | * IPs that make up the asic is walked and the resume callbacks are run for | |
3125 | * all blocks except COMMON, GMC, and IH. resume puts the hardware into a | |
3126 | * functional state after a suspend and updates the software state as | |
3127 | * necessary. This function is also used for restoring the GPU after a GPU | |
3128 | * reset. | |
3129 | * Returns 0 on success, negative error code on failure. | |
3130 | */ | |
06ec9070 | 3131 | static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) |
d38ceaf9 AD |
3132 | { |
3133 | int i, r; | |
3134 | ||
3135 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
482f0e53 | 3136 | if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) |
d38ceaf9 | 3137 | continue; |
fcf0649f | 3138 | if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || |
e3ecdffa | 3139 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || |
7a3e0bb2 RZ |
3140 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || |
3141 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) | |
fcf0649f | 3142 | continue; |
a1255107 | 3143 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
2c1a2784 | 3144 | if (r) { |
a1255107 AD |
3145 | DRM_ERROR("resume of IP block <%s> failed %d\n", |
3146 | adev->ip_blocks[i].version->funcs->name, r); | |
d38ceaf9 | 3147 | return r; |
2c1a2784 | 3148 | } |
482f0e53 | 3149 | adev->ip_blocks[i].status.hw = true; |
d38ceaf9 AD |
3150 | } |
3151 | ||
3152 | return 0; | |
3153 | } | |
3154 | ||
e3ecdffa AD |
3155 | /** |
3156 | * amdgpu_device_ip_resume - run resume for hardware IPs | |
3157 | * | |
3158 | * @adev: amdgpu_device pointer | |
3159 | * | |
3160 | * Main resume function for hardware IPs. The hardware IPs | |
3161 | * are split into two resume functions because they are | |
3162 | * are also used in in recovering from a GPU reset and some additional | |
3163 | * steps need to be take between them. In this case (S3/S4) they are | |
3164 | * run sequentially. | |
3165 | * Returns 0 on success, negative error code on failure. | |
3166 | */ | |
06ec9070 | 3167 | static int amdgpu_device_ip_resume(struct amdgpu_device *adev) |
fcf0649f CZ |
3168 | { |
3169 | int r; | |
3170 | ||
f02abeb0 JZ |
3171 | r = amdgpu_amdkfd_resume_iommu(adev); |
3172 | if (r) | |
3173 | return r; | |
3174 | ||
06ec9070 | 3175 | r = amdgpu_device_ip_resume_phase1(adev); |
fcf0649f CZ |
3176 | if (r) |
3177 | return r; | |
7a3e0bb2 RZ |
3178 | |
3179 | r = amdgpu_device_fw_loading(adev); | |
3180 | if (r) | |
3181 | return r; | |
3182 | ||
06ec9070 | 3183 | r = amdgpu_device_ip_resume_phase2(adev); |
fcf0649f CZ |
3184 | |
3185 | return r; | |
3186 | } | |
3187 | ||
e3ecdffa AD |
3188 | /** |
3189 | * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV | |
3190 | * | |
3191 | * @adev: amdgpu_device pointer | |
3192 | * | |
3193 | * Query the VBIOS data tables to determine if the board supports SR-IOV. | |
3194 | */ | |
4e99a44e | 3195 | static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev) |
048765ad | 3196 | { |
6867e1b5 ML |
3197 | if (amdgpu_sriov_vf(adev)) { |
3198 | if (adev->is_atom_fw) { | |
58ff791a | 3199 | if (amdgpu_atomfirmware_gpu_virtualization_supported(adev)) |
6867e1b5 ML |
3200 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; |
3201 | } else { | |
3202 | if (amdgpu_atombios_has_gpu_virtualization_table(adev)) | |
3203 | adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS; | |
3204 | } | |
3205 | ||
3206 | if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)) | |
3207 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0); | |
a5bde2f9 | 3208 | } |
048765ad AR |
3209 | } |
3210 | ||
e3ecdffa AD |
3211 | /** |
3212 | * amdgpu_device_asic_has_dc_support - determine if DC supports the asic | |
3213 | * | |
3214 | * @asic_type: AMD asic type | |
3215 | * | |
3216 | * Check if there is DC (new modesetting infrastructre) support for an asic. | |
3217 | * returns true if DC has support, false if not. | |
3218 | */ | |
4562236b HW |
3219 | bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) |
3220 | { | |
3221 | switch (asic_type) { | |
3222 | #if defined(CONFIG_DRM_AMD_DC) | |
64200c46 MR |
3223 | #if defined(CONFIG_DRM_AMD_DC_SI) |
3224 | case CHIP_TAHITI: | |
3225 | case CHIP_PITCAIRN: | |
3226 | case CHIP_VERDE: | |
3227 | case CHIP_OLAND: | |
3228 | #endif | |
4562236b | 3229 | case CHIP_BONAIRE: |
0d6fbccb | 3230 | case CHIP_KAVERI: |
367e6687 AD |
3231 | case CHIP_KABINI: |
3232 | case CHIP_MULLINS: | |
d9fda248 HW |
3233 | /* |
3234 | * We have systems in the wild with these ASICs that require | |
3235 | * LVDS and VGA support which is not supported with DC. | |
3236 | * | |
3237 | * Fallback to the non-DC driver here by default so as not to | |
3238 | * cause regressions. | |
3239 | */ | |
3240 | return amdgpu_dc > 0; | |
3241 | case CHIP_HAWAII: | |
4562236b HW |
3242 | case CHIP_CARRIZO: |
3243 | case CHIP_STONEY: | |
4562236b | 3244 | case CHIP_POLARIS10: |
675fd32b | 3245 | case CHIP_POLARIS11: |
2c8ad2d5 | 3246 | case CHIP_POLARIS12: |
675fd32b | 3247 | case CHIP_VEGAM: |
4562236b HW |
3248 | case CHIP_TONGA: |
3249 | case CHIP_FIJI: | |
42f8ffa1 | 3250 | case CHIP_VEGA10: |
dca7b401 | 3251 | case CHIP_VEGA12: |
c6034aa2 | 3252 | case CHIP_VEGA20: |
b86a1aa3 | 3253 | #if defined(CONFIG_DRM_AMD_DC_DCN) |
fd187853 | 3254 | case CHIP_RAVEN: |
b4f199c7 | 3255 | case CHIP_NAVI10: |
8fceceb6 | 3256 | case CHIP_NAVI14: |
078655d9 | 3257 | case CHIP_NAVI12: |
e1c14c43 | 3258 | case CHIP_RENOIR: |
81d9bfb8 | 3259 | case CHIP_SIENNA_CICHLID: |
a6c5308f | 3260 | case CHIP_NAVY_FLOUNDER: |
7cc656e2 | 3261 | case CHIP_DIMGREY_CAVEFISH: |
ddaed58b | 3262 | case CHIP_BEIGE_GOBY: |
84b934bc | 3263 | case CHIP_VANGOGH: |
c8b73f7f | 3264 | case CHIP_YELLOW_CARP: |
42f8ffa1 | 3265 | #endif |
fd187853 | 3266 | return amdgpu_dc != 0; |
4562236b HW |
3267 | #endif |
3268 | default: | |
93b09a9a | 3269 | if (amdgpu_dc > 0) |
044a48f4 | 3270 | DRM_INFO_ONCE("Display Core has been requested via kernel parameter " |
93b09a9a | 3271 | "but isn't supported by ASIC, ignoring\n"); |
4562236b HW |
3272 | return false; |
3273 | } | |
3274 | } | |
3275 | ||
3276 | /** | |
3277 | * amdgpu_device_has_dc_support - check if dc is supported | |
3278 | * | |
982a820b | 3279 | * @adev: amdgpu_device pointer |
4562236b HW |
3280 | * |
3281 | * Returns true for supported, false for not supported | |
3282 | */ | |
3283 | bool amdgpu_device_has_dc_support(struct amdgpu_device *adev) | |
3284 | { | |
abaf210c AS |
3285 | if (amdgpu_sriov_vf(adev) || |
3286 | adev->enable_virtual_display || | |
3287 | (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)) | |
2555039d XY |
3288 | return false; |
3289 | ||
4562236b HW |
3290 | return amdgpu_device_asic_has_dc_support(adev->asic_type); |
3291 | } | |
3292 | ||
d4535e2c AG |
3293 | static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) |
3294 | { | |
3295 | struct amdgpu_device *adev = | |
3296 | container_of(__work, struct amdgpu_device, xgmi_reset_work); | |
d95e8e97 | 3297 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
d4535e2c | 3298 | |
c6a6e2db AG |
3299 | /* It's a bug to not have a hive within this function */ |
3300 | if (WARN_ON(!hive)) | |
3301 | return; | |
3302 | ||
3303 | /* | |
3304 | * Use task barrier to synchronize all xgmi reset works across the | |
3305 | * hive. task_barrier_enter and task_barrier_exit will block | |
3306 | * until all the threads running the xgmi reset works reach | |
3307 | * those points. task_barrier_full will do both blocks. | |
3308 | */ | |
3309 | if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { | |
3310 | ||
3311 | task_barrier_enter(&hive->tb); | |
4a580877 | 3312 | adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev)); |
c6a6e2db AG |
3313 | |
3314 | if (adev->asic_reset_res) | |
3315 | goto fail; | |
3316 | ||
3317 | task_barrier_exit(&hive->tb); | |
4a580877 | 3318 | adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev)); |
c6a6e2db AG |
3319 | |
3320 | if (adev->asic_reset_res) | |
3321 | goto fail; | |
43c4d576 | 3322 | |
8bc7b360 HZ |
3323 | if (adev->mmhub.ras_funcs && |
3324 | adev->mmhub.ras_funcs->reset_ras_error_count) | |
3325 | adev->mmhub.ras_funcs->reset_ras_error_count(adev); | |
c6a6e2db AG |
3326 | } else { |
3327 | ||
3328 | task_barrier_full(&hive->tb); | |
3329 | adev->asic_reset_res = amdgpu_asic_reset(adev); | |
3330 | } | |
ce316fa5 | 3331 | |
c6a6e2db | 3332 | fail: |
d4535e2c | 3333 | if (adev->asic_reset_res) |
fed184e9 | 3334 | DRM_WARN("ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 3335 | adev->asic_reset_res, adev_to_drm(adev)->unique); |
d95e8e97 | 3336 | amdgpu_put_xgmi_hive(hive); |
d4535e2c AG |
3337 | } |
3338 | ||
71f98027 AD |
3339 | static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) |
3340 | { | |
3341 | char *input = amdgpu_lockup_timeout; | |
3342 | char *timeout_setting = NULL; | |
3343 | int index = 0; | |
3344 | long timeout; | |
3345 | int ret = 0; | |
3346 | ||
3347 | /* | |
67387dfe AD |
3348 | * By default timeout for non compute jobs is 10000 |
3349 | * and 60000 for compute jobs. | |
71f98027 | 3350 | * In SR-IOV or passthrough mode, timeout for compute |
b7b2a316 | 3351 | * jobs are 60000 by default. |
71f98027 AD |
3352 | */ |
3353 | adev->gfx_timeout = msecs_to_jiffies(10000); | |
3354 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; | |
9882e278 ED |
3355 | if (amdgpu_sriov_vf(adev)) |
3356 | adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ? | |
3357 | msecs_to_jiffies(60000) : msecs_to_jiffies(10000); | |
71f98027 | 3358 | else |
67387dfe | 3359 | adev->compute_timeout = msecs_to_jiffies(60000); |
71f98027 | 3360 | |
f440ff44 | 3361 | if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 | 3362 | while ((timeout_setting = strsep(&input, ",")) && |
f440ff44 | 3363 | strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { |
71f98027 AD |
3364 | ret = kstrtol(timeout_setting, 0, &timeout); |
3365 | if (ret) | |
3366 | return ret; | |
3367 | ||
3368 | if (timeout == 0) { | |
3369 | index++; | |
3370 | continue; | |
3371 | } else if (timeout < 0) { | |
3372 | timeout = MAX_SCHEDULE_TIMEOUT; | |
3373 | } else { | |
3374 | timeout = msecs_to_jiffies(timeout); | |
3375 | } | |
3376 | ||
3377 | switch (index++) { | |
3378 | case 0: | |
3379 | adev->gfx_timeout = timeout; | |
3380 | break; | |
3381 | case 1: | |
3382 | adev->compute_timeout = timeout; | |
3383 | break; | |
3384 | case 2: | |
3385 | adev->sdma_timeout = timeout; | |
3386 | break; | |
3387 | case 3: | |
3388 | adev->video_timeout = timeout; | |
3389 | break; | |
3390 | default: | |
3391 | break; | |
3392 | } | |
3393 | } | |
3394 | /* | |
3395 | * There is only one value specified and | |
3396 | * it should apply to all non-compute jobs. | |
3397 | */ | |
bcccee89 | 3398 | if (index == 1) { |
71f98027 | 3399 | adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; |
bcccee89 ED |
3400 | if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) |
3401 | adev->compute_timeout = adev->gfx_timeout; | |
3402 | } | |
71f98027 AD |
3403 | } |
3404 | ||
3405 | return ret; | |
3406 | } | |
d4535e2c | 3407 | |
77f3a5cd ND |
3408 | static const struct attribute *amdgpu_dev_attributes[] = { |
3409 | &dev_attr_product_name.attr, | |
3410 | &dev_attr_product_number.attr, | |
3411 | &dev_attr_serial_number.attr, | |
3412 | &dev_attr_pcie_replay_count.attr, | |
3413 | NULL | |
3414 | }; | |
3415 | ||
d38ceaf9 AD |
3416 | /** |
3417 | * amdgpu_device_init - initialize the driver | |
3418 | * | |
3419 | * @adev: amdgpu_device pointer | |
d38ceaf9 AD |
3420 | * @flags: driver flags |
3421 | * | |
3422 | * Initializes the driver info and hw (all asics). | |
3423 | * Returns 0 for success or an error on failure. | |
3424 | * Called at driver startup. | |
3425 | */ | |
3426 | int amdgpu_device_init(struct amdgpu_device *adev, | |
d38ceaf9 AD |
3427 | uint32_t flags) |
3428 | { | |
8aba21b7 LT |
3429 | struct drm_device *ddev = adev_to_drm(adev); |
3430 | struct pci_dev *pdev = adev->pdev; | |
d38ceaf9 | 3431 | int r, i; |
b98c6299 | 3432 | bool px = false; |
95844d20 | 3433 | u32 max_MBps; |
d38ceaf9 AD |
3434 | |
3435 | adev->shutdown = false; | |
d38ceaf9 | 3436 | adev->flags = flags; |
4e66d7d2 YZ |
3437 | |
3438 | if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST) | |
3439 | adev->asic_type = amdgpu_force_asic_type; | |
3440 | else | |
3441 | adev->asic_type = flags & AMD_ASIC_MASK; | |
3442 | ||
d38ceaf9 | 3443 | adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; |
593aa2d2 | 3444 | if (amdgpu_emu_mode == 1) |
8bdab6bb | 3445 | adev->usec_timeout *= 10; |
770d13b1 | 3446 | adev->gmc.gart_size = 512 * 1024 * 1024; |
d38ceaf9 AD |
3447 | adev->accel_working = false; |
3448 | adev->num_rings = 0; | |
3449 | adev->mman.buffer_funcs = NULL; | |
3450 | adev->mman.buffer_funcs_ring = NULL; | |
3451 | adev->vm_manager.vm_pte_funcs = NULL; | |
0c88b430 | 3452 | adev->vm_manager.vm_pte_num_scheds = 0; |
132f34e4 | 3453 | adev->gmc.gmc_funcs = NULL; |
7bd939d0 | 3454 | adev->harvest_ip_mask = 0x0; |
f54d1867 | 3455 | adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); |
b8866c26 | 3456 | bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); |
d38ceaf9 AD |
3457 | |
3458 | adev->smc_rreg = &amdgpu_invalid_rreg; | |
3459 | adev->smc_wreg = &amdgpu_invalid_wreg; | |
3460 | adev->pcie_rreg = &amdgpu_invalid_rreg; | |
3461 | adev->pcie_wreg = &amdgpu_invalid_wreg; | |
36b9a952 HR |
3462 | adev->pciep_rreg = &amdgpu_invalid_rreg; |
3463 | adev->pciep_wreg = &amdgpu_invalid_wreg; | |
4fa1c6a6 TZ |
3464 | adev->pcie_rreg64 = &amdgpu_invalid_rreg64; |
3465 | adev->pcie_wreg64 = &amdgpu_invalid_wreg64; | |
d38ceaf9 AD |
3466 | adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; |
3467 | adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; | |
3468 | adev->didt_rreg = &amdgpu_invalid_rreg; | |
3469 | adev->didt_wreg = &amdgpu_invalid_wreg; | |
ccdbb20a RZ |
3470 | adev->gc_cac_rreg = &amdgpu_invalid_rreg; |
3471 | adev->gc_cac_wreg = &amdgpu_invalid_wreg; | |
d38ceaf9 AD |
3472 | adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; |
3473 | adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; | |
3474 | ||
3e39ab90 AD |
3475 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", |
3476 | amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, | |
3477 | pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); | |
d38ceaf9 AD |
3478 | |
3479 | /* mutex initialization are all done here so we | |
3480 | * can recall function without having locking issues */ | |
0e5ca0d1 | 3481 | mutex_init(&adev->firmware.mutex); |
d38ceaf9 AD |
3482 | mutex_init(&adev->pm.mutex); |
3483 | mutex_init(&adev->gfx.gpu_clock_mutex); | |
3484 | mutex_init(&adev->srbm_mutex); | |
b8866c26 | 3485 | mutex_init(&adev->gfx.pipe_reserve_mutex); |
d23ee13f | 3486 | mutex_init(&adev->gfx.gfx_off_mutex); |
d38ceaf9 | 3487 | mutex_init(&adev->grbm_idx_mutex); |
d38ceaf9 | 3488 | mutex_init(&adev->mn_lock); |
e23b74aa | 3489 | mutex_init(&adev->virt.vf_errors.lock); |
d38ceaf9 | 3490 | hash_init(adev->mn_hash); |
53b3f8f4 | 3491 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 3492 | init_rwsem(&adev->reset_sem); |
32eaeae0 | 3493 | mutex_init(&adev->psp.mutex); |
bd052211 | 3494 | mutex_init(&adev->notifier_lock); |
d38ceaf9 | 3495 | |
9f6a7857 HR |
3496 | r = amdgpu_device_init_apu_flags(adev); |
3497 | if (r) | |
3498 | return r; | |
3499 | ||
912dfc84 EQ |
3500 | r = amdgpu_device_check_arguments(adev); |
3501 | if (r) | |
3502 | return r; | |
d38ceaf9 | 3503 | |
d38ceaf9 AD |
3504 | spin_lock_init(&adev->mmio_idx_lock); |
3505 | spin_lock_init(&adev->smc_idx_lock); | |
3506 | spin_lock_init(&adev->pcie_idx_lock); | |
3507 | spin_lock_init(&adev->uvd_ctx_idx_lock); | |
3508 | spin_lock_init(&adev->didt_idx_lock); | |
ccdbb20a | 3509 | spin_lock_init(&adev->gc_cac_idx_lock); |
16abb5d2 | 3510 | spin_lock_init(&adev->se_cac_idx_lock); |
d38ceaf9 | 3511 | spin_lock_init(&adev->audio_endpt_idx_lock); |
95844d20 | 3512 | spin_lock_init(&adev->mm_stats.lock); |
d38ceaf9 | 3513 | |
0c4e7fa5 CZ |
3514 | INIT_LIST_HEAD(&adev->shadow_list); |
3515 | mutex_init(&adev->shadow_list_lock); | |
3516 | ||
655ce9cb | 3517 | INIT_LIST_HEAD(&adev->reset_list); |
3518 | ||
beff74bc AD |
3519 | INIT_DELAYED_WORK(&adev->delayed_init_work, |
3520 | amdgpu_device_delayed_init_work_handler); | |
1e317b99 RZ |
3521 | INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, |
3522 | amdgpu_device_delay_enable_gfx_off); | |
2dc80b00 | 3523 | |
d4535e2c AG |
3524 | INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); |
3525 | ||
d23ee13f | 3526 | adev->gfx.gfx_off_req_count = 1; |
b6e79d9a | 3527 | adev->pm.ac_power = power_supply_is_system_supplied() > 0; |
b1ddf548 | 3528 | |
b265bdbd EQ |
3529 | atomic_set(&adev->throttling_logging_enabled, 1); |
3530 | /* | |
3531 | * If throttling continues, logging will be performed every minute | |
3532 | * to avoid log flooding. "-1" is subtracted since the thermal | |
3533 | * throttling interrupt comes every second. Thus, the total logging | |
3534 | * interval is 59 seconds(retelimited printk interval) + 1(waiting | |
3535 | * for throttling interrupt) = 60 seconds. | |
3536 | */ | |
3537 | ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); | |
3538 | ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); | |
3539 | ||
0fa49558 AX |
3540 | /* Registers mapping */ |
3541 | /* TODO: block userspace mapping of io register */ | |
da69c161 KW |
3542 | if (adev->asic_type >= CHIP_BONAIRE) { |
3543 | adev->rmmio_base = pci_resource_start(adev->pdev, 5); | |
3544 | adev->rmmio_size = pci_resource_len(adev->pdev, 5); | |
3545 | } else { | |
3546 | adev->rmmio_base = pci_resource_start(adev->pdev, 2); | |
3547 | adev->rmmio_size = pci_resource_len(adev->pdev, 2); | |
3548 | } | |
d38ceaf9 | 3549 | |
ce4a5488 EQ |
3550 | for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++) |
3551 | atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN); | |
3552 | ||
d38ceaf9 AD |
3553 | adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); |
3554 | if (adev->rmmio == NULL) { | |
3555 | return -ENOMEM; | |
3556 | } | |
3557 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); | |
3558 | DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size); | |
3559 | ||
b2109d8e JX |
3560 | /* enable PCIE atomic ops */ |
3561 | r = pci_enable_atomic_ops_to_root(adev->pdev, | |
3562 | PCI_EXP_DEVCAP2_ATOMIC_COMP32 | | |
3563 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); | |
3564 | if (r) { | |
3565 | adev->have_atomics_support = false; | |
3566 | DRM_INFO("PCIE atomic ops is not supported\n"); | |
3567 | } else { | |
3568 | adev->have_atomics_support = true; | |
3569 | } | |
3570 | ||
5494d864 AD |
3571 | amdgpu_device_get_pcie_info(adev); |
3572 | ||
b239c017 JX |
3573 | if (amdgpu_mcbp) |
3574 | DRM_INFO("MCBP is enabled\n"); | |
3575 | ||
5f84cc63 JX |
3576 | if (amdgpu_mes && adev->asic_type >= CHIP_NAVI10) |
3577 | adev->enable_mes = true; | |
3578 | ||
3aa0115d ML |
3579 | /* detect hw virtualization here */ |
3580 | amdgpu_detect_virtualization(adev); | |
3581 | ||
dffa11b4 ML |
3582 | r = amdgpu_device_get_job_timeout_settings(adev); |
3583 | if (r) { | |
3584 | dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n"); | |
4ef87d8f | 3585 | return r; |
a190d1c7 XY |
3586 | } |
3587 | ||
d38ceaf9 | 3588 | /* early init functions */ |
06ec9070 | 3589 | r = amdgpu_device_ip_early_init(adev); |
d38ceaf9 | 3590 | if (r) |
4ef87d8f | 3591 | return r; |
d38ceaf9 | 3592 | |
6585661d OZ |
3593 | /* doorbell bar mapping and doorbell index init*/ |
3594 | amdgpu_device_doorbell_init(adev); | |
3595 | ||
9475a943 SL |
3596 | if (amdgpu_emu_mode == 1) { |
3597 | /* post the asic on emulation mode */ | |
3598 | emu_soc_asic_init(adev); | |
bfca0289 | 3599 | goto fence_driver_init; |
9475a943 | 3600 | } |
bfca0289 | 3601 | |
04442bf7 LL |
3602 | amdgpu_reset_init(adev); |
3603 | ||
4e99a44e ML |
3604 | /* detect if we are with an SRIOV vbios */ |
3605 | amdgpu_device_detect_sriov_bios(adev); | |
048765ad | 3606 | |
95e8e59e AD |
3607 | /* check if we need to reset the asic |
3608 | * E.g., driver was not cleanly unloaded previously, etc. | |
3609 | */ | |
f14899fd | 3610 | if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { |
e3c1b071 | 3611 | if (adev->gmc.xgmi.num_physical_nodes) { |
3612 | dev_info(adev->dev, "Pending hive reset.\n"); | |
3613 | adev->gmc.xgmi.pending_reset = true; | |
3614 | /* Only need to init necessary block for SMU to handle the reset */ | |
3615 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
3616 | if (!adev->ip_blocks[i].status.valid) | |
3617 | continue; | |
3618 | if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || | |
3619 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || | |
3620 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || | |
3621 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) { | |
751f43e7 | 3622 | DRM_DEBUG("IP %s disabled for hw_init.\n", |
e3c1b071 | 3623 | adev->ip_blocks[i].version->funcs->name); |
3624 | adev->ip_blocks[i].status.hw = true; | |
3625 | } | |
3626 | } | |
3627 | } else { | |
3628 | r = amdgpu_asic_reset(adev); | |
3629 | if (r) { | |
3630 | dev_err(adev->dev, "asic reset on init failed\n"); | |
3631 | goto failed; | |
3632 | } | |
95e8e59e AD |
3633 | } |
3634 | } | |
3635 | ||
8f66090b | 3636 | pci_enable_pcie_error_reporting(adev->pdev); |
c9a6b82f | 3637 | |
d38ceaf9 | 3638 | /* Post card if necessary */ |
39c640c0 | 3639 | if (amdgpu_device_need_post(adev)) { |
d38ceaf9 | 3640 | if (!adev->bios) { |
bec86378 | 3641 | dev_err(adev->dev, "no vBIOS found\n"); |
83ba126a AD |
3642 | r = -EINVAL; |
3643 | goto failed; | |
d38ceaf9 | 3644 | } |
bec86378 | 3645 | DRM_INFO("GPU posting now...\n"); |
4d2997ab | 3646 | r = amdgpu_device_asic_init(adev); |
4e99a44e ML |
3647 | if (r) { |
3648 | dev_err(adev->dev, "gpu post error!\n"); | |
3649 | goto failed; | |
3650 | } | |
d38ceaf9 AD |
3651 | } |
3652 | ||
88b64e95 AD |
3653 | if (adev->is_atom_fw) { |
3654 | /* Initialize clocks */ | |
3655 | r = amdgpu_atomfirmware_get_clock_info(adev); | |
3656 | if (r) { | |
3657 | dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n"); | |
e23b74aa | 3658 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
88b64e95 AD |
3659 | goto failed; |
3660 | } | |
3661 | } else { | |
a5bde2f9 AD |
3662 | /* Initialize clocks */ |
3663 | r = amdgpu_atombios_get_clock_info(adev); | |
3664 | if (r) { | |
3665 | dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n"); | |
e23b74aa | 3666 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0); |
89041940 | 3667 | goto failed; |
a5bde2f9 AD |
3668 | } |
3669 | /* init i2c buses */ | |
4562236b HW |
3670 | if (!amdgpu_device_has_dc_support(adev)) |
3671 | amdgpu_atombios_i2c_init(adev); | |
2c1a2784 | 3672 | } |
d38ceaf9 | 3673 | |
bfca0289 | 3674 | fence_driver_init: |
d38ceaf9 | 3675 | /* Fence driver */ |
067f44c8 | 3676 | r = amdgpu_fence_driver_sw_init(adev); |
2c1a2784 | 3677 | if (r) { |
067f44c8 | 3678 | dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n"); |
e23b74aa | 3679 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0); |
83ba126a | 3680 | goto failed; |
2c1a2784 | 3681 | } |
d38ceaf9 AD |
3682 | |
3683 | /* init the mode config */ | |
4a580877 | 3684 | drm_mode_config_init(adev_to_drm(adev)); |
d38ceaf9 | 3685 | |
06ec9070 | 3686 | r = amdgpu_device_ip_init(adev); |
d38ceaf9 | 3687 | if (r) { |
8840a387 | 3688 | /* failed in exclusive mode due to timeout */ |
3689 | if (amdgpu_sriov_vf(adev) && | |
3690 | !amdgpu_sriov_runtime(adev) && | |
3691 | amdgpu_virt_mmio_blocked(adev) && | |
3692 | !amdgpu_virt_wait_reset(adev)) { | |
3693 | dev_err(adev->dev, "VF exclusive mode timeout\n"); | |
1daee8b4 PD |
3694 | /* Don't send request since VF is inactive. */ |
3695 | adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; | |
3696 | adev->virt.ops = NULL; | |
8840a387 | 3697 | r = -EAGAIN; |
970fd197 | 3698 | goto release_ras_con; |
8840a387 | 3699 | } |
06ec9070 | 3700 | dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); |
e23b74aa | 3701 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); |
970fd197 | 3702 | goto release_ras_con; |
d38ceaf9 AD |
3703 | } |
3704 | ||
8d35a259 LG |
3705 | amdgpu_fence_driver_hw_init(adev); |
3706 | ||
d69b8971 YZ |
3707 | dev_info(adev->dev, |
3708 | "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n", | |
d7f72fe4 YZ |
3709 | adev->gfx.config.max_shader_engines, |
3710 | adev->gfx.config.max_sh_per_se, | |
3711 | adev->gfx.config.max_cu_per_sh, | |
3712 | adev->gfx.cu_info.number); | |
3713 | ||
d38ceaf9 AD |
3714 | adev->accel_working = true; |
3715 | ||
e59c0205 AX |
3716 | amdgpu_vm_check_compute_bug(adev); |
3717 | ||
95844d20 MO |
3718 | /* Initialize the buffer migration limit. */ |
3719 | if (amdgpu_moverate >= 0) | |
3720 | max_MBps = amdgpu_moverate; | |
3721 | else | |
3722 | max_MBps = 8; /* Allow 8 MB/s. */ | |
3723 | /* Get a log2 for easy divisions. */ | |
3724 | adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); | |
3725 | ||
9bc92b9c ML |
3726 | amdgpu_fbdev_init(adev); |
3727 | ||
d2f52ac8 | 3728 | r = amdgpu_pm_sysfs_init(adev); |
7c868b59 YT |
3729 | if (r) { |
3730 | adev->pm_sysfs_en = false; | |
d2f52ac8 | 3731 | DRM_ERROR("registering pm debugfs failed (%d).\n", r); |
7c868b59 YT |
3732 | } else |
3733 | adev->pm_sysfs_en = true; | |
d2f52ac8 | 3734 | |
5bb23532 | 3735 | r = amdgpu_ucode_sysfs_init(adev); |
7c868b59 YT |
3736 | if (r) { |
3737 | adev->ucode_sysfs_en = false; | |
5bb23532 | 3738 | DRM_ERROR("Creating firmware sysfs failed (%d).\n", r); |
7c868b59 YT |
3739 | } else |
3740 | adev->ucode_sysfs_en = true; | |
5bb23532 | 3741 | |
d38ceaf9 AD |
3742 | if ((amdgpu_testing & 1)) { |
3743 | if (adev->accel_working) | |
3744 | amdgpu_test_moves(adev); | |
3745 | else | |
3746 | DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n"); | |
3747 | } | |
d38ceaf9 AD |
3748 | if (amdgpu_benchmarking) { |
3749 | if (adev->accel_working) | |
3750 | amdgpu_benchmark(adev, amdgpu_benchmarking); | |
3751 | else | |
3752 | DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n"); | |
3753 | } | |
3754 | ||
b0adca4d EQ |
3755 | /* |
3756 | * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. | |
3757 | * Otherwise the mgpu fan boost feature will be skipped due to the | |
3758 | * gpu instance is counted less. | |
3759 | */ | |
3760 | amdgpu_register_gpu_instance(adev); | |
3761 | ||
d38ceaf9 AD |
3762 | /* enable clockgating, etc. after ib tests, etc. since some blocks require |
3763 | * explicit gating rather than handling it automatically. | |
3764 | */ | |
e3c1b071 | 3765 | if (!adev->gmc.xgmi.pending_reset) { |
3766 | r = amdgpu_device_ip_late_init(adev); | |
3767 | if (r) { | |
3768 | dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); | |
3769 | amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r); | |
970fd197 | 3770 | goto release_ras_con; |
e3c1b071 | 3771 | } |
3772 | /* must succeed. */ | |
3773 | amdgpu_ras_resume(adev); | |
3774 | queue_delayed_work(system_wq, &adev->delayed_init_work, | |
3775 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
2c1a2784 | 3776 | } |
d38ceaf9 | 3777 | |
2c738637 ML |
3778 | if (amdgpu_sriov_vf(adev)) |
3779 | flush_delayed_work(&adev->delayed_init_work); | |
3780 | ||
77f3a5cd | 3781 | r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); |
5aea5327 | 3782 | if (r) |
77f3a5cd | 3783 | dev_err(adev->dev, "Could not create amdgpu device attr\n"); |
bd607166 | 3784 | |
d155bef0 AB |
3785 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3786 | r = amdgpu_pmu_init(adev); | |
9c7c85f7 JK |
3787 | if (r) |
3788 | dev_err(adev->dev, "amdgpu_pmu_init failed\n"); | |
3789 | ||
c1dd4aa6 AG |
3790 | /* Have stored pci confspace at hand for restore in sudden PCI error */ |
3791 | if (amdgpu_device_cache_pci_state(adev->pdev)) | |
3792 | pci_restore_state(pdev); | |
3793 | ||
8c3dd61c KHF |
3794 | /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */ |
3795 | /* this will fail for cards that aren't VGA class devices, just | |
3796 | * ignore it */ | |
3797 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) | |
bf44e8ce | 3798 | vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); |
8c3dd61c KHF |
3799 | |
3800 | if (amdgpu_device_supports_px(ddev)) { | |
3801 | px = true; | |
3802 | vga_switcheroo_register_client(adev->pdev, | |
3803 | &amdgpu_switcheroo_ops, px); | |
3804 | vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); | |
3805 | } | |
3806 | ||
e3c1b071 | 3807 | if (adev->gmc.xgmi.pending_reset) |
3808 | queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, | |
3809 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
3810 | ||
d38ceaf9 | 3811 | return 0; |
83ba126a | 3812 | |
970fd197 SY |
3813 | release_ras_con: |
3814 | amdgpu_release_ras_context(adev); | |
3815 | ||
83ba126a | 3816 | failed: |
89041940 | 3817 | amdgpu_vf_error_trans_all(adev); |
8840a387 | 3818 | |
83ba126a | 3819 | return r; |
d38ceaf9 AD |
3820 | } |
3821 | ||
07775fc1 AG |
3822 | static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) |
3823 | { | |
3824 | /* Clear all CPU mappings pointing to this device */ | |
3825 | unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); | |
3826 | ||
3827 | /* Unmap all mapped bars - Doorbell, registers and VRAM */ | |
3828 | amdgpu_device_doorbell_fini(adev); | |
3829 | ||
3830 | iounmap(adev->rmmio); | |
3831 | adev->rmmio = NULL; | |
3832 | if (adev->mman.aper_base_kaddr) | |
3833 | iounmap(adev->mman.aper_base_kaddr); | |
3834 | adev->mman.aper_base_kaddr = NULL; | |
3835 | ||
3836 | /* Memory manager related */ | |
3837 | if (!adev->gmc.xgmi.connected_to_cpu) { | |
3838 | arch_phys_wc_del(adev->gmc.vram_mtrr); | |
3839 | arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); | |
3840 | } | |
3841 | } | |
3842 | ||
d38ceaf9 AD |
3843 | /** |
3844 | * amdgpu_device_fini - tear down the driver | |
3845 | * | |
3846 | * @adev: amdgpu_device pointer | |
3847 | * | |
3848 | * Tear down the driver info (all asics). | |
3849 | * Called at driver shutdown. | |
3850 | */ | |
72c8c97b | 3851 | void amdgpu_device_fini_hw(struct amdgpu_device *adev) |
d38ceaf9 | 3852 | { |
aac89168 | 3853 | dev_info(adev->dev, "amdgpu: finishing device.\n"); |
9f875167 | 3854 | flush_delayed_work(&adev->delayed_init_work); |
691191a2 YW |
3855 | if (adev->mman.initialized) { |
3856 | flush_delayed_work(&adev->mman.bdev.wq); | |
e78b3197 | 3857 | ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); |
691191a2 | 3858 | } |
d0d13fe8 | 3859 | adev->shutdown = true; |
9f875167 | 3860 | |
752c683d ML |
3861 | /* make sure IB test finished before entering exclusive mode |
3862 | * to avoid preemption on IB test | |
3863 | * */ | |
519b8b76 | 3864 | if (amdgpu_sriov_vf(adev)) { |
752c683d | 3865 | amdgpu_virt_request_full_gpu(adev, false); |
519b8b76 BZ |
3866 | amdgpu_virt_fini_data_exchange(adev); |
3867 | } | |
752c683d | 3868 | |
e5b03032 ML |
3869 | /* disable all interrupts */ |
3870 | amdgpu_irq_disable_all(adev); | |
ff97cba8 | 3871 | if (adev->mode_info.mode_config_initialized){ |
fa6bf28f | 3872 | if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) |
4a580877 | 3873 | drm_helper_force_disable_all(adev_to_drm(adev)); |
ff97cba8 | 3874 | else |
4a580877 | 3875 | drm_atomic_helper_shutdown(adev_to_drm(adev)); |
ff97cba8 | 3876 | } |
8d35a259 | 3877 | amdgpu_fence_driver_hw_fini(adev); |
72c8c97b | 3878 | |
7c868b59 YT |
3879 | if (adev->pm_sysfs_en) |
3880 | amdgpu_pm_sysfs_fini(adev); | |
72c8c97b AG |
3881 | if (adev->ucode_sysfs_en) |
3882 | amdgpu_ucode_sysfs_fini(adev); | |
3883 | sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes); | |
3884 | ||
d38ceaf9 | 3885 | amdgpu_fbdev_fini(adev); |
72c8c97b AG |
3886 | |
3887 | amdgpu_irq_fini_hw(adev); | |
e9669fb7 AG |
3888 | |
3889 | amdgpu_device_ip_fini_early(adev); | |
d10d0daa AG |
3890 | |
3891 | amdgpu_gart_dummy_page_fini(adev); | |
07775fc1 AG |
3892 | |
3893 | amdgpu_device_unmap_mmio(adev); | |
72c8c97b AG |
3894 | } |
3895 | ||
3896 | void amdgpu_device_fini_sw(struct amdgpu_device *adev) | |
3897 | { | |
8d35a259 | 3898 | amdgpu_fence_driver_sw_fini(adev); |
430d456a | 3899 | amdgpu_device_ip_fini(adev); |
75e1658e ND |
3900 | release_firmware(adev->firmware.gpu_info_fw); |
3901 | adev->firmware.gpu_info_fw = NULL; | |
d38ceaf9 | 3902 | adev->accel_working = false; |
04442bf7 LL |
3903 | |
3904 | amdgpu_reset_fini(adev); | |
3905 | ||
d38ceaf9 | 3906 | /* free i2c buses */ |
4562236b HW |
3907 | if (!amdgpu_device_has_dc_support(adev)) |
3908 | amdgpu_i2c_fini(adev); | |
bfca0289 SL |
3909 | |
3910 | if (amdgpu_emu_mode != 1) | |
3911 | amdgpu_atombios_fini(adev); | |
3912 | ||
d38ceaf9 AD |
3913 | kfree(adev->bios); |
3914 | adev->bios = NULL; | |
b98c6299 | 3915 | if (amdgpu_device_supports_px(adev_to_drm(adev))) { |
84c8b22e | 3916 | vga_switcheroo_unregister_client(adev->pdev); |
83ba126a | 3917 | vga_switcheroo_fini_domain_pm_ops(adev->dev); |
b98c6299 | 3918 | } |
38d6be81 | 3919 | if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) |
b8779475 | 3920 | vga_client_unregister(adev->pdev); |
e9bc1bf7 | 3921 | |
d155bef0 AB |
3922 | if (IS_ENABLED(CONFIG_PERF_EVENTS)) |
3923 | amdgpu_pmu_fini(adev); | |
72de33f8 | 3924 | if (adev->mman.discovery_bin) |
a190d1c7 | 3925 | amdgpu_discovery_fini(adev); |
72c8c97b AG |
3926 | |
3927 | kfree(adev->pci_state); | |
3928 | ||
d38ceaf9 AD |
3929 | } |
3930 | ||
3931 | ||
3932 | /* | |
3933 | * Suspend & resume. | |
3934 | */ | |
3935 | /** | |
810ddc3a | 3936 | * amdgpu_device_suspend - initiate device suspend |
d38ceaf9 | 3937 | * |
87e3f136 | 3938 | * @dev: drm dev pointer |
87e3f136 | 3939 | * @fbcon : notify the fbdev of suspend |
d38ceaf9 AD |
3940 | * |
3941 | * Puts the hw in the suspend state (all asics). | |
3942 | * Returns 0 for success or an error on failure. | |
3943 | * Called at driver suspend. | |
3944 | */ | |
de185019 | 3945 | int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 3946 | { |
a2e15b0e | 3947 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 3948 | |
d38ceaf9 AD |
3949 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
3950 | return 0; | |
3951 | ||
44779b43 | 3952 | adev->in_suspend = true; |
3fa8f89d S |
3953 | |
3954 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3)) | |
3955 | DRM_WARN("smart shift update failed\n"); | |
3956 | ||
d38ceaf9 AD |
3957 | drm_kms_helper_poll_disable(dev); |
3958 | ||
5f818173 S |
3959 | if (fbcon) |
3960 | amdgpu_fbdev_set_suspend(adev, 1); | |
3961 | ||
beff74bc | 3962 | cancel_delayed_work_sync(&adev->delayed_init_work); |
a5459475 | 3963 | |
5e6932fe | 3964 | amdgpu_ras_suspend(adev); |
3965 | ||
2196927b | 3966 | amdgpu_device_ip_suspend_phase1(adev); |
fe1053b7 | 3967 | |
5d3a2d95 AD |
3968 | if (!adev->in_s0ix) |
3969 | amdgpu_amdkfd_suspend(adev, adev->in_runpm); | |
94fa5660 | 3970 | |
d38ceaf9 AD |
3971 | /* evict vram memory */ |
3972 | amdgpu_bo_evict_vram(adev); | |
3973 | ||
8d35a259 | 3974 | amdgpu_fence_driver_hw_fini(adev); |
d38ceaf9 | 3975 | |
2196927b | 3976 | amdgpu_device_ip_suspend_phase2(adev); |
a0a71e49 AD |
3977 | /* evict remaining vram memory |
3978 | * This second call to evict vram is to evict the gart page table | |
3979 | * using the CPU. | |
3980 | */ | |
d38ceaf9 AD |
3981 | amdgpu_bo_evict_vram(adev); |
3982 | ||
d38ceaf9 AD |
3983 | return 0; |
3984 | } | |
3985 | ||
3986 | /** | |
810ddc3a | 3987 | * amdgpu_device_resume - initiate device resume |
d38ceaf9 | 3988 | * |
87e3f136 | 3989 | * @dev: drm dev pointer |
87e3f136 | 3990 | * @fbcon : notify the fbdev of resume |
d38ceaf9 AD |
3991 | * |
3992 | * Bring the hw back to operating state (all asics). | |
3993 | * Returns 0 for success or an error on failure. | |
3994 | * Called at driver resume. | |
3995 | */ | |
de185019 | 3996 | int amdgpu_device_resume(struct drm_device *dev, bool fbcon) |
d38ceaf9 | 3997 | { |
1348969a | 3998 | struct amdgpu_device *adev = drm_to_adev(dev); |
03161a6e | 3999 | int r = 0; |
d38ceaf9 AD |
4000 | |
4001 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
4002 | return 0; | |
4003 | ||
62498733 | 4004 | if (adev->in_s0ix) |
628c36d7 PL |
4005 | amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry); |
4006 | ||
d38ceaf9 | 4007 | /* post card */ |
39c640c0 | 4008 | if (amdgpu_device_need_post(adev)) { |
4d2997ab | 4009 | r = amdgpu_device_asic_init(adev); |
74b0b157 | 4010 | if (r) |
aac89168 | 4011 | dev_err(adev->dev, "amdgpu asic init failed\n"); |
74b0b157 | 4012 | } |
d38ceaf9 | 4013 | |
06ec9070 | 4014 | r = amdgpu_device_ip_resume(adev); |
e6707218 | 4015 | if (r) { |
aac89168 | 4016 | dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); |
4d3b9ae5 | 4017 | return r; |
e6707218 | 4018 | } |
8d35a259 | 4019 | amdgpu_fence_driver_hw_init(adev); |
5ceb54c6 | 4020 | |
06ec9070 | 4021 | r = amdgpu_device_ip_late_init(adev); |
03161a6e | 4022 | if (r) |
4d3b9ae5 | 4023 | return r; |
d38ceaf9 | 4024 | |
beff74bc AD |
4025 | queue_delayed_work(system_wq, &adev->delayed_init_work, |
4026 | msecs_to_jiffies(AMDGPU_RESUME_MS)); | |
4027 | ||
5d3a2d95 AD |
4028 | if (!adev->in_s0ix) { |
4029 | r = amdgpu_amdkfd_resume(adev, adev->in_runpm); | |
4030 | if (r) | |
4031 | return r; | |
4032 | } | |
756e6880 | 4033 | |
96a5d8d4 | 4034 | /* Make sure IB tests flushed */ |
beff74bc | 4035 | flush_delayed_work(&adev->delayed_init_work); |
96a5d8d4 | 4036 | |
a2e15b0e | 4037 | if (fbcon) |
4d3b9ae5 | 4038 | amdgpu_fbdev_set_suspend(adev, 0); |
d38ceaf9 AD |
4039 | |
4040 | drm_kms_helper_poll_enable(dev); | |
23a1a9e5 | 4041 | |
5e6932fe | 4042 | amdgpu_ras_resume(adev); |
4043 | ||
23a1a9e5 L |
4044 | /* |
4045 | * Most of the connector probing functions try to acquire runtime pm | |
4046 | * refs to ensure that the GPU is powered on when connector polling is | |
4047 | * performed. Since we're calling this from a runtime PM callback, | |
4048 | * trying to acquire rpm refs will cause us to deadlock. | |
4049 | * | |
4050 | * Since we're guaranteed to be holding the rpm lock, it's safe to | |
4051 | * temporarily disable the rpm helpers so this doesn't deadlock us. | |
4052 | */ | |
4053 | #ifdef CONFIG_PM | |
4054 | dev->dev->power.disable_depth++; | |
4055 | #endif | |
4562236b HW |
4056 | if (!amdgpu_device_has_dc_support(adev)) |
4057 | drm_helper_hpd_irq_event(dev); | |
4058 | else | |
4059 | drm_kms_helper_hotplug_event(dev); | |
23a1a9e5 L |
4060 | #ifdef CONFIG_PM |
4061 | dev->dev->power.disable_depth--; | |
4062 | #endif | |
44779b43 RZ |
4063 | adev->in_suspend = false; |
4064 | ||
3fa8f89d S |
4065 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0)) |
4066 | DRM_WARN("smart shift update failed\n"); | |
4067 | ||
4d3b9ae5 | 4068 | return 0; |
d38ceaf9 AD |
4069 | } |
4070 | ||
e3ecdffa AD |
4071 | /** |
4072 | * amdgpu_device_ip_check_soft_reset - did soft reset succeed | |
4073 | * | |
4074 | * @adev: amdgpu_device pointer | |
4075 | * | |
4076 | * The list of all the hardware IPs that make up the asic is walked and | |
4077 | * the check_soft_reset callbacks are run. check_soft_reset determines | |
4078 | * if the asic is still hung or not. | |
4079 | * Returns true if any of the IPs are still in a hung state, false if not. | |
4080 | */ | |
06ec9070 | 4081 | static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) |
63fbf42f CZ |
4082 | { |
4083 | int i; | |
4084 | bool asic_hang = false; | |
4085 | ||
f993d628 ML |
4086 | if (amdgpu_sriov_vf(adev)) |
4087 | return true; | |
4088 | ||
8bc04c29 AD |
4089 | if (amdgpu_asic_need_full_reset(adev)) |
4090 | return true; | |
4091 | ||
63fbf42f | 4092 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4093 | if (!adev->ip_blocks[i].status.valid) |
63fbf42f | 4094 | continue; |
a1255107 AD |
4095 | if (adev->ip_blocks[i].version->funcs->check_soft_reset) |
4096 | adev->ip_blocks[i].status.hang = | |
4097 | adev->ip_blocks[i].version->funcs->check_soft_reset(adev); | |
4098 | if (adev->ip_blocks[i].status.hang) { | |
aac89168 | 4099 | dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); |
63fbf42f CZ |
4100 | asic_hang = true; |
4101 | } | |
4102 | } | |
4103 | return asic_hang; | |
4104 | } | |
4105 | ||
e3ecdffa AD |
4106 | /** |
4107 | * amdgpu_device_ip_pre_soft_reset - prepare for soft reset | |
4108 | * | |
4109 | * @adev: amdgpu_device pointer | |
4110 | * | |
4111 | * The list of all the hardware IPs that make up the asic is walked and the | |
4112 | * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset | |
4113 | * handles any IP specific hardware or software state changes that are | |
4114 | * necessary for a soft reset to succeed. | |
4115 | * Returns 0 on success, negative error code on failure. | |
4116 | */ | |
06ec9070 | 4117 | static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) |
d31a501e CZ |
4118 | { |
4119 | int i, r = 0; | |
4120 | ||
4121 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4122 | if (!adev->ip_blocks[i].status.valid) |
d31a501e | 4123 | continue; |
a1255107 AD |
4124 | if (adev->ip_blocks[i].status.hang && |
4125 | adev->ip_blocks[i].version->funcs->pre_soft_reset) { | |
4126 | r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); | |
d31a501e CZ |
4127 | if (r) |
4128 | return r; | |
4129 | } | |
4130 | } | |
4131 | ||
4132 | return 0; | |
4133 | } | |
4134 | ||
e3ecdffa AD |
4135 | /** |
4136 | * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed | |
4137 | * | |
4138 | * @adev: amdgpu_device pointer | |
4139 | * | |
4140 | * Some hardware IPs cannot be soft reset. If they are hung, a full gpu | |
4141 | * reset is necessary to recover. | |
4142 | * Returns true if a full asic reset is required, false if not. | |
4143 | */ | |
06ec9070 | 4144 | static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev) |
35d782fe | 4145 | { |
da146d3b AD |
4146 | int i; |
4147 | ||
8bc04c29 AD |
4148 | if (amdgpu_asic_need_full_reset(adev)) |
4149 | return true; | |
4150 | ||
da146d3b | 4151 | for (i = 0; i < adev->num_ip_blocks; i++) { |
a1255107 | 4152 | if (!adev->ip_blocks[i].status.valid) |
da146d3b | 4153 | continue; |
a1255107 AD |
4154 | if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) || |
4155 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) || | |
4156 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) || | |
98512bb8 KW |
4157 | (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) || |
4158 | adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) { | |
a1255107 | 4159 | if (adev->ip_blocks[i].status.hang) { |
aac89168 | 4160 | dev_info(adev->dev, "Some block need full reset!\n"); |
da146d3b AD |
4161 | return true; |
4162 | } | |
4163 | } | |
35d782fe CZ |
4164 | } |
4165 | return false; | |
4166 | } | |
4167 | ||
e3ecdffa AD |
4168 | /** |
4169 | * amdgpu_device_ip_soft_reset - do a soft reset | |
4170 | * | |
4171 | * @adev: amdgpu_device pointer | |
4172 | * | |
4173 | * The list of all the hardware IPs that make up the asic is walked and the | |
4174 | * soft_reset callbacks are run if the block is hung. soft_reset handles any | |
4175 | * IP specific hardware or software state changes that are necessary to soft | |
4176 | * reset the IP. | |
4177 | * Returns 0 on success, negative error code on failure. | |
4178 | */ | |
06ec9070 | 4179 | static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4180 | { |
4181 | int i, r = 0; | |
4182 | ||
4183 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4184 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4185 | continue; |
a1255107 AD |
4186 | if (adev->ip_blocks[i].status.hang && |
4187 | adev->ip_blocks[i].version->funcs->soft_reset) { | |
4188 | r = adev->ip_blocks[i].version->funcs->soft_reset(adev); | |
35d782fe CZ |
4189 | if (r) |
4190 | return r; | |
4191 | } | |
4192 | } | |
4193 | ||
4194 | return 0; | |
4195 | } | |
4196 | ||
e3ecdffa AD |
4197 | /** |
4198 | * amdgpu_device_ip_post_soft_reset - clean up from soft reset | |
4199 | * | |
4200 | * @adev: amdgpu_device pointer | |
4201 | * | |
4202 | * The list of all the hardware IPs that make up the asic is walked and the | |
4203 | * post_soft_reset callbacks are run if the asic was hung. post_soft_reset | |
4204 | * handles any IP specific hardware or software state changes that are | |
4205 | * necessary after the IP has been soft reset. | |
4206 | * Returns 0 on success, negative error code on failure. | |
4207 | */ | |
06ec9070 | 4208 | static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) |
35d782fe CZ |
4209 | { |
4210 | int i, r = 0; | |
4211 | ||
4212 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
a1255107 | 4213 | if (!adev->ip_blocks[i].status.valid) |
35d782fe | 4214 | continue; |
a1255107 AD |
4215 | if (adev->ip_blocks[i].status.hang && |
4216 | adev->ip_blocks[i].version->funcs->post_soft_reset) | |
4217 | r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); | |
35d782fe CZ |
4218 | if (r) |
4219 | return r; | |
4220 | } | |
4221 | ||
4222 | return 0; | |
4223 | } | |
4224 | ||
e3ecdffa | 4225 | /** |
c33adbc7 | 4226 | * amdgpu_device_recover_vram - Recover some VRAM contents |
e3ecdffa AD |
4227 | * |
4228 | * @adev: amdgpu_device pointer | |
4229 | * | |
4230 | * Restores the contents of VRAM buffers from the shadows in GTT. Used to | |
4231 | * restore things like GPUVM page tables after a GPU reset where | |
4232 | * the contents of VRAM might be lost. | |
403009bf CK |
4233 | * |
4234 | * Returns: | |
4235 | * 0 on success, negative error code on failure. | |
e3ecdffa | 4236 | */ |
c33adbc7 | 4237 | static int amdgpu_device_recover_vram(struct amdgpu_device *adev) |
c41d1cf6 | 4238 | { |
c41d1cf6 | 4239 | struct dma_fence *fence = NULL, *next = NULL; |
403009bf | 4240 | struct amdgpu_bo *shadow; |
e18aaea7 | 4241 | struct amdgpu_bo_vm *vmbo; |
403009bf | 4242 | long r = 1, tmo; |
c41d1cf6 ML |
4243 | |
4244 | if (amdgpu_sriov_runtime(adev)) | |
b045d3af | 4245 | tmo = msecs_to_jiffies(8000); |
c41d1cf6 ML |
4246 | else |
4247 | tmo = msecs_to_jiffies(100); | |
4248 | ||
aac89168 | 4249 | dev_info(adev->dev, "recover vram bo from shadow start\n"); |
c41d1cf6 | 4250 | mutex_lock(&adev->shadow_list_lock); |
e18aaea7 ND |
4251 | list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { |
4252 | shadow = &vmbo->bo; | |
403009bf | 4253 | /* No need to recover an evicted BO */ |
d3116756 CK |
4254 | if (shadow->tbo.resource->mem_type != TTM_PL_TT || |
4255 | shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || | |
4256 | shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM) | |
403009bf CK |
4257 | continue; |
4258 | ||
4259 | r = amdgpu_bo_restore_shadow(shadow, &next); | |
4260 | if (r) | |
4261 | break; | |
4262 | ||
c41d1cf6 | 4263 | if (fence) { |
1712fb1a | 4264 | tmo = dma_fence_wait_timeout(fence, false, tmo); |
403009bf CK |
4265 | dma_fence_put(fence); |
4266 | fence = next; | |
1712fb1a | 4267 | if (tmo == 0) { |
4268 | r = -ETIMEDOUT; | |
c41d1cf6 | 4269 | break; |
1712fb1a | 4270 | } else if (tmo < 0) { |
4271 | r = tmo; | |
4272 | break; | |
4273 | } | |
403009bf CK |
4274 | } else { |
4275 | fence = next; | |
c41d1cf6 | 4276 | } |
c41d1cf6 ML |
4277 | } |
4278 | mutex_unlock(&adev->shadow_list_lock); | |
4279 | ||
403009bf CK |
4280 | if (fence) |
4281 | tmo = dma_fence_wait_timeout(fence, false, tmo); | |
c41d1cf6 ML |
4282 | dma_fence_put(fence); |
4283 | ||
1712fb1a | 4284 | if (r < 0 || tmo <= 0) { |
aac89168 | 4285 | dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); |
403009bf CK |
4286 | return -EIO; |
4287 | } | |
c41d1cf6 | 4288 | |
aac89168 | 4289 | dev_info(adev->dev, "recover vram bo from shadow done\n"); |
403009bf | 4290 | return 0; |
c41d1cf6 ML |
4291 | } |
4292 | ||
a90ad3c2 | 4293 | |
e3ecdffa | 4294 | /** |
06ec9070 | 4295 | * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf |
5740682e | 4296 | * |
982a820b | 4297 | * @adev: amdgpu_device pointer |
87e3f136 | 4298 | * @from_hypervisor: request from hypervisor |
5740682e ML |
4299 | * |
4300 | * do VF FLR and reinitialize Asic | |
3f48c681 | 4301 | * return 0 means succeeded otherwise failed |
e3ecdffa AD |
4302 | */ |
4303 | static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, | |
4304 | bool from_hypervisor) | |
5740682e ML |
4305 | { |
4306 | int r; | |
4307 | ||
4308 | if (from_hypervisor) | |
4309 | r = amdgpu_virt_request_full_gpu(adev, true); | |
4310 | else | |
4311 | r = amdgpu_virt_reset_gpu(adev); | |
4312 | if (r) | |
4313 | return r; | |
a90ad3c2 | 4314 | |
b639c22c JZ |
4315 | amdgpu_amdkfd_pre_reset(adev); |
4316 | ||
a90ad3c2 | 4317 | /* Resume IP prior to SMC */ |
06ec9070 | 4318 | r = amdgpu_device_ip_reinit_early_sriov(adev); |
5740682e ML |
4319 | if (r) |
4320 | goto error; | |
a90ad3c2 | 4321 | |
c9ffa427 | 4322 | amdgpu_virt_init_data_exchange(adev); |
a90ad3c2 | 4323 | /* we need recover gart prior to run SMC/CP/SDMA resume */ |
6c28aed6 | 4324 | amdgpu_gtt_mgr_recover(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); |
a90ad3c2 | 4325 | |
7a3e0bb2 RZ |
4326 | r = amdgpu_device_fw_loading(adev); |
4327 | if (r) | |
4328 | return r; | |
4329 | ||
a90ad3c2 | 4330 | /* now we are okay to resume SMC/CP/SDMA */ |
06ec9070 | 4331 | r = amdgpu_device_ip_reinit_late_sriov(adev); |
5740682e ML |
4332 | if (r) |
4333 | goto error; | |
a90ad3c2 ML |
4334 | |
4335 | amdgpu_irq_gpu_reset_resume_helper(adev); | |
5740682e | 4336 | r = amdgpu_ib_ring_tests(adev); |
f81e8d53 | 4337 | amdgpu_amdkfd_post_reset(adev); |
a90ad3c2 | 4338 | |
abc34253 | 4339 | error: |
c41d1cf6 | 4340 | if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { |
e3526257 | 4341 | amdgpu_inc_vram_lost(adev); |
c33adbc7 | 4342 | r = amdgpu_device_recover_vram(adev); |
a90ad3c2 | 4343 | } |
437f3e0b | 4344 | amdgpu_virt_release_full_gpu(adev, true); |
a90ad3c2 ML |
4345 | |
4346 | return r; | |
4347 | } | |
4348 | ||
9a1cddd6 | 4349 | /** |
4350 | * amdgpu_device_has_job_running - check if there is any job in mirror list | |
4351 | * | |
982a820b | 4352 | * @adev: amdgpu_device pointer |
9a1cddd6 | 4353 | * |
4354 | * check if there is any job in mirror list | |
4355 | */ | |
4356 | bool amdgpu_device_has_job_running(struct amdgpu_device *adev) | |
4357 | { | |
4358 | int i; | |
4359 | struct drm_sched_job *job; | |
4360 | ||
4361 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4362 | struct amdgpu_ring *ring = adev->rings[i]; | |
4363 | ||
4364 | if (!ring || !ring->sched.thread) | |
4365 | continue; | |
4366 | ||
4367 | spin_lock(&ring->sched.job_list_lock); | |
6efa4b46 LT |
4368 | job = list_first_entry_or_null(&ring->sched.pending_list, |
4369 | struct drm_sched_job, list); | |
9a1cddd6 | 4370 | spin_unlock(&ring->sched.job_list_lock); |
4371 | if (job) | |
4372 | return true; | |
4373 | } | |
4374 | return false; | |
4375 | } | |
4376 | ||
12938fad CK |
4377 | /** |
4378 | * amdgpu_device_should_recover_gpu - check if we should try GPU recovery | |
4379 | * | |
982a820b | 4380 | * @adev: amdgpu_device pointer |
12938fad CK |
4381 | * |
4382 | * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover | |
4383 | * a hung GPU. | |
4384 | */ | |
4385 | bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev) | |
4386 | { | |
4387 | if (!amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4388 | dev_info(adev->dev, "Timeout, but no hardware hang detected.\n"); |
12938fad CK |
4389 | return false; |
4390 | } | |
4391 | ||
3ba7b418 AG |
4392 | if (amdgpu_gpu_recovery == 0) |
4393 | goto disabled; | |
4394 | ||
4395 | if (amdgpu_sriov_vf(adev)) | |
4396 | return true; | |
4397 | ||
4398 | if (amdgpu_gpu_recovery == -1) { | |
4399 | switch (adev->asic_type) { | |
fc42d47c AG |
4400 | case CHIP_BONAIRE: |
4401 | case CHIP_HAWAII: | |
3ba7b418 AG |
4402 | case CHIP_TOPAZ: |
4403 | case CHIP_TONGA: | |
4404 | case CHIP_FIJI: | |
4405 | case CHIP_POLARIS10: | |
4406 | case CHIP_POLARIS11: | |
4407 | case CHIP_POLARIS12: | |
4408 | case CHIP_VEGAM: | |
4409 | case CHIP_VEGA20: | |
4410 | case CHIP_VEGA10: | |
4411 | case CHIP_VEGA12: | |
c43b849f | 4412 | case CHIP_RAVEN: |
e9d4cf91 | 4413 | case CHIP_ARCTURUS: |
2cb44fb0 | 4414 | case CHIP_RENOIR: |
658c6639 AD |
4415 | case CHIP_NAVI10: |
4416 | case CHIP_NAVI14: | |
4417 | case CHIP_NAVI12: | |
131a3c74 | 4418 | case CHIP_SIENNA_CICHLID: |
665fe4dc | 4419 | case CHIP_NAVY_FLOUNDER: |
27859ee3 | 4420 | case CHIP_DIMGREY_CAVEFISH: |
a2f55040 | 4421 | case CHIP_BEIGE_GOBY: |
fe68ceef | 4422 | case CHIP_VANGOGH: |
ea4e96a7 | 4423 | case CHIP_ALDEBARAN: |
3ba7b418 AG |
4424 | break; |
4425 | default: | |
4426 | goto disabled; | |
4427 | } | |
12938fad CK |
4428 | } |
4429 | ||
4430 | return true; | |
3ba7b418 AG |
4431 | |
4432 | disabled: | |
aac89168 | 4433 | dev_info(adev->dev, "GPU recovery disabled.\n"); |
3ba7b418 | 4434 | return false; |
12938fad CK |
4435 | } |
4436 | ||
5c03e584 FX |
4437 | int amdgpu_device_mode1_reset(struct amdgpu_device *adev) |
4438 | { | |
4439 | u32 i; | |
4440 | int ret = 0; | |
4441 | ||
4442 | amdgpu_atombios_scratch_regs_engine_hung(adev, true); | |
4443 | ||
4444 | dev_info(adev->dev, "GPU mode1 reset\n"); | |
4445 | ||
4446 | /* disable BM */ | |
4447 | pci_clear_master(adev->pdev); | |
4448 | ||
4449 | amdgpu_device_cache_pci_state(adev->pdev); | |
4450 | ||
4451 | if (amdgpu_dpm_is_mode1_reset_supported(adev)) { | |
4452 | dev_info(adev->dev, "GPU smu mode1 reset\n"); | |
4453 | ret = amdgpu_dpm_mode1_reset(adev); | |
4454 | } else { | |
4455 | dev_info(adev->dev, "GPU psp mode1 reset\n"); | |
4456 | ret = psp_gpu_reset(adev); | |
4457 | } | |
4458 | ||
4459 | if (ret) | |
4460 | dev_err(adev->dev, "GPU mode1 reset failed\n"); | |
4461 | ||
4462 | amdgpu_device_load_pci_state(adev->pdev); | |
4463 | ||
4464 | /* wait for asic to come out of reset */ | |
4465 | for (i = 0; i < adev->usec_timeout; i++) { | |
4466 | u32 memsize = adev->nbio.funcs->get_memsize(adev); | |
4467 | ||
4468 | if (memsize != 0xffffffff) | |
4469 | break; | |
4470 | udelay(1); | |
4471 | } | |
4472 | ||
4473 | amdgpu_atombios_scratch_regs_engine_hung(adev, false); | |
4474 | return ret; | |
4475 | } | |
5c6dd71e | 4476 | |
e3c1b071 | 4477 | int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, |
04442bf7 | 4478 | struct amdgpu_reset_context *reset_context) |
26bc5340 | 4479 | { |
c530b02f | 4480 | int i, j, r = 0; |
04442bf7 LL |
4481 | struct amdgpu_job *job = NULL; |
4482 | bool need_full_reset = | |
4483 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4484 | ||
4485 | if (reset_context->reset_req_dev == adev) | |
4486 | job = reset_context->job; | |
71182665 | 4487 | |
b602ca5f TZ |
4488 | if (amdgpu_sriov_vf(adev)) { |
4489 | /* stop the data exchange thread */ | |
4490 | amdgpu_virt_fini_data_exchange(adev); | |
4491 | } | |
4492 | ||
71182665 | 4493 | /* block all schedulers and reset given job's ring */ |
0875dc9e CZ |
4494 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
4495 | struct amdgpu_ring *ring = adev->rings[i]; | |
4496 | ||
51687759 | 4497 | if (!ring || !ring->sched.thread) |
0875dc9e | 4498 | continue; |
5740682e | 4499 | |
c530b02f JZ |
4500 | /*clear job fence from fence drv to avoid force_completion |
4501 | *leave NULL and vm flush fence in fence drv */ | |
4502 | for (j = 0; j <= ring->fence_drv.num_fences_mask; j++) { | |
4503 | struct dma_fence *old, **ptr; | |
4504 | ||
4505 | ptr = &ring->fence_drv.fences[j]; | |
4506 | old = rcu_dereference_protected(*ptr, 1); | |
4507 | if (old && test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &old->flags)) { | |
4508 | RCU_INIT_POINTER(*ptr, NULL); | |
4509 | } | |
4510 | } | |
2f9d4084 ML |
4511 | /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ |
4512 | amdgpu_fence_driver_force_completion(ring); | |
0875dc9e | 4513 | } |
d38ceaf9 | 4514 | |
ff99849b | 4515 | if (job && job->vm) |
222b5f04 AG |
4516 | drm_sched_increase_karma(&job->base); |
4517 | ||
04442bf7 | 4518 | r = amdgpu_reset_prepare_hwcontext(adev, reset_context); |
404b277b LL |
4519 | /* If reset handler not implemented, continue; otherwise return */ |
4520 | if (r == -ENOSYS) | |
4521 | r = 0; | |
4522 | else | |
04442bf7 LL |
4523 | return r; |
4524 | ||
1d721ed6 | 4525 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
26bc5340 AG |
4526 | if (!amdgpu_sriov_vf(adev)) { |
4527 | ||
4528 | if (!need_full_reset) | |
4529 | need_full_reset = amdgpu_device_ip_need_full_reset(adev); | |
4530 | ||
4531 | if (!need_full_reset) { | |
4532 | amdgpu_device_ip_pre_soft_reset(adev); | |
4533 | r = amdgpu_device_ip_soft_reset(adev); | |
4534 | amdgpu_device_ip_post_soft_reset(adev); | |
4535 | if (r || amdgpu_device_ip_check_soft_reset(adev)) { | |
aac89168 | 4536 | dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n"); |
26bc5340 AG |
4537 | need_full_reset = true; |
4538 | } | |
4539 | } | |
4540 | ||
4541 | if (need_full_reset) | |
4542 | r = amdgpu_device_ip_suspend(adev); | |
04442bf7 LL |
4543 | if (need_full_reset) |
4544 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4545 | else | |
4546 | clear_bit(AMDGPU_NEED_FULL_RESET, | |
4547 | &reset_context->flags); | |
26bc5340 AG |
4548 | } |
4549 | ||
4550 | return r; | |
4551 | } | |
4552 | ||
04442bf7 LL |
4553 | int amdgpu_do_asic_reset(struct list_head *device_list_handle, |
4554 | struct amdgpu_reset_context *reset_context) | |
26bc5340 AG |
4555 | { |
4556 | struct amdgpu_device *tmp_adev = NULL; | |
04442bf7 | 4557 | bool need_full_reset, skip_hw_reset, vram_lost = false; |
26bc5340 AG |
4558 | int r = 0; |
4559 | ||
04442bf7 LL |
4560 | /* Try reset handler method first */ |
4561 | tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, | |
4562 | reset_list); | |
4563 | r = amdgpu_reset_perform_reset(tmp_adev, reset_context); | |
404b277b LL |
4564 | /* If reset handler not implemented, continue; otherwise return */ |
4565 | if (r == -ENOSYS) | |
4566 | r = 0; | |
4567 | else | |
04442bf7 LL |
4568 | return r; |
4569 | ||
4570 | /* Reset handler not implemented, use the default method */ | |
4571 | need_full_reset = | |
4572 | test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4573 | skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags); | |
4574 | ||
26bc5340 | 4575 | /* |
655ce9cb | 4576 | * ASIC reset has to be done on all XGMI hive nodes ASAP |
26bc5340 AG |
4577 | * to allow proper links negotiation in FW (within 1 sec) |
4578 | */ | |
7ac71382 | 4579 | if (!skip_hw_reset && need_full_reset) { |
655ce9cb | 4580 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
041a62bc | 4581 | /* For XGMI run all resets in parallel to speed up the process */ |
d4535e2c | 4582 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
e3c1b071 | 4583 | tmp_adev->gmc.xgmi.pending_reset = false; |
c96cf282 | 4584 | if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) |
d4535e2c AG |
4585 | r = -EALREADY; |
4586 | } else | |
4587 | r = amdgpu_asic_reset(tmp_adev); | |
d4535e2c | 4588 | |
041a62bc | 4589 | if (r) { |
aac89168 | 4590 | dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", |
4a580877 | 4591 | r, adev_to_drm(tmp_adev)->unique); |
041a62bc | 4592 | break; |
ce316fa5 LM |
4593 | } |
4594 | } | |
4595 | ||
041a62bc AG |
4596 | /* For XGMI wait for all resets to complete before proceed */ |
4597 | if (!r) { | |
655ce9cb | 4598 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
ce316fa5 LM |
4599 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
4600 | flush_work(&tmp_adev->xgmi_reset_work); | |
4601 | r = tmp_adev->asic_reset_res; | |
4602 | if (r) | |
4603 | break; | |
ce316fa5 LM |
4604 | } |
4605 | } | |
4606 | } | |
ce316fa5 | 4607 | } |
26bc5340 | 4608 | |
43c4d576 | 4609 | if (!r && amdgpu_ras_intr_triggered()) { |
655ce9cb | 4610 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
8bc7b360 HZ |
4611 | if (tmp_adev->mmhub.ras_funcs && |
4612 | tmp_adev->mmhub.ras_funcs->reset_ras_error_count) | |
4613 | tmp_adev->mmhub.ras_funcs->reset_ras_error_count(tmp_adev); | |
43c4d576 JC |
4614 | } |
4615 | ||
00eaa571 | 4616 | amdgpu_ras_intr_cleared(); |
43c4d576 | 4617 | } |
00eaa571 | 4618 | |
655ce9cb | 4619 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
26bc5340 AG |
4620 | if (need_full_reset) { |
4621 | /* post card */ | |
e3c1b071 | 4622 | r = amdgpu_device_asic_init(tmp_adev); |
4623 | if (r) { | |
aac89168 | 4624 | dev_warn(tmp_adev->dev, "asic atom init failed!"); |
e3c1b071 | 4625 | } else { |
26bc5340 | 4626 | dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); |
f02abeb0 JZ |
4627 | r = amdgpu_amdkfd_resume_iommu(tmp_adev); |
4628 | if (r) | |
4629 | goto out; | |
4630 | ||
26bc5340 AG |
4631 | r = amdgpu_device_ip_resume_phase1(tmp_adev); |
4632 | if (r) | |
4633 | goto out; | |
4634 | ||
4635 | vram_lost = amdgpu_device_check_vram_lost(tmp_adev); | |
4636 | if (vram_lost) { | |
77e7f829 | 4637 | DRM_INFO("VRAM is lost due to GPU reset!\n"); |
e3526257 | 4638 | amdgpu_inc_vram_lost(tmp_adev); |
26bc5340 AG |
4639 | } |
4640 | ||
6c28aed6 | 4641 | r = amdgpu_gtt_mgr_recover(ttm_manager_type(&tmp_adev->mman.bdev, TTM_PL_TT)); |
26bc5340 AG |
4642 | if (r) |
4643 | goto out; | |
4644 | ||
4645 | r = amdgpu_device_fw_loading(tmp_adev); | |
4646 | if (r) | |
4647 | return r; | |
4648 | ||
4649 | r = amdgpu_device_ip_resume_phase2(tmp_adev); | |
4650 | if (r) | |
4651 | goto out; | |
4652 | ||
4653 | if (vram_lost) | |
4654 | amdgpu_device_fill_reset_magic(tmp_adev); | |
4655 | ||
fdafb359 EQ |
4656 | /* |
4657 | * Add this ASIC as tracked as reset was already | |
4658 | * complete successfully. | |
4659 | */ | |
4660 | amdgpu_register_gpu_instance(tmp_adev); | |
4661 | ||
04442bf7 LL |
4662 | if (!reset_context->hive && |
4663 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
e3c1b071 | 4664 | amdgpu_xgmi_add_device(tmp_adev); |
4665 | ||
7c04ca50 | 4666 | r = amdgpu_device_ip_late_init(tmp_adev); |
4667 | if (r) | |
4668 | goto out; | |
4669 | ||
565d1941 EQ |
4670 | amdgpu_fbdev_set_suspend(tmp_adev, 0); |
4671 | ||
e8fbaf03 GC |
4672 | /* |
4673 | * The GPU enters bad state once faulty pages | |
4674 | * by ECC has reached the threshold, and ras | |
4675 | * recovery is scheduled next. So add one check | |
4676 | * here to break recovery if it indeed exceeds | |
4677 | * bad page threshold, and remind user to | |
4678 | * retire this GPU or setting one bigger | |
4679 | * bad_page_threshold value to fix this once | |
4680 | * probing driver again. | |
4681 | */ | |
11003c68 | 4682 | if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) { |
e8fbaf03 GC |
4683 | /* must succeed. */ |
4684 | amdgpu_ras_resume(tmp_adev); | |
4685 | } else { | |
4686 | r = -EINVAL; | |
4687 | goto out; | |
4688 | } | |
e79a04d5 | 4689 | |
26bc5340 | 4690 | /* Update PSP FW topology after reset */ |
04442bf7 LL |
4691 | if (reset_context->hive && |
4692 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) | |
4693 | r = amdgpu_xgmi_update_topology( | |
4694 | reset_context->hive, tmp_adev); | |
26bc5340 AG |
4695 | } |
4696 | } | |
4697 | ||
26bc5340 AG |
4698 | out: |
4699 | if (!r) { | |
4700 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); | |
4701 | r = amdgpu_ib_ring_tests(tmp_adev); | |
4702 | if (r) { | |
4703 | dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); | |
26bc5340 AG |
4704 | need_full_reset = true; |
4705 | r = -EAGAIN; | |
4706 | goto end; | |
4707 | } | |
4708 | } | |
4709 | ||
4710 | if (!r) | |
4711 | r = amdgpu_device_recover_vram(tmp_adev); | |
4712 | else | |
4713 | tmp_adev->asic_reset_res = r; | |
4714 | } | |
4715 | ||
4716 | end: | |
04442bf7 LL |
4717 | if (need_full_reset) |
4718 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
4719 | else | |
4720 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); | |
26bc5340 AG |
4721 | return r; |
4722 | } | |
4723 | ||
08ebb485 DL |
4724 | static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, |
4725 | struct amdgpu_hive_info *hive) | |
26bc5340 | 4726 | { |
53b3f8f4 DL |
4727 | if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0) |
4728 | return false; | |
4729 | ||
08ebb485 DL |
4730 | if (hive) { |
4731 | down_write_nest_lock(&adev->reset_sem, &hive->hive_lock); | |
4732 | } else { | |
4733 | down_write(&adev->reset_sem); | |
4734 | } | |
5740682e | 4735 | |
a3a09142 AD |
4736 | switch (amdgpu_asic_reset_method(adev)) { |
4737 | case AMD_RESET_METHOD_MODE1: | |
4738 | adev->mp1_state = PP_MP1_STATE_SHUTDOWN; | |
4739 | break; | |
4740 | case AMD_RESET_METHOD_MODE2: | |
4741 | adev->mp1_state = PP_MP1_STATE_RESET; | |
4742 | break; | |
4743 | default: | |
4744 | adev->mp1_state = PP_MP1_STATE_NONE; | |
4745 | break; | |
4746 | } | |
1d721ed6 AG |
4747 | |
4748 | return true; | |
26bc5340 | 4749 | } |
d38ceaf9 | 4750 | |
26bc5340 AG |
4751 | static void amdgpu_device_unlock_adev(struct amdgpu_device *adev) |
4752 | { | |
89041940 | 4753 | amdgpu_vf_error_trans_all(adev); |
a3a09142 | 4754 | adev->mp1_state = PP_MP1_STATE_NONE; |
53b3f8f4 | 4755 | atomic_set(&adev->in_gpu_reset, 0); |
6049db43 | 4756 | up_write(&adev->reset_sem); |
26bc5340 AG |
4757 | } |
4758 | ||
91fb309d HC |
4759 | /* |
4760 | * to lockup a list of amdgpu devices in a hive safely, if not a hive | |
4761 | * with multiple nodes, it will be similar as amdgpu_device_lock_adev. | |
4762 | * | |
4763 | * unlock won't require roll back. | |
4764 | */ | |
4765 | static int amdgpu_device_lock_hive_adev(struct amdgpu_device *adev, struct amdgpu_hive_info *hive) | |
4766 | { | |
4767 | struct amdgpu_device *tmp_adev = NULL; | |
4768 | ||
4769 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
4770 | if (!hive) { | |
4771 | dev_err(adev->dev, "Hive is NULL while device has multiple xgmi nodes"); | |
4772 | return -ENODEV; | |
4773 | } | |
4774 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
4775 | if (!amdgpu_device_lock_adev(tmp_adev, hive)) | |
4776 | goto roll_back; | |
4777 | } | |
4778 | } else if (!amdgpu_device_lock_adev(adev, hive)) | |
4779 | return -EAGAIN; | |
4780 | ||
4781 | return 0; | |
4782 | roll_back: | |
4783 | if (!list_is_first(&tmp_adev->gmc.xgmi.head, &hive->device_list)) { | |
4784 | /* | |
4785 | * if the lockup iteration break in the middle of a hive, | |
4786 | * it may means there may has a race issue, | |
4787 | * or a hive device locked up independently. | |
4788 | * we may be in trouble and may not, so will try to roll back | |
4789 | * the lock and give out a warnning. | |
4790 | */ | |
4791 | dev_warn(tmp_adev->dev, "Hive lock iteration broke in the middle. Rolling back to unlock"); | |
4792 | list_for_each_entry_continue_reverse(tmp_adev, &hive->device_list, gmc.xgmi.head) { | |
4793 | amdgpu_device_unlock_adev(tmp_adev); | |
4794 | } | |
4795 | } | |
4796 | return -EAGAIN; | |
4797 | } | |
4798 | ||
3f12acc8 EQ |
4799 | static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev) |
4800 | { | |
4801 | struct pci_dev *p = NULL; | |
4802 | ||
4803 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4804 | adev->pdev->bus->number, 1); | |
4805 | if (p) { | |
4806 | pm_runtime_enable(&(p->dev)); | |
4807 | pm_runtime_resume(&(p->dev)); | |
4808 | } | |
4809 | } | |
4810 | ||
4811 | static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev) | |
4812 | { | |
4813 | enum amd_reset_method reset_method; | |
4814 | struct pci_dev *p = NULL; | |
4815 | u64 expires; | |
4816 | ||
4817 | /* | |
4818 | * For now, only BACO and mode1 reset are confirmed | |
4819 | * to suffer the audio issue without proper suspended. | |
4820 | */ | |
4821 | reset_method = amdgpu_asic_reset_method(adev); | |
4822 | if ((reset_method != AMD_RESET_METHOD_BACO) && | |
4823 | (reset_method != AMD_RESET_METHOD_MODE1)) | |
4824 | return -EINVAL; | |
4825 | ||
4826 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), | |
4827 | adev->pdev->bus->number, 1); | |
4828 | if (!p) | |
4829 | return -ENODEV; | |
4830 | ||
4831 | expires = pm_runtime_autosuspend_expiration(&(p->dev)); | |
4832 | if (!expires) | |
4833 | /* | |
4834 | * If we cannot get the audio device autosuspend delay, | |
4835 | * a fixed 4S interval will be used. Considering 3S is | |
4836 | * the audio controller default autosuspend delay setting. | |
4837 | * 4S used here is guaranteed to cover that. | |
4838 | */ | |
54b7feb9 | 4839 | expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL; |
3f12acc8 EQ |
4840 | |
4841 | while (!pm_runtime_status_suspended(&(p->dev))) { | |
4842 | if (!pm_runtime_suspend(&(p->dev))) | |
4843 | break; | |
4844 | ||
4845 | if (expires < ktime_get_mono_fast_ns()) { | |
4846 | dev_warn(adev->dev, "failed to suspend display audio\n"); | |
4847 | /* TODO: abort the succeeding gpu reset? */ | |
4848 | return -ETIMEDOUT; | |
4849 | } | |
4850 | } | |
4851 | ||
4852 | pm_runtime_disable(&(p->dev)); | |
4853 | ||
4854 | return 0; | |
4855 | } | |
4856 | ||
9d8d96be | 4857 | static void amdgpu_device_recheck_guilty_jobs( |
04442bf7 LL |
4858 | struct amdgpu_device *adev, struct list_head *device_list_handle, |
4859 | struct amdgpu_reset_context *reset_context) | |
e6c6338f JZ |
4860 | { |
4861 | int i, r = 0; | |
4862 | ||
4863 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
4864 | struct amdgpu_ring *ring = adev->rings[i]; | |
4865 | int ret = 0; | |
4866 | struct drm_sched_job *s_job; | |
4867 | ||
4868 | if (!ring || !ring->sched.thread) | |
4869 | continue; | |
4870 | ||
4871 | s_job = list_first_entry_or_null(&ring->sched.pending_list, | |
4872 | struct drm_sched_job, list); | |
4873 | if (s_job == NULL) | |
4874 | continue; | |
4875 | ||
4876 | /* clear job's guilty and depend the folowing step to decide the real one */ | |
4877 | drm_sched_reset_karma(s_job); | |
4878 | drm_sched_resubmit_jobs_ext(&ring->sched, 1); | |
4879 | ||
4880 | ret = dma_fence_wait_timeout(s_job->s_fence->parent, false, ring->sched.timeout); | |
4881 | if (ret == 0) { /* timeout */ | |
4882 | DRM_ERROR("Found the real bad job! ring:%s, job_id:%llx\n", | |
4883 | ring->sched.name, s_job->id); | |
4884 | ||
4885 | /* set guilty */ | |
4886 | drm_sched_increase_karma(s_job); | |
4887 | retry: | |
4888 | /* do hw reset */ | |
4889 | if (amdgpu_sriov_vf(adev)) { | |
4890 | amdgpu_virt_fini_data_exchange(adev); | |
4891 | r = amdgpu_device_reset_sriov(adev, false); | |
4892 | if (r) | |
4893 | adev->asic_reset_res = r; | |
4894 | } else { | |
04442bf7 LL |
4895 | clear_bit(AMDGPU_SKIP_HW_RESET, |
4896 | &reset_context->flags); | |
4897 | r = amdgpu_do_asic_reset(device_list_handle, | |
4898 | reset_context); | |
e6c6338f JZ |
4899 | if (r && r == -EAGAIN) |
4900 | goto retry; | |
4901 | } | |
4902 | ||
4903 | /* | |
4904 | * add reset counter so that the following | |
4905 | * resubmitted job could flush vmid | |
4906 | */ | |
4907 | atomic_inc(&adev->gpu_reset_counter); | |
4908 | continue; | |
4909 | } | |
4910 | ||
4911 | /* got the hw fence, signal finished fence */ | |
4912 | atomic_dec(ring->sched.score); | |
4913 | dma_fence_get(&s_job->s_fence->finished); | |
4914 | dma_fence_signal(&s_job->s_fence->finished); | |
4915 | dma_fence_put(&s_job->s_fence->finished); | |
4916 | ||
4917 | /* remove node from list and free the job */ | |
4918 | spin_lock(&ring->sched.job_list_lock); | |
4919 | list_del_init(&s_job->list); | |
4920 | spin_unlock(&ring->sched.job_list_lock); | |
4921 | ring->sched.ops->free_job(s_job); | |
4922 | } | |
4923 | } | |
4924 | ||
26bc5340 AG |
4925 | /** |
4926 | * amdgpu_device_gpu_recover - reset the asic and recover scheduler | |
4927 | * | |
982a820b | 4928 | * @adev: amdgpu_device pointer |
26bc5340 AG |
4929 | * @job: which job trigger hang |
4930 | * | |
4931 | * Attempt to reset the GPU if it has hung (all asics). | |
4932 | * Attempt to do soft-reset or full-reset and reinitialize Asic | |
4933 | * Returns 0 for success or an error on failure. | |
4934 | */ | |
4935 | ||
4936 | int amdgpu_device_gpu_recover(struct amdgpu_device *adev, | |
4937 | struct amdgpu_job *job) | |
4938 | { | |
1d721ed6 | 4939 | struct list_head device_list, *device_list_handle = NULL; |
7dd8c205 | 4940 | bool job_signaled = false; |
26bc5340 | 4941 | struct amdgpu_hive_info *hive = NULL; |
26bc5340 | 4942 | struct amdgpu_device *tmp_adev = NULL; |
1d721ed6 | 4943 | int i, r = 0; |
bb5c7235 | 4944 | bool need_emergency_restart = false; |
3f12acc8 | 4945 | bool audio_suspended = false; |
e6c6338f | 4946 | int tmp_vram_lost_counter; |
04442bf7 LL |
4947 | struct amdgpu_reset_context reset_context; |
4948 | ||
4949 | memset(&reset_context, 0, sizeof(reset_context)); | |
26bc5340 | 4950 | |
6e3cd2a9 | 4951 | /* |
bb5c7235 WS |
4952 | * Special case: RAS triggered and full reset isn't supported |
4953 | */ | |
4954 | need_emergency_restart = amdgpu_ras_need_emergency_restart(adev); | |
4955 | ||
d5ea093e AG |
4956 | /* |
4957 | * Flush RAM to disk so that after reboot | |
4958 | * the user can read log and see why the system rebooted. | |
4959 | */ | |
bb5c7235 | 4960 | if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) { |
d5ea093e AG |
4961 | DRM_WARN("Emergency reboot."); |
4962 | ||
4963 | ksys_sync_helper(); | |
4964 | emergency_restart(); | |
4965 | } | |
4966 | ||
b823821f | 4967 | dev_info(adev->dev, "GPU %s begin!\n", |
bb5c7235 | 4968 | need_emergency_restart ? "jobs stop":"reset"); |
26bc5340 AG |
4969 | |
4970 | /* | |
1d721ed6 AG |
4971 | * Here we trylock to avoid chain of resets executing from |
4972 | * either trigger by jobs on different adevs in XGMI hive or jobs on | |
4973 | * different schedulers for same device while this TO handler is running. | |
4974 | * We always reset all schedulers for device and all devices for XGMI | |
4975 | * hive so that should take care of them too. | |
26bc5340 | 4976 | */ |
d95e8e97 | 4977 | hive = amdgpu_get_xgmi_hive(adev); |
53b3f8f4 DL |
4978 | if (hive) { |
4979 | if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) { | |
4980 | DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", | |
4981 | job ? job->base.id : -1, hive->hive_id); | |
d95e8e97 | 4982 | amdgpu_put_xgmi_hive(hive); |
ff99849b | 4983 | if (job && job->vm) |
91fb309d | 4984 | drm_sched_increase_karma(&job->base); |
53b3f8f4 DL |
4985 | return 0; |
4986 | } | |
4987 | mutex_lock(&hive->hive_lock); | |
1d721ed6 | 4988 | } |
26bc5340 | 4989 | |
04442bf7 LL |
4990 | reset_context.method = AMD_RESET_METHOD_NONE; |
4991 | reset_context.reset_req_dev = adev; | |
4992 | reset_context.job = job; | |
4993 | reset_context.hive = hive; | |
4994 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
4995 | ||
91fb309d HC |
4996 | /* |
4997 | * lock the device before we try to operate the linked list | |
4998 | * if didn't get the device lock, don't touch the linked list since | |
4999 | * others may iterating it. | |
5000 | */ | |
5001 | r = amdgpu_device_lock_hive_adev(adev, hive); | |
5002 | if (r) { | |
5003 | dev_info(adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress", | |
5004 | job ? job->base.id : -1); | |
5005 | ||
5006 | /* even we skipped this reset, still need to set the job to guilty */ | |
ff99849b | 5007 | if (job && job->vm) |
91fb309d HC |
5008 | drm_sched_increase_karma(&job->base); |
5009 | goto skip_recovery; | |
5010 | } | |
5011 | ||
9e94d22c EQ |
5012 | /* |
5013 | * Build list of devices to reset. | |
5014 | * In case we are in XGMI hive mode, resort the device list | |
5015 | * to put adev in the 1st position. | |
5016 | */ | |
5017 | INIT_LIST_HEAD(&device_list); | |
5018 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
655ce9cb | 5019 | list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) |
5020 | list_add_tail(&tmp_adev->reset_list, &device_list); | |
5021 | if (!list_is_first(&adev->reset_list, &device_list)) | |
5022 | list_rotate_to_front(&adev->reset_list, &device_list); | |
5023 | device_list_handle = &device_list; | |
26bc5340 | 5024 | } else { |
655ce9cb | 5025 | list_add_tail(&adev->reset_list, &device_list); |
26bc5340 AG |
5026 | device_list_handle = &device_list; |
5027 | } | |
5028 | ||
1d721ed6 | 5029 | /* block all schedulers and reset given job's ring */ |
655ce9cb | 5030 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
3f12acc8 EQ |
5031 | /* |
5032 | * Try to put the audio codec into suspend state | |
5033 | * before gpu reset started. | |
5034 | * | |
5035 | * Due to the power domain of the graphics device | |
5036 | * is shared with AZ power domain. Without this, | |
5037 | * we may change the audio hardware from behind | |
5038 | * the audio driver's back. That will trigger | |
5039 | * some audio codec errors. | |
5040 | */ | |
5041 | if (!amdgpu_device_suspend_display_audio(tmp_adev)) | |
5042 | audio_suspended = true; | |
5043 | ||
9e94d22c EQ |
5044 | amdgpu_ras_set_error_query_ready(tmp_adev, false); |
5045 | ||
52fb44cf EQ |
5046 | cancel_delayed_work_sync(&tmp_adev->delayed_init_work); |
5047 | ||
9e94d22c EQ |
5048 | if (!amdgpu_sriov_vf(tmp_adev)) |
5049 | amdgpu_amdkfd_pre_reset(tmp_adev); | |
5050 | ||
12ffa55d AG |
5051 | /* |
5052 | * Mark these ASICs to be reseted as untracked first | |
5053 | * And add them back after reset completed | |
5054 | */ | |
5055 | amdgpu_unregister_gpu_instance(tmp_adev); | |
5056 | ||
a2f63ee8 | 5057 | amdgpu_fbdev_set_suspend(tmp_adev, 1); |
565d1941 | 5058 | |
f1c1314b | 5059 | /* disable ras on ALL IPs */ |
bb5c7235 | 5060 | if (!need_emergency_restart && |
b823821f | 5061 | amdgpu_device_ip_need_full_reset(tmp_adev)) |
f1c1314b | 5062 | amdgpu_ras_suspend(tmp_adev); |
5063 | ||
1d721ed6 AG |
5064 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5065 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5066 | ||
5067 | if (!ring || !ring->sched.thread) | |
5068 | continue; | |
5069 | ||
0b2d2c2e | 5070 | drm_sched_stop(&ring->sched, job ? &job->base : NULL); |
7c6e68c7 | 5071 | |
bb5c7235 | 5072 | if (need_emergency_restart) |
7c6e68c7 | 5073 | amdgpu_job_stop_all_jobs_on_sched(&ring->sched); |
1d721ed6 | 5074 | } |
8f8c80f4 | 5075 | atomic_inc(&tmp_adev->gpu_reset_counter); |
1d721ed6 AG |
5076 | } |
5077 | ||
bb5c7235 | 5078 | if (need_emergency_restart) |
7c6e68c7 AG |
5079 | goto skip_sched_resume; |
5080 | ||
1d721ed6 AG |
5081 | /* |
5082 | * Must check guilty signal here since after this point all old | |
5083 | * HW fences are force signaled. | |
5084 | * | |
5085 | * job->base holds a reference to parent fence | |
5086 | */ | |
5087 | if (job && job->base.s_fence->parent && | |
7dd8c205 | 5088 | dma_fence_is_signaled(job->base.s_fence->parent)) { |
1d721ed6 | 5089 | job_signaled = true; |
1d721ed6 AG |
5090 | dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); |
5091 | goto skip_hw_reset; | |
5092 | } | |
5093 | ||
26bc5340 | 5094 | retry: /* Rest of adevs pre asic reset from XGMI hive. */ |
655ce9cb | 5095 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
04442bf7 | 5096 | r = amdgpu_device_pre_asic_reset(tmp_adev, &reset_context); |
26bc5340 AG |
5097 | /*TODO Should we stop ?*/ |
5098 | if (r) { | |
aac89168 | 5099 | dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", |
4a580877 | 5100 | r, adev_to_drm(tmp_adev)->unique); |
26bc5340 AG |
5101 | tmp_adev->asic_reset_res = r; |
5102 | } | |
5103 | } | |
5104 | ||
e6c6338f | 5105 | tmp_vram_lost_counter = atomic_read(&((adev)->vram_lost_counter)); |
26bc5340 AG |
5106 | /* Actual ASIC resets if needed.*/ |
5107 | /* TODO Implement XGMI hive reset logic for SRIOV */ | |
5108 | if (amdgpu_sriov_vf(adev)) { | |
5109 | r = amdgpu_device_reset_sriov(adev, job ? false : true); | |
5110 | if (r) | |
5111 | adev->asic_reset_res = r; | |
5112 | } else { | |
04442bf7 | 5113 | r = amdgpu_do_asic_reset(device_list_handle, &reset_context); |
26bc5340 AG |
5114 | if (r && r == -EAGAIN) |
5115 | goto retry; | |
5116 | } | |
5117 | ||
1d721ed6 AG |
5118 | skip_hw_reset: |
5119 | ||
26bc5340 | 5120 | /* Post ASIC reset for all devs .*/ |
655ce9cb | 5121 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
7c6e68c7 | 5122 | |
e6c6338f JZ |
5123 | /* |
5124 | * Sometimes a later bad compute job can block a good gfx job as gfx | |
5125 | * and compute ring share internal GC HW mutually. We add an additional | |
5126 | * guilty jobs recheck step to find the real guilty job, it synchronously | |
5127 | * submits and pends for the first job being signaled. If it gets timeout, | |
5128 | * we identify it as a real guilty job. | |
5129 | */ | |
5130 | if (amdgpu_gpu_recovery == 2 && | |
5131 | !(tmp_vram_lost_counter < atomic_read(&adev->vram_lost_counter))) | |
04442bf7 LL |
5132 | amdgpu_device_recheck_guilty_jobs( |
5133 | tmp_adev, device_list_handle, &reset_context); | |
e6c6338f | 5134 | |
1d721ed6 AG |
5135 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5136 | struct amdgpu_ring *ring = tmp_adev->rings[i]; | |
5137 | ||
5138 | if (!ring || !ring->sched.thread) | |
5139 | continue; | |
5140 | ||
5141 | /* No point to resubmit jobs if we didn't HW reset*/ | |
5142 | if (!tmp_adev->asic_reset_res && !job_signaled) | |
5143 | drm_sched_resubmit_jobs(&ring->sched); | |
5144 | ||
5145 | drm_sched_start(&ring->sched, !tmp_adev->asic_reset_res); | |
5146 | } | |
5147 | ||
fa6bf28f | 5148 | if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) { |
4a580877 | 5149 | drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); |
1d721ed6 AG |
5150 | } |
5151 | ||
5152 | tmp_adev->asic_reset_res = 0; | |
26bc5340 AG |
5153 | |
5154 | if (r) { | |
5155 | /* bad news, how to tell it to userspace ? */ | |
12ffa55d | 5156 | dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
26bc5340 AG |
5157 | amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); |
5158 | } else { | |
12ffa55d | 5159 | dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); |
3fa8f89d S |
5160 | if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0)) |
5161 | DRM_WARN("smart shift update failed\n"); | |
26bc5340 | 5162 | } |
7c6e68c7 | 5163 | } |
26bc5340 | 5164 | |
7c6e68c7 | 5165 | skip_sched_resume: |
655ce9cb | 5166 | list_for_each_entry(tmp_adev, device_list_handle, reset_list) { |
8e2712e7 | 5167 | /* unlock kfd: SRIOV would do it separately */ |
bb5c7235 | 5168 | if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev)) |
7c6e68c7 | 5169 | amdgpu_amdkfd_post_reset(tmp_adev); |
8e2712e7 | 5170 | |
5171 | /* kfd_post_reset will do nothing if kfd device is not initialized, | |
5172 | * need to bring up kfd here if it's not be initialized before | |
5173 | */ | |
5174 | if (!adev->kfd.init_complete) | |
5175 | amdgpu_amdkfd_device_init(adev); | |
5176 | ||
3f12acc8 EQ |
5177 | if (audio_suspended) |
5178 | amdgpu_device_resume_display_audio(tmp_adev); | |
26bc5340 AG |
5179 | amdgpu_device_unlock_adev(tmp_adev); |
5180 | } | |
5181 | ||
cbfd17f7 | 5182 | skip_recovery: |
9e94d22c | 5183 | if (hive) { |
53b3f8f4 | 5184 | atomic_set(&hive->in_reset, 0); |
9e94d22c | 5185 | mutex_unlock(&hive->hive_lock); |
d95e8e97 | 5186 | amdgpu_put_xgmi_hive(hive); |
9e94d22c | 5187 | } |
26bc5340 | 5188 | |
91fb309d | 5189 | if (r && r != -EAGAIN) |
26bc5340 | 5190 | dev_info(adev->dev, "GPU reset end with ret = %d\n", r); |
d38ceaf9 AD |
5191 | return r; |
5192 | } | |
5193 | ||
e3ecdffa AD |
5194 | /** |
5195 | * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot | |
5196 | * | |
5197 | * @adev: amdgpu_device pointer | |
5198 | * | |
5199 | * Fetchs and stores in the driver the PCIE capabilities (gen speed | |
5200 | * and lanes) of the slot the device is in. Handles APUs and | |
5201 | * virtualized environments where PCIE config space may not be available. | |
5202 | */ | |
5494d864 | 5203 | static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) |
d0dd7f0c | 5204 | { |
5d9a6330 | 5205 | struct pci_dev *pdev; |
c5313457 HK |
5206 | enum pci_bus_speed speed_cap, platform_speed_cap; |
5207 | enum pcie_link_width platform_link_width; | |
d0dd7f0c | 5208 | |
cd474ba0 AD |
5209 | if (amdgpu_pcie_gen_cap) |
5210 | adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap; | |
d0dd7f0c | 5211 | |
cd474ba0 AD |
5212 | if (amdgpu_pcie_lane_cap) |
5213 | adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap; | |
d0dd7f0c | 5214 | |
cd474ba0 AD |
5215 | /* covers APUs as well */ |
5216 | if (pci_is_root_bus(adev->pdev->bus)) { | |
5217 | if (adev->pm.pcie_gen_mask == 0) | |
5218 | adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK; | |
5219 | if (adev->pm.pcie_mlw_mask == 0) | |
5220 | adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK; | |
d0dd7f0c | 5221 | return; |
cd474ba0 | 5222 | } |
d0dd7f0c | 5223 | |
c5313457 HK |
5224 | if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask) |
5225 | return; | |
5226 | ||
dbaa922b AD |
5227 | pcie_bandwidth_available(adev->pdev, NULL, |
5228 | &platform_speed_cap, &platform_link_width); | |
c5313457 | 5229 | |
cd474ba0 | 5230 | if (adev->pm.pcie_gen_mask == 0) { |
5d9a6330 AD |
5231 | /* asic caps */ |
5232 | pdev = adev->pdev; | |
5233 | speed_cap = pcie_get_speed_cap(pdev); | |
5234 | if (speed_cap == PCI_SPEED_UNKNOWN) { | |
5235 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
cd474ba0 AD |
5236 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | |
5237 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
cd474ba0 | 5238 | } else { |
2b3a1f51 FX |
5239 | if (speed_cap == PCIE_SPEED_32_0GT) |
5240 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5241 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5242 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5243 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5244 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5245 | else if (speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5246 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5247 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5248 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5249 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
5250 | else if (speed_cap == PCIE_SPEED_8_0GT) | |
5251 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5252 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5253 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
5254 | else if (speed_cap == PCIE_SPEED_5_0GT) | |
5255 | adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5256 | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5257 | else | |
5258 | adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5259 | } | |
5260 | /* platform caps */ | |
c5313457 | 5261 | if (platform_speed_cap == PCI_SPEED_UNKNOWN) { |
5d9a6330 AD |
5262 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5263 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5264 | } else { | |
2b3a1f51 FX |
5265 | if (platform_speed_cap == PCIE_SPEED_32_0GT) |
5266 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | | |
5267 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5268 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5269 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 | | |
5270 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5); | |
5271 | else if (platform_speed_cap == PCIE_SPEED_16_0GT) | |
5d9a6330 AD |
5272 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5273 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5274 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 | | |
5275 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4); | |
c5313457 | 5276 | else if (platform_speed_cap == PCIE_SPEED_8_0GT) |
5d9a6330 AD |
5277 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5278 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | | |
5279 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3); | |
c5313457 | 5280 | else if (platform_speed_cap == PCIE_SPEED_5_0GT) |
5d9a6330 AD |
5281 | adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 | |
5282 | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2); | |
5283 | else | |
5284 | adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1; | |
5285 | ||
cd474ba0 AD |
5286 | } |
5287 | } | |
5288 | if (adev->pm.pcie_mlw_mask == 0) { | |
c5313457 | 5289 | if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) { |
5d9a6330 AD |
5290 | adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK; |
5291 | } else { | |
c5313457 | 5292 | switch (platform_link_width) { |
5d9a6330 | 5293 | case PCIE_LNK_X32: |
cd474ba0 AD |
5294 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 | |
5295 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | | |
5296 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5297 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5298 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5299 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5300 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5301 | break; | |
5d9a6330 | 5302 | case PCIE_LNK_X16: |
cd474ba0 AD |
5303 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 | |
5304 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | | |
5305 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5306 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5307 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5308 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5309 | break; | |
5d9a6330 | 5310 | case PCIE_LNK_X12: |
cd474ba0 AD |
5311 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 | |
5312 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | | |
5313 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5314 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5315 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5316 | break; | |
5d9a6330 | 5317 | case PCIE_LNK_X8: |
cd474ba0 AD |
5318 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 | |
5319 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | | |
5320 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5321 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5322 | break; | |
5d9a6330 | 5323 | case PCIE_LNK_X4: |
cd474ba0 AD |
5324 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 | |
5325 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | | |
5326 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5327 | break; | |
5d9a6330 | 5328 | case PCIE_LNK_X2: |
cd474ba0 AD |
5329 | adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 | |
5330 | CAIL_PCIE_LINK_WIDTH_SUPPORT_X1); | |
5331 | break; | |
5d9a6330 | 5332 | case PCIE_LNK_X1: |
cd474ba0 AD |
5333 | adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1; |
5334 | break; | |
5335 | default: | |
5336 | break; | |
5337 | } | |
d0dd7f0c AD |
5338 | } |
5339 | } | |
5340 | } | |
d38ceaf9 | 5341 | |
361dbd01 AD |
5342 | int amdgpu_device_baco_enter(struct drm_device *dev) |
5343 | { | |
1348969a | 5344 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5345 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
361dbd01 | 5346 | |
4a580877 | 5347 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5348 | return -ENOTSUPP; |
5349 | ||
8ab0d6f0 | 5350 | if (ras && adev->ras_enabled && |
acdae216 | 5351 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5352 | adev->nbio.funcs->enable_doorbell_interrupt(adev, false); |
5353 | ||
9530273e | 5354 | return amdgpu_dpm_baco_enter(adev); |
361dbd01 AD |
5355 | } |
5356 | ||
5357 | int amdgpu_device_baco_exit(struct drm_device *dev) | |
5358 | { | |
1348969a | 5359 | struct amdgpu_device *adev = drm_to_adev(dev); |
7a22677b | 5360 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
9530273e | 5361 | int ret = 0; |
361dbd01 | 5362 | |
4a580877 | 5363 | if (!amdgpu_device_supports_baco(adev_to_drm(adev))) |
361dbd01 AD |
5364 | return -ENOTSUPP; |
5365 | ||
9530273e EQ |
5366 | ret = amdgpu_dpm_baco_exit(adev); |
5367 | if (ret) | |
5368 | return ret; | |
7a22677b | 5369 | |
8ab0d6f0 | 5370 | if (ras && adev->ras_enabled && |
acdae216 | 5371 | adev->nbio.funcs->enable_doorbell_interrupt) |
7a22677b LM |
5372 | adev->nbio.funcs->enable_doorbell_interrupt(adev, true); |
5373 | ||
1bece222 CL |
5374 | if (amdgpu_passthrough(adev) && |
5375 | adev->nbio.funcs->clear_doorbell_interrupt) | |
5376 | adev->nbio.funcs->clear_doorbell_interrupt(adev); | |
5377 | ||
7a22677b | 5378 | return 0; |
361dbd01 | 5379 | } |
c9a6b82f | 5380 | |
acd89fca AG |
5381 | static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev) |
5382 | { | |
5383 | int i; | |
5384 | ||
5385 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5386 | struct amdgpu_ring *ring = adev->rings[i]; | |
5387 | ||
5388 | if (!ring || !ring->sched.thread) | |
5389 | continue; | |
5390 | ||
5391 | cancel_delayed_work_sync(&ring->sched.work_tdr); | |
5392 | } | |
5393 | } | |
5394 | ||
c9a6b82f AG |
5395 | /** |
5396 | * amdgpu_pci_error_detected - Called when a PCI error is detected. | |
5397 | * @pdev: PCI device struct | |
5398 | * @state: PCI channel state | |
5399 | * | |
5400 | * Description: Called when a PCI error is detected. | |
5401 | * | |
5402 | * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT. | |
5403 | */ | |
5404 | pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
5405 | { | |
5406 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5407 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5408 | int i; |
c9a6b82f AG |
5409 | |
5410 | DRM_INFO("PCI error: detected callback, state(%d)!!\n", state); | |
5411 | ||
6894305c AG |
5412 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
5413 | DRM_WARN("No support for XGMI hive yet..."); | |
5414 | return PCI_ERS_RESULT_DISCONNECT; | |
5415 | } | |
5416 | ||
248b0616 GC |
5417 | adev->pci_channel_state = state; |
5418 | ||
c9a6b82f AG |
5419 | switch (state) { |
5420 | case pci_channel_io_normal: | |
5421 | return PCI_ERS_RESULT_CAN_RECOVER; | |
acd89fca | 5422 | /* Fatal error, prepare for slot reset */ |
8a11d283 TZ |
5423 | case pci_channel_io_frozen: |
5424 | /* | |
acd89fca AG |
5425 | * Cancel and wait for all TDRs in progress if failing to |
5426 | * set adev->in_gpu_reset in amdgpu_device_lock_adev | |
5427 | * | |
5428 | * Locking adev->reset_sem will prevent any external access | |
5429 | * to GPU during PCI error recovery | |
5430 | */ | |
5431 | while (!amdgpu_device_lock_adev(adev, NULL)) | |
5432 | amdgpu_cancel_all_tdr(adev); | |
5433 | ||
5434 | /* | |
5435 | * Block any work scheduling as we do for regular GPU reset | |
5436 | * for the duration of the recovery | |
5437 | */ | |
5438 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
5439 | struct amdgpu_ring *ring = adev->rings[i]; | |
5440 | ||
5441 | if (!ring || !ring->sched.thread) | |
5442 | continue; | |
5443 | ||
5444 | drm_sched_stop(&ring->sched, NULL); | |
5445 | } | |
8f8c80f4 | 5446 | atomic_inc(&adev->gpu_reset_counter); |
c9a6b82f AG |
5447 | return PCI_ERS_RESULT_NEED_RESET; |
5448 | case pci_channel_io_perm_failure: | |
5449 | /* Permanent error, prepare for device removal */ | |
5450 | return PCI_ERS_RESULT_DISCONNECT; | |
5451 | } | |
5452 | ||
5453 | return PCI_ERS_RESULT_NEED_RESET; | |
5454 | } | |
5455 | ||
5456 | /** | |
5457 | * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers | |
5458 | * @pdev: pointer to PCI device | |
5459 | */ | |
5460 | pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev) | |
5461 | { | |
5462 | ||
5463 | DRM_INFO("PCI error: mmio enabled callback!!\n"); | |
5464 | ||
5465 | /* TODO - dump whatever for debugging purposes */ | |
5466 | ||
5467 | /* This called only if amdgpu_pci_error_detected returns | |
5468 | * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still | |
5469 | * works, no need to reset slot. | |
5470 | */ | |
5471 | ||
5472 | return PCI_ERS_RESULT_RECOVERED; | |
5473 | } | |
5474 | ||
5475 | /** | |
5476 | * amdgpu_pci_slot_reset - Called when PCI slot has been reset. | |
5477 | * @pdev: PCI device struct | |
5478 | * | |
5479 | * Description: This routine is called by the pci error recovery | |
5480 | * code after the PCI slot has been reset, just before we | |
5481 | * should resume normal operations. | |
5482 | */ | |
5483 | pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) | |
5484 | { | |
5485 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5486 | struct amdgpu_device *adev = drm_to_adev(dev); | |
362c7b91 | 5487 | int r, i; |
04442bf7 | 5488 | struct amdgpu_reset_context reset_context; |
362c7b91 | 5489 | u32 memsize; |
7ac71382 | 5490 | struct list_head device_list; |
c9a6b82f AG |
5491 | |
5492 | DRM_INFO("PCI error: slot reset callback!!\n"); | |
5493 | ||
04442bf7 LL |
5494 | memset(&reset_context, 0, sizeof(reset_context)); |
5495 | ||
7ac71382 | 5496 | INIT_LIST_HEAD(&device_list); |
655ce9cb | 5497 | list_add_tail(&adev->reset_list, &device_list); |
7ac71382 | 5498 | |
362c7b91 AG |
5499 | /* wait for asic to come out of reset */ |
5500 | msleep(500); | |
5501 | ||
7ac71382 | 5502 | /* Restore PCI confspace */ |
c1dd4aa6 | 5503 | amdgpu_device_load_pci_state(pdev); |
c9a6b82f | 5504 | |
362c7b91 AG |
5505 | /* confirm ASIC came out of reset */ |
5506 | for (i = 0; i < adev->usec_timeout; i++) { | |
5507 | memsize = amdgpu_asic_get_config_memsize(adev); | |
5508 | ||
5509 | if (memsize != 0xffffffff) | |
5510 | break; | |
5511 | udelay(1); | |
5512 | } | |
5513 | if (memsize == 0xffffffff) { | |
5514 | r = -ETIME; | |
5515 | goto out; | |
5516 | } | |
5517 | ||
04442bf7 LL |
5518 | reset_context.method = AMD_RESET_METHOD_NONE; |
5519 | reset_context.reset_req_dev = adev; | |
5520 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
5521 | set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); | |
5522 | ||
7afefb81 | 5523 | adev->no_hw_access = true; |
04442bf7 | 5524 | r = amdgpu_device_pre_asic_reset(adev, &reset_context); |
7afefb81 | 5525 | adev->no_hw_access = false; |
c9a6b82f AG |
5526 | if (r) |
5527 | goto out; | |
5528 | ||
04442bf7 | 5529 | r = amdgpu_do_asic_reset(&device_list, &reset_context); |
c9a6b82f AG |
5530 | |
5531 | out: | |
c9a6b82f | 5532 | if (!r) { |
c1dd4aa6 AG |
5533 | if (amdgpu_device_cache_pci_state(adev->pdev)) |
5534 | pci_restore_state(adev->pdev); | |
5535 | ||
c9a6b82f AG |
5536 | DRM_INFO("PCIe error recovery succeeded\n"); |
5537 | } else { | |
5538 | DRM_ERROR("PCIe error recovery failed, err:%d", r); | |
5539 | amdgpu_device_unlock_adev(adev); | |
5540 | } | |
5541 | ||
5542 | return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
5543 | } | |
5544 | ||
5545 | /** | |
5546 | * amdgpu_pci_resume() - resume normal ops after PCI reset | |
5547 | * @pdev: pointer to PCI device | |
5548 | * | |
5549 | * Called when the error recovery driver tells us that its | |
505199a3 | 5550 | * OK to resume normal operation. |
c9a6b82f AG |
5551 | */ |
5552 | void amdgpu_pci_resume(struct pci_dev *pdev) | |
5553 | { | |
5554 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5555 | struct amdgpu_device *adev = drm_to_adev(dev); | |
acd89fca | 5556 | int i; |
c9a6b82f | 5557 | |
c9a6b82f AG |
5558 | |
5559 | DRM_INFO("PCI error: resume callback!!\n"); | |
acd89fca | 5560 | |
248b0616 GC |
5561 | /* Only continue execution for the case of pci_channel_io_frozen */ |
5562 | if (adev->pci_channel_state != pci_channel_io_frozen) | |
5563 | return; | |
5564 | ||
acd89fca AG |
5565 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
5566 | struct amdgpu_ring *ring = adev->rings[i]; | |
5567 | ||
5568 | if (!ring || !ring->sched.thread) | |
5569 | continue; | |
5570 | ||
5571 | ||
5572 | drm_sched_resubmit_jobs(&ring->sched); | |
5573 | drm_sched_start(&ring->sched, true); | |
5574 | } | |
5575 | ||
5576 | amdgpu_device_unlock_adev(adev); | |
c9a6b82f | 5577 | } |
c1dd4aa6 AG |
5578 | |
5579 | bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) | |
5580 | { | |
5581 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5582 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5583 | int r; | |
5584 | ||
5585 | r = pci_save_state(pdev); | |
5586 | if (!r) { | |
5587 | kfree(adev->pci_state); | |
5588 | ||
5589 | adev->pci_state = pci_store_saved_state(pdev); | |
5590 | ||
5591 | if (!adev->pci_state) { | |
5592 | DRM_ERROR("Failed to store PCI saved state"); | |
5593 | return false; | |
5594 | } | |
5595 | } else { | |
5596 | DRM_WARN("Failed to save PCI state, err:%d\n", r); | |
5597 | return false; | |
5598 | } | |
5599 | ||
5600 | return true; | |
5601 | } | |
5602 | ||
5603 | bool amdgpu_device_load_pci_state(struct pci_dev *pdev) | |
5604 | { | |
5605 | struct drm_device *dev = pci_get_drvdata(pdev); | |
5606 | struct amdgpu_device *adev = drm_to_adev(dev); | |
5607 | int r; | |
5608 | ||
5609 | if (!adev->pci_state) | |
5610 | return false; | |
5611 | ||
5612 | r = pci_load_saved_state(pdev, adev->pci_state); | |
5613 | ||
5614 | if (!r) { | |
5615 | pci_restore_state(pdev); | |
5616 | } else { | |
5617 | DRM_WARN("Failed to load PCI state, err:%d\n", r); | |
5618 | return false; | |
5619 | } | |
5620 | ||
5621 | return true; | |
5622 | } | |
5623 | ||
810085dd EH |
5624 | void amdgpu_device_flush_hdp(struct amdgpu_device *adev, |
5625 | struct amdgpu_ring *ring) | |
5626 | { | |
5627 | #ifdef CONFIG_X86_64 | |
fae9e6b9 | 5628 | if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) |
810085dd EH |
5629 | return; |
5630 | #endif | |
5631 | if (adev->gmc.xgmi.connected_to_cpu) | |
5632 | return; | |
5633 | ||
5634 | if (ring && ring->funcs->emit_hdp_flush) | |
5635 | amdgpu_ring_emit_hdp_flush(ring); | |
5636 | else | |
5637 | amdgpu_asic_flush_hdp(adev, ring); | |
5638 | } | |
c1dd4aa6 | 5639 | |
810085dd EH |
5640 | void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, |
5641 | struct amdgpu_ring *ring) | |
5642 | { | |
5643 | #ifdef CONFIG_X86_64 | |
fae9e6b9 | 5644 | if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) |
810085dd EH |
5645 | return; |
5646 | #endif | |
5647 | if (adev->gmc.xgmi.connected_to_cpu) | |
5648 | return; | |
c1dd4aa6 | 5649 | |
810085dd EH |
5650 | amdgpu_asic_invalidate_hdp(adev, ring); |
5651 | } |