[mirror_ubuntu-kernels.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_discovery.c

/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "amdgpu.h"
#include "amdgpu_discovery.h"
#include "soc15_common.h"
#include "soc15_hw_ip.h"
#include "nbio/nbio_2_3_offset.h"
#include "discovery.h"

#define mmRCC_CONFIG_MEMSIZE	0xde3
#define mmMM_INDEX		0x0
#define mmMM_INDEX_HI		0x6
#define mmMM_DATA		0x1
#define HW_ID_MAX		300

const char *hw_id_names[HW_ID_MAX] = {
	[MP1_HWID]		= "MP1",
	[MP2_HWID]		= "MP2",
	[THM_HWID]		= "THM",
	[SMUIO_HWID]		= "SMUIO",
	[FUSE_HWID]		= "FUSE",
	[CLKA_HWID]		= "CLKA",
	[PWR_HWID]		= "PWR",
	[GC_HWID]		= "GC",
	[UVD_HWID]		= "UVD",
	[AUDIO_AZ_HWID]		= "AUDIO_AZ",
	[ACP_HWID]		= "ACP",
	[DCI_HWID]		= "DCI",
	[DMU_HWID]		= "DMU",
	[DCO_HWID]		= "DCO",
	[DIO_HWID]		= "DIO",
	[XDMA_HWID]		= "XDMA",
	[DCEAZ_HWID]		= "DCEAZ",
	[DAZ_HWID]		= "DAZ",
	[SDPMUX_HWID]		= "SDPMUX",
	[NTB_HWID]		= "NTB",
	[IOHC_HWID]		= "IOHC",
	[L2IMU_HWID]		= "L2IMU",
	[VCE_HWID]		= "VCE",
	[MMHUB_HWID]		= "MMHUB",
	[ATHUB_HWID]		= "ATHUB",
	[DBGU_NBIO_HWID]	= "DBGU_NBIO",
	[DFX_HWID]		= "DFX",
	[DBGU0_HWID]		= "DBGU0",
	[DBGU1_HWID]		= "DBGU1",
	[OSSSYS_HWID]		= "OSSSYS",
	[HDP_HWID]		= "HDP",
	[SDMA0_HWID]		= "SDMA0",
	[SDMA1_HWID]		= "SDMA1",
	[ISP_HWID]		= "ISP",
	[DBGU_IO_HWID]		= "DBGU_IO",
	[DF_HWID]		= "DF",
	[CLKB_HWID]		= "CLKB",
	[FCH_HWID]		= "FCH",
	[DFX_DAP_HWID]		= "DFX_DAP",
	[L1IMU_PCIE_HWID]	= "L1IMU_PCIE",
	[L1IMU_NBIF_HWID]	= "L1IMU_NBIF",
	[L1IMU_IOAGR_HWID]	= "L1IMU_IOAGR",
	[L1IMU3_HWID]		= "L1IMU3",
	[L1IMU4_HWID]		= "L1IMU4",
	[L1IMU5_HWID]		= "L1IMU5",
	[L1IMU6_HWID]		= "L1IMU6",
	[L1IMU7_HWID]		= "L1IMU7",
	[L1IMU8_HWID]		= "L1IMU8",
	[L1IMU9_HWID]		= "L1IMU9",
	[L1IMU10_HWID]		= "L1IMU10",
	[L1IMU11_HWID]		= "L1IMU11",
	[L1IMU12_HWID]		= "L1IMU12",
	[L1IMU13_HWID]		= "L1IMU13",
	[L1IMU14_HWID]		= "L1IMU14",
	[L1IMU15_HWID]		= "L1IMU15",
	[WAFLC_HWID]		= "WAFLC",
	[FCH_USB_PD_HWID]	= "FCH_USB_PD",
	[PCIE_HWID]		= "PCIE",
	[PCS_HWID]		= "PCS",
	[DDCL_HWID]		= "DDCL",
	[SST_HWID]		= "SST",
	[IOAGR_HWID]		= "IOAGR",
	[NBIF_HWID]		= "NBIF",
	[IOAPIC_HWID]		= "IOAPIC",
	[SYSTEMHUB_HWID]	= "SYSTEMHUB",
	[NTBCCP_HWID]		= "NTBCCP",
	[UMC_HWID]		= "UMC",
	[SATA_HWID]		= "SATA",
	[USB_HWID]		= "USB",
	[CCXSEC_HWID]		= "CCXSEC",
	[XGMI_HWID]		= "XGMI",
	[XGBE_HWID]		= "XGBE",
	[MP0_HWID]		= "MP0",
};

static int hw_id_map[MAX_HWIP] = {
	[GC_HWIP]	= GC_HWID,
	[HDP_HWIP]	= HDP_HWID,
	[SDMA0_HWIP]	= SDMA0_HWID,
	[SDMA1_HWIP]	= SDMA1_HWID,
	[MMHUB_HWIP]	= MMHUB_HWID,
	[ATHUB_HWIP]	= ATHUB_HWID,
	[NBIO_HWIP]	= NBIF_HWID,
	[MP0_HWIP]	= MP0_HWID,
	[MP1_HWIP]	= MP1_HWID,
	[UVD_HWIP]	= UVD_HWID,
	[VCE_HWIP]	= VCE_HWID,
	[DF_HWIP]	= DF_HWID,
	[DCE_HWIP]	= DMU_HWID,
	[OSSSYS_HWIP]	= OSSSYS_HWID,
	[SMUIO_HWIP]	= SMUIO_HWID,
	[PWR_HWIP]	= PWR_HWID,
	[NBIF_HWIP]	= NBIF_HWID,
	[THM_HWIP]	= THM_HWID,
	[CLK_HWIP]	= CLKA_HWID,
};

static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
{
	uint32_t *p = (uint32_t *)binary;
	uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
	uint64_t pos = vram_size - BINARY_MAX_SIZE;
	unsigned long flags;

	while (pos < vram_size) {
		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
		WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
		WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
		*p++ = RREG32_NO_KIQ(mmMM_DATA);
		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
		pos += 4;
	}

	return 0;
}

static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
{
	uint16_t checksum = 0;
	int i;

	for (i = 0; i < size; i++)
		checksum += data[i];

	return checksum;
}

static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
						    uint16_t expected)
{
	return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
}

int amdgpu_discovery_init(struct amdgpu_device *adev)
{
	struct table_info *info;
	struct binary_header *bhdr;
	struct ip_discovery_header *ihdr;
	struct gpu_info_header *ghdr;
	uint16_t offset;
	uint16_t size;
	uint16_t checksum;
	int r;

	adev->discovery = kzalloc(BINARY_MAX_SIZE, GFP_KERNEL);
	if (!adev->discovery)
		return -ENOMEM;

	r = amdgpu_discovery_read_binary(adev, adev->discovery);
	if (r) {
		DRM_ERROR("failed to read ip discovery binary\n");
		goto out;
	}

	bhdr = (struct binary_header *)adev->discovery;

	if (le32_to_cpu(bhdr->binary_signature) != BINARY_SIGNATURE) {
		DRM_ERROR("invalid ip discovery binary signature\n");
		r = -EINVAL;
		goto out;
	}

	offset = offsetof(struct binary_header, binary_checksum) +
		sizeof(bhdr->binary_checksum);
	size = bhdr->binary_size - offset;
	checksum = bhdr->binary_checksum;

	if (!amdgpu_discovery_verify_checksum(adev->discovery + offset,
					      size, checksum)) {
		DRM_ERROR("invalid ip discovery binary checksum\n");
		r = -EINVAL;
		goto out;
	}

	info = &bhdr->table_list[IP_DISCOVERY];
	offset = le16_to_cpu(info->offset);
	checksum = le16_to_cpu(info->checksum);
	ihdr = (struct ip_discovery_header *)(adev->discovery + offset);

	if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
		DRM_ERROR("invalid ip discovery data table signature\n");
		r = -EINVAL;
		goto out;
	}

	if (!amdgpu_discovery_verify_checksum(adev->discovery + offset,
					      ihdr->size, checksum)) {
		DRM_ERROR("invalid ip discovery data table checksum\n");
		r = -EINVAL;
		goto out;
	}

	info = &bhdr->table_list[GC];
	offset = le16_to_cpu(info->offset);
	checksum = le16_to_cpu(info->checksum);
	ghdr = (struct gpu_info_header *)(adev->discovery + offset);

	if (!amdgpu_discovery_verify_checksum(adev->discovery + offset,
				              ghdr->size, checksum)) {
		DRM_ERROR("invalid gc data table checksum\n");
		r = -EINVAL;
		goto out;
	}

	return 0;

out:
	kfree(adev->discovery);
	adev->discovery = NULL;

	return r;
}

void amdgpu_discovery_fini(struct amdgpu_device *adev)
{
	kfree(adev->discovery);
	adev->discovery = NULL;
}

int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
{
	struct binary_header *bhdr;
	struct ip_discovery_header *ihdr;
	struct die_header *dhdr;
	struct ip *ip;
	uint16_t die_offset;
	uint16_t ip_offset;
	uint16_t num_dies;
	uint16_t num_ips;
	uint8_t num_base_address;
	int hw_ip;
	int i, j, k;

	if (!adev->discovery) {
		DRM_ERROR("ip discovery uninitialized\n");
		return -EINVAL;
	}

	bhdr = (struct binary_header *)adev->discovery;
	ihdr = (struct ip_discovery_header *)(adev->discovery +
			le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
	num_dies = le16_to_cpu(ihdr->num_dies);

	DRM_DEBUG("number of dies: %d\n", num_dies);

	for (i = 0; i < num_dies; i++) {
		die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
		dhdr = (struct die_header *)(adev->discovery + die_offset);
		num_ips = le16_to_cpu(dhdr->num_ips);
		ip_offset = die_offset + sizeof(*dhdr);

		if (le16_to_cpu(dhdr->die_id) != i) {
			DRM_ERROR("invalid die id %d, expected %d\n",
					le16_to_cpu(dhdr->die_id), i);
			return -EINVAL;
		}

		DRM_DEBUG("number of hardware IPs on die%d: %d\n",
				le16_to_cpu(dhdr->die_id), num_ips);

		for (j = 0; j < num_ips; j++) {
			ip = (struct ip *)(adev->discovery + ip_offset);
			num_base_address = ip->num_base_address;

			DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
				  hw_id_names[le16_to_cpu(ip->hw_id)],
				  le16_to_cpu(ip->hw_id),
				  ip->number_instance,
				  ip->major, ip->minor,
				  ip->revision);

			for (k = 0; k < num_base_address; k++) {
				/*
				 * convert the endianness of base addresses in place,
				 * so that we don't need to convert them when accessing adev->reg_offset.
				 */
				ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
				DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
			}

			for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
				if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
					DRM_INFO("set register base offset for %s\n",
							hw_id_names[le16_to_cpu(ip->hw_id)]);
					adev->reg_offset[hw_ip][ip->number_instance] =
						ip->base_address;
				}

			}

			ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
		}
	}

	return 0;
}

int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
				    int *major, int *minor)
{
	struct binary_header *bhdr;
	struct ip_discovery_header *ihdr;
	struct die_header *dhdr;
	struct ip *ip;
	uint16_t die_offset;
	uint16_t ip_offset;
	uint16_t num_dies;
	uint16_t num_ips;
	int i, j;

	if (!adev->discovery) {
		DRM_ERROR("ip discovery uninitialized\n");
		return -EINVAL;
	}

	bhdr = (struct binary_header *)adev->discovery;
	ihdr = (struct ip_discovery_header *)(adev->discovery +
			le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
	num_dies = le16_to_cpu(ihdr->num_dies);

	for (i = 0; i < num_dies; i++) {
		die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
		dhdr = (struct die_header *)(adev->discovery + die_offset);
		num_ips = le16_to_cpu(dhdr->num_ips);
		ip_offset = die_offset + sizeof(*dhdr);

		for (j = 0; j < num_ips; j++) {
			ip = (struct ip *)(adev->discovery + ip_offset);

			if (le16_to_cpu(ip->hw_id) == hw_id) {
				if (major)
					*major = ip->major;
				if (minor)
					*minor = ip->minor;
				return 0;
			}
			ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
		}
	}

	return -EINVAL;
}

int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
{
	struct binary_header *bhdr;
	struct gc_info_v1_0 *gc_info;

	if (!adev->discovery) {
		DRM_ERROR("ip discovery uninitialized\n");
		return -EINVAL;
	}

	bhdr = (struct binary_header *)adev->discovery;
	gc_info = (struct gc_info_v1_0 *)(adev->discovery +
			le16_to_cpu(bhdr->table_list[GC].offset));

	adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
	adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
					      le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
	adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
	adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
	adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
	adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
	adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
	adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
	adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
	adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
	adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
	adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
	adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
	adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
	adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
					 le32_to_cpu(gc_info->gc_num_sa_per_se);
	adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);

	return 0;
}
Commit	Line	Data
f39f5bb1 XY	1	/*
	2	* Copyright 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#include "amdgpu.h"
	25	#include "amdgpu_discovery.h"
	26	#include "soc15_common.h"
	27	#include "soc15_hw_ip.h"
	28	#include "nbio/nbio_2_3_offset.h"
	29	#include "discovery.h"
	30
85f267a7 XY	31	#define mmRCC_CONFIG_MEMSIZE 0xde3
	32	#define mmMM_INDEX 0x0
	33	#define mmMM_INDEX_HI 0x6
	34	#define mmMM_DATA 0x1
	35	#define HW_ID_MAX 300
f39f5bb1 XY	36
	37	const char *hw_id_names[HW_ID_MAX] = {
	38	[MP1_HWID] = "MP1",
	39	[MP2_HWID] = "MP2",
	40	[THM_HWID] = "THM",
	41	[SMUIO_HWID] = "SMUIO",
	42	[FUSE_HWID] = "FUSE",
	43	[CLKA_HWID] = "CLKA",
	44	[PWR_HWID] = "PWR",
	45	[GC_HWID] = "GC",
	46	[UVD_HWID] = "UVD",
	47	[AUDIO_AZ_HWID] = "AUDIO_AZ",
	48	[ACP_HWID] = "ACP",
	49	[DCI_HWID] = "DCI",
	50	[DMU_HWID] = "DMU",
	51	[DCO_HWID] = "DCO",
	52	[DIO_HWID] = "DIO",
	53	[XDMA_HWID] = "XDMA",
	54	[DCEAZ_HWID] = "DCEAZ",
	55	[DAZ_HWID] = "DAZ",
	56	[SDPMUX_HWID] = "SDPMUX",
	57	[NTB_HWID] = "NTB",
	58	[IOHC_HWID] = "IOHC",
	59	[L2IMU_HWID] = "L2IMU",
	60	[VCE_HWID] = "VCE",
	61	[MMHUB_HWID] = "MMHUB",
	62	[ATHUB_HWID] = "ATHUB",
	63	[DBGU_NBIO_HWID] = "DBGU_NBIO",
	64	[DFX_HWID] = "DFX",
	65	[DBGU0_HWID] = "DBGU0",
	66	[DBGU1_HWID] = "DBGU1",
	67	[OSSSYS_HWID] = "OSSSYS",
	68	[HDP_HWID] = "HDP",
	69	[SDMA0_HWID] = "SDMA0",
	70	[SDMA1_HWID] = "SDMA1",
	71	[ISP_HWID] = "ISP",
	72	[DBGU_IO_HWID] = "DBGU_IO",
	73	[DF_HWID] = "DF",
	74	[CLKB_HWID] = "CLKB",
	75	[FCH_HWID] = "FCH",
	76	[DFX_DAP_HWID] = "DFX_DAP",
	77	[L1IMU_PCIE_HWID] = "L1IMU_PCIE",
	78	[L1IMU_NBIF_HWID] = "L1IMU_NBIF",
	79	[L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
	80	[L1IMU3_HWID] = "L1IMU3",
	81	[L1IMU4_HWID] = "L1IMU4",
	82	[L1IMU5_HWID] = "L1IMU5",
	83	[L1IMU6_HWID] = "L1IMU6",
	84	[L1IMU7_HWID] = "L1IMU7",
	85	[L1IMU8_HWID] = "L1IMU8",
	86	[L1IMU9_HWID] = "L1IMU9",
	87	[L1IMU10_HWID] = "L1IMU10",
	88	[L1IMU11_HWID] = "L1IMU11",
	89	[L1IMU12_HWID] = "L1IMU12",
	90	[L1IMU13_HWID] = "L1IMU13",
	91	[L1IMU14_HWID] = "L1IMU14",
	92	[L1IMU15_HWID] = "L1IMU15",
	93	[WAFLC_HWID] = "WAFLC",
	94	[FCH_USB_PD_HWID] = "FCH_USB_PD",
	95	[PCIE_HWID] = "PCIE",
	96	[PCS_HWID] = "PCS",
	97	[DDCL_HWID] = "DDCL",
	98	[SST_HWID] = "SST",
	99	[IOAGR_HWID] = "IOAGR",
100	[NBIF_HWID] = "NBIF",
101	[IOAPIC_HWID] = "IOAPIC",
102	[SYSTEMHUB_HWID] = "SYSTEMHUB",
103	[NTBCCP_HWID] = "NTBCCP",
104	[UMC_HWID] = "UMC",
105	[SATA_HWID] = "SATA",
106	[USB_HWID] = "USB",
107	[CCXSEC_HWID] = "CCXSEC",
108	[XGMI_HWID] = "XGMI",
109	[XGBE_HWID] = "XGBE",
110	[MP0_HWID] = "MP0",
111	};
112
113	static int hw_id_map[MAX_HWIP] = {
114	[GC_HWIP] = GC_HWID,
115	[HDP_HWIP] = HDP_HWID,
116	[SDMA0_HWIP] = SDMA0_HWID,
117	[SDMA1_HWIP] = SDMA1_HWID,
118	[MMHUB_HWIP] = MMHUB_HWID,
119	[ATHUB_HWIP] = ATHUB_HWID,
2de00413	120	[NBIO_HWIP] = NBIF_HWID,
f39f5bb1 XY	121	[MP0_HWIP] = MP0_HWID,
	122	[MP1_HWIP] = MP1_HWID,
	123	[UVD_HWIP] = UVD_HWID,
	124	[VCE_HWIP] = VCE_HWID,
	125	[DF_HWIP] = DF_HWID,
a349b392	126	[DCE_HWIP] = DMU_HWID,
f39f5bb1 XY	127	[OSSSYS_HWIP] = OSSSYS_HWID,
	128	[SMUIO_HWIP] = SMUIO_HWID,
	129	[PWR_HWIP] = PWR_HWID,
	130	[NBIF_HWIP] = NBIF_HWID,
	131	[THM_HWIP] = THM_HWID,
	132	[CLK_HWIP] = CLKA_HWID,
	133	};
	134
	135	static int amdgpu_discovery_read_binary(struct amdgpu_device adev, uint8_t binary)
	136	{
	137	uint32_t p = (uint32_t )binary;
85f267a7	138	uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
f39f5bb1 XY	139	uint64_t pos = vram_size - BINARY_MAX_SIZE;
	140	unsigned long flags;
	141
	142	while (pos < vram_size) {
	143	spin_lock_irqsave(&adev->mmio_idx_lock, flags);
	144	WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) \| 0x80000000);
	145	WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
	146	*p++ = RREG32_NO_KIQ(mmMM_DATA);
	147	spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
	148	pos += 4;
	149	}
	150
	151	return 0;
	152	}
	153
	154	static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
	155	{
	156	uint16_t checksum = 0;
	157	int i;
	158
	159	for (i = 0; i < size; i++)
	160	checksum += data[i];
	161
	162	return checksum;
	163	}
	164
	165	static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
	166	uint16_t expected)
	167	{
	168	return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
	169	}
	170
	171	int amdgpu_discovery_init(struct amdgpu_device *adev)
	172	{
	173	struct table_info *info;
	174	struct binary_header *bhdr;
	175	struct ip_discovery_header *ihdr;
	176	struct gpu_info_header *ghdr;
	177	uint16_t offset;
	178	uint16_t size;
	179	uint16_t checksum;
	180	int r;
	181
	182	adev->discovery = kzalloc(BINARY_MAX_SIZE, GFP_KERNEL);
	183	if (!adev->discovery)
	184	return -ENOMEM;
	185
	186	r = amdgpu_discovery_read_binary(adev, adev->discovery);
	187	if (r) {
	188	DRM_ERROR("failed to read ip discovery binary\n");
	189	goto out;
	190	}
	191
8e84aa1b	192	bhdr = (struct binary_header *)adev->discovery;
f39f5bb1 XY	193
	194	if (le32_to_cpu(bhdr->binary_signature) != BINARY_SIGNATURE) {
	195	DRM_ERROR("invalid ip discovery binary signature\n");
	196	r = -EINVAL;
	197	goto out;
	198	}
	199
8e84aa1b	200	offset = offsetof(struct binary_header, binary_checksum) +
f39f5bb1 XY	201	sizeof(bhdr->binary_checksum);
	202	size = bhdr->binary_size - offset;
	203	checksum = bhdr->binary_checksum;
	204
	205	if (!amdgpu_discovery_verify_checksum(adev->discovery + offset,
	206	size, checksum)) {
	207	DRM_ERROR("invalid ip discovery binary checksum\n");
	208	r = -EINVAL;
	209	goto out;
	210	}
	211
	212	info = &bhdr->table_list[IP_DISCOVERY];
	213	offset = le16_to_cpu(info->offset);
	214	checksum = le16_to_cpu(info->checksum);
	215	ihdr = (struct ip_discovery_header *)(adev->discovery + offset);
	216
	217	if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
	218	DRM_ERROR("invalid ip discovery data table signature\n");
	219	r = -EINVAL;
	220	goto out;
	221	}
	222
	223	if (!amdgpu_discovery_verify_checksum(adev->discovery + offset,
	224	ihdr->size, checksum)) {
	225	DRM_ERROR("invalid ip discovery data table checksum\n");
	226	r = -EINVAL;
	227	goto out;
	228	}
	229
	230	info = &bhdr->table_list[GC];
	231	offset = le16_to_cpu(info->offset);
	232	checksum = le16_to_cpu(info->checksum);
	233	ghdr = (struct gpu_info_header *)(adev->discovery + offset);
	234
	235	if (!amdgpu_discovery_verify_checksum(adev->discovery + offset,
	236	ghdr->size, checksum)) {
	237	DRM_ERROR("invalid gc data table checksum\n");
	238	r = -EINVAL;
	239	goto out;
	240	}
	241
	242	return 0;
	243
	244	out:
	245	kfree(adev->discovery);
	246	adev->discovery = NULL;
	247
	248	return r;
	249	}
	250
	251	void amdgpu_discovery_fini(struct amdgpu_device *adev)
	252	{
	253	kfree(adev->discovery);
	254	adev->discovery = NULL;
	255	}
	256
	257	int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
	258	{
	259	struct binary_header *bhdr;
	260	struct ip_discovery_header *ihdr;
	261	struct die_header *dhdr;
	262	struct ip *ip;
	263	uint16_t die_offset;
	264	uint16_t ip_offset;
265	uint16_t num_dies;
266	uint16_t num_ips;
267	uint8_t num_base_address;
268	int hw_ip;
f39f5bb1 XY	269	int i, j, k;
	270
	271	if (!adev->discovery) {
	272	DRM_ERROR("ip discovery uninitialized\n");
	273	return -EINVAL;
	274	}
	275
8e84aa1b	276	bhdr = (struct binary_header *)adev->discovery;
f39f5bb1 XY	277	ihdr = (struct ip_discovery_header *)(adev->discovery +
	278	le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
	279	num_dies = le16_to_cpu(ihdr->num_dies);
	280
437298b8	281	DRM_DEBUG("number of dies: %d\n", num_dies);
f39f5bb1	282
437298b8 XY	283	for (i = 0; i < num_dies; i++) {
	284	die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
	285	dhdr = (struct die_header *)(adev->discovery + die_offset);
	286	num_ips = le16_to_cpu(dhdr->num_ips);
	287	ip_offset = die_offset + sizeof(*dhdr);
	288
	289	if (le16_to_cpu(dhdr->die_id) != i) {
	290	DRM_ERROR("invalid die id %d, expected %d\n",
	291	le16_to_cpu(dhdr->die_id), i);
	292	return -EINVAL;
	293	}
	294
	295	DRM_DEBUG("number of hardware IPs on die%d: %d\n",
	296	le16_to_cpu(dhdr->die_id), num_ips);
	297
	298	for (j = 0; j < num_ips; j++) {
	299	ip = (struct ip *)(adev->discovery + ip_offset);
	300	num_base_address = ip->num_base_address;
	301
	302	DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
	303	hw_id_names[le16_to_cpu(ip->hw_id)],
	304	le16_to_cpu(ip->hw_id),
	305	ip->number_instance,
	306	ip->major, ip->minor,
	307	ip->revision);
	308
	309	for (k = 0; k < num_base_address; k++) {
	310	/*
	311	* convert the endianness of base addresses in place,
	312	* so that we don't need to convert them when accessing adev->reg_offset.
	313	*/
	314	ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
	315	DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
	316	}
	317
	318	for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
	319	if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
	320	DRM_INFO("set register base offset for %s\n",
	321	hw_id_names[le16_to_cpu(ip->hw_id)]);
f39f5bb1 XY	322	adev->reg_offset[hw_ip][ip->number_instance] =
	323	ip->base_address;
	324	}
	325
f39f5bb1	326	}
437298b8 XY	327
437298b8 XY	328	ip_offset += sizeof(ip) + 4 (ip->num_base_address - 1);
f39f5bb1 XY	329	}
	330	}
	331
	332	return 0;
	333	}
	334
	335	int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
	336	int major, int minor)
	337	{
	338	struct binary_header *bhdr;
	339	struct ip_discovery_header *ihdr;
	340	struct die_header *dhdr;
	341	struct ip *ip;
	342	uint16_t die_offset;
	343	uint16_t ip_offset;
	344	uint16_t num_dies;
	345	uint16_t num_ips;
	346	int i, j;
	347
	348	if (!adev->discovery) {
	349	DRM_ERROR("ip discovery uninitialized\n");
	350	return -EINVAL;
	351	}
	352
8e84aa1b	353	bhdr = (struct binary_header *)adev->discovery;
f39f5bb1 XY	354	ihdr = (struct ip_discovery_header *)(adev->discovery +
	355	le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
	356	num_dies = le16_to_cpu(ihdr->num_dies);
	357
	358	for (i = 0; i < num_dies; i++) {
	359	die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
	360	dhdr = (struct die_header *)(adev->discovery + die_offset);
	361	num_ips = le16_to_cpu(dhdr->num_ips);
	362	ip_offset = die_offset + sizeof(*dhdr);
	363
	364	for (j = 0; j < num_ips; j++) {
	365	ip = (struct ip *)(adev->discovery + ip_offset);
	366
	367	if (le16_to_cpu(ip->hw_id) == hw_id) {
	368	if (major)
	369	*major = ip->major;
	370	if (minor)
	371	*minor = ip->minor;
	372	return 0;
	373	}
	374	ip_offset += sizeof(ip) + 4 (ip->num_base_address - 1);
	375	}
	376	}
	377
	378	return -EINVAL;
	379	}
	380
	381	int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
	382	{
	383	struct binary_header *bhdr;
	384	struct gc_info_v1_0 *gc_info;
	385
	386	if (!adev->discovery) {
	387	DRM_ERROR("ip discovery uninitialized\n");
	388	return -EINVAL;
	389	}
	390
8e84aa1b	391	bhdr = (struct binary_header *)adev->discovery;
f39f5bb1 XY	392	gc_info = (struct gc_info_v1_0 *)(adev->discovery +
	393	le16_to_cpu(bhdr->table_list[GC].offset));
	394
	395	adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
987da729 XY	396	adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
	397	le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
	398	adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
f39f5bb1 XY	399	adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
	400	adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
	401	adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
	402	adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
	403	adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
	404	adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
	405	adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
	406	adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
	407	adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
	408	adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
	409	adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
987da729 XY	410	adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
	411	le32_to_cpu(gc_info->gc_num_sa_per_se);
	412	adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);
f39f5bb1 XY	413
	414	return 0;
	415	}