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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include <drm/drmP.h> | |
27 | #include <drm/amdgpu_drm.h> | |
28 | #include "amdgpu.h" | |
29 | #include "amdgpu_i2c.h" | |
30 | #include "atom.h" | |
31 | #include "amdgpu_connectors.h" | |
5d43be0c | 32 | #include "amdgpu_display.h" |
d38ceaf9 AD |
33 | #include <asm/div64.h> |
34 | ||
35 | #include <linux/pm_runtime.h> | |
36 | #include <drm/drm_crtc_helper.h> | |
37 | #include <drm/drm_edid.h> | |
ab77e02c | 38 | #include <drm/drm_fb_helper.h> |
d38ceaf9 | 39 | |
3a05dc00 SL |
40 | static void amdgpu_display_flip_callback(struct dma_fence *f, |
41 | struct dma_fence_cb *cb) | |
1ffd2652 | 42 | { |
c3874b75 CK |
43 | struct amdgpu_flip_work *work = |
44 | container_of(cb, struct amdgpu_flip_work, cb); | |
1ffd2652 | 45 | |
f54d1867 | 46 | dma_fence_put(f); |
325cbba1 | 47 | schedule_work(&work->flip_work.work); |
c3874b75 | 48 | } |
1ffd2652 | 49 | |
3a05dc00 SL |
50 | static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, |
51 | struct dma_fence **f) | |
c3874b75 | 52 | { |
f54d1867 | 53 | struct dma_fence *fence= *f; |
c3874b75 CK |
54 | |
55 | if (fence == NULL) | |
56 | return false; | |
1ffd2652 | 57 | |
1ffd2652 | 58 | *f = NULL; |
c3874b75 | 59 | |
3a05dc00 SL |
60 | if (!dma_fence_add_callback(fence, &work->cb, |
61 | amdgpu_display_flip_callback)) | |
c3874b75 CK |
62 | return true; |
63 | ||
f54d1867 | 64 | dma_fence_put(fence); |
c3874b75 | 65 | return false; |
1ffd2652 | 66 | } |
d38ceaf9 | 67 | |
3a05dc00 | 68 | static void amdgpu_display_flip_work_func(struct work_struct *__work) |
d38ceaf9 | 69 | { |
325cbba1 MD |
70 | struct delayed_work *delayed_work = |
71 | container_of(__work, struct delayed_work, work); | |
d38ceaf9 | 72 | struct amdgpu_flip_work *work = |
325cbba1 | 73 | container_of(delayed_work, struct amdgpu_flip_work, flip_work); |
d38ceaf9 | 74 | struct amdgpu_device *adev = work->adev; |
f93932bc | 75 | struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; |
d38ceaf9 | 76 | |
f93932bc | 77 | struct drm_crtc *crtc = &amdgpu_crtc->base; |
d38ceaf9 | 78 | unsigned long flags; |
325cbba1 MD |
79 | unsigned i; |
80 | int vpos, hpos; | |
d38ceaf9 | 81 | |
3a05dc00 | 82 | if (amdgpu_display_flip_handle_fence(work, &work->excl)) |
c3874b75 CK |
83 | return; |
84 | ||
1ffd2652 | 85 | for (i = 0; i < work->shared_count; ++i) |
3a05dc00 | 86 | if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) |
c3874b75 | 87 | return; |
d38ceaf9 | 88 | |
325cbba1 MD |
89 | /* Wait until we're out of the vertical blank period before the one |
90 | * targeted by the flip | |
8e36f9d3 | 91 | */ |
f93932bc | 92 | if (amdgpu_crtc->enabled && |
325cbba1 MD |
93 | (amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0, |
94 | &vpos, &hpos, NULL, NULL, | |
95 | &crtc->hwmode) | |
96 | & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == | |
97 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && | |
98 | (int)(work->target_vblank - | |
f93932bc | 99 | amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) { |
325cbba1 MD |
100 | schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); |
101 | return; | |
9c3578af | 102 | } |
8e36f9d3 | 103 | |
325cbba1 MD |
104 | /* We borrow the event spin lock for protecting flip_status */ |
105 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
e1d09dc0 | 106 | |
bd4c72d1 | 107 | /* Do the flip (mmio) */ |
cb9e59d7 | 108 | adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); |
bd4c72d1 AG |
109 | |
110 | /* Set the flip status */ | |
f93932bc | 111 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; |
d38ceaf9 | 112 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
6bd9e877 | 113 | |
bd4c72d1 AG |
114 | |
115 | DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", | |
f93932bc | 116 | amdgpu_crtc->crtc_id, amdgpu_crtc, work); |
bd4c72d1 | 117 | |
d38ceaf9 AD |
118 | } |
119 | ||
120 | /* | |
121 | * Handle unpin events outside the interrupt handler proper. | |
122 | */ | |
3a05dc00 | 123 | static void amdgpu_display_unpin_work_func(struct work_struct *__work) |
d38ceaf9 AD |
124 | { |
125 | struct amdgpu_flip_work *work = | |
126 | container_of(__work, struct amdgpu_flip_work, unpin_work); | |
127 | int r; | |
128 | ||
129 | /* unpin of the old buffer */ | |
c81a1a74 | 130 | r = amdgpu_bo_reserve(work->old_abo, true); |
d38ceaf9 | 131 | if (likely(r == 0)) { |
765e7fbf | 132 | r = amdgpu_bo_unpin(work->old_abo); |
d38ceaf9 AD |
133 | if (unlikely(r != 0)) { |
134 | DRM_ERROR("failed to unpin buffer after flip\n"); | |
135 | } | |
765e7fbf | 136 | amdgpu_bo_unreserve(work->old_abo); |
d38ceaf9 AD |
137 | } else |
138 | DRM_ERROR("failed to reserve buffer after flip\n"); | |
139 | ||
765e7fbf | 140 | amdgpu_bo_unref(&work->old_abo); |
1ffd2652 | 141 | kfree(work->shared); |
d38ceaf9 AD |
142 | kfree(work); |
143 | } | |
144 | ||
0cd11932 SL |
145 | int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, |
146 | struct drm_framebuffer *fb, | |
147 | struct drm_pending_vblank_event *event, | |
148 | uint32_t page_flip_flags, uint32_t target, | |
149 | struct drm_modeset_acquire_ctx *ctx) | |
d38ceaf9 AD |
150 | { |
151 | struct drm_device *dev = crtc->dev; | |
152 | struct amdgpu_device *adev = dev->dev_private; | |
153 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
154 | struct amdgpu_framebuffer *old_amdgpu_fb; | |
155 | struct amdgpu_framebuffer *new_amdgpu_fb; | |
156 | struct drm_gem_object *obj; | |
157 | struct amdgpu_flip_work *work; | |
765e7fbf | 158 | struct amdgpu_bo *new_abo; |
d38ceaf9 AD |
159 | unsigned long flags; |
160 | u64 tiling_flags; | |
161 | u64 base; | |
5f42aa39 | 162 | int i, r; |
d38ceaf9 AD |
163 | |
164 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
165 | if (work == NULL) | |
166 | return -ENOMEM; | |
167 | ||
3a05dc00 SL |
168 | INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); |
169 | INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); | |
d38ceaf9 AD |
170 | |
171 | work->event = event; | |
172 | work->adev = adev; | |
173 | work->crtc_id = amdgpu_crtc->crtc_id; | |
cb9e59d7 | 174 | work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; |
d38ceaf9 AD |
175 | |
176 | /* schedule unpin of the old buffer */ | |
177 | old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); | |
178 | obj = old_amdgpu_fb->obj; | |
179 | ||
180 | /* take a reference to the old object */ | |
765e7fbf CK |
181 | work->old_abo = gem_to_amdgpu_bo(obj); |
182 | amdgpu_bo_ref(work->old_abo); | |
d38ceaf9 AD |
183 | |
184 | new_amdgpu_fb = to_amdgpu_framebuffer(fb); | |
185 | obj = new_amdgpu_fb->obj; | |
765e7fbf | 186 | new_abo = gem_to_amdgpu_bo(obj); |
d38ceaf9 AD |
187 | |
188 | /* pin the new buffer */ | |
765e7fbf | 189 | r = amdgpu_bo_reserve(new_abo, false); |
d38ceaf9 | 190 | if (unlikely(r != 0)) { |
765e7fbf | 191 | DRM_ERROR("failed to reserve new abo buffer before flip\n"); |
d38ceaf9 AD |
192 | goto cleanup; |
193 | } | |
194 | ||
5d43be0c | 195 | r = amdgpu_bo_pin(new_abo, amdgpu_display_framebuffer_domains(adev), &base); |
d38ceaf9 | 196 | if (unlikely(r != 0)) { |
765e7fbf | 197 | DRM_ERROR("failed to pin new abo buffer before flip\n"); |
ee7fd957 | 198 | goto unreserve; |
d38ceaf9 AD |
199 | } |
200 | ||
765e7fbf | 201 | r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl, |
1ffd2652 CK |
202 | &work->shared_count, |
203 | &work->shared); | |
204 | if (unlikely(r != 0)) { | |
1ffd2652 | 205 | DRM_ERROR("failed to get fences for buffer\n"); |
ee7fd957 | 206 | goto unpin; |
1ffd2652 CK |
207 | } |
208 | ||
765e7fbf CK |
209 | amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); |
210 | amdgpu_bo_unreserve(new_abo); | |
d38ceaf9 AD |
211 | |
212 | work->base = base; | |
325cbba1 MD |
213 | work->target_vblank = target - drm_crtc_vblank_count(crtc) + |
214 | amdgpu_get_vblank_counter_kms(dev, work->crtc_id); | |
d38ceaf9 AD |
215 | |
216 | /* we borrow the event spin lock for protecting flip_wrok */ | |
217 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
218 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { | |
219 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
220 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
221 | r = -EBUSY; | |
325cbba1 | 222 | goto pflip_cleanup; |
d38ceaf9 AD |
223 | } |
224 | ||
225 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; | |
226 | amdgpu_crtc->pflip_works = work; | |
227 | ||
5f42aa39 HW |
228 | |
229 | DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", | |
230 | amdgpu_crtc->crtc_id, amdgpu_crtc, work); | |
d38ceaf9 AD |
231 | /* update crtc fb */ |
232 | crtc->primary->fb = fb; | |
233 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
3a05dc00 | 234 | amdgpu_display_flip_work_func(&work->flip_work.work); |
5f42aa39 | 235 | return 0; |
d38ceaf9 | 236 | |
5f42aa39 HW |
237 | pflip_cleanup: |
238 | if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { | |
239 | DRM_ERROR("failed to reserve new abo in error path\n"); | |
240 | goto cleanup; | |
241 | } | |
242 | unpin: | |
243 | if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { | |
244 | DRM_ERROR("failed to unpin new abo in error path\n"); | |
245 | } | |
246 | unreserve: | |
247 | amdgpu_bo_unreserve(new_abo); | |
cb341a31 | 248 | |
5f42aa39 HW |
249 | cleanup: |
250 | amdgpu_bo_unref(&work->old_abo); | |
251 | dma_fence_put(work->excl); | |
252 | for (i = 0; i < work->shared_count; ++i) | |
253 | dma_fence_put(work->shared[i]); | |
254 | kfree(work->shared); | |
255 | kfree(work); | |
9c5b2b0d | 256 | |
5f42aa39 | 257 | return r; |
d38ceaf9 AD |
258 | } |
259 | ||
a4eff9aa DV |
260 | int amdgpu_crtc_set_config(struct drm_mode_set *set, |
261 | struct drm_modeset_acquire_ctx *ctx) | |
d38ceaf9 AD |
262 | { |
263 | struct drm_device *dev; | |
264 | struct amdgpu_device *adev; | |
265 | struct drm_crtc *crtc; | |
266 | bool active = false; | |
267 | int ret; | |
268 | ||
269 | if (!set || !set->crtc) | |
270 | return -EINVAL; | |
271 | ||
272 | dev = set->crtc->dev; | |
273 | ||
274 | ret = pm_runtime_get_sync(dev->dev); | |
275 | if (ret < 0) | |
276 | return ret; | |
277 | ||
a4eff9aa | 278 | ret = drm_crtc_helper_set_config(set, ctx); |
d38ceaf9 AD |
279 | |
280 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
281 | if (crtc->enabled) | |
282 | active = true; | |
283 | ||
284 | pm_runtime_mark_last_busy(dev->dev); | |
285 | ||
286 | adev = dev->dev_private; | |
287 | /* if we have active crtcs and we don't have a power ref, | |
288 | take the current one */ | |
289 | if (active && !adev->have_disp_power_ref) { | |
290 | adev->have_disp_power_ref = true; | |
291 | return ret; | |
292 | } | |
293 | /* if we have no active crtcs, then drop the power ref | |
294 | we got before */ | |
295 | if (!active && adev->have_disp_power_ref) { | |
296 | pm_runtime_put_autosuspend(dev->dev); | |
297 | adev->have_disp_power_ref = false; | |
298 | } | |
299 | ||
300 | /* drop the power reference we got coming in here */ | |
301 | pm_runtime_put_autosuspend(dev->dev); | |
302 | return ret; | |
303 | } | |
304 | ||
c6e14f40 | 305 | static const char *encoder_names[41] = { |
d38ceaf9 AD |
306 | "NONE", |
307 | "INTERNAL_LVDS", | |
308 | "INTERNAL_TMDS1", | |
309 | "INTERNAL_TMDS2", | |
310 | "INTERNAL_DAC1", | |
311 | "INTERNAL_DAC2", | |
312 | "INTERNAL_SDVOA", | |
313 | "INTERNAL_SDVOB", | |
314 | "SI170B", | |
315 | "CH7303", | |
316 | "CH7301", | |
317 | "INTERNAL_DVO1", | |
318 | "EXTERNAL_SDVOA", | |
319 | "EXTERNAL_SDVOB", | |
320 | "TITFP513", | |
321 | "INTERNAL_LVTM1", | |
322 | "VT1623", | |
323 | "HDMI_SI1930", | |
324 | "HDMI_INTERNAL", | |
325 | "INTERNAL_KLDSCP_TMDS1", | |
326 | "INTERNAL_KLDSCP_DVO1", | |
327 | "INTERNAL_KLDSCP_DAC1", | |
328 | "INTERNAL_KLDSCP_DAC2", | |
329 | "SI178", | |
330 | "MVPU_FPGA", | |
331 | "INTERNAL_DDI", | |
332 | "VT1625", | |
333 | "HDMI_SI1932", | |
334 | "DP_AN9801", | |
335 | "DP_DP501", | |
336 | "INTERNAL_UNIPHY", | |
337 | "INTERNAL_KLDSCP_LVTMA", | |
338 | "INTERNAL_UNIPHY1", | |
339 | "INTERNAL_UNIPHY2", | |
340 | "NUTMEG", | |
341 | "TRAVIS", | |
342 | "INTERNAL_VCE", | |
343 | "INTERNAL_UNIPHY3", | |
c6e14f40 ED |
344 | "HDMI_ANX9805", |
345 | "INTERNAL_AMCLK", | |
346 | "VIRTUAL", | |
d38ceaf9 AD |
347 | }; |
348 | ||
349 | static const char *hpd_names[6] = { | |
350 | "HPD1", | |
351 | "HPD2", | |
352 | "HPD3", | |
353 | "HPD4", | |
354 | "HPD5", | |
355 | "HPD6", | |
356 | }; | |
357 | ||
358 | void amdgpu_print_display_setup(struct drm_device *dev) | |
359 | { | |
360 | struct drm_connector *connector; | |
361 | struct amdgpu_connector *amdgpu_connector; | |
362 | struct drm_encoder *encoder; | |
363 | struct amdgpu_encoder *amdgpu_encoder; | |
364 | uint32_t devices; | |
365 | int i = 0; | |
366 | ||
367 | DRM_INFO("AMDGPU Display Connectors\n"); | |
368 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
369 | amdgpu_connector = to_amdgpu_connector(connector); | |
370 | DRM_INFO("Connector %d:\n", i); | |
371 | DRM_INFO(" %s\n", connector->name); | |
372 | if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) | |
373 | DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); | |
374 | if (amdgpu_connector->ddc_bus) { | |
375 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", | |
376 | amdgpu_connector->ddc_bus->rec.mask_clk_reg, | |
377 | amdgpu_connector->ddc_bus->rec.mask_data_reg, | |
378 | amdgpu_connector->ddc_bus->rec.a_clk_reg, | |
379 | amdgpu_connector->ddc_bus->rec.a_data_reg, | |
380 | amdgpu_connector->ddc_bus->rec.en_clk_reg, | |
381 | amdgpu_connector->ddc_bus->rec.en_data_reg, | |
382 | amdgpu_connector->ddc_bus->rec.y_clk_reg, | |
383 | amdgpu_connector->ddc_bus->rec.y_data_reg); | |
384 | if (amdgpu_connector->router.ddc_valid) | |
385 | DRM_INFO(" DDC Router 0x%x/0x%x\n", | |
386 | amdgpu_connector->router.ddc_mux_control_pin, | |
387 | amdgpu_connector->router.ddc_mux_state); | |
388 | if (amdgpu_connector->router.cd_valid) | |
389 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", | |
390 | amdgpu_connector->router.cd_mux_control_pin, | |
391 | amdgpu_connector->router.cd_mux_state); | |
392 | } else { | |
393 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || | |
394 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || | |
395 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || | |
396 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || | |
397 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
398 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
399 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); | |
400 | } | |
401 | DRM_INFO(" Encoders:\n"); | |
402 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
403 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
404 | devices = amdgpu_encoder->devices & amdgpu_connector->devices; | |
405 | if (devices) { | |
406 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) | |
407 | DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
408 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) | |
409 | DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
410 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) | |
411 | DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
412 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) | |
413 | DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
414 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) | |
415 | DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
416 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) | |
417 | DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
418 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) | |
419 | DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
420 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) | |
421 | DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
422 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) | |
423 | DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
424 | if (devices & ATOM_DEVICE_TV1_SUPPORT) | |
425 | DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
426 | if (devices & ATOM_DEVICE_CV_SUPPORT) | |
427 | DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
428 | } | |
429 | } | |
430 | i++; | |
431 | } | |
432 | } | |
433 | ||
434 | /** | |
435 | * amdgpu_ddc_probe | |
436 | * | |
437 | */ | |
438 | bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, | |
439 | bool use_aux) | |
440 | { | |
441 | u8 out = 0x0; | |
442 | u8 buf[8]; | |
443 | int ret; | |
444 | struct i2c_msg msgs[] = { | |
445 | { | |
446 | .addr = DDC_ADDR, | |
447 | .flags = 0, | |
448 | .len = 1, | |
449 | .buf = &out, | |
450 | }, | |
451 | { | |
452 | .addr = DDC_ADDR, | |
453 | .flags = I2C_M_RD, | |
454 | .len = 8, | |
455 | .buf = buf, | |
456 | } | |
457 | }; | |
458 | ||
459 | /* on hw with routers, select right port */ | |
460 | if (amdgpu_connector->router.ddc_valid) | |
461 | amdgpu_i2c_router_select_ddc_port(amdgpu_connector); | |
462 | ||
463 | if (use_aux) { | |
464 | ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); | |
465 | } else { | |
466 | ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); | |
467 | } | |
468 | ||
469 | if (ret != 2) | |
470 | /* Couldn't find an accessible DDC on this connector */ | |
471 | return false; | |
472 | /* Probe also for valid EDID header | |
473 | * EDID header starts with: | |
474 | * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. | |
475 | * Only the first 6 bytes must be valid as | |
476 | * drm_edid_block_valid() can fix the last 2 bytes */ | |
477 | if (drm_edid_header_is_valid(buf) < 6) { | |
478 | /* Couldn't find an accessible EDID on this | |
479 | * connector */ | |
480 | return false; | |
481 | } | |
482 | return true; | |
483 | } | |
484 | ||
3a05dc00 | 485 | static void amdgpu_display_user_framebuffer_destroy(struct drm_framebuffer *fb) |
d38ceaf9 AD |
486 | { |
487 | struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); | |
488 | ||
f62facc2 | 489 | drm_gem_object_put_unlocked(amdgpu_fb->obj); |
d38ceaf9 AD |
490 | drm_framebuffer_cleanup(fb); |
491 | kfree(amdgpu_fb); | |
492 | } | |
493 | ||
3a05dc00 SL |
494 | static int amdgpu_display_user_framebuffer_create_handle( |
495 | struct drm_framebuffer *fb, | |
496 | struct drm_file *file_priv, | |
497 | unsigned int *handle) | |
d38ceaf9 AD |
498 | { |
499 | struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); | |
500 | ||
501 | return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); | |
502 | } | |
503 | ||
504 | static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { | |
3a05dc00 SL |
505 | .destroy = amdgpu_display_user_framebuffer_destroy, |
506 | .create_handle = amdgpu_display_user_framebuffer_create_handle, | |
d38ceaf9 AD |
507 | }; |
508 | ||
5d43be0c CK |
509 | uint32_t amdgpu_display_framebuffer_domains(struct amdgpu_device *adev) |
510 | { | |
511 | uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; | |
512 | ||
2c9c178b | 513 | #if defined(CONFIG_DRM_AMD_DC) |
5d43be0c | 514 | if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && |
2c9c178b AD |
515 | adev->flags & AMD_IS_APU && |
516 | amdgpu_device_asic_has_dc_support(adev->asic_type)) | |
5d43be0c | 517 | domain |= AMDGPU_GEM_DOMAIN_GTT; |
2c9c178b | 518 | #endif |
5d43be0c CK |
519 | |
520 | return domain; | |
521 | } | |
522 | ||
d38ceaf9 AD |
523 | int |
524 | amdgpu_framebuffer_init(struct drm_device *dev, | |
525 | struct amdgpu_framebuffer *rfb, | |
1eb83451 | 526 | const struct drm_mode_fb_cmd2 *mode_cmd, |
d38ceaf9 AD |
527 | struct drm_gem_object *obj) |
528 | { | |
529 | int ret; | |
530 | rfb->obj = obj; | |
a3f913ca | 531 | drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); |
d38ceaf9 AD |
532 | ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); |
533 | if (ret) { | |
534 | rfb->obj = NULL; | |
535 | return ret; | |
536 | } | |
537 | return 0; | |
538 | } | |
539 | ||
b0fb632f | 540 | struct drm_framebuffer * |
d38ceaf9 AD |
541 | amdgpu_user_framebuffer_create(struct drm_device *dev, |
542 | struct drm_file *file_priv, | |
1eb83451 | 543 | const struct drm_mode_fb_cmd2 *mode_cmd) |
d38ceaf9 AD |
544 | { |
545 | struct drm_gem_object *obj; | |
546 | struct amdgpu_framebuffer *amdgpu_fb; | |
547 | int ret; | |
548 | ||
a8ad0bd8 | 549 | obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); |
d38ceaf9 AD |
550 | if (obj == NULL) { |
551 | dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " | |
552 | "can't create framebuffer\n", mode_cmd->handles[0]); | |
553 | return ERR_PTR(-ENOENT); | |
554 | } | |
555 | ||
1769152a CJHR |
556 | /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ |
557 | if (obj->import_attach) { | |
558 | DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); | |
559 | return ERR_PTR(-EINVAL); | |
560 | } | |
561 | ||
d38ceaf9 AD |
562 | amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); |
563 | if (amdgpu_fb == NULL) { | |
f62facc2 | 564 | drm_gem_object_put_unlocked(obj); |
d38ceaf9 AD |
565 | return ERR_PTR(-ENOMEM); |
566 | } | |
567 | ||
568 | ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); | |
569 | if (ret) { | |
570 | kfree(amdgpu_fb); | |
f62facc2 | 571 | drm_gem_object_put_unlocked(obj); |
d38ceaf9 AD |
572 | return ERR_PTR(ret); |
573 | } | |
574 | ||
575 | return &amdgpu_fb->base; | |
576 | } | |
577 | ||
d38ceaf9 AD |
578 | const struct drm_mode_config_funcs amdgpu_mode_funcs = { |
579 | .fb_create = amdgpu_user_framebuffer_create, | |
ab77e02c | 580 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
d38ceaf9 AD |
581 | }; |
582 | ||
f498d9ed | 583 | static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = |
d38ceaf9 AD |
584 | { { UNDERSCAN_OFF, "off" }, |
585 | { UNDERSCAN_ON, "on" }, | |
586 | { UNDERSCAN_AUTO, "auto" }, | |
587 | }; | |
588 | ||
f498d9ed | 589 | static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = |
d38ceaf9 AD |
590 | { { AMDGPU_AUDIO_DISABLE, "off" }, |
591 | { AMDGPU_AUDIO_ENABLE, "on" }, | |
592 | { AMDGPU_AUDIO_AUTO, "auto" }, | |
593 | }; | |
594 | ||
595 | /* XXX support different dither options? spatial, temporal, both, etc. */ | |
f498d9ed | 596 | static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = |
d38ceaf9 AD |
597 | { { AMDGPU_FMT_DITHER_DISABLE, "off" }, |
598 | { AMDGPU_FMT_DITHER_ENABLE, "on" }, | |
599 | }; | |
600 | ||
601 | int amdgpu_modeset_create_props(struct amdgpu_device *adev) | |
602 | { | |
603 | int sz; | |
604 | ||
f7e9e9fe NW |
605 | adev->mode_info.coherent_mode_property = |
606 | drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); | |
607 | if (!adev->mode_info.coherent_mode_property) | |
608 | return -ENOMEM; | |
d38ceaf9 AD |
609 | |
610 | adev->mode_info.load_detect_property = | |
611 | drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); | |
612 | if (!adev->mode_info.load_detect_property) | |
613 | return -ENOMEM; | |
614 | ||
615 | drm_mode_create_scaling_mode_property(adev->ddev); | |
616 | ||
617 | sz = ARRAY_SIZE(amdgpu_underscan_enum_list); | |
618 | adev->mode_info.underscan_property = | |
619 | drm_property_create_enum(adev->ddev, 0, | |
620 | "underscan", | |
621 | amdgpu_underscan_enum_list, sz); | |
622 | ||
623 | adev->mode_info.underscan_hborder_property = | |
624 | drm_property_create_range(adev->ddev, 0, | |
625 | "underscan hborder", 0, 128); | |
626 | if (!adev->mode_info.underscan_hborder_property) | |
627 | return -ENOMEM; | |
628 | ||
629 | adev->mode_info.underscan_vborder_property = | |
630 | drm_property_create_range(adev->ddev, 0, | |
631 | "underscan vborder", 0, 128); | |
632 | if (!adev->mode_info.underscan_vborder_property) | |
633 | return -ENOMEM; | |
634 | ||
635 | sz = ARRAY_SIZE(amdgpu_audio_enum_list); | |
636 | adev->mode_info.audio_property = | |
637 | drm_property_create_enum(adev->ddev, 0, | |
638 | "audio", | |
639 | amdgpu_audio_enum_list, sz); | |
640 | ||
641 | sz = ARRAY_SIZE(amdgpu_dither_enum_list); | |
642 | adev->mode_info.dither_property = | |
643 | drm_property_create_enum(adev->ddev, 0, | |
644 | "dither", | |
645 | amdgpu_dither_enum_list, sz); | |
646 | ||
647 | return 0; | |
648 | } | |
649 | ||
650 | void amdgpu_update_display_priority(struct amdgpu_device *adev) | |
651 | { | |
652 | /* adjustment options for the display watermarks */ | |
653 | if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) | |
654 | adev->mode_info.disp_priority = 0; | |
655 | else | |
656 | adev->mode_info.disp_priority = amdgpu_disp_priority; | |
657 | ||
658 | } | |
659 | ||
3a05dc00 | 660 | static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) |
d38ceaf9 AD |
661 | { |
662 | /* try and guess if this is a tv or a monitor */ | |
663 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ | |
664 | (mode->vdisplay == 576) || /* 576p */ | |
665 | (mode->vdisplay == 720) || /* 720p */ | |
666 | (mode->vdisplay == 1080)) /* 1080p */ | |
667 | return true; | |
668 | else | |
669 | return false; | |
670 | } | |
671 | ||
672 | bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, | |
673 | const struct drm_display_mode *mode, | |
674 | struct drm_display_mode *adjusted_mode) | |
675 | { | |
676 | struct drm_device *dev = crtc->dev; | |
677 | struct drm_encoder *encoder; | |
678 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
679 | struct amdgpu_encoder *amdgpu_encoder; | |
680 | struct drm_connector *connector; | |
681 | struct amdgpu_connector *amdgpu_connector; | |
682 | u32 src_v = 1, dst_v = 1; | |
683 | u32 src_h = 1, dst_h = 1; | |
684 | ||
685 | amdgpu_crtc->h_border = 0; | |
686 | amdgpu_crtc->v_border = 0; | |
687 | ||
688 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
689 | if (encoder->crtc != crtc) | |
690 | continue; | |
691 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
692 | connector = amdgpu_get_connector_for_encoder(encoder); | |
693 | amdgpu_connector = to_amdgpu_connector(connector); | |
694 | ||
695 | /* set scaling */ | |
696 | if (amdgpu_encoder->rmx_type == RMX_OFF) | |
697 | amdgpu_crtc->rmx_type = RMX_OFF; | |
698 | else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || | |
699 | mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) | |
700 | amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; | |
701 | else | |
702 | amdgpu_crtc->rmx_type = RMX_OFF; | |
703 | /* copy native mode */ | |
704 | memcpy(&amdgpu_crtc->native_mode, | |
705 | &amdgpu_encoder->native_mode, | |
706 | sizeof(struct drm_display_mode)); | |
707 | src_v = crtc->mode.vdisplay; | |
708 | dst_v = amdgpu_crtc->native_mode.vdisplay; | |
709 | src_h = crtc->mode.hdisplay; | |
710 | dst_h = amdgpu_crtc->native_mode.hdisplay; | |
711 | ||
712 | /* fix up for overscan on hdmi */ | |
713 | if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && | |
714 | ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || | |
715 | ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && | |
716 | drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && | |
3a05dc00 | 717 | amdgpu_display_is_hdtv_mode(mode)))) { |
d38ceaf9 AD |
718 | if (amdgpu_encoder->underscan_hborder != 0) |
719 | amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; | |
720 | else | |
721 | amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; | |
722 | if (amdgpu_encoder->underscan_vborder != 0) | |
723 | amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; | |
724 | else | |
725 | amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; | |
726 | amdgpu_crtc->rmx_type = RMX_FULL; | |
727 | src_v = crtc->mode.vdisplay; | |
728 | dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); | |
729 | src_h = crtc->mode.hdisplay; | |
730 | dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); | |
731 | } | |
732 | } | |
733 | if (amdgpu_crtc->rmx_type != RMX_OFF) { | |
734 | fixed20_12 a, b; | |
735 | a.full = dfixed_const(src_v); | |
736 | b.full = dfixed_const(dst_v); | |
737 | amdgpu_crtc->vsc.full = dfixed_div(a, b); | |
738 | a.full = dfixed_const(src_h); | |
739 | b.full = dfixed_const(dst_h); | |
740 | amdgpu_crtc->hsc.full = dfixed_div(a, b); | |
741 | } else { | |
742 | amdgpu_crtc->vsc.full = dfixed_const(1); | |
743 | amdgpu_crtc->hsc.full = dfixed_const(1); | |
744 | } | |
745 | return true; | |
746 | } | |
747 | ||
748 | /* | |
749 | * Retrieve current video scanout position of crtc on a given gpu, and | |
750 | * an optional accurate timestamp of when query happened. | |
751 | * | |
752 | * \param dev Device to query. | |
88e72717 | 753 | * \param pipe Crtc to query. |
d38ceaf9 | 754 | * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). |
8e36f9d3 AD |
755 | * For driver internal use only also supports these flags: |
756 | * | |
757 | * USE_REAL_VBLANKSTART to use the real start of vblank instead | |
758 | * of a fudged earlier start of vblank. | |
759 | * | |
760 | * GET_DISTANCE_TO_VBLANKSTART to return distance to the | |
761 | * fudged earlier start of vblank in *vpos and the distance | |
762 | * to true start of vblank in *hpos. | |
763 | * | |
d38ceaf9 AD |
764 | * \param *vpos Location where vertical scanout position should be stored. |
765 | * \param *hpos Location where horizontal scanout position should go. | |
766 | * \param *stime Target location for timestamp taken immediately before | |
767 | * scanout position query. Can be NULL to skip timestamp. | |
768 | * \param *etime Target location for timestamp taken immediately after | |
769 | * scanout position query. Can be NULL to skip timestamp. | |
770 | * | |
771 | * Returns vpos as a positive number while in active scanout area. | |
772 | * Returns vpos as a negative number inside vblank, counting the number | |
773 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline | |
774 | * until start of active scanout / end of vblank." | |
775 | * | |
776 | * \return Flags, or'ed together as follows: | |
777 | * | |
778 | * DRM_SCANOUTPOS_VALID = Query successful. | |
779 | * DRM_SCANOUTPOS_INVBL = Inside vblank. | |
780 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of | |
781 | * this flag means that returned position may be offset by a constant but | |
782 | * unknown small number of scanlines wrt. real scanout position. | |
783 | * | |
784 | */ | |
88e72717 TR |
785 | int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
786 | unsigned int flags, int *vpos, int *hpos, | |
787 | ktime_t *stime, ktime_t *etime, | |
3bb403bf | 788 | const struct drm_display_mode *mode) |
d38ceaf9 AD |
789 | { |
790 | u32 vbl = 0, position = 0; | |
791 | int vbl_start, vbl_end, vtotal, ret = 0; | |
792 | bool in_vbl = true; | |
793 | ||
794 | struct amdgpu_device *adev = dev->dev_private; | |
795 | ||
796 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ | |
797 | ||
798 | /* Get optional system timestamp before query. */ | |
799 | if (stime) | |
800 | *stime = ktime_get(); | |
801 | ||
88e72717 | 802 | if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) |
d38ceaf9 AD |
803 | ret |= DRM_SCANOUTPOS_VALID; |
804 | ||
805 | /* Get optional system timestamp after query. */ | |
806 | if (etime) | |
807 | *etime = ktime_get(); | |
808 | ||
809 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
810 | ||
811 | /* Decode into vertical and horizontal scanout position. */ | |
812 | *vpos = position & 0x1fff; | |
813 | *hpos = (position >> 16) & 0x1fff; | |
814 | ||
815 | /* Valid vblank area boundaries from gpu retrieved? */ | |
816 | if (vbl > 0) { | |
817 | /* Yes: Decode. */ | |
818 | ret |= DRM_SCANOUTPOS_ACCURATE; | |
819 | vbl_start = vbl & 0x1fff; | |
820 | vbl_end = (vbl >> 16) & 0x1fff; | |
821 | } | |
822 | else { | |
823 | /* No: Fake something reasonable which gives at least ok results. */ | |
3bb403bf | 824 | vbl_start = mode->crtc_vdisplay; |
d38ceaf9 AD |
825 | vbl_end = 0; |
826 | } | |
827 | ||
8e36f9d3 AD |
828 | /* Called from driver internal vblank counter query code? */ |
829 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { | |
830 | /* Caller wants distance from real vbl_start in *hpos */ | |
831 | *hpos = *vpos - vbl_start; | |
832 | } | |
833 | ||
834 | /* Fudge vblank to start a few scanlines earlier to handle the | |
835 | * problem that vblank irqs fire a few scanlines before start | |
836 | * of vblank. Some driver internal callers need the true vblank | |
837 | * start to be used and signal this via the USE_REAL_VBLANKSTART flag. | |
838 | * | |
839 | * The cause of the "early" vblank irq is that the irq is triggered | |
840 | * by the line buffer logic when the line buffer read position enters | |
841 | * the vblank, whereas our crtc scanout position naturally lags the | |
842 | * line buffer read position. | |
843 | */ | |
844 | if (!(flags & USE_REAL_VBLANKSTART)) | |
845 | vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; | |
846 | ||
d38ceaf9 AD |
847 | /* Test scanout position against vblank region. */ |
848 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) | |
849 | in_vbl = false; | |
850 | ||
8e36f9d3 AD |
851 | /* In vblank? */ |
852 | if (in_vbl) | |
853 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
854 | ||
855 | /* Called from driver internal vblank counter query code? */ | |
856 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { | |
857 | /* Caller wants distance from fudged earlier vbl_start */ | |
858 | *vpos -= vbl_start; | |
859 | return ret; | |
860 | } | |
861 | ||
d38ceaf9 AD |
862 | /* Check if inside vblank area and apply corrective offsets: |
863 | * vpos will then be >=0 in video scanout area, but negative | |
864 | * within vblank area, counting down the number of lines until | |
865 | * start of scanout. | |
866 | */ | |
867 | ||
868 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ | |
869 | if (in_vbl && (*vpos >= vbl_start)) { | |
3bb403bf | 870 | vtotal = mode->crtc_vtotal; |
d38ceaf9 AD |
871 | *vpos = *vpos - vtotal; |
872 | } | |
873 | ||
874 | /* Correct for shifted end of vbl at vbl_end. */ | |
875 | *vpos = *vpos - vbl_end; | |
876 | ||
d38ceaf9 AD |
877 | return ret; |
878 | } | |
879 | ||
880 | int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) | |
881 | { | |
882 | if (crtc < 0 || crtc >= adev->mode_info.num_crtc) | |
883 | return AMDGPU_CRTC_IRQ_NONE; | |
884 | ||
885 | switch (crtc) { | |
886 | case 0: | |
887 | return AMDGPU_CRTC_IRQ_VBLANK1; | |
888 | case 1: | |
889 | return AMDGPU_CRTC_IRQ_VBLANK2; | |
890 | case 2: | |
891 | return AMDGPU_CRTC_IRQ_VBLANK3; | |
892 | case 3: | |
893 | return AMDGPU_CRTC_IRQ_VBLANK4; | |
894 | case 4: | |
895 | return AMDGPU_CRTC_IRQ_VBLANK5; | |
896 | case 5: | |
897 | return AMDGPU_CRTC_IRQ_VBLANK6; | |
898 | default: | |
899 | return AMDGPU_CRTC_IRQ_NONE; | |
900 | } | |
901 | } |