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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include <drm/drmP.h> | |
27 | #include <drm/amdgpu_drm.h> | |
28 | #include "amdgpu.h" | |
29 | #include "amdgpu_i2c.h" | |
30 | #include "atom.h" | |
31 | #include "amdgpu_connectors.h" | |
5d43be0c | 32 | #include "amdgpu_display.h" |
d38ceaf9 AD |
33 | #include <asm/div64.h> |
34 | ||
35 | #include <linux/pm_runtime.h> | |
36 | #include <drm/drm_crtc_helper.h> | |
37 | #include <drm/drm_edid.h> | |
ab77e02c | 38 | #include <drm/drm_fb_helper.h> |
d38ceaf9 | 39 | |
f54d1867 | 40 | static void amdgpu_flip_callback(struct dma_fence *f, struct dma_fence_cb *cb) |
1ffd2652 | 41 | { |
c3874b75 CK |
42 | struct amdgpu_flip_work *work = |
43 | container_of(cb, struct amdgpu_flip_work, cb); | |
1ffd2652 | 44 | |
f54d1867 | 45 | dma_fence_put(f); |
325cbba1 | 46 | schedule_work(&work->flip_work.work); |
c3874b75 | 47 | } |
1ffd2652 | 48 | |
c3874b75 | 49 | static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work, |
f54d1867 | 50 | struct dma_fence **f) |
c3874b75 | 51 | { |
f54d1867 | 52 | struct dma_fence *fence= *f; |
c3874b75 CK |
53 | |
54 | if (fence == NULL) | |
55 | return false; | |
1ffd2652 | 56 | |
1ffd2652 | 57 | *f = NULL; |
c3874b75 | 58 | |
f54d1867 | 59 | if (!dma_fence_add_callback(fence, &work->cb, amdgpu_flip_callback)) |
c3874b75 CK |
60 | return true; |
61 | ||
f54d1867 | 62 | dma_fence_put(fence); |
c3874b75 | 63 | return false; |
1ffd2652 | 64 | } |
d38ceaf9 AD |
65 | |
66 | static void amdgpu_flip_work_func(struct work_struct *__work) | |
67 | { | |
325cbba1 MD |
68 | struct delayed_work *delayed_work = |
69 | container_of(__work, struct delayed_work, work); | |
d38ceaf9 | 70 | struct amdgpu_flip_work *work = |
325cbba1 | 71 | container_of(delayed_work, struct amdgpu_flip_work, flip_work); |
d38ceaf9 | 72 | struct amdgpu_device *adev = work->adev; |
f93932bc | 73 | struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; |
d38ceaf9 | 74 | |
f93932bc | 75 | struct drm_crtc *crtc = &amdgpu_crtc->base; |
d38ceaf9 | 76 | unsigned long flags; |
325cbba1 MD |
77 | unsigned i; |
78 | int vpos, hpos; | |
d38ceaf9 | 79 | |
c3874b75 CK |
80 | if (amdgpu_flip_handle_fence(work, &work->excl)) |
81 | return; | |
82 | ||
1ffd2652 | 83 | for (i = 0; i < work->shared_count; ++i) |
c3874b75 CK |
84 | if (amdgpu_flip_handle_fence(work, &work->shared[i])) |
85 | return; | |
d38ceaf9 | 86 | |
325cbba1 MD |
87 | /* Wait until we're out of the vertical blank period before the one |
88 | * targeted by the flip | |
8e36f9d3 | 89 | */ |
f93932bc | 90 | if (amdgpu_crtc->enabled && |
325cbba1 MD |
91 | (amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0, |
92 | &vpos, &hpos, NULL, NULL, | |
93 | &crtc->hwmode) | |
94 | & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == | |
95 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && | |
96 | (int)(work->target_vblank - | |
f93932bc | 97 | amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) { |
325cbba1 MD |
98 | schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); |
99 | return; | |
9c3578af | 100 | } |
8e36f9d3 | 101 | |
325cbba1 MD |
102 | /* We borrow the event spin lock for protecting flip_status */ |
103 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
e1d09dc0 | 104 | |
bd4c72d1 | 105 | /* Do the flip (mmio) */ |
cb9e59d7 | 106 | adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); |
bd4c72d1 AG |
107 | |
108 | /* Set the flip status */ | |
f93932bc | 109 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; |
d38ceaf9 | 110 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
6bd9e877 | 111 | |
bd4c72d1 AG |
112 | |
113 | DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", | |
f93932bc | 114 | amdgpu_crtc->crtc_id, amdgpu_crtc, work); |
bd4c72d1 | 115 | |
d38ceaf9 AD |
116 | } |
117 | ||
118 | /* | |
119 | * Handle unpin events outside the interrupt handler proper. | |
120 | */ | |
121 | static void amdgpu_unpin_work_func(struct work_struct *__work) | |
122 | { | |
123 | struct amdgpu_flip_work *work = | |
124 | container_of(__work, struct amdgpu_flip_work, unpin_work); | |
125 | int r; | |
126 | ||
127 | /* unpin of the old buffer */ | |
c81a1a74 | 128 | r = amdgpu_bo_reserve(work->old_abo, true); |
d38ceaf9 | 129 | if (likely(r == 0)) { |
765e7fbf | 130 | r = amdgpu_bo_unpin(work->old_abo); |
d38ceaf9 AD |
131 | if (unlikely(r != 0)) { |
132 | DRM_ERROR("failed to unpin buffer after flip\n"); | |
133 | } | |
765e7fbf | 134 | amdgpu_bo_unreserve(work->old_abo); |
d38ceaf9 AD |
135 | } else |
136 | DRM_ERROR("failed to reserve buffer after flip\n"); | |
137 | ||
765e7fbf | 138 | amdgpu_bo_unref(&work->old_abo); |
1ffd2652 | 139 | kfree(work->shared); |
d38ceaf9 AD |
140 | kfree(work); |
141 | } | |
142 | ||
5f42aa39 HW |
143 | int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc, |
144 | struct drm_framebuffer *fb, | |
145 | struct drm_pending_vblank_event *event, | |
146 | uint32_t page_flip_flags, uint32_t target, | |
147 | struct drm_modeset_acquire_ctx *ctx) | |
d38ceaf9 AD |
148 | { |
149 | struct drm_device *dev = crtc->dev; | |
150 | struct amdgpu_device *adev = dev->dev_private; | |
151 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
152 | struct amdgpu_framebuffer *old_amdgpu_fb; | |
153 | struct amdgpu_framebuffer *new_amdgpu_fb; | |
154 | struct drm_gem_object *obj; | |
155 | struct amdgpu_flip_work *work; | |
765e7fbf | 156 | struct amdgpu_bo *new_abo; |
d38ceaf9 AD |
157 | unsigned long flags; |
158 | u64 tiling_flags; | |
159 | u64 base; | |
5f42aa39 | 160 | int i, r; |
d38ceaf9 AD |
161 | |
162 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
163 | if (work == NULL) | |
164 | return -ENOMEM; | |
165 | ||
325cbba1 | 166 | INIT_DELAYED_WORK(&work->flip_work, amdgpu_flip_work_func); |
d38ceaf9 AD |
167 | INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func); |
168 | ||
169 | work->event = event; | |
170 | work->adev = adev; | |
171 | work->crtc_id = amdgpu_crtc->crtc_id; | |
cb9e59d7 | 172 | work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; |
d38ceaf9 AD |
173 | |
174 | /* schedule unpin of the old buffer */ | |
175 | old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); | |
176 | obj = old_amdgpu_fb->obj; | |
177 | ||
178 | /* take a reference to the old object */ | |
765e7fbf CK |
179 | work->old_abo = gem_to_amdgpu_bo(obj); |
180 | amdgpu_bo_ref(work->old_abo); | |
d38ceaf9 AD |
181 | |
182 | new_amdgpu_fb = to_amdgpu_framebuffer(fb); | |
183 | obj = new_amdgpu_fb->obj; | |
765e7fbf | 184 | new_abo = gem_to_amdgpu_bo(obj); |
d38ceaf9 AD |
185 | |
186 | /* pin the new buffer */ | |
765e7fbf | 187 | r = amdgpu_bo_reserve(new_abo, false); |
d38ceaf9 | 188 | if (unlikely(r != 0)) { |
765e7fbf | 189 | DRM_ERROR("failed to reserve new abo buffer before flip\n"); |
d38ceaf9 AD |
190 | goto cleanup; |
191 | } | |
192 | ||
5d43be0c | 193 | r = amdgpu_bo_pin(new_abo, amdgpu_display_framebuffer_domains(adev), &base); |
d38ceaf9 | 194 | if (unlikely(r != 0)) { |
765e7fbf | 195 | DRM_ERROR("failed to pin new abo buffer before flip\n"); |
ee7fd957 | 196 | goto unreserve; |
d38ceaf9 AD |
197 | } |
198 | ||
765e7fbf | 199 | r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl, |
1ffd2652 CK |
200 | &work->shared_count, |
201 | &work->shared); | |
202 | if (unlikely(r != 0)) { | |
1ffd2652 | 203 | DRM_ERROR("failed to get fences for buffer\n"); |
ee7fd957 | 204 | goto unpin; |
1ffd2652 CK |
205 | } |
206 | ||
765e7fbf CK |
207 | amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); |
208 | amdgpu_bo_unreserve(new_abo); | |
d38ceaf9 AD |
209 | |
210 | work->base = base; | |
325cbba1 MD |
211 | work->target_vblank = target - drm_crtc_vblank_count(crtc) + |
212 | amdgpu_get_vblank_counter_kms(dev, work->crtc_id); | |
d38ceaf9 AD |
213 | |
214 | /* we borrow the event spin lock for protecting flip_wrok */ | |
215 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
216 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { | |
217 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
218 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
219 | r = -EBUSY; | |
325cbba1 | 220 | goto pflip_cleanup; |
d38ceaf9 AD |
221 | } |
222 | ||
223 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; | |
224 | amdgpu_crtc->pflip_works = work; | |
225 | ||
5f42aa39 HW |
226 | |
227 | DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", | |
228 | amdgpu_crtc->crtc_id, amdgpu_crtc, work); | |
d38ceaf9 AD |
229 | /* update crtc fb */ |
230 | crtc->primary->fb = fb; | |
231 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
325cbba1 | 232 | amdgpu_flip_work_func(&work->flip_work.work); |
5f42aa39 | 233 | return 0; |
d38ceaf9 | 234 | |
5f42aa39 HW |
235 | pflip_cleanup: |
236 | if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { | |
237 | DRM_ERROR("failed to reserve new abo in error path\n"); | |
238 | goto cleanup; | |
239 | } | |
240 | unpin: | |
241 | if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { | |
242 | DRM_ERROR("failed to unpin new abo in error path\n"); | |
243 | } | |
244 | unreserve: | |
245 | amdgpu_bo_unreserve(new_abo); | |
cb341a31 | 246 | |
5f42aa39 HW |
247 | cleanup: |
248 | amdgpu_bo_unref(&work->old_abo); | |
249 | dma_fence_put(work->excl); | |
250 | for (i = 0; i < work->shared_count; ++i) | |
251 | dma_fence_put(work->shared[i]); | |
252 | kfree(work->shared); | |
253 | kfree(work); | |
9c5b2b0d | 254 | |
5f42aa39 | 255 | return r; |
d38ceaf9 AD |
256 | } |
257 | ||
a4eff9aa DV |
258 | int amdgpu_crtc_set_config(struct drm_mode_set *set, |
259 | struct drm_modeset_acquire_ctx *ctx) | |
d38ceaf9 AD |
260 | { |
261 | struct drm_device *dev; | |
262 | struct amdgpu_device *adev; | |
263 | struct drm_crtc *crtc; | |
264 | bool active = false; | |
265 | int ret; | |
266 | ||
267 | if (!set || !set->crtc) | |
268 | return -EINVAL; | |
269 | ||
270 | dev = set->crtc->dev; | |
271 | ||
272 | ret = pm_runtime_get_sync(dev->dev); | |
273 | if (ret < 0) | |
274 | return ret; | |
275 | ||
a4eff9aa | 276 | ret = drm_crtc_helper_set_config(set, ctx); |
d38ceaf9 AD |
277 | |
278 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
279 | if (crtc->enabled) | |
280 | active = true; | |
281 | ||
282 | pm_runtime_mark_last_busy(dev->dev); | |
283 | ||
284 | adev = dev->dev_private; | |
285 | /* if we have active crtcs and we don't have a power ref, | |
286 | take the current one */ | |
287 | if (active && !adev->have_disp_power_ref) { | |
288 | adev->have_disp_power_ref = true; | |
289 | return ret; | |
290 | } | |
291 | /* if we have no active crtcs, then drop the power ref | |
292 | we got before */ | |
293 | if (!active && adev->have_disp_power_ref) { | |
294 | pm_runtime_put_autosuspend(dev->dev); | |
295 | adev->have_disp_power_ref = false; | |
296 | } | |
297 | ||
298 | /* drop the power reference we got coming in here */ | |
299 | pm_runtime_put_autosuspend(dev->dev); | |
300 | return ret; | |
301 | } | |
302 | ||
c6e14f40 | 303 | static const char *encoder_names[41] = { |
d38ceaf9 AD |
304 | "NONE", |
305 | "INTERNAL_LVDS", | |
306 | "INTERNAL_TMDS1", | |
307 | "INTERNAL_TMDS2", | |
308 | "INTERNAL_DAC1", | |
309 | "INTERNAL_DAC2", | |
310 | "INTERNAL_SDVOA", | |
311 | "INTERNAL_SDVOB", | |
312 | "SI170B", | |
313 | "CH7303", | |
314 | "CH7301", | |
315 | "INTERNAL_DVO1", | |
316 | "EXTERNAL_SDVOA", | |
317 | "EXTERNAL_SDVOB", | |
318 | "TITFP513", | |
319 | "INTERNAL_LVTM1", | |
320 | "VT1623", | |
321 | "HDMI_SI1930", | |
322 | "HDMI_INTERNAL", | |
323 | "INTERNAL_KLDSCP_TMDS1", | |
324 | "INTERNAL_KLDSCP_DVO1", | |
325 | "INTERNAL_KLDSCP_DAC1", | |
326 | "INTERNAL_KLDSCP_DAC2", | |
327 | "SI178", | |
328 | "MVPU_FPGA", | |
329 | "INTERNAL_DDI", | |
330 | "VT1625", | |
331 | "HDMI_SI1932", | |
332 | "DP_AN9801", | |
333 | "DP_DP501", | |
334 | "INTERNAL_UNIPHY", | |
335 | "INTERNAL_KLDSCP_LVTMA", | |
336 | "INTERNAL_UNIPHY1", | |
337 | "INTERNAL_UNIPHY2", | |
338 | "NUTMEG", | |
339 | "TRAVIS", | |
340 | "INTERNAL_VCE", | |
341 | "INTERNAL_UNIPHY3", | |
c6e14f40 ED |
342 | "HDMI_ANX9805", |
343 | "INTERNAL_AMCLK", | |
344 | "VIRTUAL", | |
d38ceaf9 AD |
345 | }; |
346 | ||
347 | static const char *hpd_names[6] = { | |
348 | "HPD1", | |
349 | "HPD2", | |
350 | "HPD3", | |
351 | "HPD4", | |
352 | "HPD5", | |
353 | "HPD6", | |
354 | }; | |
355 | ||
356 | void amdgpu_print_display_setup(struct drm_device *dev) | |
357 | { | |
358 | struct drm_connector *connector; | |
359 | struct amdgpu_connector *amdgpu_connector; | |
360 | struct drm_encoder *encoder; | |
361 | struct amdgpu_encoder *amdgpu_encoder; | |
362 | uint32_t devices; | |
363 | int i = 0; | |
364 | ||
365 | DRM_INFO("AMDGPU Display Connectors\n"); | |
366 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
367 | amdgpu_connector = to_amdgpu_connector(connector); | |
368 | DRM_INFO("Connector %d:\n", i); | |
369 | DRM_INFO(" %s\n", connector->name); | |
370 | if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) | |
371 | DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); | |
372 | if (amdgpu_connector->ddc_bus) { | |
373 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", | |
374 | amdgpu_connector->ddc_bus->rec.mask_clk_reg, | |
375 | amdgpu_connector->ddc_bus->rec.mask_data_reg, | |
376 | amdgpu_connector->ddc_bus->rec.a_clk_reg, | |
377 | amdgpu_connector->ddc_bus->rec.a_data_reg, | |
378 | amdgpu_connector->ddc_bus->rec.en_clk_reg, | |
379 | amdgpu_connector->ddc_bus->rec.en_data_reg, | |
380 | amdgpu_connector->ddc_bus->rec.y_clk_reg, | |
381 | amdgpu_connector->ddc_bus->rec.y_data_reg); | |
382 | if (amdgpu_connector->router.ddc_valid) | |
383 | DRM_INFO(" DDC Router 0x%x/0x%x\n", | |
384 | amdgpu_connector->router.ddc_mux_control_pin, | |
385 | amdgpu_connector->router.ddc_mux_state); | |
386 | if (amdgpu_connector->router.cd_valid) | |
387 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", | |
388 | amdgpu_connector->router.cd_mux_control_pin, | |
389 | amdgpu_connector->router.cd_mux_state); | |
390 | } else { | |
391 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || | |
392 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || | |
393 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || | |
394 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || | |
395 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
396 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
397 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); | |
398 | } | |
399 | DRM_INFO(" Encoders:\n"); | |
400 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
401 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
402 | devices = amdgpu_encoder->devices & amdgpu_connector->devices; | |
403 | if (devices) { | |
404 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) | |
405 | DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
406 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) | |
407 | DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
408 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) | |
409 | DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
410 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) | |
411 | DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
412 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) | |
413 | DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
414 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) | |
415 | DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
416 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) | |
417 | DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
418 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) | |
419 | DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
420 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) | |
421 | DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
422 | if (devices & ATOM_DEVICE_TV1_SUPPORT) | |
423 | DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
424 | if (devices & ATOM_DEVICE_CV_SUPPORT) | |
425 | DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
426 | } | |
427 | } | |
428 | i++; | |
429 | } | |
430 | } | |
431 | ||
432 | /** | |
433 | * amdgpu_ddc_probe | |
434 | * | |
435 | */ | |
436 | bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, | |
437 | bool use_aux) | |
438 | { | |
439 | u8 out = 0x0; | |
440 | u8 buf[8]; | |
441 | int ret; | |
442 | struct i2c_msg msgs[] = { | |
443 | { | |
444 | .addr = DDC_ADDR, | |
445 | .flags = 0, | |
446 | .len = 1, | |
447 | .buf = &out, | |
448 | }, | |
449 | { | |
450 | .addr = DDC_ADDR, | |
451 | .flags = I2C_M_RD, | |
452 | .len = 8, | |
453 | .buf = buf, | |
454 | } | |
455 | }; | |
456 | ||
457 | /* on hw with routers, select right port */ | |
458 | if (amdgpu_connector->router.ddc_valid) | |
459 | amdgpu_i2c_router_select_ddc_port(amdgpu_connector); | |
460 | ||
461 | if (use_aux) { | |
462 | ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); | |
463 | } else { | |
464 | ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); | |
465 | } | |
466 | ||
467 | if (ret != 2) | |
468 | /* Couldn't find an accessible DDC on this connector */ | |
469 | return false; | |
470 | /* Probe also for valid EDID header | |
471 | * EDID header starts with: | |
472 | * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. | |
473 | * Only the first 6 bytes must be valid as | |
474 | * drm_edid_block_valid() can fix the last 2 bytes */ | |
475 | if (drm_edid_header_is_valid(buf) < 6) { | |
476 | /* Couldn't find an accessible EDID on this | |
477 | * connector */ | |
478 | return false; | |
479 | } | |
480 | return true; | |
481 | } | |
482 | ||
483 | static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
484 | { | |
485 | struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); | |
486 | ||
f62facc2 | 487 | drm_gem_object_put_unlocked(amdgpu_fb->obj); |
d38ceaf9 AD |
488 | drm_framebuffer_cleanup(fb); |
489 | kfree(amdgpu_fb); | |
490 | } | |
491 | ||
492 | static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
493 | struct drm_file *file_priv, | |
494 | unsigned int *handle) | |
495 | { | |
496 | struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); | |
497 | ||
498 | return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); | |
499 | } | |
500 | ||
501 | static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { | |
502 | .destroy = amdgpu_user_framebuffer_destroy, | |
503 | .create_handle = amdgpu_user_framebuffer_create_handle, | |
504 | }; | |
505 | ||
5d43be0c CK |
506 | uint32_t amdgpu_display_framebuffer_domains(struct amdgpu_device *adev) |
507 | { | |
508 | uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; | |
509 | ||
2c9c178b | 510 | #if defined(CONFIG_DRM_AMD_DC) |
5d43be0c | 511 | if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && |
2c9c178b AD |
512 | adev->flags & AMD_IS_APU && |
513 | amdgpu_device_asic_has_dc_support(adev->asic_type)) | |
5d43be0c | 514 | domain |= AMDGPU_GEM_DOMAIN_GTT; |
2c9c178b | 515 | #endif |
5d43be0c CK |
516 | |
517 | return domain; | |
518 | } | |
519 | ||
d38ceaf9 AD |
520 | int |
521 | amdgpu_framebuffer_init(struct drm_device *dev, | |
522 | struct amdgpu_framebuffer *rfb, | |
1eb83451 | 523 | const struct drm_mode_fb_cmd2 *mode_cmd, |
d38ceaf9 AD |
524 | struct drm_gem_object *obj) |
525 | { | |
526 | int ret; | |
527 | rfb->obj = obj; | |
a3f913ca | 528 | drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); |
d38ceaf9 AD |
529 | ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); |
530 | if (ret) { | |
531 | rfb->obj = NULL; | |
532 | return ret; | |
533 | } | |
534 | return 0; | |
535 | } | |
536 | ||
b0fb632f | 537 | struct drm_framebuffer * |
d38ceaf9 AD |
538 | amdgpu_user_framebuffer_create(struct drm_device *dev, |
539 | struct drm_file *file_priv, | |
1eb83451 | 540 | const struct drm_mode_fb_cmd2 *mode_cmd) |
d38ceaf9 AD |
541 | { |
542 | struct drm_gem_object *obj; | |
543 | struct amdgpu_framebuffer *amdgpu_fb; | |
544 | int ret; | |
545 | ||
a8ad0bd8 | 546 | obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); |
d38ceaf9 AD |
547 | if (obj == NULL) { |
548 | dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " | |
549 | "can't create framebuffer\n", mode_cmd->handles[0]); | |
550 | return ERR_PTR(-ENOENT); | |
551 | } | |
552 | ||
1769152a CJHR |
553 | /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ |
554 | if (obj->import_attach) { | |
555 | DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); | |
556 | return ERR_PTR(-EINVAL); | |
557 | } | |
558 | ||
d38ceaf9 AD |
559 | amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); |
560 | if (amdgpu_fb == NULL) { | |
f62facc2 | 561 | drm_gem_object_put_unlocked(obj); |
d38ceaf9 AD |
562 | return ERR_PTR(-ENOMEM); |
563 | } | |
564 | ||
565 | ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); | |
566 | if (ret) { | |
567 | kfree(amdgpu_fb); | |
f62facc2 | 568 | drm_gem_object_put_unlocked(obj); |
d38ceaf9 AD |
569 | return ERR_PTR(ret); |
570 | } | |
571 | ||
572 | return &amdgpu_fb->base; | |
573 | } | |
574 | ||
d38ceaf9 AD |
575 | const struct drm_mode_config_funcs amdgpu_mode_funcs = { |
576 | .fb_create = amdgpu_user_framebuffer_create, | |
ab77e02c | 577 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
d38ceaf9 AD |
578 | }; |
579 | ||
f498d9ed | 580 | static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = |
d38ceaf9 AD |
581 | { { UNDERSCAN_OFF, "off" }, |
582 | { UNDERSCAN_ON, "on" }, | |
583 | { UNDERSCAN_AUTO, "auto" }, | |
584 | }; | |
585 | ||
f498d9ed | 586 | static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = |
d38ceaf9 AD |
587 | { { AMDGPU_AUDIO_DISABLE, "off" }, |
588 | { AMDGPU_AUDIO_ENABLE, "on" }, | |
589 | { AMDGPU_AUDIO_AUTO, "auto" }, | |
590 | }; | |
591 | ||
592 | /* XXX support different dither options? spatial, temporal, both, etc. */ | |
f498d9ed | 593 | static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = |
d38ceaf9 AD |
594 | { { AMDGPU_FMT_DITHER_DISABLE, "off" }, |
595 | { AMDGPU_FMT_DITHER_ENABLE, "on" }, | |
596 | }; | |
597 | ||
598 | int amdgpu_modeset_create_props(struct amdgpu_device *adev) | |
599 | { | |
600 | int sz; | |
601 | ||
f7e9e9fe NW |
602 | adev->mode_info.coherent_mode_property = |
603 | drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); | |
604 | if (!adev->mode_info.coherent_mode_property) | |
605 | return -ENOMEM; | |
d38ceaf9 AD |
606 | |
607 | adev->mode_info.load_detect_property = | |
608 | drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); | |
609 | if (!adev->mode_info.load_detect_property) | |
610 | return -ENOMEM; | |
611 | ||
612 | drm_mode_create_scaling_mode_property(adev->ddev); | |
613 | ||
614 | sz = ARRAY_SIZE(amdgpu_underscan_enum_list); | |
615 | adev->mode_info.underscan_property = | |
616 | drm_property_create_enum(adev->ddev, 0, | |
617 | "underscan", | |
618 | amdgpu_underscan_enum_list, sz); | |
619 | ||
620 | adev->mode_info.underscan_hborder_property = | |
621 | drm_property_create_range(adev->ddev, 0, | |
622 | "underscan hborder", 0, 128); | |
623 | if (!adev->mode_info.underscan_hborder_property) | |
624 | return -ENOMEM; | |
625 | ||
626 | adev->mode_info.underscan_vborder_property = | |
627 | drm_property_create_range(adev->ddev, 0, | |
628 | "underscan vborder", 0, 128); | |
629 | if (!adev->mode_info.underscan_vborder_property) | |
630 | return -ENOMEM; | |
631 | ||
632 | sz = ARRAY_SIZE(amdgpu_audio_enum_list); | |
633 | adev->mode_info.audio_property = | |
634 | drm_property_create_enum(adev->ddev, 0, | |
635 | "audio", | |
636 | amdgpu_audio_enum_list, sz); | |
637 | ||
638 | sz = ARRAY_SIZE(amdgpu_dither_enum_list); | |
639 | adev->mode_info.dither_property = | |
640 | drm_property_create_enum(adev->ddev, 0, | |
641 | "dither", | |
642 | amdgpu_dither_enum_list, sz); | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
647 | void amdgpu_update_display_priority(struct amdgpu_device *adev) | |
648 | { | |
649 | /* adjustment options for the display watermarks */ | |
650 | if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) | |
651 | adev->mode_info.disp_priority = 0; | |
652 | else | |
653 | adev->mode_info.disp_priority = amdgpu_disp_priority; | |
654 | ||
655 | } | |
656 | ||
657 | static bool is_hdtv_mode(const struct drm_display_mode *mode) | |
658 | { | |
659 | /* try and guess if this is a tv or a monitor */ | |
660 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ | |
661 | (mode->vdisplay == 576) || /* 576p */ | |
662 | (mode->vdisplay == 720) || /* 720p */ | |
663 | (mode->vdisplay == 1080)) /* 1080p */ | |
664 | return true; | |
665 | else | |
666 | return false; | |
667 | } | |
668 | ||
669 | bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, | |
670 | const struct drm_display_mode *mode, | |
671 | struct drm_display_mode *adjusted_mode) | |
672 | { | |
673 | struct drm_device *dev = crtc->dev; | |
674 | struct drm_encoder *encoder; | |
675 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
676 | struct amdgpu_encoder *amdgpu_encoder; | |
677 | struct drm_connector *connector; | |
678 | struct amdgpu_connector *amdgpu_connector; | |
679 | u32 src_v = 1, dst_v = 1; | |
680 | u32 src_h = 1, dst_h = 1; | |
681 | ||
682 | amdgpu_crtc->h_border = 0; | |
683 | amdgpu_crtc->v_border = 0; | |
684 | ||
685 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
686 | if (encoder->crtc != crtc) | |
687 | continue; | |
688 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
689 | connector = amdgpu_get_connector_for_encoder(encoder); | |
690 | amdgpu_connector = to_amdgpu_connector(connector); | |
691 | ||
692 | /* set scaling */ | |
693 | if (amdgpu_encoder->rmx_type == RMX_OFF) | |
694 | amdgpu_crtc->rmx_type = RMX_OFF; | |
695 | else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || | |
696 | mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) | |
697 | amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; | |
698 | else | |
699 | amdgpu_crtc->rmx_type = RMX_OFF; | |
700 | /* copy native mode */ | |
701 | memcpy(&amdgpu_crtc->native_mode, | |
702 | &amdgpu_encoder->native_mode, | |
703 | sizeof(struct drm_display_mode)); | |
704 | src_v = crtc->mode.vdisplay; | |
705 | dst_v = amdgpu_crtc->native_mode.vdisplay; | |
706 | src_h = crtc->mode.hdisplay; | |
707 | dst_h = amdgpu_crtc->native_mode.hdisplay; | |
708 | ||
709 | /* fix up for overscan on hdmi */ | |
710 | if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && | |
711 | ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || | |
712 | ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && | |
713 | drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && | |
714 | is_hdtv_mode(mode)))) { | |
715 | if (amdgpu_encoder->underscan_hborder != 0) | |
716 | amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; | |
717 | else | |
718 | amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; | |
719 | if (amdgpu_encoder->underscan_vborder != 0) | |
720 | amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; | |
721 | else | |
722 | amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; | |
723 | amdgpu_crtc->rmx_type = RMX_FULL; | |
724 | src_v = crtc->mode.vdisplay; | |
725 | dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); | |
726 | src_h = crtc->mode.hdisplay; | |
727 | dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); | |
728 | } | |
729 | } | |
730 | if (amdgpu_crtc->rmx_type != RMX_OFF) { | |
731 | fixed20_12 a, b; | |
732 | a.full = dfixed_const(src_v); | |
733 | b.full = dfixed_const(dst_v); | |
734 | amdgpu_crtc->vsc.full = dfixed_div(a, b); | |
735 | a.full = dfixed_const(src_h); | |
736 | b.full = dfixed_const(dst_h); | |
737 | amdgpu_crtc->hsc.full = dfixed_div(a, b); | |
738 | } else { | |
739 | amdgpu_crtc->vsc.full = dfixed_const(1); | |
740 | amdgpu_crtc->hsc.full = dfixed_const(1); | |
741 | } | |
742 | return true; | |
743 | } | |
744 | ||
745 | /* | |
746 | * Retrieve current video scanout position of crtc on a given gpu, and | |
747 | * an optional accurate timestamp of when query happened. | |
748 | * | |
749 | * \param dev Device to query. | |
88e72717 | 750 | * \param pipe Crtc to query. |
d38ceaf9 | 751 | * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). |
8e36f9d3 AD |
752 | * For driver internal use only also supports these flags: |
753 | * | |
754 | * USE_REAL_VBLANKSTART to use the real start of vblank instead | |
755 | * of a fudged earlier start of vblank. | |
756 | * | |
757 | * GET_DISTANCE_TO_VBLANKSTART to return distance to the | |
758 | * fudged earlier start of vblank in *vpos and the distance | |
759 | * to true start of vblank in *hpos. | |
760 | * | |
d38ceaf9 AD |
761 | * \param *vpos Location where vertical scanout position should be stored. |
762 | * \param *hpos Location where horizontal scanout position should go. | |
763 | * \param *stime Target location for timestamp taken immediately before | |
764 | * scanout position query. Can be NULL to skip timestamp. | |
765 | * \param *etime Target location for timestamp taken immediately after | |
766 | * scanout position query. Can be NULL to skip timestamp. | |
767 | * | |
768 | * Returns vpos as a positive number while in active scanout area. | |
769 | * Returns vpos as a negative number inside vblank, counting the number | |
770 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline | |
771 | * until start of active scanout / end of vblank." | |
772 | * | |
773 | * \return Flags, or'ed together as follows: | |
774 | * | |
775 | * DRM_SCANOUTPOS_VALID = Query successful. | |
776 | * DRM_SCANOUTPOS_INVBL = Inside vblank. | |
777 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of | |
778 | * this flag means that returned position may be offset by a constant but | |
779 | * unknown small number of scanlines wrt. real scanout position. | |
780 | * | |
781 | */ | |
88e72717 TR |
782 | int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
783 | unsigned int flags, int *vpos, int *hpos, | |
784 | ktime_t *stime, ktime_t *etime, | |
3bb403bf | 785 | const struct drm_display_mode *mode) |
d38ceaf9 AD |
786 | { |
787 | u32 vbl = 0, position = 0; | |
788 | int vbl_start, vbl_end, vtotal, ret = 0; | |
789 | bool in_vbl = true; | |
790 | ||
791 | struct amdgpu_device *adev = dev->dev_private; | |
792 | ||
793 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ | |
794 | ||
795 | /* Get optional system timestamp before query. */ | |
796 | if (stime) | |
797 | *stime = ktime_get(); | |
798 | ||
88e72717 | 799 | if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) |
d38ceaf9 AD |
800 | ret |= DRM_SCANOUTPOS_VALID; |
801 | ||
802 | /* Get optional system timestamp after query. */ | |
803 | if (etime) | |
804 | *etime = ktime_get(); | |
805 | ||
806 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
807 | ||
808 | /* Decode into vertical and horizontal scanout position. */ | |
809 | *vpos = position & 0x1fff; | |
810 | *hpos = (position >> 16) & 0x1fff; | |
811 | ||
812 | /* Valid vblank area boundaries from gpu retrieved? */ | |
813 | if (vbl > 0) { | |
814 | /* Yes: Decode. */ | |
815 | ret |= DRM_SCANOUTPOS_ACCURATE; | |
816 | vbl_start = vbl & 0x1fff; | |
817 | vbl_end = (vbl >> 16) & 0x1fff; | |
818 | } | |
819 | else { | |
820 | /* No: Fake something reasonable which gives at least ok results. */ | |
3bb403bf | 821 | vbl_start = mode->crtc_vdisplay; |
d38ceaf9 AD |
822 | vbl_end = 0; |
823 | } | |
824 | ||
8e36f9d3 AD |
825 | /* Called from driver internal vblank counter query code? */ |
826 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { | |
827 | /* Caller wants distance from real vbl_start in *hpos */ | |
828 | *hpos = *vpos - vbl_start; | |
829 | } | |
830 | ||
831 | /* Fudge vblank to start a few scanlines earlier to handle the | |
832 | * problem that vblank irqs fire a few scanlines before start | |
833 | * of vblank. Some driver internal callers need the true vblank | |
834 | * start to be used and signal this via the USE_REAL_VBLANKSTART flag. | |
835 | * | |
836 | * The cause of the "early" vblank irq is that the irq is triggered | |
837 | * by the line buffer logic when the line buffer read position enters | |
838 | * the vblank, whereas our crtc scanout position naturally lags the | |
839 | * line buffer read position. | |
840 | */ | |
841 | if (!(flags & USE_REAL_VBLANKSTART)) | |
842 | vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; | |
843 | ||
d38ceaf9 AD |
844 | /* Test scanout position against vblank region. */ |
845 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) | |
846 | in_vbl = false; | |
847 | ||
8e36f9d3 AD |
848 | /* In vblank? */ |
849 | if (in_vbl) | |
850 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
851 | ||
852 | /* Called from driver internal vblank counter query code? */ | |
853 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { | |
854 | /* Caller wants distance from fudged earlier vbl_start */ | |
855 | *vpos -= vbl_start; | |
856 | return ret; | |
857 | } | |
858 | ||
d38ceaf9 AD |
859 | /* Check if inside vblank area and apply corrective offsets: |
860 | * vpos will then be >=0 in video scanout area, but negative | |
861 | * within vblank area, counting down the number of lines until | |
862 | * start of scanout. | |
863 | */ | |
864 | ||
865 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ | |
866 | if (in_vbl && (*vpos >= vbl_start)) { | |
3bb403bf | 867 | vtotal = mode->crtc_vtotal; |
d38ceaf9 AD |
868 | *vpos = *vpos - vtotal; |
869 | } | |
870 | ||
871 | /* Correct for shifted end of vbl at vbl_end. */ | |
872 | *vpos = *vpos - vbl_end; | |
873 | ||
d38ceaf9 AD |
874 | return ret; |
875 | } | |
876 | ||
877 | int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) | |
878 | { | |
879 | if (crtc < 0 || crtc >= adev->mode_info.num_crtc) | |
880 | return AMDGPU_CRTC_IRQ_NONE; | |
881 | ||
882 | switch (crtc) { | |
883 | case 0: | |
884 | return AMDGPU_CRTC_IRQ_VBLANK1; | |
885 | case 1: | |
886 | return AMDGPU_CRTC_IRQ_VBLANK2; | |
887 | case 2: | |
888 | return AMDGPU_CRTC_IRQ_VBLANK3; | |
889 | case 3: | |
890 | return AMDGPU_CRTC_IRQ_VBLANK4; | |
891 | case 4: | |
892 | return AMDGPU_CRTC_IRQ_VBLANK5; | |
893 | case 5: | |
894 | return AMDGPU_CRTC_IRQ_VBLANK6; | |
895 | default: | |
896 | return AMDGPU_CRTC_IRQ_NONE; | |
897 | } | |
898 | } |