]>
Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
fdf2f6c5 | 26 | |
d38ceaf9 AD |
27 | #include <drm/amdgpu_drm.h> |
28 | #include "amdgpu.h" | |
29 | #include "amdgpu_i2c.h" | |
30 | #include "atom.h" | |
31 | #include "amdgpu_connectors.h" | |
5d43be0c | 32 | #include "amdgpu_display.h" |
d38ceaf9 AD |
33 | #include <asm/div64.h> |
34 | ||
fdf2f6c5 | 35 | #include <linux/pci.h> |
d38ceaf9 AD |
36 | #include <linux/pm_runtime.h> |
37 | #include <drm/drm_crtc_helper.h> | |
38 | #include <drm/drm_edid.h> | |
e68d14dd | 39 | #include <drm/drm_gem_framebuffer_helper.h> |
ab77e02c | 40 | #include <drm/drm_fb_helper.h> |
fdf2f6c5 | 41 | #include <drm/drm_vblank.h> |
d38ceaf9 | 42 | |
3a05dc00 SL |
43 | static void amdgpu_display_flip_callback(struct dma_fence *f, |
44 | struct dma_fence_cb *cb) | |
1ffd2652 | 45 | { |
c3874b75 CK |
46 | struct amdgpu_flip_work *work = |
47 | container_of(cb, struct amdgpu_flip_work, cb); | |
1ffd2652 | 48 | |
f54d1867 | 49 | dma_fence_put(f); |
325cbba1 | 50 | schedule_work(&work->flip_work.work); |
c3874b75 | 51 | } |
1ffd2652 | 52 | |
3a05dc00 SL |
53 | static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, |
54 | struct dma_fence **f) | |
c3874b75 | 55 | { |
f54d1867 | 56 | struct dma_fence *fence= *f; |
c3874b75 CK |
57 | |
58 | if (fence == NULL) | |
59 | return false; | |
1ffd2652 | 60 | |
1ffd2652 | 61 | *f = NULL; |
c3874b75 | 62 | |
3a05dc00 SL |
63 | if (!dma_fence_add_callback(fence, &work->cb, |
64 | amdgpu_display_flip_callback)) | |
c3874b75 CK |
65 | return true; |
66 | ||
f54d1867 | 67 | dma_fence_put(fence); |
c3874b75 | 68 | return false; |
1ffd2652 | 69 | } |
d38ceaf9 | 70 | |
3a05dc00 | 71 | static void amdgpu_display_flip_work_func(struct work_struct *__work) |
d38ceaf9 | 72 | { |
325cbba1 MD |
73 | struct delayed_work *delayed_work = |
74 | container_of(__work, struct delayed_work, work); | |
d38ceaf9 | 75 | struct amdgpu_flip_work *work = |
325cbba1 | 76 | container_of(delayed_work, struct amdgpu_flip_work, flip_work); |
d38ceaf9 | 77 | struct amdgpu_device *adev = work->adev; |
f93932bc | 78 | struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; |
d38ceaf9 | 79 | |
f93932bc | 80 | struct drm_crtc *crtc = &amdgpu_crtc->base; |
d38ceaf9 | 81 | unsigned long flags; |
325cbba1 MD |
82 | unsigned i; |
83 | int vpos, hpos; | |
d38ceaf9 | 84 | |
3a05dc00 | 85 | if (amdgpu_display_flip_handle_fence(work, &work->excl)) |
c3874b75 CK |
86 | return; |
87 | ||
1ffd2652 | 88 | for (i = 0; i < work->shared_count; ++i) |
3a05dc00 | 89 | if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) |
c3874b75 | 90 | return; |
d38ceaf9 | 91 | |
325cbba1 MD |
92 | /* Wait until we're out of the vertical blank period before the one |
93 | * targeted by the flip | |
8e36f9d3 | 94 | */ |
f93932bc | 95 | if (amdgpu_crtc->enabled && |
aa8e286a SL |
96 | (amdgpu_display_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 0, |
97 | &vpos, &hpos, NULL, NULL, | |
98 | &crtc->hwmode) | |
325cbba1 MD |
99 | & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == |
100 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && | |
101 | (int)(work->target_vblank - | |
f93932bc | 102 | amdgpu_get_vblank_counter_kms(adev->ddev, amdgpu_crtc->crtc_id)) > 0) { |
325cbba1 MD |
103 | schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); |
104 | return; | |
9c3578af | 105 | } |
8e36f9d3 | 106 | |
325cbba1 MD |
107 | /* We borrow the event spin lock for protecting flip_status */ |
108 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
e1d09dc0 | 109 | |
bd4c72d1 | 110 | /* Do the flip (mmio) */ |
cb9e59d7 | 111 | adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); |
bd4c72d1 AG |
112 | |
113 | /* Set the flip status */ | |
f93932bc | 114 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; |
d38ceaf9 | 115 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
6bd9e877 | 116 | |
bd4c72d1 AG |
117 | |
118 | DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", | |
f93932bc | 119 | amdgpu_crtc->crtc_id, amdgpu_crtc, work); |
bd4c72d1 | 120 | |
d38ceaf9 AD |
121 | } |
122 | ||
123 | /* | |
124 | * Handle unpin events outside the interrupt handler proper. | |
125 | */ | |
3a05dc00 | 126 | static void amdgpu_display_unpin_work_func(struct work_struct *__work) |
d38ceaf9 AD |
127 | { |
128 | struct amdgpu_flip_work *work = | |
129 | container_of(__work, struct amdgpu_flip_work, unpin_work); | |
130 | int r; | |
131 | ||
132 | /* unpin of the old buffer */ | |
c81a1a74 | 133 | r = amdgpu_bo_reserve(work->old_abo, true); |
d38ceaf9 | 134 | if (likely(r == 0)) { |
765e7fbf | 135 | r = amdgpu_bo_unpin(work->old_abo); |
d38ceaf9 AD |
136 | if (unlikely(r != 0)) { |
137 | DRM_ERROR("failed to unpin buffer after flip\n"); | |
138 | } | |
765e7fbf | 139 | amdgpu_bo_unreserve(work->old_abo); |
d38ceaf9 AD |
140 | } else |
141 | DRM_ERROR("failed to reserve buffer after flip\n"); | |
142 | ||
765e7fbf | 143 | amdgpu_bo_unref(&work->old_abo); |
1ffd2652 | 144 | kfree(work->shared); |
d38ceaf9 AD |
145 | kfree(work); |
146 | } | |
147 | ||
0cd11932 SL |
148 | int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, |
149 | struct drm_framebuffer *fb, | |
150 | struct drm_pending_vblank_event *event, | |
151 | uint32_t page_flip_flags, uint32_t target, | |
152 | struct drm_modeset_acquire_ctx *ctx) | |
d38ceaf9 AD |
153 | { |
154 | struct drm_device *dev = crtc->dev; | |
155 | struct amdgpu_device *adev = dev->dev_private; | |
156 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
d38ceaf9 AD |
157 | struct drm_gem_object *obj; |
158 | struct amdgpu_flip_work *work; | |
765e7fbf | 159 | struct amdgpu_bo *new_abo; |
d38ceaf9 AD |
160 | unsigned long flags; |
161 | u64 tiling_flags; | |
5f42aa39 | 162 | int i, r; |
d38ceaf9 AD |
163 | |
164 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
165 | if (work == NULL) | |
166 | return -ENOMEM; | |
167 | ||
3a05dc00 SL |
168 | INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); |
169 | INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); | |
d38ceaf9 AD |
170 | |
171 | work->event = event; | |
172 | work->adev = adev; | |
173 | work->crtc_id = amdgpu_crtc->crtc_id; | |
cb9e59d7 | 174 | work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; |
d38ceaf9 AD |
175 | |
176 | /* schedule unpin of the old buffer */ | |
e68d14dd | 177 | obj = crtc->primary->fb->obj[0]; |
d38ceaf9 AD |
178 | |
179 | /* take a reference to the old object */ | |
765e7fbf CK |
180 | work->old_abo = gem_to_amdgpu_bo(obj); |
181 | amdgpu_bo_ref(work->old_abo); | |
d38ceaf9 | 182 | |
e68d14dd | 183 | obj = fb->obj[0]; |
765e7fbf | 184 | new_abo = gem_to_amdgpu_bo(obj); |
d38ceaf9 AD |
185 | |
186 | /* pin the new buffer */ | |
765e7fbf | 187 | r = amdgpu_bo_reserve(new_abo, false); |
d38ceaf9 | 188 | if (unlikely(r != 0)) { |
765e7fbf | 189 | DRM_ERROR("failed to reserve new abo buffer before flip\n"); |
d38ceaf9 AD |
190 | goto cleanup; |
191 | } | |
192 | ||
47bbcc1e | 193 | if (!adev->enable_virtual_display) { |
f2bd8a0e AG |
194 | r = amdgpu_bo_pin(new_abo, |
195 | amdgpu_display_supported_domains(adev, new_abo->flags)); | |
47bbcc1e ED |
196 | if (unlikely(r != 0)) { |
197 | DRM_ERROR("failed to pin new abo buffer before flip\n"); | |
198 | goto unreserve; | |
199 | } | |
d38ceaf9 AD |
200 | } |
201 | ||
bb812f1e JZ |
202 | r = amdgpu_ttm_alloc_gart(&new_abo->tbo); |
203 | if (unlikely(r != 0)) { | |
204 | DRM_ERROR("%p bind failed\n", new_abo); | |
205 | goto unpin; | |
206 | } | |
207 | ||
52791eee | 208 | r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl, |
1ffd2652 CK |
209 | &work->shared_count, |
210 | &work->shared); | |
211 | if (unlikely(r != 0)) { | |
1ffd2652 | 212 | DRM_ERROR("failed to get fences for buffer\n"); |
ee7fd957 | 213 | goto unpin; |
1ffd2652 CK |
214 | } |
215 | ||
765e7fbf CK |
216 | amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); |
217 | amdgpu_bo_unreserve(new_abo); | |
d38ceaf9 | 218 | |
47bbcc1e ED |
219 | if (!adev->enable_virtual_display) |
220 | work->base = amdgpu_bo_gpu_offset(new_abo); | |
23effc11 | 221 | work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + |
325cbba1 | 222 | amdgpu_get_vblank_counter_kms(dev, work->crtc_id); |
d38ceaf9 AD |
223 | |
224 | /* we borrow the event spin lock for protecting flip_wrok */ | |
225 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
226 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { | |
227 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
228 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
229 | r = -EBUSY; | |
325cbba1 | 230 | goto pflip_cleanup; |
d38ceaf9 AD |
231 | } |
232 | ||
233 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; | |
234 | amdgpu_crtc->pflip_works = work; | |
235 | ||
5f42aa39 HW |
236 | |
237 | DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", | |
238 | amdgpu_crtc->crtc_id, amdgpu_crtc, work); | |
d38ceaf9 AD |
239 | /* update crtc fb */ |
240 | crtc->primary->fb = fb; | |
241 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
3a05dc00 | 242 | amdgpu_display_flip_work_func(&work->flip_work.work); |
5f42aa39 | 243 | return 0; |
d38ceaf9 | 244 | |
5f42aa39 HW |
245 | pflip_cleanup: |
246 | if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { | |
247 | DRM_ERROR("failed to reserve new abo in error path\n"); | |
248 | goto cleanup; | |
249 | } | |
250 | unpin: | |
47bbcc1e ED |
251 | if (!adev->enable_virtual_display) |
252 | if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) | |
253 | DRM_ERROR("failed to unpin new abo in error path\n"); | |
254 | ||
5f42aa39 HW |
255 | unreserve: |
256 | amdgpu_bo_unreserve(new_abo); | |
cb341a31 | 257 | |
5f42aa39 HW |
258 | cleanup: |
259 | amdgpu_bo_unref(&work->old_abo); | |
260 | dma_fence_put(work->excl); | |
261 | for (i = 0; i < work->shared_count; ++i) | |
262 | dma_fence_put(work->shared[i]); | |
263 | kfree(work->shared); | |
264 | kfree(work); | |
9c5b2b0d | 265 | |
5f42aa39 | 266 | return r; |
d38ceaf9 AD |
267 | } |
268 | ||
775a8364 SL |
269 | int amdgpu_display_crtc_set_config(struct drm_mode_set *set, |
270 | struct drm_modeset_acquire_ctx *ctx) | |
d38ceaf9 AD |
271 | { |
272 | struct drm_device *dev; | |
273 | struct amdgpu_device *adev; | |
274 | struct drm_crtc *crtc; | |
275 | bool active = false; | |
276 | int ret; | |
277 | ||
278 | if (!set || !set->crtc) | |
279 | return -EINVAL; | |
280 | ||
281 | dev = set->crtc->dev; | |
282 | ||
283 | ret = pm_runtime_get_sync(dev->dev); | |
284 | if (ret < 0) | |
285 | return ret; | |
286 | ||
a4eff9aa | 287 | ret = drm_crtc_helper_set_config(set, ctx); |
d38ceaf9 AD |
288 | |
289 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
290 | if (crtc->enabled) | |
291 | active = true; | |
292 | ||
293 | pm_runtime_mark_last_busy(dev->dev); | |
294 | ||
295 | adev = dev->dev_private; | |
296 | /* if we have active crtcs and we don't have a power ref, | |
297 | take the current one */ | |
298 | if (active && !adev->have_disp_power_ref) { | |
299 | adev->have_disp_power_ref = true; | |
300 | return ret; | |
301 | } | |
302 | /* if we have no active crtcs, then drop the power ref | |
303 | we got before */ | |
304 | if (!active && adev->have_disp_power_ref) { | |
305 | pm_runtime_put_autosuspend(dev->dev); | |
306 | adev->have_disp_power_ref = false; | |
307 | } | |
308 | ||
309 | /* drop the power reference we got coming in here */ | |
310 | pm_runtime_put_autosuspend(dev->dev); | |
311 | return ret; | |
312 | } | |
313 | ||
c6e14f40 | 314 | static const char *encoder_names[41] = { |
d38ceaf9 AD |
315 | "NONE", |
316 | "INTERNAL_LVDS", | |
317 | "INTERNAL_TMDS1", | |
318 | "INTERNAL_TMDS2", | |
319 | "INTERNAL_DAC1", | |
320 | "INTERNAL_DAC2", | |
321 | "INTERNAL_SDVOA", | |
322 | "INTERNAL_SDVOB", | |
323 | "SI170B", | |
324 | "CH7303", | |
325 | "CH7301", | |
326 | "INTERNAL_DVO1", | |
327 | "EXTERNAL_SDVOA", | |
328 | "EXTERNAL_SDVOB", | |
329 | "TITFP513", | |
330 | "INTERNAL_LVTM1", | |
331 | "VT1623", | |
332 | "HDMI_SI1930", | |
333 | "HDMI_INTERNAL", | |
334 | "INTERNAL_KLDSCP_TMDS1", | |
335 | "INTERNAL_KLDSCP_DVO1", | |
336 | "INTERNAL_KLDSCP_DAC1", | |
337 | "INTERNAL_KLDSCP_DAC2", | |
338 | "SI178", | |
339 | "MVPU_FPGA", | |
340 | "INTERNAL_DDI", | |
341 | "VT1625", | |
342 | "HDMI_SI1932", | |
343 | "DP_AN9801", | |
344 | "DP_DP501", | |
345 | "INTERNAL_UNIPHY", | |
346 | "INTERNAL_KLDSCP_LVTMA", | |
347 | "INTERNAL_UNIPHY1", | |
348 | "INTERNAL_UNIPHY2", | |
349 | "NUTMEG", | |
350 | "TRAVIS", | |
351 | "INTERNAL_VCE", | |
352 | "INTERNAL_UNIPHY3", | |
c6e14f40 ED |
353 | "HDMI_ANX9805", |
354 | "INTERNAL_AMCLK", | |
355 | "VIRTUAL", | |
d38ceaf9 AD |
356 | }; |
357 | ||
358 | static const char *hpd_names[6] = { | |
359 | "HPD1", | |
360 | "HPD2", | |
361 | "HPD3", | |
362 | "HPD4", | |
363 | "HPD5", | |
364 | "HPD6", | |
365 | }; | |
366 | ||
50af9193 | 367 | void amdgpu_display_print_display_setup(struct drm_device *dev) |
d38ceaf9 AD |
368 | { |
369 | struct drm_connector *connector; | |
370 | struct amdgpu_connector *amdgpu_connector; | |
371 | struct drm_encoder *encoder; | |
372 | struct amdgpu_encoder *amdgpu_encoder; | |
f8d2d39e | 373 | struct drm_connector_list_iter iter; |
d38ceaf9 AD |
374 | uint32_t devices; |
375 | int i = 0; | |
376 | ||
f8d2d39e | 377 | drm_connector_list_iter_begin(dev, &iter); |
d38ceaf9 | 378 | DRM_INFO("AMDGPU Display Connectors\n"); |
f8d2d39e | 379 | drm_for_each_connector_iter(connector, &iter) { |
d38ceaf9 AD |
380 | amdgpu_connector = to_amdgpu_connector(connector); |
381 | DRM_INFO("Connector %d:\n", i); | |
382 | DRM_INFO(" %s\n", connector->name); | |
383 | if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) | |
384 | DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); | |
385 | if (amdgpu_connector->ddc_bus) { | |
386 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", | |
387 | amdgpu_connector->ddc_bus->rec.mask_clk_reg, | |
388 | amdgpu_connector->ddc_bus->rec.mask_data_reg, | |
389 | amdgpu_connector->ddc_bus->rec.a_clk_reg, | |
390 | amdgpu_connector->ddc_bus->rec.a_data_reg, | |
391 | amdgpu_connector->ddc_bus->rec.en_clk_reg, | |
392 | amdgpu_connector->ddc_bus->rec.en_data_reg, | |
393 | amdgpu_connector->ddc_bus->rec.y_clk_reg, | |
394 | amdgpu_connector->ddc_bus->rec.y_data_reg); | |
395 | if (amdgpu_connector->router.ddc_valid) | |
396 | DRM_INFO(" DDC Router 0x%x/0x%x\n", | |
397 | amdgpu_connector->router.ddc_mux_control_pin, | |
398 | amdgpu_connector->router.ddc_mux_state); | |
399 | if (amdgpu_connector->router.cd_valid) | |
400 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", | |
401 | amdgpu_connector->router.cd_mux_control_pin, | |
402 | amdgpu_connector->router.cd_mux_state); | |
403 | } else { | |
404 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || | |
405 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || | |
406 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || | |
407 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || | |
408 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
409 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
410 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); | |
411 | } | |
412 | DRM_INFO(" Encoders:\n"); | |
413 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
414 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
415 | devices = amdgpu_encoder->devices & amdgpu_connector->devices; | |
416 | if (devices) { | |
417 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) | |
418 | DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
419 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) | |
420 | DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
421 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) | |
422 | DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
423 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) | |
424 | DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
425 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) | |
426 | DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
427 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) | |
428 | DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
429 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) | |
430 | DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
431 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) | |
432 | DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
433 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) | |
434 | DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
435 | if (devices & ATOM_DEVICE_TV1_SUPPORT) | |
436 | DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
437 | if (devices & ATOM_DEVICE_CV_SUPPORT) | |
438 | DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
439 | } | |
440 | } | |
441 | i++; | |
442 | } | |
f8d2d39e | 443 | drm_connector_list_iter_end(&iter); |
d38ceaf9 AD |
444 | } |
445 | ||
446 | /** | |
e0b5b5ec | 447 | * amdgpu_display_ddc_probe |
d38ceaf9 AD |
448 | * |
449 | */ | |
e0b5b5ec SL |
450 | bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, |
451 | bool use_aux) | |
d38ceaf9 AD |
452 | { |
453 | u8 out = 0x0; | |
454 | u8 buf[8]; | |
455 | int ret; | |
456 | struct i2c_msg msgs[] = { | |
457 | { | |
458 | .addr = DDC_ADDR, | |
459 | .flags = 0, | |
460 | .len = 1, | |
461 | .buf = &out, | |
462 | }, | |
463 | { | |
464 | .addr = DDC_ADDR, | |
465 | .flags = I2C_M_RD, | |
466 | .len = 8, | |
467 | .buf = buf, | |
468 | } | |
469 | }; | |
470 | ||
471 | /* on hw with routers, select right port */ | |
472 | if (amdgpu_connector->router.ddc_valid) | |
473 | amdgpu_i2c_router_select_ddc_port(amdgpu_connector); | |
474 | ||
475 | if (use_aux) { | |
476 | ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); | |
477 | } else { | |
478 | ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); | |
479 | } | |
480 | ||
481 | if (ret != 2) | |
482 | /* Couldn't find an accessible DDC on this connector */ | |
483 | return false; | |
484 | /* Probe also for valid EDID header | |
485 | * EDID header starts with: | |
486 | * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. | |
487 | * Only the first 6 bytes must be valid as | |
488 | * drm_edid_block_valid() can fix the last 2 bytes */ | |
489 | if (drm_edid_header_is_valid(buf) < 6) { | |
490 | /* Couldn't find an accessible EDID on this | |
491 | * connector */ | |
492 | return false; | |
493 | } | |
494 | return true; | |
495 | } | |
496 | ||
d38ceaf9 | 497 | static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { |
e68d14dd DS |
498 | .destroy = drm_gem_fb_destroy, |
499 | .create_handle = drm_gem_fb_create_handle, | |
d38ceaf9 AD |
500 | }; |
501 | ||
f2bd8a0e AG |
502 | uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, |
503 | uint64_t bo_flags) | |
5d43be0c CK |
504 | { |
505 | uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; | |
506 | ||
2c9c178b | 507 | #if defined(CONFIG_DRM_AMD_DC) |
ddcb7fc6 | 508 | /* |
f2bd8a0e | 509 | * if amdgpu_bo_support_uswc returns false it means that USWC mappings |
ddcb7fc6 AG |
510 | * is not supported for this board. But this mapping is required |
511 | * to avoid hang caused by placement of scanout BO in GTT on certain | |
512 | * APUs. So force the BO placement to VRAM in case this architecture | |
513 | * will not allow USWC mappings. | |
f2bd8a0e | 514 | * Also, don't allow GTT domain if the BO doens't have USWC falg set. |
ddcb7fc6 | 515 | */ |
f2bd8a0e | 516 | if (adev->asic_type >= CHIP_CARRIZO && |
2aa87ba5 | 517 | adev->asic_type < CHIP_RAVEN && |
f2bd8a0e AG |
518 | (adev->flags & AMD_IS_APU) && |
519 | (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && | |
520 | amdgpu_bo_support_uswc(bo_flags) && | |
2c9c178b | 521 | amdgpu_device_asic_has_dc_support(adev->asic_type)) |
5d43be0c | 522 | domain |= AMDGPU_GEM_DOMAIN_GTT; |
2c9c178b | 523 | #endif |
5d43be0c CK |
524 | |
525 | return domain; | |
526 | } | |
527 | ||
9da3f2d9 SL |
528 | int amdgpu_display_framebuffer_init(struct drm_device *dev, |
529 | struct amdgpu_framebuffer *rfb, | |
530 | const struct drm_mode_fb_cmd2 *mode_cmd, | |
531 | struct drm_gem_object *obj) | |
d38ceaf9 AD |
532 | { |
533 | int ret; | |
e68d14dd | 534 | rfb->base.obj[0] = obj; |
a3f913ca | 535 | drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); |
d38ceaf9 AD |
536 | ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); |
537 | if (ret) { | |
e68d14dd | 538 | rfb->base.obj[0] = NULL; |
d38ceaf9 AD |
539 | return ret; |
540 | } | |
541 | return 0; | |
542 | } | |
543 | ||
b0fb632f | 544 | struct drm_framebuffer * |
4d4772f6 SL |
545 | amdgpu_display_user_framebuffer_create(struct drm_device *dev, |
546 | struct drm_file *file_priv, | |
547 | const struct drm_mode_fb_cmd2 *mode_cmd) | |
d38ceaf9 AD |
548 | { |
549 | struct drm_gem_object *obj; | |
550 | struct amdgpu_framebuffer *amdgpu_fb; | |
551 | int ret; | |
552 | ||
a8ad0bd8 | 553 | obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); |
d38ceaf9 AD |
554 | if (obj == NULL) { |
555 | dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " | |
556 | "can't create framebuffer\n", mode_cmd->handles[0]); | |
557 | return ERR_PTR(-ENOENT); | |
558 | } | |
559 | ||
1769152a CJHR |
560 | /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ |
561 | if (obj->import_attach) { | |
562 | DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); | |
563 | return ERR_PTR(-EINVAL); | |
564 | } | |
565 | ||
d38ceaf9 AD |
566 | amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); |
567 | if (amdgpu_fb == NULL) { | |
f62facc2 | 568 | drm_gem_object_put_unlocked(obj); |
d38ceaf9 AD |
569 | return ERR_PTR(-ENOMEM); |
570 | } | |
571 | ||
9da3f2d9 | 572 | ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); |
d38ceaf9 AD |
573 | if (ret) { |
574 | kfree(amdgpu_fb); | |
f62facc2 | 575 | drm_gem_object_put_unlocked(obj); |
d38ceaf9 AD |
576 | return ERR_PTR(ret); |
577 | } | |
578 | ||
579 | return &amdgpu_fb->base; | |
580 | } | |
581 | ||
d38ceaf9 | 582 | const struct drm_mode_config_funcs amdgpu_mode_funcs = { |
4d4772f6 | 583 | .fb_create = amdgpu_display_user_framebuffer_create, |
ab77e02c | 584 | .output_poll_changed = drm_fb_helper_output_poll_changed, |
d38ceaf9 AD |
585 | }; |
586 | ||
f498d9ed | 587 | static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = |
d38ceaf9 AD |
588 | { { UNDERSCAN_OFF, "off" }, |
589 | { UNDERSCAN_ON, "on" }, | |
590 | { UNDERSCAN_AUTO, "auto" }, | |
591 | }; | |
592 | ||
f498d9ed | 593 | static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = |
d38ceaf9 AD |
594 | { { AMDGPU_AUDIO_DISABLE, "off" }, |
595 | { AMDGPU_AUDIO_ENABLE, "on" }, | |
596 | { AMDGPU_AUDIO_AUTO, "auto" }, | |
597 | }; | |
598 | ||
599 | /* XXX support different dither options? spatial, temporal, both, etc. */ | |
f498d9ed | 600 | static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = |
d38ceaf9 AD |
601 | { { AMDGPU_FMT_DITHER_DISABLE, "off" }, |
602 | { AMDGPU_FMT_DITHER_ENABLE, "on" }, | |
603 | }; | |
604 | ||
3dc9b1ce | 605 | int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) |
d38ceaf9 AD |
606 | { |
607 | int sz; | |
608 | ||
f7e9e9fe NW |
609 | adev->mode_info.coherent_mode_property = |
610 | drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); | |
611 | if (!adev->mode_info.coherent_mode_property) | |
612 | return -ENOMEM; | |
d38ceaf9 AD |
613 | |
614 | adev->mode_info.load_detect_property = | |
615 | drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); | |
616 | if (!adev->mode_info.load_detect_property) | |
617 | return -ENOMEM; | |
618 | ||
619 | drm_mode_create_scaling_mode_property(adev->ddev); | |
620 | ||
621 | sz = ARRAY_SIZE(amdgpu_underscan_enum_list); | |
622 | adev->mode_info.underscan_property = | |
623 | drm_property_create_enum(adev->ddev, 0, | |
624 | "underscan", | |
625 | amdgpu_underscan_enum_list, sz); | |
626 | ||
627 | adev->mode_info.underscan_hborder_property = | |
628 | drm_property_create_range(adev->ddev, 0, | |
629 | "underscan hborder", 0, 128); | |
630 | if (!adev->mode_info.underscan_hborder_property) | |
631 | return -ENOMEM; | |
632 | ||
633 | adev->mode_info.underscan_vborder_property = | |
634 | drm_property_create_range(adev->ddev, 0, | |
635 | "underscan vborder", 0, 128); | |
636 | if (!adev->mode_info.underscan_vborder_property) | |
637 | return -ENOMEM; | |
638 | ||
639 | sz = ARRAY_SIZE(amdgpu_audio_enum_list); | |
640 | adev->mode_info.audio_property = | |
641 | drm_property_create_enum(adev->ddev, 0, | |
642 | "audio", | |
643 | amdgpu_audio_enum_list, sz); | |
644 | ||
645 | sz = ARRAY_SIZE(amdgpu_dither_enum_list); | |
646 | adev->mode_info.dither_property = | |
647 | drm_property_create_enum(adev->ddev, 0, | |
648 | "dither", | |
649 | amdgpu_dither_enum_list, sz); | |
650 | ||
e2306cc6 | 651 | if (amdgpu_device_has_dc_support(adev)) { |
c1ee92f9 DF |
652 | adev->mode_info.abm_level_property = |
653 | drm_property_create_range(adev->ddev, 0, | |
654 | "abm level", 0, 4); | |
655 | if (!adev->mode_info.abm_level_property) | |
656 | return -ENOMEM; | |
e2306cc6 NK |
657 | } |
658 | ||
d38ceaf9 AD |
659 | return 0; |
660 | } | |
661 | ||
166140fb | 662 | void amdgpu_display_update_priority(struct amdgpu_device *adev) |
d38ceaf9 AD |
663 | { |
664 | /* adjustment options for the display watermarks */ | |
665 | if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) | |
666 | adev->mode_info.disp_priority = 0; | |
667 | else | |
668 | adev->mode_info.disp_priority = amdgpu_disp_priority; | |
669 | ||
670 | } | |
671 | ||
3a05dc00 | 672 | static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) |
d38ceaf9 AD |
673 | { |
674 | /* try and guess if this is a tv or a monitor */ | |
675 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ | |
676 | (mode->vdisplay == 576) || /* 576p */ | |
677 | (mode->vdisplay == 720) || /* 720p */ | |
678 | (mode->vdisplay == 1080)) /* 1080p */ | |
679 | return true; | |
680 | else | |
681 | return false; | |
682 | } | |
683 | ||
0c16443a SL |
684 | bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
685 | const struct drm_display_mode *mode, | |
686 | struct drm_display_mode *adjusted_mode) | |
d38ceaf9 AD |
687 | { |
688 | struct drm_device *dev = crtc->dev; | |
689 | struct drm_encoder *encoder; | |
690 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
691 | struct amdgpu_encoder *amdgpu_encoder; | |
692 | struct drm_connector *connector; | |
d38ceaf9 AD |
693 | u32 src_v = 1, dst_v = 1; |
694 | u32 src_h = 1, dst_h = 1; | |
695 | ||
696 | amdgpu_crtc->h_border = 0; | |
697 | amdgpu_crtc->v_border = 0; | |
698 | ||
699 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
700 | if (encoder->crtc != crtc) | |
701 | continue; | |
702 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
703 | connector = amdgpu_get_connector_for_encoder(encoder); | |
d38ceaf9 AD |
704 | |
705 | /* set scaling */ | |
706 | if (amdgpu_encoder->rmx_type == RMX_OFF) | |
707 | amdgpu_crtc->rmx_type = RMX_OFF; | |
708 | else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || | |
709 | mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) | |
710 | amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; | |
711 | else | |
712 | amdgpu_crtc->rmx_type = RMX_OFF; | |
713 | /* copy native mode */ | |
714 | memcpy(&amdgpu_crtc->native_mode, | |
715 | &amdgpu_encoder->native_mode, | |
716 | sizeof(struct drm_display_mode)); | |
717 | src_v = crtc->mode.vdisplay; | |
718 | dst_v = amdgpu_crtc->native_mode.vdisplay; | |
719 | src_h = crtc->mode.hdisplay; | |
720 | dst_h = amdgpu_crtc->native_mode.hdisplay; | |
721 | ||
722 | /* fix up for overscan on hdmi */ | |
723 | if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && | |
724 | ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || | |
725 | ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && | |
726 | drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && | |
3a05dc00 | 727 | amdgpu_display_is_hdtv_mode(mode)))) { |
d38ceaf9 AD |
728 | if (amdgpu_encoder->underscan_hborder != 0) |
729 | amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; | |
730 | else | |
731 | amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; | |
732 | if (amdgpu_encoder->underscan_vborder != 0) | |
733 | amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; | |
734 | else | |
735 | amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; | |
736 | amdgpu_crtc->rmx_type = RMX_FULL; | |
737 | src_v = crtc->mode.vdisplay; | |
738 | dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); | |
739 | src_h = crtc->mode.hdisplay; | |
740 | dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); | |
741 | } | |
742 | } | |
743 | if (amdgpu_crtc->rmx_type != RMX_OFF) { | |
744 | fixed20_12 a, b; | |
745 | a.full = dfixed_const(src_v); | |
746 | b.full = dfixed_const(dst_v); | |
747 | amdgpu_crtc->vsc.full = dfixed_div(a, b); | |
748 | a.full = dfixed_const(src_h); | |
749 | b.full = dfixed_const(dst_h); | |
750 | amdgpu_crtc->hsc.full = dfixed_div(a, b); | |
751 | } else { | |
752 | amdgpu_crtc->vsc.full = dfixed_const(1); | |
753 | amdgpu_crtc->hsc.full = dfixed_const(1); | |
754 | } | |
755 | return true; | |
756 | } | |
757 | ||
758 | /* | |
759 | * Retrieve current video scanout position of crtc on a given gpu, and | |
760 | * an optional accurate timestamp of when query happened. | |
761 | * | |
762 | * \param dev Device to query. | |
88e72717 | 763 | * \param pipe Crtc to query. |
d38ceaf9 | 764 | * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). |
8e36f9d3 AD |
765 | * For driver internal use only also supports these flags: |
766 | * | |
767 | * USE_REAL_VBLANKSTART to use the real start of vblank instead | |
768 | * of a fudged earlier start of vblank. | |
769 | * | |
770 | * GET_DISTANCE_TO_VBLANKSTART to return distance to the | |
771 | * fudged earlier start of vblank in *vpos and the distance | |
772 | * to true start of vblank in *hpos. | |
773 | * | |
d38ceaf9 AD |
774 | * \param *vpos Location where vertical scanout position should be stored. |
775 | * \param *hpos Location where horizontal scanout position should go. | |
776 | * \param *stime Target location for timestamp taken immediately before | |
777 | * scanout position query. Can be NULL to skip timestamp. | |
778 | * \param *etime Target location for timestamp taken immediately after | |
779 | * scanout position query. Can be NULL to skip timestamp. | |
780 | * | |
781 | * Returns vpos as a positive number while in active scanout area. | |
782 | * Returns vpos as a negative number inside vblank, counting the number | |
783 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline | |
784 | * until start of active scanout / end of vblank." | |
785 | * | |
786 | * \return Flags, or'ed together as follows: | |
787 | * | |
788 | * DRM_SCANOUTPOS_VALID = Query successful. | |
789 | * DRM_SCANOUTPOS_INVBL = Inside vblank. | |
790 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of | |
791 | * this flag means that returned position may be offset by a constant but | |
792 | * unknown small number of scanlines wrt. real scanout position. | |
793 | * | |
794 | */ | |
aa8e286a SL |
795 | int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, |
796 | unsigned int pipe, unsigned int flags, int *vpos, | |
797 | int *hpos, ktime_t *stime, ktime_t *etime, | |
798 | const struct drm_display_mode *mode) | |
d38ceaf9 AD |
799 | { |
800 | u32 vbl = 0, position = 0; | |
801 | int vbl_start, vbl_end, vtotal, ret = 0; | |
802 | bool in_vbl = true; | |
803 | ||
804 | struct amdgpu_device *adev = dev->dev_private; | |
805 | ||
806 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ | |
807 | ||
808 | /* Get optional system timestamp before query. */ | |
809 | if (stime) | |
810 | *stime = ktime_get(); | |
811 | ||
88e72717 | 812 | if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) |
d38ceaf9 AD |
813 | ret |= DRM_SCANOUTPOS_VALID; |
814 | ||
815 | /* Get optional system timestamp after query. */ | |
816 | if (etime) | |
817 | *etime = ktime_get(); | |
818 | ||
819 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
820 | ||
821 | /* Decode into vertical and horizontal scanout position. */ | |
822 | *vpos = position & 0x1fff; | |
823 | *hpos = (position >> 16) & 0x1fff; | |
824 | ||
825 | /* Valid vblank area boundaries from gpu retrieved? */ | |
826 | if (vbl > 0) { | |
827 | /* Yes: Decode. */ | |
828 | ret |= DRM_SCANOUTPOS_ACCURATE; | |
829 | vbl_start = vbl & 0x1fff; | |
830 | vbl_end = (vbl >> 16) & 0x1fff; | |
831 | } | |
832 | else { | |
833 | /* No: Fake something reasonable which gives at least ok results. */ | |
3bb403bf | 834 | vbl_start = mode->crtc_vdisplay; |
d38ceaf9 AD |
835 | vbl_end = 0; |
836 | } | |
837 | ||
8e36f9d3 AD |
838 | /* Called from driver internal vblank counter query code? */ |
839 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { | |
840 | /* Caller wants distance from real vbl_start in *hpos */ | |
841 | *hpos = *vpos - vbl_start; | |
842 | } | |
843 | ||
844 | /* Fudge vblank to start a few scanlines earlier to handle the | |
845 | * problem that vblank irqs fire a few scanlines before start | |
846 | * of vblank. Some driver internal callers need the true vblank | |
847 | * start to be used and signal this via the USE_REAL_VBLANKSTART flag. | |
848 | * | |
849 | * The cause of the "early" vblank irq is that the irq is triggered | |
850 | * by the line buffer logic when the line buffer read position enters | |
851 | * the vblank, whereas our crtc scanout position naturally lags the | |
852 | * line buffer read position. | |
853 | */ | |
854 | if (!(flags & USE_REAL_VBLANKSTART)) | |
855 | vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; | |
856 | ||
d38ceaf9 AD |
857 | /* Test scanout position against vblank region. */ |
858 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) | |
859 | in_vbl = false; | |
860 | ||
8e36f9d3 AD |
861 | /* In vblank? */ |
862 | if (in_vbl) | |
863 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
864 | ||
865 | /* Called from driver internal vblank counter query code? */ | |
866 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { | |
867 | /* Caller wants distance from fudged earlier vbl_start */ | |
868 | *vpos -= vbl_start; | |
869 | return ret; | |
870 | } | |
871 | ||
d38ceaf9 AD |
872 | /* Check if inside vblank area and apply corrective offsets: |
873 | * vpos will then be >=0 in video scanout area, but negative | |
874 | * within vblank area, counting down the number of lines until | |
875 | * start of scanout. | |
876 | */ | |
877 | ||
878 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ | |
879 | if (in_vbl && (*vpos >= vbl_start)) { | |
3bb403bf | 880 | vtotal = mode->crtc_vtotal; |
520f08df NK |
881 | |
882 | /* With variable refresh rate displays the vpos can exceed | |
883 | * the vtotal value. Clamp to 0 to return -vbl_end instead | |
884 | * of guessing the remaining number of lines until scanout. | |
885 | */ | |
886 | *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; | |
d38ceaf9 AD |
887 | } |
888 | ||
889 | /* Correct for shifted end of vbl at vbl_end. */ | |
890 | *vpos = *vpos - vbl_end; | |
891 | ||
d38ceaf9 AD |
892 | return ret; |
893 | } | |
894 | ||
734dd01d | 895 | int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) |
d38ceaf9 AD |
896 | { |
897 | if (crtc < 0 || crtc >= adev->mode_info.num_crtc) | |
898 | return AMDGPU_CRTC_IRQ_NONE; | |
899 | ||
900 | switch (crtc) { | |
901 | case 0: | |
902 | return AMDGPU_CRTC_IRQ_VBLANK1; | |
903 | case 1: | |
904 | return AMDGPU_CRTC_IRQ_VBLANK2; | |
905 | case 2: | |
906 | return AMDGPU_CRTC_IRQ_VBLANK3; | |
907 | case 3: | |
908 | return AMDGPU_CRTC_IRQ_VBLANK4; | |
909 | case 4: | |
910 | return AMDGPU_CRTC_IRQ_VBLANK5; | |
911 | case 5: | |
912 | return AMDGPU_CRTC_IRQ_VBLANK6; | |
913 | default: | |
914 | return AMDGPU_CRTC_IRQ_NONE; | |
915 | } | |
916 | } |