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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include <drm/drmP.h> | |
27 | #include <drm/amdgpu_drm.h> | |
28 | #include "amdgpu.h" | |
29 | #include "amdgpu_i2c.h" | |
30 | #include "atom.h" | |
31 | #include "amdgpu_connectors.h" | |
32 | #include <asm/div64.h> | |
33 | ||
34 | #include <linux/pm_runtime.h> | |
35 | #include <drm/drm_crtc_helper.h> | |
36 | #include <drm/drm_edid.h> | |
37 | ||
c3874b75 | 38 | static void amdgpu_flip_callback(struct fence *f, struct fence_cb *cb) |
1ffd2652 | 39 | { |
c3874b75 CK |
40 | struct amdgpu_flip_work *work = |
41 | container_of(cb, struct amdgpu_flip_work, cb); | |
1ffd2652 | 42 | |
c3874b75 | 43 | fence_put(f); |
87d58c11 | 44 | schedule_work(&work->flip_work); |
c3874b75 | 45 | } |
1ffd2652 | 46 | |
c3874b75 CK |
47 | static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work, |
48 | struct fence **f) | |
49 | { | |
50 | struct fence *fence= *f; | |
51 | ||
52 | if (fence == NULL) | |
53 | return false; | |
1ffd2652 | 54 | |
1ffd2652 | 55 | *f = NULL; |
c3874b75 CK |
56 | |
57 | if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback)) | |
58 | return true; | |
59 | ||
ab7e9c13 | 60 | fence_put(fence); |
c3874b75 | 61 | return false; |
1ffd2652 | 62 | } |
d38ceaf9 AD |
63 | |
64 | static void amdgpu_flip_work_func(struct work_struct *__work) | |
65 | { | |
66 | struct amdgpu_flip_work *work = | |
67 | container_of(__work, struct amdgpu_flip_work, flip_work); | |
68 | struct amdgpu_device *adev = work->adev; | |
69 | struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; | |
70 | ||
71 | struct drm_crtc *crtc = &amdgpuCrtc->base; | |
d38ceaf9 | 72 | unsigned long flags; |
e1d09dc0 MK |
73 | unsigned i, repcnt = 4; |
74 | int vpos, hpos, stat, min_udelay = 0; | |
8e36f9d3 | 75 | struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; |
d38ceaf9 | 76 | |
c3874b75 CK |
77 | if (amdgpu_flip_handle_fence(work, &work->excl)) |
78 | return; | |
79 | ||
1ffd2652 | 80 | for (i = 0; i < work->shared_count; ++i) |
c3874b75 CK |
81 | if (amdgpu_flip_handle_fence(work, &work->shared[i])) |
82 | return; | |
d38ceaf9 AD |
83 | |
84 | /* We borrow the event spin lock for protecting flip_status */ | |
85 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
86 | ||
8e36f9d3 AD |
87 | /* If this happens to execute within the "virtually extended" vblank |
88 | * interval before the start of the real vblank interval then it needs | |
89 | * to delay programming the mmio flip until the real vblank is entered. | |
90 | * This prevents completing a flip too early due to the way we fudge | |
91 | * our vblank counter and vblank timestamps in order to work around the | |
92 | * problem that the hw fires vblank interrupts before actual start of | |
93 | * vblank (when line buffer refilling is done for a frame). It | |
94 | * complements the fudging logic in amdgpu_get_crtc_scanoutpos() for | |
95 | * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts. | |
96 | * | |
97 | * In practice this won't execute very often unless on very fast | |
98 | * machines because the time window for this to happen is very small. | |
99 | */ | |
90e94b16 | 100 | while (amdgpuCrtc->enabled && --repcnt) { |
8e36f9d3 AD |
101 | /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank |
102 | * start in hpos, and to the "fudged earlier" vblank start in | |
103 | * vpos. | |
104 | */ | |
105 | stat = amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, | |
106 | GET_DISTANCE_TO_VBLANKSTART, | |
107 | &vpos, &hpos, NULL, NULL, | |
108 | &crtc->hwmode); | |
109 | ||
110 | if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != | |
111 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || | |
112 | !(vpos >= 0 && hpos <= 0)) | |
113 | break; | |
114 | ||
115 | /* Sleep at least until estimated real start of hw vblank */ | |
8e36f9d3 | 116 | min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); |
e1d09dc0 MK |
117 | if (min_udelay > vblank->framedur_ns / 2000) { |
118 | /* Don't wait ridiculously long - something is wrong */ | |
119 | repcnt = 0; | |
120 | break; | |
121 | } | |
90e94b16 | 122 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
8e36f9d3 AD |
123 | usleep_range(min_udelay, 2 * min_udelay); |
124 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
125 | }; | |
126 | ||
e1d09dc0 MK |
127 | if (!repcnt) |
128 | DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " | |
129 | "framedur %d, linedur %d, stat %d, vpos %d, " | |
130 | "hpos %d\n", work->crtc_id, min_udelay, | |
131 | vblank->framedur_ns / 1000, | |
132 | vblank->linedur_ns / 1000, stat, vpos, hpos); | |
133 | ||
bd4c72d1 AG |
134 | /* Do the flip (mmio) */ |
135 | adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base); | |
136 | ||
137 | /* Set the flip status */ | |
d38ceaf9 | 138 | amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; |
d38ceaf9 | 139 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
6bd9e877 | 140 | |
bd4c72d1 AG |
141 | |
142 | DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", | |
143 | amdgpuCrtc->crtc_id, amdgpuCrtc, work); | |
144 | ||
d38ceaf9 AD |
145 | } |
146 | ||
147 | /* | |
148 | * Handle unpin events outside the interrupt handler proper. | |
149 | */ | |
150 | static void amdgpu_unpin_work_func(struct work_struct *__work) | |
151 | { | |
152 | struct amdgpu_flip_work *work = | |
153 | container_of(__work, struct amdgpu_flip_work, unpin_work); | |
154 | int r; | |
155 | ||
156 | /* unpin of the old buffer */ | |
157 | r = amdgpu_bo_reserve(work->old_rbo, false); | |
158 | if (likely(r == 0)) { | |
159 | r = amdgpu_bo_unpin(work->old_rbo); | |
160 | if (unlikely(r != 0)) { | |
161 | DRM_ERROR("failed to unpin buffer after flip\n"); | |
162 | } | |
163 | amdgpu_bo_unreserve(work->old_rbo); | |
164 | } else | |
165 | DRM_ERROR("failed to reserve buffer after flip\n"); | |
166 | ||
e9d951a8 | 167 | amdgpu_bo_unref(&work->old_rbo); |
1ffd2652 | 168 | kfree(work->shared); |
d38ceaf9 AD |
169 | kfree(work); |
170 | } | |
171 | ||
172 | int amdgpu_crtc_page_flip(struct drm_crtc *crtc, | |
173 | struct drm_framebuffer *fb, | |
174 | struct drm_pending_vblank_event *event, | |
175 | uint32_t page_flip_flags) | |
176 | { | |
177 | struct drm_device *dev = crtc->dev; | |
178 | struct amdgpu_device *adev = dev->dev_private; | |
179 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
180 | struct amdgpu_framebuffer *old_amdgpu_fb; | |
181 | struct amdgpu_framebuffer *new_amdgpu_fb; | |
182 | struct drm_gem_object *obj; | |
183 | struct amdgpu_flip_work *work; | |
184 | struct amdgpu_bo *new_rbo; | |
185 | unsigned long flags; | |
186 | u64 tiling_flags; | |
187 | u64 base; | |
1ffd2652 | 188 | int i, r; |
d38ceaf9 AD |
189 | |
190 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
191 | if (work == NULL) | |
192 | return -ENOMEM; | |
193 | ||
194 | INIT_WORK(&work->flip_work, amdgpu_flip_work_func); | |
195 | INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func); | |
196 | ||
197 | work->event = event; | |
198 | work->adev = adev; | |
199 | work->crtc_id = amdgpu_crtc->crtc_id; | |
200 | ||
201 | /* schedule unpin of the old buffer */ | |
202 | old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); | |
203 | obj = old_amdgpu_fb->obj; | |
204 | ||
205 | /* take a reference to the old object */ | |
d38ceaf9 | 206 | work->old_rbo = gem_to_amdgpu_bo(obj); |
e9d951a8 | 207 | amdgpu_bo_ref(work->old_rbo); |
d38ceaf9 AD |
208 | |
209 | new_amdgpu_fb = to_amdgpu_framebuffer(fb); | |
210 | obj = new_amdgpu_fb->obj; | |
211 | new_rbo = gem_to_amdgpu_bo(obj); | |
212 | ||
213 | /* pin the new buffer */ | |
214 | r = amdgpu_bo_reserve(new_rbo, false); | |
215 | if (unlikely(r != 0)) { | |
216 | DRM_ERROR("failed to reserve new rbo buffer before flip\n"); | |
217 | goto cleanup; | |
218 | } | |
219 | ||
7e5a547f | 220 | r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); |
d38ceaf9 AD |
221 | if (unlikely(r != 0)) { |
222 | amdgpu_bo_unreserve(new_rbo); | |
223 | r = -EINVAL; | |
224 | DRM_ERROR("failed to pin new rbo buffer before flip\n"); | |
225 | goto cleanup; | |
226 | } | |
227 | ||
1ffd2652 CK |
228 | r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl, |
229 | &work->shared_count, | |
230 | &work->shared); | |
231 | if (unlikely(r != 0)) { | |
232 | amdgpu_bo_unreserve(new_rbo); | |
233 | DRM_ERROR("failed to get fences for buffer\n"); | |
234 | goto cleanup; | |
235 | } | |
236 | ||
d38ceaf9 AD |
237 | amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags); |
238 | amdgpu_bo_unreserve(new_rbo); | |
239 | ||
240 | work->base = base; | |
241 | ||
242 | r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id); | |
243 | if (r) { | |
244 | DRM_ERROR("failed to get vblank before flip\n"); | |
245 | goto pflip_cleanup; | |
246 | } | |
247 | ||
248 | /* we borrow the event spin lock for protecting flip_wrok */ | |
249 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
250 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { | |
251 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
252 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
253 | r = -EBUSY; | |
254 | goto vblank_cleanup; | |
255 | } | |
256 | ||
257 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; | |
258 | amdgpu_crtc->pflip_works = work; | |
259 | ||
bd4c72d1 AG |
260 | |
261 | DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", | |
262 | amdgpu_crtc->crtc_id, amdgpu_crtc, work); | |
d38ceaf9 AD |
263 | /* update crtc fb */ |
264 | crtc->primary->fb = fb; | |
265 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
c3874b75 | 266 | amdgpu_flip_work_func(&work->flip_work); |
d38ceaf9 AD |
267 | return 0; |
268 | ||
269 | vblank_cleanup: | |
270 | drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id); | |
271 | ||
272 | pflip_cleanup: | |
273 | if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) { | |
274 | DRM_ERROR("failed to reserve new rbo in error path\n"); | |
275 | goto cleanup; | |
276 | } | |
277 | if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) { | |
278 | DRM_ERROR("failed to unpin new rbo in error path\n"); | |
279 | } | |
280 | amdgpu_bo_unreserve(new_rbo); | |
281 | ||
282 | cleanup: | |
e9d951a8 | 283 | amdgpu_bo_unref(&work->old_rbo); |
1ffd2652 CK |
284 | fence_put(work->excl); |
285 | for (i = 0; i < work->shared_count; ++i) | |
286 | fence_put(work->shared[i]); | |
287 | kfree(work->shared); | |
d38ceaf9 AD |
288 | kfree(work); |
289 | ||
290 | return r; | |
291 | } | |
292 | ||
293 | int amdgpu_crtc_set_config(struct drm_mode_set *set) | |
294 | { | |
295 | struct drm_device *dev; | |
296 | struct amdgpu_device *adev; | |
297 | struct drm_crtc *crtc; | |
298 | bool active = false; | |
299 | int ret; | |
300 | ||
301 | if (!set || !set->crtc) | |
302 | return -EINVAL; | |
303 | ||
304 | dev = set->crtc->dev; | |
305 | ||
306 | ret = pm_runtime_get_sync(dev->dev); | |
307 | if (ret < 0) | |
308 | return ret; | |
309 | ||
310 | ret = drm_crtc_helper_set_config(set); | |
311 | ||
312 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
313 | if (crtc->enabled) | |
314 | active = true; | |
315 | ||
316 | pm_runtime_mark_last_busy(dev->dev); | |
317 | ||
318 | adev = dev->dev_private; | |
319 | /* if we have active crtcs and we don't have a power ref, | |
320 | take the current one */ | |
321 | if (active && !adev->have_disp_power_ref) { | |
322 | adev->have_disp_power_ref = true; | |
323 | return ret; | |
324 | } | |
325 | /* if we have no active crtcs, then drop the power ref | |
326 | we got before */ | |
327 | if (!active && adev->have_disp_power_ref) { | |
328 | pm_runtime_put_autosuspend(dev->dev); | |
329 | adev->have_disp_power_ref = false; | |
330 | } | |
331 | ||
332 | /* drop the power reference we got coming in here */ | |
333 | pm_runtime_put_autosuspend(dev->dev); | |
334 | return ret; | |
335 | } | |
336 | ||
337 | static const char *encoder_names[38] = { | |
338 | "NONE", | |
339 | "INTERNAL_LVDS", | |
340 | "INTERNAL_TMDS1", | |
341 | "INTERNAL_TMDS2", | |
342 | "INTERNAL_DAC1", | |
343 | "INTERNAL_DAC2", | |
344 | "INTERNAL_SDVOA", | |
345 | "INTERNAL_SDVOB", | |
346 | "SI170B", | |
347 | "CH7303", | |
348 | "CH7301", | |
349 | "INTERNAL_DVO1", | |
350 | "EXTERNAL_SDVOA", | |
351 | "EXTERNAL_SDVOB", | |
352 | "TITFP513", | |
353 | "INTERNAL_LVTM1", | |
354 | "VT1623", | |
355 | "HDMI_SI1930", | |
356 | "HDMI_INTERNAL", | |
357 | "INTERNAL_KLDSCP_TMDS1", | |
358 | "INTERNAL_KLDSCP_DVO1", | |
359 | "INTERNAL_KLDSCP_DAC1", | |
360 | "INTERNAL_KLDSCP_DAC2", | |
361 | "SI178", | |
362 | "MVPU_FPGA", | |
363 | "INTERNAL_DDI", | |
364 | "VT1625", | |
365 | "HDMI_SI1932", | |
366 | "DP_AN9801", | |
367 | "DP_DP501", | |
368 | "INTERNAL_UNIPHY", | |
369 | "INTERNAL_KLDSCP_LVTMA", | |
370 | "INTERNAL_UNIPHY1", | |
371 | "INTERNAL_UNIPHY2", | |
372 | "NUTMEG", | |
373 | "TRAVIS", | |
374 | "INTERNAL_VCE", | |
375 | "INTERNAL_UNIPHY3", | |
376 | }; | |
377 | ||
378 | static const char *hpd_names[6] = { | |
379 | "HPD1", | |
380 | "HPD2", | |
381 | "HPD3", | |
382 | "HPD4", | |
383 | "HPD5", | |
384 | "HPD6", | |
385 | }; | |
386 | ||
387 | void amdgpu_print_display_setup(struct drm_device *dev) | |
388 | { | |
389 | struct drm_connector *connector; | |
390 | struct amdgpu_connector *amdgpu_connector; | |
391 | struct drm_encoder *encoder; | |
392 | struct amdgpu_encoder *amdgpu_encoder; | |
393 | uint32_t devices; | |
394 | int i = 0; | |
395 | ||
396 | DRM_INFO("AMDGPU Display Connectors\n"); | |
397 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
398 | amdgpu_connector = to_amdgpu_connector(connector); | |
399 | DRM_INFO("Connector %d:\n", i); | |
400 | DRM_INFO(" %s\n", connector->name); | |
401 | if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) | |
402 | DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); | |
403 | if (amdgpu_connector->ddc_bus) { | |
404 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", | |
405 | amdgpu_connector->ddc_bus->rec.mask_clk_reg, | |
406 | amdgpu_connector->ddc_bus->rec.mask_data_reg, | |
407 | amdgpu_connector->ddc_bus->rec.a_clk_reg, | |
408 | amdgpu_connector->ddc_bus->rec.a_data_reg, | |
409 | amdgpu_connector->ddc_bus->rec.en_clk_reg, | |
410 | amdgpu_connector->ddc_bus->rec.en_data_reg, | |
411 | amdgpu_connector->ddc_bus->rec.y_clk_reg, | |
412 | amdgpu_connector->ddc_bus->rec.y_data_reg); | |
413 | if (amdgpu_connector->router.ddc_valid) | |
414 | DRM_INFO(" DDC Router 0x%x/0x%x\n", | |
415 | amdgpu_connector->router.ddc_mux_control_pin, | |
416 | amdgpu_connector->router.ddc_mux_state); | |
417 | if (amdgpu_connector->router.cd_valid) | |
418 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", | |
419 | amdgpu_connector->router.cd_mux_control_pin, | |
420 | amdgpu_connector->router.cd_mux_state); | |
421 | } else { | |
422 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || | |
423 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || | |
424 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || | |
425 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || | |
426 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || | |
427 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
428 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); | |
429 | } | |
430 | DRM_INFO(" Encoders:\n"); | |
431 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
432 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
433 | devices = amdgpu_encoder->devices & amdgpu_connector->devices; | |
434 | if (devices) { | |
435 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) | |
436 | DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
437 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) | |
438 | DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
439 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) | |
440 | DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
441 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) | |
442 | DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
443 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) | |
444 | DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
445 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) | |
446 | DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
447 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) | |
448 | DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
449 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) | |
450 | DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
451 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) | |
452 | DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
453 | if (devices & ATOM_DEVICE_TV1_SUPPORT) | |
454 | DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
455 | if (devices & ATOM_DEVICE_CV_SUPPORT) | |
456 | DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); | |
457 | } | |
458 | } | |
459 | i++; | |
460 | } | |
461 | } | |
462 | ||
463 | /** | |
464 | * amdgpu_ddc_probe | |
465 | * | |
466 | */ | |
467 | bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, | |
468 | bool use_aux) | |
469 | { | |
470 | u8 out = 0x0; | |
471 | u8 buf[8]; | |
472 | int ret; | |
473 | struct i2c_msg msgs[] = { | |
474 | { | |
475 | .addr = DDC_ADDR, | |
476 | .flags = 0, | |
477 | .len = 1, | |
478 | .buf = &out, | |
479 | }, | |
480 | { | |
481 | .addr = DDC_ADDR, | |
482 | .flags = I2C_M_RD, | |
483 | .len = 8, | |
484 | .buf = buf, | |
485 | } | |
486 | }; | |
487 | ||
488 | /* on hw with routers, select right port */ | |
489 | if (amdgpu_connector->router.ddc_valid) | |
490 | amdgpu_i2c_router_select_ddc_port(amdgpu_connector); | |
491 | ||
492 | if (use_aux) { | |
493 | ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); | |
494 | } else { | |
495 | ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); | |
496 | } | |
497 | ||
498 | if (ret != 2) | |
499 | /* Couldn't find an accessible DDC on this connector */ | |
500 | return false; | |
501 | /* Probe also for valid EDID header | |
502 | * EDID header starts with: | |
503 | * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. | |
504 | * Only the first 6 bytes must be valid as | |
505 | * drm_edid_block_valid() can fix the last 2 bytes */ | |
506 | if (drm_edid_header_is_valid(buf) < 6) { | |
507 | /* Couldn't find an accessible EDID on this | |
508 | * connector */ | |
509 | return false; | |
510 | } | |
511 | return true; | |
512 | } | |
513 | ||
514 | static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
515 | { | |
516 | struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); | |
517 | ||
518 | if (amdgpu_fb->obj) { | |
519 | drm_gem_object_unreference_unlocked(amdgpu_fb->obj); | |
520 | } | |
521 | drm_framebuffer_cleanup(fb); | |
522 | kfree(amdgpu_fb); | |
523 | } | |
524 | ||
525 | static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
526 | struct drm_file *file_priv, | |
527 | unsigned int *handle) | |
528 | { | |
529 | struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); | |
530 | ||
531 | return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); | |
532 | } | |
533 | ||
534 | static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { | |
535 | .destroy = amdgpu_user_framebuffer_destroy, | |
536 | .create_handle = amdgpu_user_framebuffer_create_handle, | |
537 | }; | |
538 | ||
539 | int | |
540 | amdgpu_framebuffer_init(struct drm_device *dev, | |
541 | struct amdgpu_framebuffer *rfb, | |
1eb83451 | 542 | const struct drm_mode_fb_cmd2 *mode_cmd, |
d38ceaf9 AD |
543 | struct drm_gem_object *obj) |
544 | { | |
545 | int ret; | |
546 | rfb->obj = obj; | |
547 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); | |
548 | ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); | |
549 | if (ret) { | |
550 | rfb->obj = NULL; | |
551 | return ret; | |
552 | } | |
553 | return 0; | |
554 | } | |
555 | ||
556 | static struct drm_framebuffer * | |
557 | amdgpu_user_framebuffer_create(struct drm_device *dev, | |
558 | struct drm_file *file_priv, | |
1eb83451 | 559 | const struct drm_mode_fb_cmd2 *mode_cmd) |
d38ceaf9 AD |
560 | { |
561 | struct drm_gem_object *obj; | |
562 | struct amdgpu_framebuffer *amdgpu_fb; | |
563 | int ret; | |
564 | ||
565 | obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); | |
566 | if (obj == NULL) { | |
567 | dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " | |
568 | "can't create framebuffer\n", mode_cmd->handles[0]); | |
569 | return ERR_PTR(-ENOENT); | |
570 | } | |
571 | ||
572 | amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); | |
573 | if (amdgpu_fb == NULL) { | |
574 | drm_gem_object_unreference_unlocked(obj); | |
575 | return ERR_PTR(-ENOMEM); | |
576 | } | |
577 | ||
578 | ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); | |
579 | if (ret) { | |
580 | kfree(amdgpu_fb); | |
581 | drm_gem_object_unreference_unlocked(obj); | |
582 | return ERR_PTR(ret); | |
583 | } | |
584 | ||
585 | return &amdgpu_fb->base; | |
586 | } | |
587 | ||
588 | static void amdgpu_output_poll_changed(struct drm_device *dev) | |
589 | { | |
590 | struct amdgpu_device *adev = dev->dev_private; | |
591 | amdgpu_fb_output_poll_changed(adev); | |
592 | } | |
593 | ||
594 | const struct drm_mode_config_funcs amdgpu_mode_funcs = { | |
595 | .fb_create = amdgpu_user_framebuffer_create, | |
596 | .output_poll_changed = amdgpu_output_poll_changed | |
597 | }; | |
598 | ||
f498d9ed | 599 | static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = |
d38ceaf9 AD |
600 | { { UNDERSCAN_OFF, "off" }, |
601 | { UNDERSCAN_ON, "on" }, | |
602 | { UNDERSCAN_AUTO, "auto" }, | |
603 | }; | |
604 | ||
f498d9ed | 605 | static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = |
d38ceaf9 AD |
606 | { { AMDGPU_AUDIO_DISABLE, "off" }, |
607 | { AMDGPU_AUDIO_ENABLE, "on" }, | |
608 | { AMDGPU_AUDIO_AUTO, "auto" }, | |
609 | }; | |
610 | ||
611 | /* XXX support different dither options? spatial, temporal, both, etc. */ | |
f498d9ed | 612 | static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = |
d38ceaf9 AD |
613 | { { AMDGPU_FMT_DITHER_DISABLE, "off" }, |
614 | { AMDGPU_FMT_DITHER_ENABLE, "on" }, | |
615 | }; | |
616 | ||
617 | int amdgpu_modeset_create_props(struct amdgpu_device *adev) | |
618 | { | |
619 | int sz; | |
620 | ||
621 | if (adev->is_atom_bios) { | |
622 | adev->mode_info.coherent_mode_property = | |
623 | drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); | |
624 | if (!adev->mode_info.coherent_mode_property) | |
625 | return -ENOMEM; | |
626 | } | |
627 | ||
628 | adev->mode_info.load_detect_property = | |
629 | drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); | |
630 | if (!adev->mode_info.load_detect_property) | |
631 | return -ENOMEM; | |
632 | ||
633 | drm_mode_create_scaling_mode_property(adev->ddev); | |
634 | ||
635 | sz = ARRAY_SIZE(amdgpu_underscan_enum_list); | |
636 | adev->mode_info.underscan_property = | |
637 | drm_property_create_enum(adev->ddev, 0, | |
638 | "underscan", | |
639 | amdgpu_underscan_enum_list, sz); | |
640 | ||
641 | adev->mode_info.underscan_hborder_property = | |
642 | drm_property_create_range(adev->ddev, 0, | |
643 | "underscan hborder", 0, 128); | |
644 | if (!adev->mode_info.underscan_hborder_property) | |
645 | return -ENOMEM; | |
646 | ||
647 | adev->mode_info.underscan_vborder_property = | |
648 | drm_property_create_range(adev->ddev, 0, | |
649 | "underscan vborder", 0, 128); | |
650 | if (!adev->mode_info.underscan_vborder_property) | |
651 | return -ENOMEM; | |
652 | ||
653 | sz = ARRAY_SIZE(amdgpu_audio_enum_list); | |
654 | adev->mode_info.audio_property = | |
655 | drm_property_create_enum(adev->ddev, 0, | |
656 | "audio", | |
657 | amdgpu_audio_enum_list, sz); | |
658 | ||
659 | sz = ARRAY_SIZE(amdgpu_dither_enum_list); | |
660 | adev->mode_info.dither_property = | |
661 | drm_property_create_enum(adev->ddev, 0, | |
662 | "dither", | |
663 | amdgpu_dither_enum_list, sz); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
668 | void amdgpu_update_display_priority(struct amdgpu_device *adev) | |
669 | { | |
670 | /* adjustment options for the display watermarks */ | |
671 | if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) | |
672 | adev->mode_info.disp_priority = 0; | |
673 | else | |
674 | adev->mode_info.disp_priority = amdgpu_disp_priority; | |
675 | ||
676 | } | |
677 | ||
678 | static bool is_hdtv_mode(const struct drm_display_mode *mode) | |
679 | { | |
680 | /* try and guess if this is a tv or a monitor */ | |
681 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ | |
682 | (mode->vdisplay == 576) || /* 576p */ | |
683 | (mode->vdisplay == 720) || /* 720p */ | |
684 | (mode->vdisplay == 1080)) /* 1080p */ | |
685 | return true; | |
686 | else | |
687 | return false; | |
688 | } | |
689 | ||
690 | bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, | |
691 | const struct drm_display_mode *mode, | |
692 | struct drm_display_mode *adjusted_mode) | |
693 | { | |
694 | struct drm_device *dev = crtc->dev; | |
695 | struct drm_encoder *encoder; | |
696 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
697 | struct amdgpu_encoder *amdgpu_encoder; | |
698 | struct drm_connector *connector; | |
699 | struct amdgpu_connector *amdgpu_connector; | |
700 | u32 src_v = 1, dst_v = 1; | |
701 | u32 src_h = 1, dst_h = 1; | |
702 | ||
703 | amdgpu_crtc->h_border = 0; | |
704 | amdgpu_crtc->v_border = 0; | |
705 | ||
706 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
707 | if (encoder->crtc != crtc) | |
708 | continue; | |
709 | amdgpu_encoder = to_amdgpu_encoder(encoder); | |
710 | connector = amdgpu_get_connector_for_encoder(encoder); | |
711 | amdgpu_connector = to_amdgpu_connector(connector); | |
712 | ||
713 | /* set scaling */ | |
714 | if (amdgpu_encoder->rmx_type == RMX_OFF) | |
715 | amdgpu_crtc->rmx_type = RMX_OFF; | |
716 | else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || | |
717 | mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) | |
718 | amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; | |
719 | else | |
720 | amdgpu_crtc->rmx_type = RMX_OFF; | |
721 | /* copy native mode */ | |
722 | memcpy(&amdgpu_crtc->native_mode, | |
723 | &amdgpu_encoder->native_mode, | |
724 | sizeof(struct drm_display_mode)); | |
725 | src_v = crtc->mode.vdisplay; | |
726 | dst_v = amdgpu_crtc->native_mode.vdisplay; | |
727 | src_h = crtc->mode.hdisplay; | |
728 | dst_h = amdgpu_crtc->native_mode.hdisplay; | |
729 | ||
730 | /* fix up for overscan on hdmi */ | |
731 | if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && | |
732 | ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || | |
733 | ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && | |
734 | drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && | |
735 | is_hdtv_mode(mode)))) { | |
736 | if (amdgpu_encoder->underscan_hborder != 0) | |
737 | amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; | |
738 | else | |
739 | amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; | |
740 | if (amdgpu_encoder->underscan_vborder != 0) | |
741 | amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; | |
742 | else | |
743 | amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; | |
744 | amdgpu_crtc->rmx_type = RMX_FULL; | |
745 | src_v = crtc->mode.vdisplay; | |
746 | dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); | |
747 | src_h = crtc->mode.hdisplay; | |
748 | dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); | |
749 | } | |
750 | } | |
751 | if (amdgpu_crtc->rmx_type != RMX_OFF) { | |
752 | fixed20_12 a, b; | |
753 | a.full = dfixed_const(src_v); | |
754 | b.full = dfixed_const(dst_v); | |
755 | amdgpu_crtc->vsc.full = dfixed_div(a, b); | |
756 | a.full = dfixed_const(src_h); | |
757 | b.full = dfixed_const(dst_h); | |
758 | amdgpu_crtc->hsc.full = dfixed_div(a, b); | |
759 | } else { | |
760 | amdgpu_crtc->vsc.full = dfixed_const(1); | |
761 | amdgpu_crtc->hsc.full = dfixed_const(1); | |
762 | } | |
763 | return true; | |
764 | } | |
765 | ||
766 | /* | |
767 | * Retrieve current video scanout position of crtc on a given gpu, and | |
768 | * an optional accurate timestamp of when query happened. | |
769 | * | |
770 | * \param dev Device to query. | |
88e72717 | 771 | * \param pipe Crtc to query. |
d38ceaf9 | 772 | * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). |
8e36f9d3 AD |
773 | * For driver internal use only also supports these flags: |
774 | * | |
775 | * USE_REAL_VBLANKSTART to use the real start of vblank instead | |
776 | * of a fudged earlier start of vblank. | |
777 | * | |
778 | * GET_DISTANCE_TO_VBLANKSTART to return distance to the | |
779 | * fudged earlier start of vblank in *vpos and the distance | |
780 | * to true start of vblank in *hpos. | |
781 | * | |
d38ceaf9 AD |
782 | * \param *vpos Location where vertical scanout position should be stored. |
783 | * \param *hpos Location where horizontal scanout position should go. | |
784 | * \param *stime Target location for timestamp taken immediately before | |
785 | * scanout position query. Can be NULL to skip timestamp. | |
786 | * \param *etime Target location for timestamp taken immediately after | |
787 | * scanout position query. Can be NULL to skip timestamp. | |
788 | * | |
789 | * Returns vpos as a positive number while in active scanout area. | |
790 | * Returns vpos as a negative number inside vblank, counting the number | |
791 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline | |
792 | * until start of active scanout / end of vblank." | |
793 | * | |
794 | * \return Flags, or'ed together as follows: | |
795 | * | |
796 | * DRM_SCANOUTPOS_VALID = Query successful. | |
797 | * DRM_SCANOUTPOS_INVBL = Inside vblank. | |
798 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of | |
799 | * this flag means that returned position may be offset by a constant but | |
800 | * unknown small number of scanlines wrt. real scanout position. | |
801 | * | |
802 | */ | |
88e72717 TR |
803 | int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
804 | unsigned int flags, int *vpos, int *hpos, | |
805 | ktime_t *stime, ktime_t *etime, | |
3bb403bf | 806 | const struct drm_display_mode *mode) |
d38ceaf9 AD |
807 | { |
808 | u32 vbl = 0, position = 0; | |
809 | int vbl_start, vbl_end, vtotal, ret = 0; | |
810 | bool in_vbl = true; | |
811 | ||
812 | struct amdgpu_device *adev = dev->dev_private; | |
813 | ||
814 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ | |
815 | ||
816 | /* Get optional system timestamp before query. */ | |
817 | if (stime) | |
818 | *stime = ktime_get(); | |
819 | ||
88e72717 | 820 | if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) |
d38ceaf9 AD |
821 | ret |= DRM_SCANOUTPOS_VALID; |
822 | ||
823 | /* Get optional system timestamp after query. */ | |
824 | if (etime) | |
825 | *etime = ktime_get(); | |
826 | ||
827 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
828 | ||
829 | /* Decode into vertical and horizontal scanout position. */ | |
830 | *vpos = position & 0x1fff; | |
831 | *hpos = (position >> 16) & 0x1fff; | |
832 | ||
833 | /* Valid vblank area boundaries from gpu retrieved? */ | |
834 | if (vbl > 0) { | |
835 | /* Yes: Decode. */ | |
836 | ret |= DRM_SCANOUTPOS_ACCURATE; | |
837 | vbl_start = vbl & 0x1fff; | |
838 | vbl_end = (vbl >> 16) & 0x1fff; | |
839 | } | |
840 | else { | |
841 | /* No: Fake something reasonable which gives at least ok results. */ | |
3bb403bf | 842 | vbl_start = mode->crtc_vdisplay; |
d38ceaf9 AD |
843 | vbl_end = 0; |
844 | } | |
845 | ||
8e36f9d3 AD |
846 | /* Called from driver internal vblank counter query code? */ |
847 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { | |
848 | /* Caller wants distance from real vbl_start in *hpos */ | |
849 | *hpos = *vpos - vbl_start; | |
850 | } | |
851 | ||
852 | /* Fudge vblank to start a few scanlines earlier to handle the | |
853 | * problem that vblank irqs fire a few scanlines before start | |
854 | * of vblank. Some driver internal callers need the true vblank | |
855 | * start to be used and signal this via the USE_REAL_VBLANKSTART flag. | |
856 | * | |
857 | * The cause of the "early" vblank irq is that the irq is triggered | |
858 | * by the line buffer logic when the line buffer read position enters | |
859 | * the vblank, whereas our crtc scanout position naturally lags the | |
860 | * line buffer read position. | |
861 | */ | |
862 | if (!(flags & USE_REAL_VBLANKSTART)) | |
863 | vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; | |
864 | ||
d38ceaf9 AD |
865 | /* Test scanout position against vblank region. */ |
866 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) | |
867 | in_vbl = false; | |
868 | ||
8e36f9d3 AD |
869 | /* In vblank? */ |
870 | if (in_vbl) | |
871 | ret |= DRM_SCANOUTPOS_IN_VBLANK; | |
872 | ||
873 | /* Called from driver internal vblank counter query code? */ | |
874 | if (flags & GET_DISTANCE_TO_VBLANKSTART) { | |
875 | /* Caller wants distance from fudged earlier vbl_start */ | |
876 | *vpos -= vbl_start; | |
877 | return ret; | |
878 | } | |
879 | ||
d38ceaf9 AD |
880 | /* Check if inside vblank area and apply corrective offsets: |
881 | * vpos will then be >=0 in video scanout area, but negative | |
882 | * within vblank area, counting down the number of lines until | |
883 | * start of scanout. | |
884 | */ | |
885 | ||
886 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ | |
887 | if (in_vbl && (*vpos >= vbl_start)) { | |
3bb403bf | 888 | vtotal = mode->crtc_vtotal; |
d38ceaf9 AD |
889 | *vpos = *vpos - vtotal; |
890 | } | |
891 | ||
892 | /* Correct for shifted end of vbl at vbl_end. */ | |
893 | *vpos = *vpos - vbl_end; | |
894 | ||
d38ceaf9 AD |
895 | return ret; |
896 | } | |
897 | ||
898 | int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) | |
899 | { | |
900 | if (crtc < 0 || crtc >= adev->mode_info.num_crtc) | |
901 | return AMDGPU_CRTC_IRQ_NONE; | |
902 | ||
903 | switch (crtc) { | |
904 | case 0: | |
905 | return AMDGPU_CRTC_IRQ_VBLANK1; | |
906 | case 1: | |
907 | return AMDGPU_CRTC_IRQ_VBLANK2; | |
908 | case 2: | |
909 | return AMDGPU_CRTC_IRQ_VBLANK3; | |
910 | case 3: | |
911 | return AMDGPU_CRTC_IRQ_VBLANK4; | |
912 | case 4: | |
913 | return AMDGPU_CRTC_IRQ_VBLANK5; | |
914 | case 5: | |
915 | return AMDGPU_CRTC_IRQ_VBLANK6; | |
916 | default: | |
917 | return AMDGPU_CRTC_IRQ_NONE; | |
918 | } | |
919 | } |