projects / mirror_ubuntu-jammy-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| cde577bd OZ |
1 | /* |
| 2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice shall be included in | |
| 12 | * all copies or substantial portions of the Software. | |
| 13 | * | |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | * | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * GPU doorbell structures, functions & helpers | |
| 26 | */ | |
| 27 | struct amdgpu_doorbell { | |
| 28 | /* doorbell mmio */ | |
| 29 | resource_size_t base; | |
| 30 | resource_size_t size; | |
| 31 | u32 __iomem *ptr; | |
| 32 | u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ | |
| 33 | }; | |
| 34 | ||
| 35 | /* Reserved doorbells for amdgpu (including multimedia). | |
| 36 | * KFD can use all the rest in the 2M doorbell bar. | |
| 37 | * For asic before vega10, doorbell is 32-bit, so the | |
| 38 | * index/offset is in dword. For vega10 and after, doorbell | |
| 39 | * can be 64-bit, so the index defined is in qword. | |
| 40 | */ | |
| 41 | struct amdgpu_doorbell_index { | |
| 42 | uint32_t kiq; | |
| 43 | uint32_t mec_ring0; | |
| 44 | uint32_t mec_ring1; | |
| 45 | uint32_t mec_ring2; | |
| 46 | uint32_t mec_ring3; | |
| 47 | uint32_t mec_ring4; | |
| 48 | uint32_t mec_ring5; | |
| 49 | uint32_t mec_ring6; | |
| 50 | uint32_t mec_ring7; | |
| e02c80d6 YZ |
51 | uint32_t userqueue_start; |
| 52 | uint32_t userqueue_end; | |
| cde577bd | 53 | uint32_t gfx_ring0; |
| 898e0d9d | 54 | uint32_t sdma_engine[8]; |
| cde577bd OZ |
55 | uint32_t ih; |
| 56 | union { | |
| 57 | struct { | |
| 58 | uint32_t vcn_ring0_1; | |
| 59 | uint32_t vcn_ring2_3; | |
| 60 | uint32_t vcn_ring4_5; | |
| 61 | uint32_t vcn_ring6_7; | |
| 62 | } vcn; | |
| 63 | struct { | |
| 64 | uint32_t uvd_ring0_1; | |
| 65 | uint32_t uvd_ring2_3; | |
| 66 | uint32_t uvd_ring4_5; | |
| 67 | uint32_t uvd_ring6_7; | |
| 68 | uint32_t vce_ring0_1; | |
| 69 | uint32_t vce_ring2_3; | |
| 70 | uint32_t vce_ring4_5; | |
| 71 | uint32_t vce_ring6_7; | |
| 72 | } uvd_vce; | |
| 73 | }; | |
| 828845b7 YZ |
74 | uint32_t first_non_cp; |
| 75 | uint32_t last_non_cp; | |
| cde577bd | 76 | uint32_t max_assignment; |
| fd485540 OZ |
77 | /* Per engine SDMA doorbell size in dword */ |
| 78 | uint32_t sdma_doorbell_range; | |
| cde577bd OZ |
79 | }; |
| 80 | ||
| 81 | typedef enum _AMDGPU_DOORBELL_ASSIGNMENT | |
| 82 | { | |
| 83 | AMDGPU_DOORBELL_KIQ = 0x000, | |
| 84 | AMDGPU_DOORBELL_HIQ = 0x001, | |
| 85 | AMDGPU_DOORBELL_DIQ = 0x002, | |
| 86 | AMDGPU_DOORBELL_MEC_RING0 = 0x010, | |
| 87 | AMDGPU_DOORBELL_MEC_RING1 = 0x011, | |
| 88 | AMDGPU_DOORBELL_MEC_RING2 = 0x012, | |
| 89 | AMDGPU_DOORBELL_MEC_RING3 = 0x013, | |
| 90 | AMDGPU_DOORBELL_MEC_RING4 = 0x014, | |
| 91 | AMDGPU_DOORBELL_MEC_RING5 = 0x015, | |
| 92 | AMDGPU_DOORBELL_MEC_RING6 = 0x016, | |
| 93 | AMDGPU_DOORBELL_MEC_RING7 = 0x017, | |
| 94 | AMDGPU_DOORBELL_GFX_RING0 = 0x020, | |
| 95 | AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, | |
| 96 | AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, | |
| 97 | AMDGPU_DOORBELL_IH = 0x1E8, | |
| 98 | AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, | |
| 99 | AMDGPU_DOORBELL_INVALID = 0xFFFF | |
| 100 | } AMDGPU_DOORBELL_ASSIGNMENT; | |
| 101 | ||
| 102 | typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT | |
| 103 | { | |
| 104 | /* Compute + GFX: 0~255 */ | |
| 105 | AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, | |
| 106 | AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, | |
| 107 | AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, | |
| 108 | AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, | |
| 109 | AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, | |
| 110 | AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, | |
| 111 | AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, | |
| 112 | AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, | |
| 113 | AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, | |
| 114 | AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, | |
| 115 | AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, | |
| e02c80d6 YZ |
116 | AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, |
| 117 | AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, | |
| cde577bd OZ |
118 | AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, |
| 119 | /* SDMA:256~335*/ | |
| 120 | AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, | |
| 121 | AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, | |
| 122 | AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, | |
| 123 | AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, | |
| 124 | AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, | |
| 125 | AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, | |
| 126 | AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, | |
| 127 | AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, | |
| 128 | /* IH: 376~391 */ | |
| 129 | AMDGPU_VEGA20_DOORBELL_IH = 0x178, | |
| 130 | /* MMSCH: 392~407 | |
| 131 | * overlap the doorbell assignment with VCN as they are mutually exclusive | |
| 132 | * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD | |
| 133 | */ | |
| 134 | AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ | |
| 135 | AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, | |
| 136 | AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, | |
| 137 | AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, | |
| 138 | ||
| 139 | AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, | |
| 140 | AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, | |
| 141 | AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, | |
| 142 | AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, | |
| 143 | ||
| 144 | AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, | |
| 145 | AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, | |
| 146 | AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, | |
| 147 | AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, | |
| 828845b7 YZ |
148 | |
| 149 | AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, | |
| 150 | AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, | |
| 151 | ||
| cde577bd OZ |
152 | AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F, |
| 153 | AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF | |
| 154 | } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT; | |
| 155 | ||
| 156 | /* | |
| 157 | * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space | |
| 158 | */ | |
| 159 | typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT | |
| 160 | { | |
| 161 | /* | |
| 162 | * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in | |
| 163 | * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. | |
| 164 | * Compute related doorbells are allocated from 0x00 to 0x8a | |
| 165 | */ | |
| 166 | ||
| 167 | ||
| 168 | /* kernel scheduling */ | |
| 169 | AMDGPU_DOORBELL64_KIQ = 0x00, | |
| 170 | ||
| 171 | /* HSA interface queue and debug queue */ | |
| 172 | AMDGPU_DOORBELL64_HIQ = 0x01, | |
| 173 | AMDGPU_DOORBELL64_DIQ = 0x02, | |
| 174 | ||
| 175 | /* Compute engines */ | |
| 176 | AMDGPU_DOORBELL64_MEC_RING0 = 0x03, | |
| 177 | AMDGPU_DOORBELL64_MEC_RING1 = 0x04, | |
| 178 | AMDGPU_DOORBELL64_MEC_RING2 = 0x05, | |
| 179 | AMDGPU_DOORBELL64_MEC_RING3 = 0x06, | |
| 180 | AMDGPU_DOORBELL64_MEC_RING4 = 0x07, | |
| 181 | AMDGPU_DOORBELL64_MEC_RING5 = 0x08, | |
| 182 | AMDGPU_DOORBELL64_MEC_RING6 = 0x09, | |
| 183 | AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, | |
| 184 | ||
| e02c80d6 YZ |
185 | /* User queue doorbell range (128 doorbells) */ |
| 186 | AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, | |
| 187 | AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, | |
| 188 | ||
| cde577bd OZ |
189 | /* Graphics engine */ |
| 190 | AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, | |
| 191 | ||
| 192 | /* | |
| 193 | * Other graphics doorbells can be allocated here: from 0x8c to 0xdf | |
| 194 | * Graphics voltage island aperture 1 | |
| 195 | * default non-graphics QWORD index is 0xe0 - 0xFF inclusive | |
| 196 | */ | |
| 197 | ||
| 198 | /* For vega10 sriov, the sdma doorbell must be fixed as follow | |
| 199 | * to keep the same setting with host driver, or it will | |
| 200 | * happen conflicts | |
| 201 | */ | |
| 202 | AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, | |
| 203 | AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, | |
| 204 | AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, | |
| 205 | AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, | |
| 206 | ||
| 207 | /* Interrupt handler */ | |
| 208 | AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ | |
| 209 | AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ | |
| 210 | AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ | |
| 211 | ||
| 212 | /* VCN engine use 32 bits doorbell */ | |
| 213 | AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ | |
| 214 | AMDGPU_DOORBELL64_VCN2_3 = 0xF9, | |
| 215 | AMDGPU_DOORBELL64_VCN4_5 = 0xFA, | |
| 216 | AMDGPU_DOORBELL64_VCN6_7 = 0xFB, | |
| 217 | ||
| 218 | /* overlap the doorbell assignment with VCN as they are mutually exclusive | |
| 219 | * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD | |
| 220 | */ | |
| 221 | AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, | |
| 222 | AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, | |
| 223 | AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, | |
| 224 | AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, | |
| 225 | ||
| 226 | AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, | |
| 227 | AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, | |
| 228 | AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, | |
| 229 | AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, | |
| 230 | ||
| 828845b7 YZ |
231 | AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, |
| 232 | AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, | |
| 233 | ||
| cde577bd OZ |
234 | AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, |
| 235 | AMDGPU_DOORBELL64_INVALID = 0xFFFF | |
| 236 | } AMDGPU_DOORBELL64_ASSIGNMENT; | |
| 237 | ||
| 238 | u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); | |
| 239 | void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); | |
| 240 | u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); | |
| 241 | void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); | |
| 242 | ||
| 243 | #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) | |
| 244 | #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) | |
| 245 | #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) | |
| 246 | #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) | |
| 247 |