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drm/amdgpu: Bail earlier when amdgpu.cik_/si_support is not set to 1
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
248a1d6f 42#include <drm/drm_crtc_helper.h>
d38ceaf9
AD		 43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
130e0371
OG		 47#include "amdgpu_amdkfd.h"
48
d38ceaf9
AD		 49/*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
6055f37a 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
54 * at the end of IBs.
d347ce66 55 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 57 * - 3.5.0 - Add support for new UVD_NO_OP register.
753ad49c 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
9cee3c1f 59 * - 3.7.0 - Add support for VCE clock list packet
b62b5931 60 * - 3.8.0 - Add support raster config init in the kernel
ef704318 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
a5b11dac 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
5ebbac4b 63 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
dfe38bd8 64 * - 3.12.0 - Add query for double offchip LDS buffers
8eafd505 65 * - 3.13.0 - Add PRT support
203eb0cb 66 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
44eb8c1b 67 * - 3.15.0 - Export more gpu info for gfx9
b98b8dbc 68 * - 3.16.0 - Add reserved vmid support
68e2c5ff 69 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
dbfe85ea 70 * - 3.18.0 - Export gpu always on cu bitmap
33476319 71 * - 3.19.0 - Add support for UVD MJPEG decode
fd8bf087 72 * - 3.20.0 - Add support for local BOs
7ca24cf2 73 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
b285f1db 74 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
c057c114 75 * - 3.23.0 - Add query for VRAM lost counter
d38ceaf9
AD		 76 */
77#define KMS_DRIVER_MAJOR 3
c057c114 78#define KMS_DRIVER_MINOR 23
d38ceaf9
AD		 79#define KMS_DRIVER_PATCHLEVEL 0
80
81int amdgpu_vram_limit = 0;
218b5dcd 82int amdgpu_vis_vram_limit = 0;
83e74db6 83int amdgpu_gart_size = -1; /* auto */
36d38372 84int amdgpu_gtt_size = -1; /* auto */
95844d20 85int amdgpu_moverate = -1; /* auto */
d38ceaf9
AD		 86int amdgpu_benchmarking = 0;
87int amdgpu_testing = 0;
88int amdgpu_audio = -1;
89int amdgpu_disp_priority = 0;
90int amdgpu_hw_i2c = 0;
91int amdgpu_pcie_gen2 = -1;
92int amdgpu_msi = -1;
a895c222 93int amdgpu_lockup_timeout = 0;
d38ceaf9 94int amdgpu_dpm = -1;
e635ee07 95int amdgpu_fw_load_type = -1;
d38ceaf9
AD		 96int amdgpu_aspm = -1;
97int amdgpu_runtime_pm = -1;
0b693f0b 98uint amdgpu_ip_block_mask = 0xffffffff;
d38ceaf9
AD		 99int amdgpu_bapm = -1;
100int amdgpu_deep_color = 0;
bab4fee7 101int amdgpu_vm_size = -1;
d07f14be 102int amdgpu_vm_fragment_size = -1;
d38ceaf9 103int amdgpu_vm_block_size = -1;
d9c13156 104int amdgpu_vm_fault_stop = 0;
b495bd3a 105int amdgpu_vm_debug = 0;
60bfcd31 106int amdgpu_vram_page_split = 512;
9a4b7d4c 107int amdgpu_vm_update_mode = -1;
d38ceaf9 108int amdgpu_exp_hw_support = 0;
4562236b 109int amdgpu_dc = -1;
02e749dc 110int amdgpu_dc_log = 0;
b70f014d 111int amdgpu_sched_jobs = 32;
4afcb303 112int amdgpu_sched_hw_submission = 2;
3ca67300
RZ		 113int amdgpu_no_evict = 0;
114int amdgpu_direct_gma_size = 0;
0b693f0b
RZ		 115uint amdgpu_pcie_gen_cap = 0;
116uint amdgpu_pcie_lane_cap = 0;
117uint amdgpu_cg_mask = 0xffffffff;
118uint amdgpu_pg_mask = 0xffffffff;
119uint amdgpu_sdma_phase_quantum = 32;
6f8941a2 120char *amdgpu_disable_cu = NULL;
9accf2fd 121char *amdgpu_virtual_display = NULL;
0b693f0b 122uint amdgpu_pp_feature_mask = 0xffffffff;
bce23e00
AD		 123int amdgpu_ngg = 0;
124int amdgpu_prim_buf_per_se = 0;
125int amdgpu_pos_buf_per_se = 0;
126int amdgpu_cntl_sb_buf_per_se = 0;
127int amdgpu_param_buf_per_se = 0;
65781c78 128int amdgpu_job_hang_limit = 0;
e8835e0e 129int amdgpu_lbpw = -1;
4a75aefe 130int amdgpu_compute_multipipe = -1;
d38ceaf9
AD		 131
132MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
133module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
134
218b5dcd
JB		 135MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
136module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
137
a4da14cc 138MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
f9321cc4 139module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
d38ceaf9 140
36d38372
CK		 141MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
142module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
d38ceaf9 143
95844d20
MO		 144MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
145module_param_named(moverate, amdgpu_moverate, int, 0600);
146
d38ceaf9
AD		 147MODULE_PARM_DESC(benchmark, "Run benchmark");
148module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
149
150MODULE_PARM_DESC(test, "Run tests");
151module_param_named(test, amdgpu_testing, int, 0444);
152
153MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
154module_param_named(audio, amdgpu_audio, int, 0444);
155
156MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
157module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
158
159MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
160module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
161
162MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
163module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
164
165MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
166module_param_named(msi, amdgpu_msi, int, 0444);
167
a895c222 168MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
d38ceaf9
AD		 169module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
170
171MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
172module_param_named(dpm, amdgpu_dpm, int, 0444);
173
e635ee07
HR		 174MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
175module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
d38ceaf9
AD		 176
177MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
178module_param_named(aspm, amdgpu_aspm, int, 0444);
179
180MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
181module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
182
d38ceaf9
AD		 183MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
184module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
185
186MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
187module_param_named(bapm, amdgpu_bapm, int, 0444);
188
189MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
190module_param_named(deep_color, amdgpu_deep_color, int, 0444);
191
ed885b21 192MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9 193module_param_named(vm_size, amdgpu_vm_size, int, 0444);
d07f14be
RH		 194
195MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
196module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
d38ceaf9
AD		 197
198MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
199module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
200
d9c13156
CK		 201MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
202module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
203
b495bd3a
CK		 204MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
205module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
206
9a4b7d4c
HK		 207MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
208module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
209
ccfee95c 210MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)");
6a7f76e7
CK		 211module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
212
d38ceaf9
AD		 213MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
214module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
215
4562236b
HW		 216MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
217module_param_named(dc, amdgpu_dc, int, 0444);
218
02e749dc
HW		 219MODULE_PARM_DESC(dc, "Display Core Log Level (0 = minimal (default), 1 = chatty");
220module_param_named(dc_log, amdgpu_dc_log, int, 0444);
221
b70f014d 222MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 223module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
224
4afcb303
JZ		 225MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
226module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
227
5141e9d2 228MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
88826351 229module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
3a74f6f2 230
3ca67300
RZ		 231MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");
232module_param_named(no_evict, amdgpu_no_evict, int, 0444);
233
234MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
235module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
af223dfa 236
cd474ba0
AD		 237MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
238module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
239
240MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
241module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
242
395d1fb9
NH		 243MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
244module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
245
246MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
247module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
248
a667386c
FK		 249MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
250module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
251
6f8941a2
NH		 252MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
253module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
254
0f66356d
ED		 255MODULE_PARM_DESC(virtual_display,
256 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
9accf2fd 257module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 258
bce23e00
AD		 259MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
260module_param_named(ngg, amdgpu_ngg, int, 0444);
261
262MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
263module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
264
265MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
266module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
267
268MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
269module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
270
271MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
272module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
273
65781c78
ML		 274MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
275module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
276
e8835e0e
HZ		 277MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
278module_param_named(lbpw, amdgpu_lbpw, int, 0444);
bce23e00 279
4a75aefe
AR		 280MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
281module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
282
6dd13096 283#ifdef CONFIG_DRM_AMDGPU_SI
53efaf56
MD		 284
285#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
6dd13096
FK		 286int amdgpu_si_support = 0;
287MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 288#else
289int amdgpu_si_support = 1;
290MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
291#endif
292
6dd13096
FK		 293module_param_named(si_support, amdgpu_si_support, int, 0444);
294#endif
295
7df28986 296#ifdef CONFIG_DRM_AMDGPU_CIK
53efaf56
MD		 297
298#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
2b059658
MD		 299int amdgpu_cik_support = 0;
300MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 301#else
302int amdgpu_cik_support = 1;
303MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
304#endif
305
7df28986
FK		 306module_param_named(cik_support, amdgpu_cik_support, int, 0444);
307#endif
308
bce23e00 309
f498d9ed 310static const struct pci_device_id pciidlist[] = {
78fbb685
KW		 311#ifdef CONFIG_DRM_AMDGPU_SI
312 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
313 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
314 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
315 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
316 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
317 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
318 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
319 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
320 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
321 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
322 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
323 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
324 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
325 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
326 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
327 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
328 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
329 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
330 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
331 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
332 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
333 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
334 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
335 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
336 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
337 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
338 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
339 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
340 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
341 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
342 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
343 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
344 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
345 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
346 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
347 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
348 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
349 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
350 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
351 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
352 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
353 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
354 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
355 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
356 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
357 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
358 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
359 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
360 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
361 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
362 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
363 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
364 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
365 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
366 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
367 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
368 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
369 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
370 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
371 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
372 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
373 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
374 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
375 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
376 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
377 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
378 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
379 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
380 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
381 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
382 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
383 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
384#endif
89330c39
AD		 385#ifdef CONFIG_DRM_AMDGPU_CIK
386 /* Kaveri */
2f7d10b3
JZ		 387 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
388 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
389 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
390 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
391 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
392 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
393 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
394 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
395 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
396 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
397 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
398 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
399 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
400 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
401 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
402 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
403 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
404 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
405 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
406 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
407 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
408 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 409 /* Bonaire */
2f7d10b3
JZ		 410 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
411 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
412 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
413 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 414 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
415 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
416 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
417 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
418 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
419 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 420 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 421 /* Hawaii */
422 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
423 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
424 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
425 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
426 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
427 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
428 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
429 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
430 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
431 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
432 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
433 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
434 /* Kabini */
2f7d10b3
JZ		 435 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
436 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
437 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
438 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
439 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
440 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
441 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
442 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
443 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
444 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
445 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
446 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
447 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
448 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
449 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
450 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 451 /* mullins */
2f7d10b3
JZ		 452 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
453 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
454 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
455 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
456 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
457 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
458 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
459 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
460 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
461 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
462 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
463 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
464 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
465 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
466 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
467 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 468#endif
1256a8b8 469 /* topaz */
dba280b2
AD		 470 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
471 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
472 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
473 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
474 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 475 /* tonga */
476 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
477 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
478 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 479 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 480 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
481 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 482 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 483 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
484 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 485 /* fiji */
486 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
e1d99217 487 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 488 /* carrizo */
2f7d10b3
JZ		 489 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
490 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
491 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
492 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
493 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 494 /* stoney */
495 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 496 /* Polaris11 */
497 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 498 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 499 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 500 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 501 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 502 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 503 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
504 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
505 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 506 /* Polaris10 */
507 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 508 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
509 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
510 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
511 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
7dae6181 512 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 513 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 514 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
515 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
516 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
517 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
518 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
0ff6731d 519 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
fc8e9c54
JZ		 520 /* Polaris12 */
521 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
522 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
523 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
524 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
525 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
cf8c73af 526 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
6e88491c 527 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
fc8e9c54 528 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
ca2f1cca 529 /* Vega 10 */
dfbf0c14
AD		 530 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
531 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
532 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
533 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
534 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
535 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
536 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
537 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
538 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
df515052 539 /* Raven */
acc34503 540 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
df515052 541
d38ceaf9
AD		 542 {0, 0, 0}
543};
544
545MODULE_DEVICE_TABLE(pci, pciidlist);
546
547static struct drm_driver kms_driver;
548
549static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
550{
551 struct apertures_struct *ap;
552 bool primary = false;
553
554 ap = alloc_apertures(1);
555 if (!ap)
556 return -ENOMEM;
557
558 ap->ranges[0].base = pci_resource_start(pdev, 0);
559 ap->ranges[0].size = pci_resource_len(pdev, 0);
560
561#ifdef CONFIG_X86
562 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
563#endif
44adece5 564 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
d38ceaf9
AD		 565 kfree(ap);
566
567 return 0;
568}
569
570static int amdgpu_pci_probe(struct pci_dev *pdev,
571 const struct pci_device_id *ent)
572{
b58c1131 573 struct drm_device *dev;
d38ceaf9
AD		 574 unsigned long flags = ent->driver_data;
575 int ret;
576
2f7d10b3 577 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 578 DRM_INFO("This hardware requires experimental hardware support.\n"
579 "See modparam exp_hw_support\n");
580 return -ENODEV;
581 }
582
efb1c658
OG		 583 /*
584 * Initialize amdkfd before starting radeon. If it was not loaded yet,
585 * defer radeon probing
586 */
587 ret = amdgpu_amdkfd_init();
588 if (ret == -EPROBE_DEFER)
589 return ret;
590
3bded3c0
HG		 591#ifdef CONFIG_DRM_AMDGPU_SI
592 if (!amdgpu_si_support) {
593 switch (flags & AMD_ASIC_MASK) {
594 case CHIP_TAHITI:
595 case CHIP_PITCAIRN:
596 case CHIP_VERDE:
597 case CHIP_OLAND:
598 case CHIP_HAINAN:
599 dev_info(&pdev->dev,
600 "SI support provided by radeon.\n");
601 dev_info(&pdev->dev,
602 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
603 );
604 return -ENODEV;
605 }
606 }
607#endif
608#ifdef CONFIG_DRM_AMDGPU_CIK
609 if (!amdgpu_cik_support) {
610 switch (flags & AMD_ASIC_MASK) {
611 case CHIP_KAVERI:
612 case CHIP_BONAIRE:
613 case CHIP_HAWAII:
614 case CHIP_KABINI:
615 case CHIP_MULLINS:
616 dev_info(&pdev->dev,
617 "CIK support provided by radeon.\n");
618 dev_info(&pdev->dev,
619 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
620 );
621 return -ENODEV;
622 }
623 }
624#endif
625
d38ceaf9
AD		 626 /* Get rid of things like offb */
627 ret = amdgpu_kick_out_firmware_fb(pdev);
628 if (ret)
629 return ret;
630
b58c1131
AD		 631 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
632 if (IS_ERR(dev))
633 return PTR_ERR(dev);
634
635 ret = pci_enable_device(pdev);
636 if (ret)
637 goto err_free;
638
639 dev->pdev = pdev;
640
641 pci_set_drvdata(pdev, dev);
642
643 ret = drm_dev_register(dev, ent->driver_data);
644 if (ret)
645 goto err_pci;
646
647 return 0;
648
649err_pci:
650 pci_disable_device(pdev);
651err_free:
652 drm_dev_unref(dev);
653 return ret;
d38ceaf9
AD		 654}
655
656static void
657amdgpu_pci_remove(struct pci_dev *pdev)
658{
659 struct drm_device *dev = pci_get_drvdata(pdev);
660
b58c1131
AD		 661 drm_dev_unregister(dev);
662 drm_dev_unref(dev);
fd4495e5
XY		 663 pci_disable_device(pdev);
664 pci_set_drvdata(pdev, NULL);
d38ceaf9
AD		 665}
666
61e11306
AD		 667static void
668amdgpu_pci_shutdown(struct pci_dev *pdev)
669{
faefba95
AD		 670 struct drm_device *dev = pci_get_drvdata(pdev);
671 struct amdgpu_device *adev = dev->dev_private;
672
61e11306 673 /* if we are running in a VM, make sure the device
00ea8cba
AD		 674 * torn down properly on reboot/shutdown.
675 * unfortunately we can't detect certain
676 * hypervisors so just do this all the time.
61e11306 677 */
faefba95 678 amdgpu_suspend(adev);
61e11306
AD		 679}
680
d38ceaf9
AD		 681static int amdgpu_pmops_suspend(struct device *dev)
682{
683 struct pci_dev *pdev = to_pci_dev(dev);
74b0b157 684
d38ceaf9 685 struct drm_device *drm_dev = pci_get_drvdata(pdev);
810ddc3a 686 return amdgpu_device_suspend(drm_dev, true, true);
d38ceaf9
AD		 687}
688
689static int amdgpu_pmops_resume(struct device *dev)
690{
691 struct pci_dev *pdev = to_pci_dev(dev);
692 struct drm_device *drm_dev = pci_get_drvdata(pdev);
85e154c2
AD		 693
694 /* GPU comes up enabled by the bios on resume */
695 if (amdgpu_device_is_px(drm_dev)) {
696 pm_runtime_disable(dev);
697 pm_runtime_set_active(dev);
698 pm_runtime_enable(dev);
699 }
700
810ddc3a 701 return amdgpu_device_resume(drm_dev, true, true);
d38ceaf9
AD		 702}
703
704static int amdgpu_pmops_freeze(struct device *dev)
705{
706 struct pci_dev *pdev = to_pci_dev(dev);
74b0b157 707
d38ceaf9 708 struct drm_device *drm_dev = pci_get_drvdata(pdev);
810ddc3a 709 return amdgpu_device_suspend(drm_dev, false, true);
d38ceaf9
AD		 710}
711
712static int amdgpu_pmops_thaw(struct device *dev)
713{
714 struct pci_dev *pdev = to_pci_dev(dev);
74b0b157 715
716 struct drm_device *drm_dev = pci_get_drvdata(pdev);
717 return amdgpu_device_resume(drm_dev, false, true);
718}
719
720static int amdgpu_pmops_poweroff(struct device *dev)
721{
722 struct pci_dev *pdev = to_pci_dev(dev);
723
724 struct drm_device *drm_dev = pci_get_drvdata(pdev);
725 return amdgpu_device_suspend(drm_dev, true, true);
726}
727
728static int amdgpu_pmops_restore(struct device *dev)
729{
730 struct pci_dev *pdev = to_pci_dev(dev);
731
d38ceaf9 732 struct drm_device *drm_dev = pci_get_drvdata(pdev);
810ddc3a 733 return amdgpu_device_resume(drm_dev, false, true);
d38ceaf9
AD		 734}
735
736static int amdgpu_pmops_runtime_suspend(struct device *dev)
737{
738 struct pci_dev *pdev = to_pci_dev(dev);
739 struct drm_device *drm_dev = pci_get_drvdata(pdev);
740 int ret;
741
742 if (!amdgpu_device_is_px(drm_dev)) {
743 pm_runtime_forbid(dev);
744 return -EBUSY;
745 }
746
747 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
748 drm_kms_helper_poll_disable(drm_dev);
749 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
750
810ddc3a 751 ret = amdgpu_device_suspend(drm_dev, false, false);
d38ceaf9
AD		 752 pci_save_state(pdev);
753 pci_disable_device(pdev);
754 pci_ignore_hotplug(pdev);
11670975
AD		 755 if (amdgpu_is_atpx_hybrid())
756 pci_set_power_state(pdev, PCI_D3cold);
522761cb 757 else if (!amdgpu_has_atpx_dgpu_power_cntl())
7e32aa61 758 pci_set_power_state(pdev, PCI_D3hot);
d38ceaf9
AD		 759 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
760
761 return 0;
762}
763
764static int amdgpu_pmops_runtime_resume(struct device *dev)
765{
766 struct pci_dev *pdev = to_pci_dev(dev);
767 struct drm_device *drm_dev = pci_get_drvdata(pdev);
768 int ret;
769
770 if (!amdgpu_device_is_px(drm_dev))
771 return -EINVAL;
772
773 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
774
522761cb
AD		 775 if (amdgpu_is_atpx_hybrid() ||
776 !amdgpu_has_atpx_dgpu_power_cntl())
777 pci_set_power_state(pdev, PCI_D0);
d38ceaf9
AD		 778 pci_restore_state(pdev);
779 ret = pci_enable_device(pdev);
780 if (ret)
781 return ret;
782 pci_set_master(pdev);
783
810ddc3a 784 ret = amdgpu_device_resume(drm_dev, false, false);
d38ceaf9
AD		 785 drm_kms_helper_poll_enable(drm_dev);
786 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
787 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
788 return 0;
789}
790
791static int amdgpu_pmops_runtime_idle(struct device *dev)
792{
793 struct pci_dev *pdev = to_pci_dev(dev);
794 struct drm_device *drm_dev = pci_get_drvdata(pdev);
795 struct drm_crtc *crtc;
796
797 if (!amdgpu_device_is_px(drm_dev)) {
798 pm_runtime_forbid(dev);
799 return -EBUSY;
800 }
801
802 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
803 if (crtc->enabled) {
804 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
805 return -EBUSY;
806 }
807 }
808
809 pm_runtime_mark_last_busy(dev);
810 pm_runtime_autosuspend(dev);
811 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
812 return 1;
813}
814
815long amdgpu_drm_ioctl(struct file *filp,
816 unsigned int cmd, unsigned long arg)
817{
818 struct drm_file *file_priv = filp->private_data;
819 struct drm_device *dev;
820 long ret;
821 dev = file_priv->minor->dev;
822 ret = pm_runtime_get_sync(dev->dev);
823 if (ret < 0)
824 return ret;
825
826 ret = drm_ioctl(filp, cmd, arg);
827
828 pm_runtime_mark_last_busy(dev->dev);
829 pm_runtime_put_autosuspend(dev->dev);
830 return ret;
831}
832
833static const struct dev_pm_ops amdgpu_pm_ops = {
834 .suspend = amdgpu_pmops_suspend,
835 .resume = amdgpu_pmops_resume,
836 .freeze = amdgpu_pmops_freeze,
837 .thaw = amdgpu_pmops_thaw,
74b0b157 838 .poweroff = amdgpu_pmops_poweroff,
839 .restore = amdgpu_pmops_restore,
d38ceaf9
AD		 840 .runtime_suspend = amdgpu_pmops_runtime_suspend,
841 .runtime_resume = amdgpu_pmops_runtime_resume,
842 .runtime_idle = amdgpu_pmops_runtime_idle,
843};
844
845static const struct file_operations amdgpu_driver_kms_fops = {
846 .owner = THIS_MODULE,
847 .open = drm_open,
848 .release = drm_release,
849 .unlocked_ioctl = amdgpu_drm_ioctl,
850 .mmap = amdgpu_mmap,
851 .poll = drm_poll,
852 .read = drm_read,
853#ifdef CONFIG_COMPAT
854 .compat_ioctl = amdgpu_kms_compat_ioctl,
855#endif
856};
857
1bf6ad62
DV		 858static bool
859amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
860 bool in_vblank_irq, int *vpos, int *hpos,
861 ktime_t *stime, ktime_t *etime,
862 const struct drm_display_mode *mode)
863{
864 return amdgpu_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
865 stime, etime, mode);
866}
867
d38ceaf9
AD		 868static struct drm_driver kms_driver = {
869 .driver_features =
870 DRIVER_USE_AGP |
871 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
660e8558 872 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
d38ceaf9
AD		 873 .load = amdgpu_driver_load_kms,
874 .open = amdgpu_driver_open_kms,
d38ceaf9
AD		 875 .postclose = amdgpu_driver_postclose_kms,
876 .lastclose = amdgpu_driver_lastclose_kms,
d38ceaf9
AD		 877 .unload = amdgpu_driver_unload_kms,
878 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
879 .enable_vblank = amdgpu_enable_vblank_kms,
880 .disable_vblank = amdgpu_disable_vblank_kms,
1bf6ad62
DV		 881 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
882 .get_scanout_position = amdgpu_get_crtc_scanout_position,
d38ceaf9
AD		 883#if defined(CONFIG_DEBUG_FS)
884 .debugfs_init = amdgpu_debugfs_init,
d38ceaf9
AD		 885#endif
886 .irq_preinstall = amdgpu_irq_preinstall,
887 .irq_postinstall = amdgpu_irq_postinstall,
888 .irq_uninstall = amdgpu_irq_uninstall,
889 .irq_handler = amdgpu_irq_handler,
890 .ioctls = amdgpu_ioctls_kms,
e7294dee 891 .gem_free_object_unlocked = amdgpu_gem_object_free,
d38ceaf9
AD		 892 .gem_open_object = amdgpu_gem_object_open,
893 .gem_close_object = amdgpu_gem_object_close,
894 .dumb_create = amdgpu_mode_dumb_create,
895 .dumb_map_offset = amdgpu_mode_dumb_mmap,
d38ceaf9
AD		 896 .fops = &amdgpu_driver_kms_fops,
897
898 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
899 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
900 .gem_prime_export = amdgpu_gem_prime_export,
901 .gem_prime_import = drm_gem_prime_import,
902 .gem_prime_pin = amdgpu_gem_prime_pin,
903 .gem_prime_unpin = amdgpu_gem_prime_unpin,
904 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
905 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
906 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
907 .gem_prime_vmap = amdgpu_gem_prime_vmap,
908 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
dfced2e4 909 .gem_prime_mmap = amdgpu_gem_prime_mmap,
d38ceaf9
AD		 910
911 .name = DRIVER_NAME,
912 .desc = DRIVER_DESC,
913 .date = DRIVER_DATE,
914 .major = KMS_DRIVER_MAJOR,
915 .minor = KMS_DRIVER_MINOR,
916 .patchlevel = KMS_DRIVER_PATCHLEVEL,
917};
918
919static struct drm_driver *driver;
920static struct pci_driver *pdriver;
921
922static struct pci_driver amdgpu_kms_pci_driver = {
923 .name = DRIVER_NAME,
924 .id_table = pciidlist,
925 .probe = amdgpu_pci_probe,
926 .remove = amdgpu_pci_remove,
61e11306 927 .shutdown = amdgpu_pci_shutdown,
d38ceaf9
AD		 928 .driver.pm = &amdgpu_pm_ops,
929};
930
d573de2d
RZ		 931
932
d38ceaf9
AD		 933static int __init amdgpu_init(void)
934{
245ae5e9
CK		 935 int r;
936
937 r = amdgpu_sync_init();
938 if (r)
939 goto error_sync;
940
941 r = amdgpu_fence_slab_init();
942 if (r)
943 goto error_fence;
944
945 r = amd_sched_fence_slab_init();
946 if (r)
947 goto error_sched;
948
d38ceaf9
AD		 949 if (vgacon_text_force()) {
950 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
951 return -EINVAL;
952 }
d38ceaf9
AD		 953 DRM_INFO("amdgpu kernel modesetting enabled.\n");
954 driver = &kms_driver;
955 pdriver = &amdgpu_kms_pci_driver;
d38ceaf9
AD		 956 driver->num_ioctls = amdgpu_max_kms_ioctl;
957 amdgpu_register_atpx_handler();
d38ceaf9 958 /* let modprobe override vga console setting */
10631d72 959 return pci_register_driver(pdriver);
245ae5e9
CK		 960
961error_sched:
962 amdgpu_fence_slab_fini();
963
964error_fence:
965 amdgpu_sync_fini();
966
967error_sync:
968 return r;
d38ceaf9
AD		 969}
970
971static void __exit amdgpu_exit(void)
972{
130e0371 973 amdgpu_amdkfd_fini();
10631d72 974 pci_unregister_driver(pdriver);
d38ceaf9 975 amdgpu_unregister_atpx_handler();
257bf15a 976 amdgpu_sync_fini();
c24784f0 977 amd_sched_fence_slab_fini();
d573de2d 978 amdgpu_fence_slab_fini();
d38ceaf9
AD		 979}
980
981module_init(amdgpu_init);
982module_exit(amdgpu_exit);
983
984MODULE_AUTHOR(DRIVER_AUTHOR);
985MODULE_DESCRIPTION(DRIVER_DESC);
986MODULE_LICENSE("GPL and additional rights");
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