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Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi into...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
42#include "drm_crtc_helper.h"
43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
130e0371
OG		 47#include "amdgpu_amdkfd.h"
48
d38ceaf9
AD		 49/*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
6055f37a 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
54 * at the end of IBs.
d347ce66 55 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 57 * - 3.5.0 - Add support for new UVD_NO_OP register.
753ad49c 58 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
9cee3c1f 59 * - 3.7.0 - Add support for VCE clock list packet
b62b5931 60 * - 3.8.0 - Add support raster config init in the kernel
ef704318 61 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
a5b11dac 62 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
d38ceaf9
AD		 63 */
64#define KMS_DRIVER_MAJOR 3
a5b11dac 65#define KMS_DRIVER_MINOR 10
d38ceaf9
AD		 66#define KMS_DRIVER_PATCHLEVEL 0
67
68int amdgpu_vram_limit = 0;
69int amdgpu_gart_size = -1; /* auto */
95844d20 70int amdgpu_moverate = -1; /* auto */
d38ceaf9
AD		 71int amdgpu_benchmarking = 0;
72int amdgpu_testing = 0;
73int amdgpu_audio = -1;
74int amdgpu_disp_priority = 0;
75int amdgpu_hw_i2c = 0;
76int amdgpu_pcie_gen2 = -1;
77int amdgpu_msi = -1;
a895c222 78int amdgpu_lockup_timeout = 0;
d38ceaf9
AD		 79int amdgpu_dpm = -1;
80int amdgpu_smc_load_fw = 1;
81int amdgpu_aspm = -1;
82int amdgpu_runtime_pm = -1;
d38ceaf9
AD		 83unsigned amdgpu_ip_block_mask = 0xffffffff;
84int amdgpu_bapm = -1;
85int amdgpu_deep_color = 0;
ed885b21 86int amdgpu_vm_size = 64;
d38ceaf9 87int amdgpu_vm_block_size = -1;
d9c13156 88int amdgpu_vm_fault_stop = 0;
b495bd3a 89int amdgpu_vm_debug = 0;
6a7f76e7 90int amdgpu_vram_page_split = 1024;
d38ceaf9 91int amdgpu_exp_hw_support = 0;
b70f014d 92int amdgpu_sched_jobs = 32;
4afcb303 93int amdgpu_sched_hw_submission = 2;
3ca67300
RZ		 94int amdgpu_no_evict = 0;
95int amdgpu_direct_gma_size = 0;
cd474ba0
AD		 96unsigned amdgpu_pcie_gen_cap = 0;
97unsigned amdgpu_pcie_lane_cap = 0;
395d1fb9
NH		 98unsigned amdgpu_cg_mask = 0xffffffff;
99unsigned amdgpu_pg_mask = 0xffffffff;
6f8941a2 100char *amdgpu_disable_cu = NULL;
9accf2fd 101char *amdgpu_virtual_display = NULL;
5141e9d2 102unsigned amdgpu_pp_feature_mask = 0xffffffff;
d38ceaf9
AD		 103
104MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
105module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
106
107MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
108module_param_named(gartsize, amdgpu_gart_size, int, 0600);
109
95844d20
MO		 110MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
111module_param_named(moverate, amdgpu_moverate, int, 0600);
112
d38ceaf9
AD		 113MODULE_PARM_DESC(benchmark, "Run benchmark");
114module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
115
116MODULE_PARM_DESC(test, "Run tests");
117module_param_named(test, amdgpu_testing, int, 0444);
118
119MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
120module_param_named(audio, amdgpu_audio, int, 0444);
121
122MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
123module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
124
125MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
126module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
127
128MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
129module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
130
131MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
132module_param_named(msi, amdgpu_msi, int, 0444);
133
a895c222 134MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
d38ceaf9
AD		 135module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
136
137MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
138module_param_named(dpm, amdgpu_dpm, int, 0444);
139
140MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
141module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
142
143MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
144module_param_named(aspm, amdgpu_aspm, int, 0444);
145
146MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
147module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
148
d38ceaf9
AD		 149MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
150module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
151
152MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
153module_param_named(bapm, amdgpu_bapm, int, 0444);
154
155MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
156module_param_named(deep_color, amdgpu_deep_color, int, 0444);
157
ed885b21 158MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9
AD		 159module_param_named(vm_size, amdgpu_vm_size, int, 0444);
160
161MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
162module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
163
d9c13156
CK		 164MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
165module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
166
b495bd3a
CK		 167MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
168module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
169
6a7f76e7
CK		 170MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 1024, -1 = disable)");
171module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
172
d38ceaf9
AD		 173MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
174module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
175
b70f014d 176MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 177module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
178
4afcb303
JZ		 179MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
180module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
181
5141e9d2
RZ		 182MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
183module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444);
3a74f6f2 184
3ca67300
RZ		 185MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");
186module_param_named(no_evict, amdgpu_no_evict, int, 0444);
187
188MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
189module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
af223dfa 190
cd474ba0
AD		 191MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
192module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
193
194MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
195module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
196
395d1fb9
NH		 197MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
198module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
199
200MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
201module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
202
6f8941a2
NH		 203MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
204module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
205
0f66356d
ED		 206MODULE_PARM_DESC(virtual_display,
207 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
9accf2fd 208module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 209
f498d9ed 210static const struct pci_device_id pciidlist[] = {
78fbb685
KW		 211#ifdef CONFIG_DRM_AMDGPU_SI
212 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
213 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
214 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
215 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
216 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
217 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
218 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
219 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
220 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
221 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
222 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
223 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
224 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
225 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
226 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
227 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
228 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
229 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
230 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
231 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
232 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
233 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
234 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
235 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
236 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
237 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
238 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
239 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
240 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
241 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
242 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
243 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
244 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
245 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
246 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
247 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
248 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
249 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
250 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
251 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
252 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
253 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
254 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
255 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
256 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
257 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
258 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
259 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
260 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
261 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
262 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
263 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
264 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
265 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
266 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
267 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
268 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
269 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
270 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
271 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
272 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
273 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
274 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
275 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
276 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
277 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
278 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
279 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
280 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
281 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
282 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
283 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
284#endif
89330c39
AD		 285#ifdef CONFIG_DRM_AMDGPU_CIK
286 /* Kaveri */
2f7d10b3
JZ		 287 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
288 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
289 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
290 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
291 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
292 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
293 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
294 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
295 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
296 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
297 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
298 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
299 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
300 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
301 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
302 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
303 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
304 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
305 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
306 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
307 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
308 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 309 /* Bonaire */
2f7d10b3
JZ		 310 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
311 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
312 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
313 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 314 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
315 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
316 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
317 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
318 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
319 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 320 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 321 /* Hawaii */
322 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
323 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
324 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
325 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
326 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
327 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
328 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
329 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
330 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
331 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
332 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
333 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
334 /* Kabini */
2f7d10b3
JZ		 335 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
336 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
337 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
338 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
339 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
340 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
341 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
342 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
343 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
344 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
345 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
346 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
347 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
348 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
349 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
350 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 351 /* mullins */
2f7d10b3
JZ		 352 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
353 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
354 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
355 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
356 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
357 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
358 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
359 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
360 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
361 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
362 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
363 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
364 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
365 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
366 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
367 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 368#endif
1256a8b8 369 /* topaz */
dba280b2
AD		 370 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
371 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
372 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
373 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
374 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 375 /* tonga */
376 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
377 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
378 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 379 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 380 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
381 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 382 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 383 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
384 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 385 /* fiji */
386 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
e1d99217 387 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 388 /* carrizo */
2f7d10b3
JZ		 389 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
390 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
391 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
392 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
393 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 394 /* stoney */
395 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 396 /* Polaris11 */
397 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 398 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 399 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 400 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 401 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 402 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 403 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
404 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
405 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 406 /* Polaris10 */
407 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 408 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
409 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
410 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
411 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 412 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 413 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
414 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
415 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
416 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
417 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
fc8e9c54
JZ		 418 /* Polaris12 */
419 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
420 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
421 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
422 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
423 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
424 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
d38ceaf9
AD		 425
426 {0, 0, 0}
427};
428
429MODULE_DEVICE_TABLE(pci, pciidlist);
430
431static struct drm_driver kms_driver;
432
433static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
434{
435 struct apertures_struct *ap;
436 bool primary = false;
437
438 ap = alloc_apertures(1);
439 if (!ap)
440 return -ENOMEM;
441
442 ap->ranges[0].base = pci_resource_start(pdev, 0);
443 ap->ranges[0].size = pci_resource_len(pdev, 0);
444
445#ifdef CONFIG_X86
446 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
447#endif
44adece5 448 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
d38ceaf9
AD		 449 kfree(ap);
450
451 return 0;
452}
453
454static int amdgpu_pci_probe(struct pci_dev *pdev,
455 const struct pci_device_id *ent)
456{
457 unsigned long flags = ent->driver_data;
458 int ret;
459
2f7d10b3 460 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 461 DRM_INFO("This hardware requires experimental hardware support.\n"
462 "See modparam exp_hw_support\n");
463 return -ENODEV;
464 }
465
efb1c658
OG		 466 /*
467 * Initialize amdkfd before starting radeon. If it was not loaded yet,
468 * defer radeon probing
469 */
470 ret = amdgpu_amdkfd_init();
471 if (ret == -EPROBE_DEFER)
472 return ret;
473
d38ceaf9
AD		 474 /* Get rid of things like offb */
475 ret = amdgpu_kick_out_firmware_fb(pdev);
476 if (ret)
477 return ret;
478
479 return drm_get_pci_dev(pdev, ent, &kms_driver);
480}
481
482static void
483amdgpu_pci_remove(struct pci_dev *pdev)
484{
485 struct drm_device *dev = pci_get_drvdata(pdev);
486
487 drm_put_dev(dev);
488}
489
61e11306
AD		 490static void
491amdgpu_pci_shutdown(struct pci_dev *pdev)
492{
faefba95
AD		 493 struct drm_device *dev = pci_get_drvdata(pdev);
494 struct amdgpu_device *adev = dev->dev_private;
495
61e11306 496 /* if we are running in a VM, make sure the device
00ea8cba
AD		 497 * torn down properly on reboot/shutdown.
498 * unfortunately we can't detect certain
499 * hypervisors so just do this all the time.
61e11306 500 */
faefba95 501 amdgpu_suspend(adev);
61e11306
AD		 502}
503
d38ceaf9
AD		 504static int amdgpu_pmops_suspend(struct device *dev)
505{
506 struct pci_dev *pdev = to_pci_dev(dev);
74b0b157 507
d38ceaf9 508 struct drm_device *drm_dev = pci_get_drvdata(pdev);
810ddc3a 509 return amdgpu_device_suspend(drm_dev, true, true);
d38ceaf9
AD		 510}
511
512static int amdgpu_pmops_resume(struct device *dev)
513{
514 struct pci_dev *pdev = to_pci_dev(dev);
515 struct drm_device *drm_dev = pci_get_drvdata(pdev);
85e154c2
AD		 516
517 /* GPU comes up enabled by the bios on resume */
518 if (amdgpu_device_is_px(drm_dev)) {
519 pm_runtime_disable(dev);
520 pm_runtime_set_active(dev);
521 pm_runtime_enable(dev);
522 }
523
810ddc3a 524 return amdgpu_device_resume(drm_dev, true, true);
d38ceaf9
AD		 525}
526
527static int amdgpu_pmops_freeze(struct device *dev)
528{
529 struct pci_dev *pdev = to_pci_dev(dev);
74b0b157 530
d38ceaf9 531 struct drm_device *drm_dev = pci_get_drvdata(pdev);
810ddc3a 532 return amdgpu_device_suspend(drm_dev, false, true);
d38ceaf9
AD		 533}
534
535static int amdgpu_pmops_thaw(struct device *dev)
536{
537 struct pci_dev *pdev = to_pci_dev(dev);
74b0b157 538
539 struct drm_device *drm_dev = pci_get_drvdata(pdev);
540 return amdgpu_device_resume(drm_dev, false, true);
541}
542
543static int amdgpu_pmops_poweroff(struct device *dev)
544{
545 struct pci_dev *pdev = to_pci_dev(dev);
546
547 struct drm_device *drm_dev = pci_get_drvdata(pdev);
548 return amdgpu_device_suspend(drm_dev, true, true);
549}
550
551static int amdgpu_pmops_restore(struct device *dev)
552{
553 struct pci_dev *pdev = to_pci_dev(dev);
554
d38ceaf9 555 struct drm_device *drm_dev = pci_get_drvdata(pdev);
810ddc3a 556 return amdgpu_device_resume(drm_dev, false, true);
d38ceaf9
AD		 557}
558
559static int amdgpu_pmops_runtime_suspend(struct device *dev)
560{
561 struct pci_dev *pdev = to_pci_dev(dev);
562 struct drm_device *drm_dev = pci_get_drvdata(pdev);
563 int ret;
564
565 if (!amdgpu_device_is_px(drm_dev)) {
566 pm_runtime_forbid(dev);
567 return -EBUSY;
568 }
569
570 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
571 drm_kms_helper_poll_disable(drm_dev);
572 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
573
810ddc3a 574 ret = amdgpu_device_suspend(drm_dev, false, false);
d38ceaf9
AD		 575 pci_save_state(pdev);
576 pci_disable_device(pdev);
577 pci_ignore_hotplug(pdev);
11670975
AD		 578 if (amdgpu_is_atpx_hybrid())
579 pci_set_power_state(pdev, PCI_D3cold);
522761cb 580 else if (!amdgpu_has_atpx_dgpu_power_cntl())
7e32aa61 581 pci_set_power_state(pdev, PCI_D3hot);
d38ceaf9
AD		 582 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
583
584 return 0;
585}
586
587static int amdgpu_pmops_runtime_resume(struct device *dev)
588{
589 struct pci_dev *pdev = to_pci_dev(dev);
590 struct drm_device *drm_dev = pci_get_drvdata(pdev);
591 int ret;
592
593 if (!amdgpu_device_is_px(drm_dev))
594 return -EINVAL;
595
596 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
597
522761cb
AD		 598 if (amdgpu_is_atpx_hybrid() ||
599 !amdgpu_has_atpx_dgpu_power_cntl())
600 pci_set_power_state(pdev, PCI_D0);
d38ceaf9
AD		 601 pci_restore_state(pdev);
602 ret = pci_enable_device(pdev);
603 if (ret)
604 return ret;
605 pci_set_master(pdev);
606
810ddc3a 607 ret = amdgpu_device_resume(drm_dev, false, false);
d38ceaf9
AD		 608 drm_kms_helper_poll_enable(drm_dev);
609 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
610 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
611 return 0;
612}
613
614static int amdgpu_pmops_runtime_idle(struct device *dev)
615{
616 struct pci_dev *pdev = to_pci_dev(dev);
617 struct drm_device *drm_dev = pci_get_drvdata(pdev);
618 struct drm_crtc *crtc;
619
620 if (!amdgpu_device_is_px(drm_dev)) {
621 pm_runtime_forbid(dev);
622 return -EBUSY;
623 }
624
625 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
626 if (crtc->enabled) {
627 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
628 return -EBUSY;
629 }
630 }
631
632 pm_runtime_mark_last_busy(dev);
633 pm_runtime_autosuspend(dev);
634 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
635 return 1;
636}
637
638long amdgpu_drm_ioctl(struct file *filp,
639 unsigned int cmd, unsigned long arg)
640{
641 struct drm_file *file_priv = filp->private_data;
642 struct drm_device *dev;
643 long ret;
644 dev = file_priv->minor->dev;
645 ret = pm_runtime_get_sync(dev->dev);
646 if (ret < 0)
647 return ret;
648
649 ret = drm_ioctl(filp, cmd, arg);
650
651 pm_runtime_mark_last_busy(dev->dev);
652 pm_runtime_put_autosuspend(dev->dev);
653 return ret;
654}
655
656static const struct dev_pm_ops amdgpu_pm_ops = {
657 .suspend = amdgpu_pmops_suspend,
658 .resume = amdgpu_pmops_resume,
659 .freeze = amdgpu_pmops_freeze,
660 .thaw = amdgpu_pmops_thaw,
74b0b157 661 .poweroff = amdgpu_pmops_poweroff,
662 .restore = amdgpu_pmops_restore,
d38ceaf9
AD		 663 .runtime_suspend = amdgpu_pmops_runtime_suspend,
664 .runtime_resume = amdgpu_pmops_runtime_resume,
665 .runtime_idle = amdgpu_pmops_runtime_idle,
666};
667
668static const struct file_operations amdgpu_driver_kms_fops = {
669 .owner = THIS_MODULE,
670 .open = drm_open,
671 .release = drm_release,
672 .unlocked_ioctl = amdgpu_drm_ioctl,
673 .mmap = amdgpu_mmap,
674 .poll = drm_poll,
675 .read = drm_read,
676#ifdef CONFIG_COMPAT
677 .compat_ioctl = amdgpu_kms_compat_ioctl,
678#endif
679};
680
681static struct drm_driver kms_driver = {
682 .driver_features =
683 DRIVER_USE_AGP |
684 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
7056bb5c 685 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET,
d38ceaf9
AD		 686 .load = amdgpu_driver_load_kms,
687 .open = amdgpu_driver_open_kms,
688 .preclose = amdgpu_driver_preclose_kms,
689 .postclose = amdgpu_driver_postclose_kms,
690 .lastclose = amdgpu_driver_lastclose_kms,
691 .set_busid = drm_pci_set_busid,
692 .unload = amdgpu_driver_unload_kms,
693 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
694 .enable_vblank = amdgpu_enable_vblank_kms,
695 .disable_vblank = amdgpu_disable_vblank_kms,
696 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
697 .get_scanout_position = amdgpu_get_crtc_scanoutpos,
698#if defined(CONFIG_DEBUG_FS)
699 .debugfs_init = amdgpu_debugfs_init,
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AD		 700#endif
701 .irq_preinstall = amdgpu_irq_preinstall,
702 .irq_postinstall = amdgpu_irq_postinstall,
703 .irq_uninstall = amdgpu_irq_uninstall,
704 .irq_handler = amdgpu_irq_handler,
705 .ioctls = amdgpu_ioctls_kms,
e7294dee 706 .gem_free_object_unlocked = amdgpu_gem_object_free,
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AD		 707 .gem_open_object = amdgpu_gem_object_open,
708 .gem_close_object = amdgpu_gem_object_close,
709 .dumb_create = amdgpu_mode_dumb_create,
710 .dumb_map_offset = amdgpu_mode_dumb_mmap,
711 .dumb_destroy = drm_gem_dumb_destroy,
712 .fops = &amdgpu_driver_kms_fops,
713
714 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
715 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
716 .gem_prime_export = amdgpu_gem_prime_export,
717 .gem_prime_import = drm_gem_prime_import,
718 .gem_prime_pin = amdgpu_gem_prime_pin,
719 .gem_prime_unpin = amdgpu_gem_prime_unpin,
720 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
721 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
722 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
723 .gem_prime_vmap = amdgpu_gem_prime_vmap,
724 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
725
726 .name = DRIVER_NAME,
727 .desc = DRIVER_DESC,
728 .date = DRIVER_DATE,
729 .major = KMS_DRIVER_MAJOR,
730 .minor = KMS_DRIVER_MINOR,
731 .patchlevel = KMS_DRIVER_PATCHLEVEL,
732};
733
734static struct drm_driver *driver;
735static struct pci_driver *pdriver;
736
737static struct pci_driver amdgpu_kms_pci_driver = {
738 .name = DRIVER_NAME,
739 .id_table = pciidlist,
740 .probe = amdgpu_pci_probe,
741 .remove = amdgpu_pci_remove,
61e11306 742 .shutdown = amdgpu_pci_shutdown,
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AD		 743 .driver.pm = &amdgpu_pm_ops,
744};
745
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RZ		 746
747
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AD		 748static int __init amdgpu_init(void)
749{
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CK		 750 int r;
751
752 r = amdgpu_sync_init();
753 if (r)
754 goto error_sync;
755
756 r = amdgpu_fence_slab_init();
757 if (r)
758 goto error_fence;
759
760 r = amd_sched_fence_slab_init();
761 if (r)
762 goto error_sched;
763
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AD		 764 if (vgacon_text_force()) {
765 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
766 return -EINVAL;
767 }
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AD		 768 DRM_INFO("amdgpu kernel modesetting enabled.\n");
769 driver = &kms_driver;
770 pdriver = &amdgpu_kms_pci_driver;
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AD		 771 driver->num_ioctls = amdgpu_max_kms_ioctl;
772 amdgpu_register_atpx_handler();
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AD		 773 /* let modprobe override vga console setting */
774 return drm_pci_init(driver, pdriver);
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CK		 775
776error_sched:
777 amdgpu_fence_slab_fini();
778
779error_fence:
780 amdgpu_sync_fini();
781
782error_sync:
783 return r;
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AD		 784}
785
786static void __exit amdgpu_exit(void)
787{
130e0371 788 amdgpu_amdkfd_fini();
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AD		 789 drm_pci_exit(driver, pdriver);
790 amdgpu_unregister_atpx_handler();
257bf15a 791 amdgpu_sync_fini();
c24784f0 792 amd_sched_fence_slab_fini();
d573de2d 793 amdgpu_fence_slab_fini();
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AD		 794}
795
796module_init(amdgpu_init);
797module_exit(amdgpu_exit);
798
799MODULE_AUTHOR(DRIVER_AUTHOR);
800MODULE_DESCRIPTION(DRIVER_DESC);
801MODULE_LICENSE("GPL and additional rights");
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