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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
d38ceaf9 | 25 | #include <drm/amdgpu_drm.h> |
fdf2f6c5 | 26 | #include <drm/drm_drv.h> |
d38ceaf9 | 27 | #include <drm/drm_gem.h> |
fdf2f6c5 | 28 | #include <drm/drm_vblank.h> |
8aba21b7 | 29 | #include <drm/drm_managed.h> |
d38ceaf9 AD |
30 | #include "amdgpu_drv.h" |
31 | ||
32 | #include <drm/drm_pciids.h> | |
33 | #include <linux/console.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pm_runtime.h> | |
36 | #include <linux/vga_switcheroo.h> | |
fcd70cd3 | 37 | #include <drm/drm_probe_helper.h> |
c7d8b782 | 38 | #include <linux/mmu_notifier.h> |
d38ceaf9 AD |
39 | |
40 | #include "amdgpu.h" | |
41 | #include "amdgpu_irq.h" | |
2fbd6f94 | 42 | #include "amdgpu_dma_buf.h" |
5088d657 | 43 | #include "amdgpu_sched.h" |
d38ceaf9 | 44 | |
130e0371 OG |
45 | #include "amdgpu_amdkfd.h" |
46 | ||
7c6e68c7 AG |
47 | #include "amdgpu_ras.h" |
48 | ||
d38ceaf9 AD |
49 | /* |
50 | * KMS wrapper. | |
51 | * - 3.0.0 - initial driver | |
6055f37a | 52 | * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) |
f84e63f2 MO |
53 | * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same |
54 | * at the end of IBs. | |
d347ce66 | 55 | * - 3.3.0 - Add VM support for UVD on supported hardware. |
83a59b63 | 56 | * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. |
8dd31d74 | 57 | * - 3.5.0 - Add support for new UVD_NO_OP register. |
753ad49c | 58 | * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. |
9cee3c1f | 59 | * - 3.7.0 - Add support for VCE clock list packet |
b62b5931 | 60 | * - 3.8.0 - Add support raster config init in the kernel |
ef704318 | 61 | * - 3.9.0 - Add support for memory query info about VRAM and GTT. |
a5b11dac | 62 | * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags |
5ebbac4b | 63 | * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). |
dfe38bd8 | 64 | * - 3.12.0 - Add query for double offchip LDS buffers |
8eafd505 | 65 | * - 3.13.0 - Add PRT support |
203eb0cb | 66 | * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality |
44eb8c1b | 67 | * - 3.15.0 - Export more gpu info for gfx9 |
b98b8dbc | 68 | * - 3.16.0 - Add reserved vmid support |
68e2c5ff | 69 | * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. |
dbfe85ea | 70 | * - 3.18.0 - Export gpu always on cu bitmap |
33476319 | 71 | * - 3.19.0 - Add support for UVD MJPEG decode |
fd8bf087 | 72 | * - 3.20.0 - Add support for local BOs |
7ca24cf2 | 73 | * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl |
b285f1db | 74 | * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl |
c057c114 | 75 | * - 3.23.0 - Add query for VRAM lost counter |
f8e3e0ee | 76 | * - 3.24.0 - Add high priority compute support for gfx9 |
7b158d16 | 77 | * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). |
d240cd9e | 78 | * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. |
964d0fbf | 79 | * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. |
67dd1a36 | 80 | * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES |
41cca166 | 81 | * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID |
767e06a9 | 82 | * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. |
df8368be | 83 | * - 3.31.0 - Add support for per-flip tiling attribute changes with DC |
1afeb314 | 84 | * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. |
635e2c5f | 85 | * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. |
965ebe3d | 86 | * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches |
815fb4c9 | 87 | * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask |
664fe85a | 88 | * - 3.36.0 - Allow reading more status registers on si/cik |
ff532461 | 89 | * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness |
43c8546b | 90 | * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC |
174b328b | 91 | * - 3.39.0 - DMABUF implicit sync does a full pipeline sync |
16c642ec | 92 | * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ |
d38ceaf9 AD |
93 | */ |
94 | #define KMS_DRIVER_MAJOR 3 | |
16c642ec | 95 | #define KMS_DRIVER_MINOR 40 |
d38ceaf9 AD |
96 | #define KMS_DRIVER_PATCHLEVEL 0 |
97 | ||
87fb7833 DV |
98 | int amdgpu_vram_limit; |
99 | int amdgpu_vis_vram_limit; | |
83e74db6 | 100 | int amdgpu_gart_size = -1; /* auto */ |
36d38372 | 101 | int amdgpu_gtt_size = -1; /* auto */ |
95844d20 | 102 | int amdgpu_moverate = -1; /* auto */ |
87fb7833 DV |
103 | int amdgpu_benchmarking; |
104 | int amdgpu_testing; | |
d38ceaf9 | 105 | int amdgpu_audio = -1; |
87fb7833 DV |
106 | int amdgpu_disp_priority; |
107 | int amdgpu_hw_i2c; | |
d38ceaf9 AD |
108 | int amdgpu_pcie_gen2 = -1; |
109 | int amdgpu_msi = -1; | |
f440ff44 | 110 | char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; |
d38ceaf9 | 111 | int amdgpu_dpm = -1; |
e635ee07 | 112 | int amdgpu_fw_load_type = -1; |
d38ceaf9 AD |
113 | int amdgpu_aspm = -1; |
114 | int amdgpu_runtime_pm = -1; | |
0b693f0b | 115 | uint amdgpu_ip_block_mask = 0xffffffff; |
d38ceaf9 | 116 | int amdgpu_bapm = -1; |
87fb7833 | 117 | int amdgpu_deep_color; |
bab4fee7 | 118 | int amdgpu_vm_size = -1; |
d07f14be | 119 | int amdgpu_vm_fragment_size = -1; |
d38ceaf9 | 120 | int amdgpu_vm_block_size = -1; |
87fb7833 DV |
121 | int amdgpu_vm_fault_stop; |
122 | int amdgpu_vm_debug; | |
9a4b7d4c | 123 | int amdgpu_vm_update_mode = -1; |
87fb7833 | 124 | int amdgpu_exp_hw_support; |
4562236b | 125 | int amdgpu_dc = -1; |
b70f014d | 126 | int amdgpu_sched_jobs = 32; |
4afcb303 | 127 | int amdgpu_sched_hw_submission = 2; |
87fb7833 DV |
128 | uint amdgpu_pcie_gen_cap; |
129 | uint amdgpu_pcie_lane_cap; | |
0b693f0b RZ |
130 | uint amdgpu_cg_mask = 0xffffffff; |
131 | uint amdgpu_pg_mask = 0xffffffff; | |
132 | uint amdgpu_sdma_phase_quantum = 32; | |
6f8941a2 | 133 | char *amdgpu_disable_cu = NULL; |
9accf2fd | 134 | char *amdgpu_virtual_display = NULL; |
00544006 HR |
135 | /* OverDrive(bit 14) disabled by default*/ |
136 | uint amdgpu_pp_feature_mask = 0xffffbfff; | |
87fb7833 DV |
137 | uint amdgpu_force_long_training; |
138 | int amdgpu_job_hang_limit; | |
e8835e0e | 139 | int amdgpu_lbpw = -1; |
4a75aefe | 140 | int amdgpu_compute_multipipe = -1; |
dcebf026 | 141 | int amdgpu_gpu_recovery = -1; /* auto */ |
87fb7833 DV |
142 | int amdgpu_emu_mode; |
143 | uint amdgpu_smu_memory_pool_size; | |
191a3c04 EQ |
144 | /* |
145 | * FBC (bit 0) disabled by default | |
146 | * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default | |
147 | * - With this, for multiple monitors in sync(e.g. with the same model), | |
148 | * mclk switching will be allowed. And the mclk will be not foced to the | |
149 | * highest. That helps saving some idle power. | |
150 | * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default | |
151 | * PSR (bit 3) disabled by default | |
152 | */ | |
153 | uint amdgpu_dc_feature_mask = 2; | |
87fb7833 | 154 | uint amdgpu_dc_debug_mask; |
5bfca069 | 155 | int amdgpu_async_gfx_ring = 1; |
87fb7833 | 156 | int amdgpu_mcbp; |
63e2fef6 | 157 | int amdgpu_discovery = -1; |
87fb7833 | 158 | int amdgpu_mes; |
d5cc02d9 | 159 | int amdgpu_noretry = -1; |
4e66d7d2 | 160 | int amdgpu_force_asic_type = -1; |
87fb7833 | 161 | int amdgpu_tmz; |
273da6ff | 162 | int amdgpu_reset_method = -1; /* auto */ |
a300de40 | 163 | int amdgpu_num_kcq = -1; |
7875a226 | 164 | |
62d73fbc EQ |
165 | struct amdgpu_mgpu_info mgpu_info = { |
166 | .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), | |
167 | }; | |
1218252f | 168 | int amdgpu_ras_enable = -1; |
e53aec7e | 169 | uint amdgpu_ras_mask = 0xffffffff; |
acc0204c | 170 | int amdgpu_bad_page_threshold = -1; |
d38ceaf9 | 171 | |
8405cf39 SJ |
172 | /** |
173 | * DOC: vramlimit (int) | |
174 | * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). | |
175 | */ | |
d38ceaf9 AD |
176 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); |
177 | module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); | |
178 | ||
8405cf39 SJ |
179 | /** |
180 | * DOC: vis_vramlimit (int) | |
181 | * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). | |
182 | */ | |
218b5dcd JB |
183 | MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); |
184 | module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); | |
185 | ||
8405cf39 SJ |
186 | /** |
187 | * DOC: gartsize (uint) | |
188 | * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). | |
189 | */ | |
a4da14cc | 190 | MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); |
f9321cc4 | 191 | module_param_named(gartsize, amdgpu_gart_size, uint, 0600); |
d38ceaf9 | 192 | |
8405cf39 SJ |
193 | /** |
194 | * DOC: gttsize (int) | |
195 | * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, | |
196 | * otherwise 3/4 RAM size). | |
197 | */ | |
36d38372 CK |
198 | MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); |
199 | module_param_named(gttsize, amdgpu_gtt_size, int, 0600); | |
d38ceaf9 | 200 | |
8405cf39 SJ |
201 | /** |
202 | * DOC: moverate (int) | |
203 | * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). | |
204 | */ | |
95844d20 MO |
205 | MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); |
206 | module_param_named(moverate, amdgpu_moverate, int, 0600); | |
207 | ||
8405cf39 SJ |
208 | /** |
209 | * DOC: benchmark (int) | |
210 | * Run benchmarks. The default is 0 (Skip benchmarks). | |
211 | */ | |
d38ceaf9 AD |
212 | MODULE_PARM_DESC(benchmark, "Run benchmark"); |
213 | module_param_named(benchmark, amdgpu_benchmarking, int, 0444); | |
214 | ||
8405cf39 SJ |
215 | /** |
216 | * DOC: test (int) | |
217 | * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). | |
218 | */ | |
d38ceaf9 AD |
219 | MODULE_PARM_DESC(test, "Run tests"); |
220 | module_param_named(test, amdgpu_testing, int, 0444); | |
221 | ||
8405cf39 SJ |
222 | /** |
223 | * DOC: audio (int) | |
224 | * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. | |
225 | */ | |
d38ceaf9 AD |
226 | MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); |
227 | module_param_named(audio, amdgpu_audio, int, 0444); | |
228 | ||
8405cf39 SJ |
229 | /** |
230 | * DOC: disp_priority (int) | |
231 | * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). | |
232 | */ | |
d38ceaf9 AD |
233 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); |
234 | module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); | |
235 | ||
8405cf39 SJ |
236 | /** |
237 | * DOC: hw_i2c (int) | |
238 | * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). | |
239 | */ | |
d38ceaf9 AD |
240 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); |
241 | module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); | |
242 | ||
8405cf39 SJ |
243 | /** |
244 | * DOC: pcie_gen2 (int) | |
245 | * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). | |
246 | */ | |
d38ceaf9 AD |
247 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); |
248 | module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); | |
249 | ||
8405cf39 SJ |
250 | /** |
251 | * DOC: msi (int) | |
252 | * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). | |
253 | */ | |
d38ceaf9 AD |
254 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); |
255 | module_param_named(msi, amdgpu_msi, int, 0444); | |
256 | ||
8405cf39 | 257 | /** |
912dfc84 EQ |
258 | * DOC: lockup_timeout (string) |
259 | * Set GPU scheduler timeout value in ms. | |
260 | * | |
261 | * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or | |
262 | * multiple values specified. 0 and negative values are invalidated. They will be adjusted | |
879e723d AZ |
263 | * to the default timeout. |
264 | * | |
265 | * - With one value specified, the setting will apply to all non-compute jobs. | |
266 | * - With multiple values specified, the first one will be for GFX. | |
267 | * The second one is for Compute. The third and fourth ones are | |
268 | * for SDMA and Video. | |
269 | * | |
912dfc84 EQ |
270 | * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) |
271 | * jobs is 10000. And there is no timeout enforced on compute jobs. | |
272 | */ | |
bcccee89 ED |
273 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " |
274 | "for passthrough or sriov, 10000 for all jobs." | |
71cc9ef3 | 275 | " 0: keep default value. negative: infinity timeout), " |
bcccee89 ED |
276 | "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " |
277 | "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); | |
912dfc84 | 278 | module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); |
d38ceaf9 | 279 | |
8405cf39 SJ |
280 | /** |
281 | * DOC: dpm (int) | |
54b998ca | 282 | * Override for dynamic power management setting |
5c9a6272 | 283 | * (0 = disable, 1 = enable) |
54b998ca | 284 | * The default is -1 (auto). |
8405cf39 | 285 | */ |
d38ceaf9 AD |
286 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); |
287 | module_param_named(dpm, amdgpu_dpm, int, 0444); | |
288 | ||
8405cf39 SJ |
289 | /** |
290 | * DOC: fw_load_type (int) | |
291 | * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). | |
292 | */ | |
e635ee07 HR |
293 | MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); |
294 | module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); | |
d38ceaf9 | 295 | |
8405cf39 SJ |
296 | /** |
297 | * DOC: aspm (int) | |
298 | * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). | |
299 | */ | |
d38ceaf9 AD |
300 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); |
301 | module_param_named(aspm, amdgpu_aspm, int, 0444); | |
302 | ||
8405cf39 SJ |
303 | /** |
304 | * DOC: runpm (int) | |
305 | * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down | |
306 | * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. | |
307 | */ | |
2261229c | 308 | MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); |
d38ceaf9 AD |
309 | module_param_named(runpm, amdgpu_runtime_pm, int, 0444); |
310 | ||
8405cf39 SJ |
311 | /** |
312 | * DOC: ip_block_mask (uint) | |
313 | * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). | |
314 | * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have | |
315 | * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in | |
316 | * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). | |
317 | */ | |
d38ceaf9 AD |
318 | MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); |
319 | module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); | |
320 | ||
8405cf39 SJ |
321 | /** |
322 | * DOC: bapm (int) | |
323 | * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. | |
324 | * The default -1 (auto, enabled) | |
325 | */ | |
d38ceaf9 AD |
326 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); |
327 | module_param_named(bapm, amdgpu_bapm, int, 0444); | |
328 | ||
8405cf39 SJ |
329 | /** |
330 | * DOC: deep_color (int) | |
331 | * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). | |
332 | */ | |
d38ceaf9 AD |
333 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); |
334 | module_param_named(deep_color, amdgpu_deep_color, int, 0444); | |
335 | ||
8405cf39 SJ |
336 | /** |
337 | * DOC: vm_size (int) | |
338 | * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). | |
339 | */ | |
ed885b21 | 340 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); |
d38ceaf9 | 341 | module_param_named(vm_size, amdgpu_vm_size, int, 0444); |
d07f14be | 342 | |
8405cf39 SJ |
343 | /** |
344 | * DOC: vm_fragment_size (int) | |
345 | * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). | |
346 | */ | |
d07f14be RH |
347 | MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); |
348 | module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); | |
d38ceaf9 | 349 | |
8405cf39 SJ |
350 | /** |
351 | * DOC: vm_block_size (int) | |
352 | * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). | |
353 | */ | |
d38ceaf9 AD |
354 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); |
355 | module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); | |
356 | ||
8405cf39 SJ |
357 | /** |
358 | * DOC: vm_fault_stop (int) | |
359 | * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). | |
360 | */ | |
d9c13156 CK |
361 | MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); |
362 | module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); | |
363 | ||
8405cf39 SJ |
364 | /** |
365 | * DOC: vm_debug (int) | |
366 | * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). | |
367 | */ | |
b495bd3a CK |
368 | MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); |
369 | module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); | |
370 | ||
8405cf39 SJ |
371 | /** |
372 | * DOC: vm_update_mode (int) | |
373 | * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default | |
374 | * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). | |
375 | */ | |
9a4b7d4c HK |
376 | MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); |
377 | module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); | |
378 | ||
8405cf39 SJ |
379 | /** |
380 | * DOC: exp_hw_support (int) | |
381 | * Enable experimental hw support (1 = enable). The default is 0 (disabled). | |
382 | */ | |
d38ceaf9 AD |
383 | MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); |
384 | module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); | |
385 | ||
8405cf39 SJ |
386 | /** |
387 | * DOC: dc (int) | |
388 | * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). | |
389 | */ | |
4562236b HW |
390 | MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); |
391 | module_param_named(dc, amdgpu_dc, int, 0444); | |
392 | ||
8405cf39 SJ |
393 | /** |
394 | * DOC: sched_jobs (int) | |
395 | * Override the max number of jobs supported in the sw queue. The default is 32. | |
396 | */ | |
b70f014d | 397 | MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); |
1333f723 JZ |
398 | module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); |
399 | ||
8405cf39 SJ |
400 | /** |
401 | * DOC: sched_hw_submission (int) | |
402 | * Override the max number of HW submissions. The default is 2. | |
403 | */ | |
4afcb303 JZ |
404 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); |
405 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); | |
406 | ||
8405cf39 | 407 | /** |
7427a7a0 | 408 | * DOC: ppfeaturemask (hexint) |
8405cf39 SJ |
409 | * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. |
410 | * The default is the current set of stable power features. | |
411 | */ | |
5141e9d2 | 412 | MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); |
7427a7a0 | 413 | module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); |
3a74f6f2 | 414 | |
367039bf TY |
415 | /** |
416 | * DOC: forcelongtraining (uint) | |
417 | * Force long memory training in resume. | |
418 | * The default is zero, indicates short training in resume. | |
419 | */ | |
420 | MODULE_PARM_DESC(forcelongtraining, "force memory long training"); | |
421 | module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); | |
422 | ||
8405cf39 SJ |
423 | /** |
424 | * DOC: pcie_gen_cap (uint) | |
425 | * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. | |
426 | * The default is 0 (automatic for each asic). | |
427 | */ | |
cd474ba0 AD |
428 | MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); |
429 | module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); | |
430 | ||
8405cf39 SJ |
431 | /** |
432 | * DOC: pcie_lane_cap (uint) | |
433 | * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. | |
434 | * The default is 0 (automatic for each asic). | |
435 | */ | |
cd474ba0 AD |
436 | MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); |
437 | module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); | |
438 | ||
8405cf39 SJ |
439 | /** |
440 | * DOC: cg_mask (uint) | |
441 | * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in | |
442 | * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). | |
443 | */ | |
395d1fb9 NH |
444 | MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); |
445 | module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); | |
446 | ||
8405cf39 SJ |
447 | /** |
448 | * DOC: pg_mask (uint) | |
449 | * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in | |
450 | * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). | |
451 | */ | |
395d1fb9 NH |
452 | MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); |
453 | module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); | |
454 | ||
8405cf39 SJ |
455 | /** |
456 | * DOC: sdma_phase_quantum (uint) | |
457 | * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. | |
458 | */ | |
a667386c FK |
459 | MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); |
460 | module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); | |
461 | ||
8405cf39 SJ |
462 | /** |
463 | * DOC: disable_cu (charp) | |
464 | * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. | |
465 | */ | |
6f8941a2 NH |
466 | MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); |
467 | module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); | |
468 | ||
8405cf39 SJ |
469 | /** |
470 | * DOC: virtual_display (charp) | |
471 | * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards | |
472 | * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of | |
473 | * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci | |
474 | * device at 26:00.0. The default is NULL. | |
475 | */ | |
0f66356d ED |
476 | MODULE_PARM_DESC(virtual_display, |
477 | "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); | |
9accf2fd | 478 | module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); |
e443059d | 479 | |
8405cf39 SJ |
480 | /** |
481 | * DOC: job_hang_limit (int) | |
482 | * Set how much time allow a job hang and not drop it. The default is 0. | |
483 | */ | |
65781c78 ML |
484 | MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); |
485 | module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); | |
486 | ||
8405cf39 SJ |
487 | /** |
488 | * DOC: lbpw (int) | |
489 | * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). | |
490 | */ | |
e8835e0e HZ |
491 | MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); |
492 | module_param_named(lbpw, amdgpu_lbpw, int, 0444); | |
bce23e00 | 493 | |
4a75aefe AR |
494 | MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); |
495 | module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); | |
496 | ||
8405cf39 SJ |
497 | /** |
498 | * DOC: gpu_recovery (int) | |
499 | * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). | |
500 | */ | |
d869ae09 | 501 | MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); |
dcebf026 AG |
502 | module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); |
503 | ||
8405cf39 SJ |
504 | /** |
505 | * DOC: emu_mode (int) | |
506 | * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). | |
507 | */ | |
d869ae09 | 508 | MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); |
bfca0289 SL |
509 | module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); |
510 | ||
1218252f | 511 | /** |
2f3940e9 | 512 | * DOC: ras_enable (int) |
1218252f | 513 | * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) |
514 | */ | |
2f3940e9 | 515 | MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); |
1218252f | 516 | module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); |
517 | ||
518 | /** | |
2f3940e9 | 519 | * DOC: ras_mask (uint) |
1218252f | 520 | * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 |
521 | * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | |
522 | */ | |
2f3940e9 | 523 | MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); |
1218252f | 524 | module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); |
525 | ||
8405cf39 SJ |
526 | /** |
527 | * DOC: si_support (int) | |
528 | * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, | |
529 | * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, | |
530 | * otherwise using amdgpu driver. | |
531 | */ | |
6dd13096 | 532 | #ifdef CONFIG_DRM_AMDGPU_SI |
53efaf56 MD |
533 | |
534 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) | |
6dd13096 FK |
535 | int amdgpu_si_support = 0; |
536 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); | |
53efaf56 MD |
537 | #else |
538 | int amdgpu_si_support = 1; | |
539 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); | |
540 | #endif | |
541 | ||
6dd13096 FK |
542 | module_param_named(si_support, amdgpu_si_support, int, 0444); |
543 | #endif | |
544 | ||
8405cf39 SJ |
545 | /** |
546 | * DOC: cik_support (int) | |
547 | * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, | |
548 | * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, | |
549 | * otherwise using amdgpu driver. | |
550 | */ | |
7df28986 | 551 | #ifdef CONFIG_DRM_AMDGPU_CIK |
53efaf56 MD |
552 | |
553 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) | |
2b059658 MD |
554 | int amdgpu_cik_support = 0; |
555 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); | |
53efaf56 MD |
556 | #else |
557 | int amdgpu_cik_support = 1; | |
558 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); | |
559 | #endif | |
560 | ||
7df28986 FK |
561 | module_param_named(cik_support, amdgpu_cik_support, int, 0444); |
562 | #endif | |
563 | ||
8405cf39 SJ |
564 | /** |
565 | * DOC: smu_memory_pool_size (uint) | |
566 | * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. | |
567 | * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). | |
568 | */ | |
7951e376 RZ |
569 | MODULE_PARM_DESC(smu_memory_pool_size, |
570 | "reserve gtt for smu debug usage, 0 = disable," | |
571 | "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); | |
572 | module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); | |
573 | ||
51bcce46 HZ |
574 | /** |
575 | * DOC: async_gfx_ring (int) | |
576 | * It is used to enable gfx rings that could be configured with different prioritites or equal priorities | |
577 | */ | |
578 | MODULE_PARM_DESC(async_gfx_ring, | |
5bfca069 | 579 | "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); |
51bcce46 HZ |
580 | module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); |
581 | ||
40562787 AD |
582 | /** |
583 | * DOC: mcbp (int) | |
584 | * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) | |
585 | */ | |
b239c017 JX |
586 | MODULE_PARM_DESC(mcbp, |
587 | "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); | |
588 | module_param_named(mcbp, amdgpu_mcbp, int, 0444); | |
589 | ||
40562787 AD |
590 | /** |
591 | * DOC: discovery (int) | |
592 | * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. | |
63e2fef6 | 593 | * (-1 = auto (default), 0 = disabled, 1 = enabled) |
40562787 | 594 | */ |
a190d1c7 XY |
595 | MODULE_PARM_DESC(discovery, |
596 | "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); | |
597 | module_param_named(discovery, amdgpu_discovery, int, 0444); | |
598 | ||
40562787 AD |
599 | /** |
600 | * DOC: mes (int) | |
601 | * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. | |
602 | * (0 = disabled (default), 1 = enabled) | |
603 | */ | |
38487284 JX |
604 | MODULE_PARM_DESC(mes, |
605 | "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); | |
606 | module_param_named(mes, amdgpu_mes, int, 0444); | |
607 | ||
d5cc02d9 AD |
608 | /** |
609 | * DOC: noretry (int) | |
610 | * Disable retry faults in the GPU memory controller. | |
611 | * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) | |
612 | */ | |
75ee6487 | 613 | MODULE_PARM_DESC(noretry, |
d5cc02d9 | 614 | "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); |
75ee6487 FK |
615 | module_param_named(noretry, amdgpu_noretry, int, 0644); |
616 | ||
4e66d7d2 YZ |
617 | /** |
618 | * DOC: force_asic_type (int) | |
619 | * A non negative value used to specify the asic type for all supported GPUs. | |
620 | */ | |
621 | MODULE_PARM_DESC(force_asic_type, | |
622 | "A non negative value used to specify the asic type for all supported GPUs"); | |
623 | module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); | |
624 | ||
625 | ||
626 | ||
2690262e | 627 | #ifdef CONFIG_HSA_AMD |
521fb7d0 AL |
628 | /** |
629 | * DOC: sched_policy (int) | |
630 | * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. | |
631 | * Setting 1 disables over-subscription. Setting 2 disables HWS and statically | |
632 | * assigns queues to HQDs. | |
633 | */ | |
2690262e | 634 | int sched_policy = KFD_SCHED_POLICY_HWS; |
521fb7d0 AL |
635 | module_param(sched_policy, int, 0444); |
636 | MODULE_PARM_DESC(sched_policy, | |
637 | "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); | |
638 | ||
639 | /** | |
640 | * DOC: hws_max_conc_proc (int) | |
641 | * Maximum number of processes that HWS can schedule concurrently. The maximum is the | |
642 | * number of VMIDs assigned to the HWS, which is also the default. | |
643 | */ | |
2690262e | 644 | int hws_max_conc_proc = 8; |
521fb7d0 AL |
645 | module_param(hws_max_conc_proc, int, 0444); |
646 | MODULE_PARM_DESC(hws_max_conc_proc, | |
647 | "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); | |
648 | ||
649 | /** | |
650 | * DOC: cwsr_enable (int) | |
651 | * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in | |
652 | * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 | |
653 | * disables it. | |
654 | */ | |
2690262e | 655 | int cwsr_enable = 1; |
521fb7d0 AL |
656 | module_param(cwsr_enable, int, 0444); |
657 | MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); | |
658 | ||
659 | /** | |
660 | * DOC: max_num_of_queues_per_device (int) | |
661 | * Maximum number of queues per device. Valid setting is between 1 and 4096. Default | |
662 | * is 4096. | |
663 | */ | |
2690262e | 664 | int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; |
521fb7d0 AL |
665 | module_param(max_num_of_queues_per_device, int, 0444); |
666 | MODULE_PARM_DESC(max_num_of_queues_per_device, | |
667 | "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); | |
668 | ||
669 | /** | |
670 | * DOC: send_sigterm (int) | |
671 | * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm | |
672 | * but just print errors on dmesg. Setting 1 enables sending sigterm. | |
673 | */ | |
2690262e | 674 | int send_sigterm; |
521fb7d0 AL |
675 | module_param(send_sigterm, int, 0444); |
676 | MODULE_PARM_DESC(send_sigterm, | |
677 | "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); | |
678 | ||
679 | /** | |
680 | * DOC: debug_largebar (int) | |
681 | * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar | |
682 | * system. This limits the VRAM size reported to ROCm applications to the visible | |
683 | * size, usually 256MB. | |
684 | * Default value is 0, diabled. | |
685 | */ | |
2690262e | 686 | int debug_largebar; |
521fb7d0 AL |
687 | module_param(debug_largebar, int, 0444); |
688 | MODULE_PARM_DESC(debug_largebar, | |
689 | "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); | |
690 | ||
691 | /** | |
692 | * DOC: ignore_crat (int) | |
693 | * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT | |
694 | * table to get information about AMD APUs. This option can serve as a workaround on | |
695 | * systems with a broken CRAT table. | |
6127896f HR |
696 | * |
697 | * Default is auto (according to asic type, iommu_v2, and crat table, to decide | |
698 | * whehter use CRAT) | |
521fb7d0 | 699 | */ |
2690262e | 700 | int ignore_crat; |
521fb7d0 AL |
701 | module_param(ignore_crat, int, 0444); |
702 | MODULE_PARM_DESC(ignore_crat, | |
6127896f | 703 | "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); |
521fb7d0 | 704 | |
521fb7d0 AL |
705 | /** |
706 | * DOC: halt_if_hws_hang (int) | |
707 | * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. | |
708 | * Setting 1 enables halt on hang. | |
709 | */ | |
2690262e | 710 | int halt_if_hws_hang; |
521fb7d0 AL |
711 | module_param(halt_if_hws_hang, int, 0644); |
712 | MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); | |
29e76462 OZ |
713 | |
714 | /** | |
715 | * DOC: hws_gws_support(bool) | |
29633d0e JG |
716 | * Assume that HWS supports GWS barriers regardless of what firmware version |
717 | * check says. Default value: false (rely on MEC2 firmware version check). | |
29e76462 OZ |
718 | */ |
719 | bool hws_gws_support; | |
720 | module_param(hws_gws_support, bool, 0444); | |
29633d0e | 721 | MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); |
14328aa5 PC |
722 | |
723 | /** | |
724 | * DOC: queue_preemption_timeout_ms (int) | |
725 | * queue preemption timeout in ms (1 = Minimum, 9000 = default) | |
726 | */ | |
f51af435 | 727 | int queue_preemption_timeout_ms = 9000; |
14328aa5 PC |
728 | module_param(queue_preemption_timeout_ms, int, 0644); |
729 | MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); | |
b2057956 FK |
730 | |
731 | /** | |
732 | * DOC: debug_evictions(bool) | |
733 | * Enable extra debug messages to help determine the cause of evictions | |
734 | */ | |
735 | bool debug_evictions; | |
736 | module_param(debug_evictions, bool, 0644); | |
737 | MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); | |
b80f050f PY |
738 | |
739 | /** | |
740 | * DOC: no_system_mem_limit(bool) | |
741 | * Disable system memory limit, to support multiple process shared memory | |
742 | */ | |
743 | bool no_system_mem_limit; | |
744 | module_param(no_system_mem_limit, bool, 0644); | |
745 | MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); | |
746 | ||
2690262e | 747 | #endif |
521fb7d0 | 748 | |
7875a226 AD |
749 | /** |
750 | * DOC: dcfeaturemask (uint) | |
751 | * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. | |
752 | * The default is the current set of stable display features. | |
753 | */ | |
754 | MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); | |
755 | module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); | |
756 | ||
8a791dab HW |
757 | /** |
758 | * DOC: dcdebugmask (uint) | |
759 | * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. | |
760 | */ | |
761 | MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); | |
762 | module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); | |
763 | ||
ad4de27f NK |
764 | /** |
765 | * DOC: abmlevel (uint) | |
766 | * Override the default ABM (Adaptive Backlight Management) level used for DC | |
767 | * enabled hardware. Requires DMCU to be supported and loaded. | |
768 | * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by | |
769 | * default. Values 1-4 control the maximum allowable brightness reduction via | |
770 | * the ABM algorithm, with 1 being the least reduction and 4 being the most | |
771 | * reduction. | |
772 | * | |
773 | * Defaults to 0, or disabled. Userspace can still override this level later | |
774 | * after boot. | |
775 | */ | |
87fb7833 | 776 | uint amdgpu_dm_abm_level; |
ad4de27f NK |
777 | MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); |
778 | module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); | |
779 | ||
3402b746 TI |
780 | int amdgpu_backlight = -1; |
781 | MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); | |
782 | module_param_named(backlight, amdgpu_backlight, bint, 0444); | |
783 | ||
d7ccb38d HR |
784 | /** |
785 | * DOC: tmz (int) | |
786 | * Trusted Memory Zone (TMZ) is a method to protect data being written | |
787 | * to or read from memory. | |
788 | * | |
789 | * The default value: 0 (off). TODO: change to auto till it is completed. | |
790 | */ | |
791 | MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)"); | |
792 | module_param_named(tmz, amdgpu_tmz, int, 0444); | |
793 | ||
273da6ff WS |
794 | /** |
795 | * DOC: reset_method (int) | |
796 | * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) | |
797 | */ | |
2261229c | 798 | MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); |
273da6ff WS |
799 | module_param_named(reset_method, amdgpu_reset_method, int, 0444); |
800 | ||
acc0204c GC |
801 | /** |
802 | * DOC: bad_page_threshold (int) | |
803 | * Bad page threshold is to specify the threshold value of faulty pages | |
804 | * detected by RAS ECC, that may result in GPU entering bad status if total | |
805 | * faulty pages by ECC exceed threshold value and leave it for user's further | |
806 | * check. | |
807 | */ | |
808 | MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); | |
809 | module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); | |
810 | ||
a300de40 ML |
811 | MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); |
812 | module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); | |
813 | ||
f498d9ed | 814 | static const struct pci_device_id pciidlist[] = { |
78fbb685 KW |
815 | #ifdef CONFIG_DRM_AMDGPU_SI |
816 | {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
817 | {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
818 | {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
819 | {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
820 | {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
821 | {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
822 | {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
823 | {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
824 | {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
825 | {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
826 | {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
827 | {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
828 | {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
829 | {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
830 | {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
831 | {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
832 | {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
833 | {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
834 | {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
835 | {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
836 | {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
837 | {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
838 | {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
839 | {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
840 | {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
841 | {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
842 | {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
843 | {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
844 | {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
845 | {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
846 | {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
847 | {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
848 | {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
849 | {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
850 | {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
851 | {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
852 | {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
853 | {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
854 | {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
855 | {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
856 | {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
857 | {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
858 | {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
859 | {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
860 | {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
861 | {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
862 | {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
863 | {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
864 | {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
865 | {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
866 | {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
867 | {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
868 | {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
869 | {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
870 | {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
871 | {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
872 | {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
873 | {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
874 | {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
875 | {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
876 | {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
877 | {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
878 | {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
879 | {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
880 | {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
881 | {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
882 | {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
883 | {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
884 | {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
885 | {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
886 | {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
887 | {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
888 | #endif | |
89330c39 AD |
889 | #ifdef CONFIG_DRM_AMDGPU_CIK |
890 | /* Kaveri */ | |
2f7d10b3 JZ |
891 | {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
892 | {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
893 | {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
894 | {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
895 | {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
896 | {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
897 | {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
898 | {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
899 | {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
900 | {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
901 | {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
902 | {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
903 | {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
904 | {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
905 | {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
906 | {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
907 | {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
908 | {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
909 | {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
910 | {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
911 | {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
912 | {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
89330c39 | 913 | /* Bonaire */ |
2f7d10b3 JZ |
914 | {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
915 | {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
916 | {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
917 | {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
89330c39 AD |
918 | {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
919 | {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
920 | {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
921 | {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
922 | {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
923 | {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
fb4f1737 | 924 | {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
89330c39 AD |
925 | /* Hawaii */ |
926 | {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
927 | {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
928 | {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
929 | {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
930 | {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
931 | {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
932 | {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
933 | {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
934 | {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
935 | {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
936 | {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
937 | {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
938 | /* Kabini */ | |
2f7d10b3 JZ |
939 | {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
940 | {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
941 | {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
942 | {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
943 | {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
944 | {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
945 | {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
946 | {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
947 | {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
948 | {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
949 | {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
950 | {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
951 | {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
952 | {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
953 | {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
954 | {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
89330c39 | 955 | /* mullins */ |
2f7d10b3 JZ |
956 | {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
957 | {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
958 | {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
959 | {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
960 | {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
961 | {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
962 | {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
963 | {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
964 | {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
965 | {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
966 | {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
967 | {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
968 | {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
969 | {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
970 | {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
971 | {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
89330c39 | 972 | #endif |
1256a8b8 | 973 | /* topaz */ |
dba280b2 AD |
974 | {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
975 | {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
976 | {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
977 | {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
978 | {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
1256a8b8 AD |
979 | /* tonga */ |
980 | {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
981 | {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
982 | {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
1f8d9625 | 983 | {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
1256a8b8 AD |
984 | {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
985 | {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
1f8d9625 | 986 | {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
1256a8b8 AD |
987 | {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
988 | {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
2da78e21 DZ |
989 | /* fiji */ |
990 | {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, | |
e1d99217 | 991 | {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, |
1256a8b8 | 992 | /* carrizo */ |
2f7d10b3 JZ |
993 | {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
994 | {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
995 | {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
996 | {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
997 | {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
81b1509a SL |
998 | /* stoney */ |
999 | {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, | |
2cc0c0b5 FC |
1000 | /* Polaris11 */ |
1001 | {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
35621b80 | 1002 | {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 1003 | {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 1004 | {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
35621b80 | 1005 | {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 1006 | {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
35621b80 FC |
1007 | {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
1008 | {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
1009 | {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
2cc0c0b5 FC |
1010 | /* Polaris10 */ |
1011 | {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
1dcf4801 FC |
1012 | {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
1013 | {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
1014 | {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
1015 | {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
7dae6181 | 1016 | {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
2cc0c0b5 | 1017 | {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
1dcf4801 FC |
1018 | {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
1019 | {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
1020 | {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
1021 | {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
1022 | {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
30f3984e | 1023 | {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
fc8e9c54 JZ |
1024 | /* Polaris12 */ |
1025 | {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
1026 | {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
1027 | {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
1028 | {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
1029 | {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
cf8c73af | 1030 | {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
6e88491c | 1031 | {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
fc8e9c54 | 1032 | {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
e9307932 LL |
1033 | /* VEGAM */ |
1034 | {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, | |
1035 | {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, | |
f6653a0e | 1036 | {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, |
ca2f1cca | 1037 | /* Vega 10 */ |
dfbf0c14 AD |
1038 | {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
1039 | {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
1040 | {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
1041 | {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
1042 | {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
1043 | {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
1044 | {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
2244b588 AD |
1045 | {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
1046 | {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
1047 | {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
dfbf0c14 | 1048 | {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
2244b588 AD |
1049 | {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
1050 | {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
1051 | {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
dfbf0c14 | 1052 | {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
dc53d543 AD |
1053 | /* Vega 12 */ |
1054 | {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
1055 | {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
1056 | {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
1057 | {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
1058 | {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
1204a26e | 1059 | /* Vega 20 */ |
6dddaeef AD |
1060 | {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
1061 | {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, | |
1062 | {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, | |
1063 | {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, | |
ec5b2020 | 1064 | {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
6dddaeef AD |
1065 | {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
1066 | {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, | |
df515052 | 1067 | /* Raven */ |
acc34503 | 1068 | {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
741deade | 1069 | {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
48c69cda | 1070 | /* Arcturus */ |
12c5365e AD |
1071 | {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, |
1072 | {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, | |
1073 | {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, | |
1074 | {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, | |
bd1c0fdf AD |
1075 | /* Navi10 */ |
1076 | {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, | |
1077 | {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, | |
1078 | {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, | |
4f56d9d4 | 1079 | {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
bd1c0fdf | 1080 | {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
4f56d9d4 | 1081 | {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
89428811 | 1082 | {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
bd1c0fdf | 1083 | {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
26051720 | 1084 | /* Navi14 */ |
b62d9554 AD |
1085 | {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, |
1086 | {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, | |
1087 | {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, | |
1088 | {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, | |
df515052 | 1089 | |
61bdb39c | 1090 | /* Renoir */ |
23fe1390 | 1091 | {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
21702c8c | 1092 | {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
53f1e7f6 | 1093 | {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
61bdb39c | 1094 | |
10e85054 | 1095 | /* Navi12 */ |
d34c7b7b AD |
1096 | {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, |
1097 | {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, | |
10e85054 | 1098 | |
61278d14 LG |
1099 | /* Sienna_Cichlid */ |
1100 | {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, | |
1101 | {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, | |
1102 | {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, | |
1103 | {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, | |
1104 | {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, | |
d50d0e41 | 1105 | {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, |
61278d14 | 1106 | {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, |
10e85054 | 1107 | |
894052d6 HR |
1108 | /* Van Gogh */ |
1109 | {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, | |
1110 | ||
2c1eaddd TZ |
1111 | /* Navy_Flounder */ |
1112 | {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, | |
1113 | {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, | |
1114 | {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, | |
1115 | {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, | |
1116 | ||
e7de4aee TZ |
1117 | /* DIMGREY_CAVEFISH */ |
1118 | {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, | |
1119 | {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, | |
1120 | {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, | |
1121 | {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, | |
1122 | ||
d38ceaf9 AD |
1123 | {0, 0, 0} |
1124 | }; | |
1125 | ||
1126 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
1127 | ||
5088d657 | 1128 | static const struct drm_driver amdgpu_kms_driver; |
d38ceaf9 | 1129 | |
d38ceaf9 AD |
1130 | static int amdgpu_pci_probe(struct pci_dev *pdev, |
1131 | const struct pci_device_id *ent) | |
1132 | { | |
8aba21b7 | 1133 | struct drm_device *ddev; |
c6385e50 | 1134 | struct amdgpu_device *adev; |
d38ceaf9 | 1135 | unsigned long flags = ent->driver_data; |
1daee8b4 | 1136 | int ret, retry = 0; |
3fa203af AD |
1137 | bool supports_atomic = false; |
1138 | ||
1139 | if (!amdgpu_virtual_display && | |
1140 | amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) | |
1141 | supports_atomic = true; | |
d38ceaf9 | 1142 | |
2f7d10b3 | 1143 | if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { |
d38ceaf9 AD |
1144 | DRM_INFO("This hardware requires experimental hardware support.\n" |
1145 | "See modparam exp_hw_support\n"); | |
1146 | return -ENODEV; | |
1147 | } | |
1148 | ||
ea68573d AD |
1149 | /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, |
1150 | * however, SME requires an indirect IOMMU mapping because the encryption | |
1151 | * bit is beyond the DMA mask of the chip. | |
1152 | */ | |
1153 | if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { | |
1154 | dev_info(&pdev->dev, | |
1155 | "SME is not compatible with RAVEN\n"); | |
1156 | return -ENOTSUPP; | |
1157 | } | |
1158 | ||
984d7a92 HG |
1159 | #ifdef CONFIG_DRM_AMDGPU_SI |
1160 | if (!amdgpu_si_support) { | |
1161 | switch (flags & AMD_ASIC_MASK) { | |
1162 | case CHIP_TAHITI: | |
1163 | case CHIP_PITCAIRN: | |
1164 | case CHIP_VERDE: | |
1165 | case CHIP_OLAND: | |
1166 | case CHIP_HAINAN: | |
1167 | dev_info(&pdev->dev, | |
1168 | "SI support provided by radeon.\n"); | |
1169 | dev_info(&pdev->dev, | |
1170 | "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" | |
1171 | ); | |
1172 | return -ENODEV; | |
1173 | } | |
1174 | } | |
1175 | #endif | |
1176 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1177 | if (!amdgpu_cik_support) { | |
1178 | switch (flags & AMD_ASIC_MASK) { | |
1179 | case CHIP_KAVERI: | |
1180 | case CHIP_BONAIRE: | |
1181 | case CHIP_HAWAII: | |
1182 | case CHIP_KABINI: | |
1183 | case CHIP_MULLINS: | |
1184 | dev_info(&pdev->dev, | |
1185 | "CIK support provided by radeon.\n"); | |
1186 | dev_info(&pdev->dev, | |
1187 | "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" | |
1188 | ); | |
1189 | return -ENODEV; | |
1190 | } | |
1191 | } | |
1192 | #endif | |
1193 | ||
d38ceaf9 | 1194 | /* Get rid of things like offb */ |
35616a4a | 1195 | ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); |
d38ceaf9 AD |
1196 | if (ret) |
1197 | return ret; | |
1198 | ||
5088d657 | 1199 | adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); |
df2ce459 LT |
1200 | if (IS_ERR(adev)) |
1201 | return PTR_ERR(adev); | |
8aba21b7 LT |
1202 | |
1203 | adev->dev = &pdev->dev; | |
1204 | adev->pdev = pdev; | |
1205 | ddev = adev_to_drm(adev); | |
b58c1131 | 1206 | |
351c4dbe | 1207 | if (!supports_atomic) |
8aba21b7 | 1208 | ddev->driver_features &= ~DRIVER_ATOMIC; |
351c4dbe | 1209 | |
b58c1131 AD |
1210 | ret = pci_enable_device(pdev); |
1211 | if (ret) | |
df2ce459 | 1212 | return ret; |
b58c1131 | 1213 | |
8aba21b7 LT |
1214 | ddev->pdev = pdev; |
1215 | pci_set_drvdata(pdev, ddev); | |
b58c1131 | 1216 | |
8aba21b7 | 1217 | ret = amdgpu_driver_load_kms(adev, ent->driver_data); |
7504d3bb LC |
1218 | if (ret) |
1219 | goto err_pci; | |
c6385e50 | 1220 | |
1daee8b4 | 1221 | retry_init: |
8aba21b7 | 1222 | ret = drm_dev_register(ddev, ent->driver_data); |
1daee8b4 PD |
1223 | if (ret == -EAGAIN && ++retry <= 3) { |
1224 | DRM_INFO("retry init %d\n", retry); | |
1225 | /* Don't request EX mode too frequently which is attacking */ | |
1226 | msleep(5000); | |
1227 | goto retry_init; | |
8aba21b7 | 1228 | } else if (ret) { |
b58c1131 | 1229 | goto err_pci; |
8aba21b7 | 1230 | } |
b58c1131 | 1231 | |
c6385e50 AD |
1232 | ret = amdgpu_debugfs_init(adev); |
1233 | if (ret) | |
1234 | DRM_ERROR("Creating debugfs files failed (%d).\n", ret); | |
1235 | ||
b58c1131 AD |
1236 | return 0; |
1237 | ||
1238 | err_pci: | |
1239 | pci_disable_device(pdev); | |
b58c1131 | 1240 | return ret; |
d38ceaf9 AD |
1241 | } |
1242 | ||
1243 | static void | |
1244 | amdgpu_pci_remove(struct pci_dev *pdev) | |
1245 | { | |
1246 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1247 | ||
56f074d8 CK |
1248 | #ifdef MODULE |
1249 | if (THIS_MODULE->state != MODULE_STATE_GOING) | |
1250 | #endif | |
1251 | DRM_ERROR("Hotplug removal is not supported\n"); | |
88b35d83 | 1252 | drm_dev_unplug(dev); |
c6385e50 | 1253 | amdgpu_driver_unload_kms(dev); |
fd4495e5 XY |
1254 | pci_disable_device(pdev); |
1255 | pci_set_drvdata(pdev, NULL); | |
d38ceaf9 AD |
1256 | } |
1257 | ||
61e11306 AD |
1258 | static void |
1259 | amdgpu_pci_shutdown(struct pci_dev *pdev) | |
1260 | { | |
faefba95 | 1261 | struct drm_device *dev = pci_get_drvdata(pdev); |
1348969a | 1262 | struct amdgpu_device *adev = drm_to_adev(dev); |
faefba95 | 1263 | |
7c6e68c7 AG |
1264 | if (amdgpu_ras_intr_triggered()) |
1265 | return; | |
1266 | ||
61e11306 | 1267 | /* if we are running in a VM, make sure the device |
00ea8cba AD |
1268 | * torn down properly on reboot/shutdown. |
1269 | * unfortunately we can't detect certain | |
1270 | * hypervisors so just do this all the time. | |
61e11306 | 1271 | */ |
05cac1ae ND |
1272 | if (!amdgpu_passthrough(adev)) |
1273 | adev->mp1_state = PP_MP1_STATE_UNLOAD; | |
f22e40e1 | 1274 | adev->in_poweroff_reboot_com = true; |
cdd61df6 | 1275 | amdgpu_device_ip_suspend(adev); |
f22e40e1 | 1276 | adev->in_poweroff_reboot_com = false; |
a3a09142 | 1277 | adev->mp1_state = PP_MP1_STATE_NONE; |
61e11306 AD |
1278 | } |
1279 | ||
d38ceaf9 AD |
1280 | static int amdgpu_pmops_suspend(struct device *dev) |
1281 | { | |
911d8b30 | 1282 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
74b0b157 | 1283 | |
de185019 | 1284 | return amdgpu_device_suspend(drm_dev, true); |
d38ceaf9 AD |
1285 | } |
1286 | ||
1287 | static int amdgpu_pmops_resume(struct device *dev) | |
1288 | { | |
911d8b30 | 1289 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
85e154c2 | 1290 | |
de185019 | 1291 | return amdgpu_device_resume(drm_dev, true); |
d38ceaf9 AD |
1292 | } |
1293 | ||
1294 | static int amdgpu_pmops_freeze(struct device *dev) | |
1295 | { | |
911d8b30 | 1296 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
1348969a | 1297 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
897483d8 | 1298 | int r; |
74b0b157 | 1299 | |
85625e64 | 1300 | adev->in_hibernate = true; |
de185019 | 1301 | r = amdgpu_device_suspend(drm_dev, true); |
85625e64 | 1302 | adev->in_hibernate = false; |
897483d8 AD |
1303 | if (r) |
1304 | return r; | |
1305 | return amdgpu_asic_reset(adev); | |
d38ceaf9 AD |
1306 | } |
1307 | ||
1308 | static int amdgpu_pmops_thaw(struct device *dev) | |
1309 | { | |
911d8b30 | 1310 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
74b0b157 | 1311 | |
de185019 | 1312 | return amdgpu_device_resume(drm_dev, true); |
74b0b157 | 1313 | } |
1314 | ||
1315 | static int amdgpu_pmops_poweroff(struct device *dev) | |
1316 | { | |
911d8b30 | 1317 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
f22e40e1 PL |
1318 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
1319 | int r; | |
74b0b157 | 1320 | |
f22e40e1 PL |
1321 | adev->in_poweroff_reboot_com = true; |
1322 | r = amdgpu_device_suspend(drm_dev, true); | |
1323 | adev->in_poweroff_reboot_com = false; | |
1324 | return r; | |
74b0b157 | 1325 | } |
1326 | ||
1327 | static int amdgpu_pmops_restore(struct device *dev) | |
1328 | { | |
911d8b30 | 1329 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
74b0b157 | 1330 | |
de185019 | 1331 | return amdgpu_device_resume(drm_dev, true); |
d38ceaf9 AD |
1332 | } |
1333 | ||
1334 | static int amdgpu_pmops_runtime_suspend(struct device *dev) | |
1335 | { | |
1336 | struct pci_dev *pdev = to_pci_dev(dev); | |
1337 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1348969a | 1338 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
719423f6 | 1339 | int ret, i; |
d38ceaf9 | 1340 | |
6ae6c7d4 | 1341 | if (!adev->runpm) { |
d38ceaf9 AD |
1342 | pm_runtime_forbid(dev); |
1343 | return -EBUSY; | |
1344 | } | |
1345 | ||
719423f6 AD |
1346 | /* wait for all rings to drain before suspending */ |
1347 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
1348 | struct amdgpu_ring *ring = adev->rings[i]; | |
1349 | if (ring && ring->sched.ready) { | |
1350 | ret = amdgpu_fence_wait_empty(ring); | |
1351 | if (ret) | |
1352 | return -EBUSY; | |
1353 | } | |
1354 | } | |
1355 | ||
f0f7ddfc | 1356 | adev->in_runpm = true; |
fd496ca8 | 1357 | if (amdgpu_device_supports_atpx(drm_dev)) |
b97e9d47 | 1358 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
d38ceaf9 | 1359 | drm_kms_helper_poll_disable(drm_dev); |
d38ceaf9 | 1360 | |
de185019 | 1361 | ret = amdgpu_device_suspend(drm_dev, false); |
70bedd68 RB |
1362 | if (ret) |
1363 | return ret; | |
1364 | ||
fd496ca8 | 1365 | if (amdgpu_device_supports_atpx(drm_dev)) { |
562b49fc AD |
1366 | /* Only need to handle PCI state in the driver for ATPX |
1367 | * PCI core handles it for _PR3. | |
1368 | */ | |
ceb4de67 | 1369 | if (!amdgpu_is_atpx_hybrid()) { |
c1dd4aa6 | 1370 | amdgpu_device_cache_pci_state(pdev); |
562b49fc AD |
1371 | pci_disable_device(pdev); |
1372 | pci_ignore_hotplug(pdev); | |
b97e9d47 | 1373 | pci_set_power_state(pdev, PCI_D3cold); |
562b49fc | 1374 | } |
b97e9d47 | 1375 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; |
19134317 AD |
1376 | } else if (amdgpu_device_supports_baco(drm_dev)) { |
1377 | amdgpu_device_baco_enter(drm_dev); | |
b97e9d47 | 1378 | } |
d38ceaf9 AD |
1379 | |
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | static int amdgpu_pmops_runtime_resume(struct device *dev) | |
1384 | { | |
1385 | struct pci_dev *pdev = to_pci_dev(dev); | |
1386 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
1348969a | 1387 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
d38ceaf9 AD |
1388 | int ret; |
1389 | ||
6ae6c7d4 | 1390 | if (!adev->runpm) |
d38ceaf9 AD |
1391 | return -EINVAL; |
1392 | ||
fd496ca8 | 1393 | if (amdgpu_device_supports_atpx(drm_dev)) { |
b97e9d47 AD |
1394 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
1395 | ||
562b49fc AD |
1396 | /* Only need to handle PCI state in the driver for ATPX |
1397 | * PCI core handles it for _PR3. | |
1398 | */ | |
637bb036 | 1399 | if (!amdgpu_is_atpx_hybrid()) { |
b97e9d47 | 1400 | pci_set_power_state(pdev, PCI_D0); |
c1dd4aa6 | 1401 | amdgpu_device_load_pci_state(pdev); |
562b49fc AD |
1402 | ret = pci_enable_device(pdev); |
1403 | if (ret) | |
1404 | return ret; | |
562b49fc | 1405 | } |
637bb036 | 1406 | pci_set_master(pdev); |
fd496ca8 AD |
1407 | } else if (amdgpu_device_supports_boco(drm_dev)) { |
1408 | /* Only need to handle PCI state in the driver for ATPX | |
1409 | * PCI core handles it for _PR3. | |
1410 | */ | |
1411 | pci_set_master(pdev); | |
19134317 AD |
1412 | } else if (amdgpu_device_supports_baco(drm_dev)) { |
1413 | amdgpu_device_baco_exit(drm_dev); | |
b97e9d47 | 1414 | } |
de185019 | 1415 | ret = amdgpu_device_resume(drm_dev, false); |
d38ceaf9 | 1416 | drm_kms_helper_poll_enable(drm_dev); |
fd496ca8 | 1417 | if (amdgpu_device_supports_atpx(drm_dev)) |
b97e9d47 | 1418 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; |
f0f7ddfc | 1419 | adev->in_runpm = false; |
d38ceaf9 AD |
1420 | return 0; |
1421 | } | |
1422 | ||
1423 | static int amdgpu_pmops_runtime_idle(struct device *dev) | |
1424 | { | |
911d8b30 | 1425 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
1348969a | 1426 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
97f6a21b AG |
1427 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ |
1428 | int ret = 1; | |
d38ceaf9 | 1429 | |
6ae6c7d4 | 1430 | if (!adev->runpm) { |
d38ceaf9 AD |
1431 | pm_runtime_forbid(dev); |
1432 | return -EBUSY; | |
1433 | } | |
1434 | ||
97f6a21b AG |
1435 | if (amdgpu_device_has_dc_support(adev)) { |
1436 | struct drm_crtc *crtc; | |
1437 | ||
1438 | drm_modeset_lock_all(drm_dev); | |
1439 | ||
1440 | drm_for_each_crtc(crtc, drm_dev) { | |
1441 | if (crtc->state->active) { | |
1442 | ret = -EBUSY; | |
1443 | break; | |
1444 | } | |
d38ceaf9 | 1445 | } |
97f6a21b AG |
1446 | |
1447 | drm_modeset_unlock_all(drm_dev); | |
1448 | ||
1449 | } else { | |
1450 | struct drm_connector *list_connector; | |
1451 | struct drm_connector_list_iter iter; | |
1452 | ||
1453 | mutex_lock(&drm_dev->mode_config.mutex); | |
1454 | drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); | |
1455 | ||
1456 | drm_connector_list_iter_begin(drm_dev, &iter); | |
1457 | drm_for_each_connector_iter(list_connector, &iter) { | |
1458 | if (list_connector->dpms == DRM_MODE_DPMS_ON) { | |
1459 | ret = -EBUSY; | |
1460 | break; | |
1461 | } | |
1462 | } | |
1463 | ||
1464 | drm_connector_list_iter_end(&iter); | |
1465 | ||
1466 | drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); | |
1467 | mutex_unlock(&drm_dev->mode_config.mutex); | |
d38ceaf9 AD |
1468 | } |
1469 | ||
97f6a21b AG |
1470 | if (ret == -EBUSY) |
1471 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
1472 | ||
d38ceaf9 AD |
1473 | pm_runtime_mark_last_busy(dev); |
1474 | pm_runtime_autosuspend(dev); | |
97f6a21b | 1475 | return ret; |
d38ceaf9 AD |
1476 | } |
1477 | ||
1478 | long amdgpu_drm_ioctl(struct file *filp, | |
1479 | unsigned int cmd, unsigned long arg) | |
1480 | { | |
1481 | struct drm_file *file_priv = filp->private_data; | |
1482 | struct drm_device *dev; | |
1483 | long ret; | |
1484 | dev = file_priv->minor->dev; | |
1485 | ret = pm_runtime_get_sync(dev->dev); | |
1486 | if (ret < 0) | |
5509ac65 | 1487 | goto out; |
d38ceaf9 AD |
1488 | |
1489 | ret = drm_ioctl(filp, cmd, arg); | |
1490 | ||
1491 | pm_runtime_mark_last_busy(dev->dev); | |
5509ac65 | 1492 | out: |
d38ceaf9 AD |
1493 | pm_runtime_put_autosuspend(dev->dev); |
1494 | return ret; | |
1495 | } | |
1496 | ||
1497 | static const struct dev_pm_ops amdgpu_pm_ops = { | |
1498 | .suspend = amdgpu_pmops_suspend, | |
1499 | .resume = amdgpu_pmops_resume, | |
1500 | .freeze = amdgpu_pmops_freeze, | |
1501 | .thaw = amdgpu_pmops_thaw, | |
74b0b157 | 1502 | .poweroff = amdgpu_pmops_poweroff, |
1503 | .restore = amdgpu_pmops_restore, | |
d38ceaf9 AD |
1504 | .runtime_suspend = amdgpu_pmops_runtime_suspend, |
1505 | .runtime_resume = amdgpu_pmops_runtime_resume, | |
1506 | .runtime_idle = amdgpu_pmops_runtime_idle, | |
1507 | }; | |
1508 | ||
48ad368a AG |
1509 | static int amdgpu_flush(struct file *f, fl_owner_t id) |
1510 | { | |
1511 | struct drm_file *file_priv = f->private_data; | |
1512 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
56753e73 | 1513 | long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; |
48ad368a | 1514 | |
56753e73 CK |
1515 | timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); |
1516 | timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); | |
48ad368a | 1517 | |
56753e73 | 1518 | return timeout >= 0 ? 0 : timeout; |
48ad368a AG |
1519 | } |
1520 | ||
d38ceaf9 AD |
1521 | static const struct file_operations amdgpu_driver_kms_fops = { |
1522 | .owner = THIS_MODULE, | |
1523 | .open = drm_open, | |
48ad368a | 1524 | .flush = amdgpu_flush, |
d38ceaf9 AD |
1525 | .release = drm_release, |
1526 | .unlocked_ioctl = amdgpu_drm_ioctl, | |
1527 | .mmap = amdgpu_mmap, | |
1528 | .poll = drm_poll, | |
1529 | .read = drm_read, | |
1530 | #ifdef CONFIG_COMPAT | |
1531 | .compat_ioctl = amdgpu_kms_compat_ioctl, | |
1532 | #endif | |
1533 | }; | |
1534 | ||
021830d2 BN |
1535 | int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) |
1536 | { | |
f3729f7b | 1537 | struct drm_file *file; |
021830d2 BN |
1538 | |
1539 | if (!filp) | |
1540 | return -EINVAL; | |
1541 | ||
1542 | if (filp->f_op != &amdgpu_driver_kms_fops) { | |
1543 | return -EINVAL; | |
1544 | } | |
1545 | ||
1546 | file = filp->private_data; | |
1547 | *fpriv = file->driver_priv; | |
1548 | return 0; | |
1549 | } | |
1550 | ||
5088d657 LT |
1551 | const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { |
1552 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1553 | DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1554 | DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1555 | DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), | |
1556 | DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1557 | DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1558 | /* KMS */ | |
1559 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1560 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1561 | DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1562 | DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1563 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1564 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1565 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1566 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1567 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1568 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
1569 | }; | |
1570 | ||
1571 | static const struct drm_driver amdgpu_kms_driver = { | |
d38ceaf9 | 1572 | .driver_features = |
f3ed6739 | 1573 | DRIVER_ATOMIC | |
1ff49481 | 1574 | DRIVER_GEM | |
db4ff423 CZ |
1575 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | |
1576 | DRIVER_SYNCOBJ_TIMELINE, | |
d38ceaf9 | 1577 | .open = amdgpu_driver_open_kms, |
d38ceaf9 AD |
1578 | .postclose = amdgpu_driver_postclose_kms, |
1579 | .lastclose = amdgpu_driver_lastclose_kms, | |
d38ceaf9 AD |
1580 | .irq_handler = amdgpu_irq_handler, |
1581 | .ioctls = amdgpu_ioctls_kms, | |
5088d657 | 1582 | .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), |
d38ceaf9 AD |
1583 | .dumb_create = amdgpu_mode_dumb_create, |
1584 | .dumb_map_offset = amdgpu_mode_dumb_mmap, | |
d38ceaf9 AD |
1585 | .fops = &amdgpu_driver_kms_fops, |
1586 | ||
1587 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1588 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
09052fc3 | 1589 | .gem_prime_import = amdgpu_gem_prime_import, |
dfced2e4 | 1590 | .gem_prime_mmap = amdgpu_gem_prime_mmap, |
d38ceaf9 AD |
1591 | |
1592 | .name = DRIVER_NAME, | |
1593 | .desc = DRIVER_DESC, | |
1594 | .date = DRIVER_DATE, | |
1595 | .major = KMS_DRIVER_MAJOR, | |
1596 | .minor = KMS_DRIVER_MINOR, | |
1597 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
1598 | }; | |
1599 | ||
c9a6b82f AG |
1600 | static struct pci_error_handlers amdgpu_pci_err_handler = { |
1601 | .error_detected = amdgpu_pci_error_detected, | |
1602 | .mmio_enabled = amdgpu_pci_mmio_enabled, | |
1603 | .slot_reset = amdgpu_pci_slot_reset, | |
1604 | .resume = amdgpu_pci_resume, | |
1605 | }; | |
1606 | ||
d38ceaf9 AD |
1607 | static struct pci_driver amdgpu_kms_pci_driver = { |
1608 | .name = DRIVER_NAME, | |
1609 | .id_table = pciidlist, | |
1610 | .probe = amdgpu_pci_probe, | |
1611 | .remove = amdgpu_pci_remove, | |
61e11306 | 1612 | .shutdown = amdgpu_pci_shutdown, |
d38ceaf9 | 1613 | .driver.pm = &amdgpu_pm_ops, |
c9a6b82f | 1614 | .err_handler = &amdgpu_pci_err_handler, |
d38ceaf9 AD |
1615 | }; |
1616 | ||
1617 | static int __init amdgpu_init(void) | |
1618 | { | |
245ae5e9 CK |
1619 | int r; |
1620 | ||
c60e22f7 TI |
1621 | if (vgacon_text_force()) { |
1622 | DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); | |
1623 | return -EINVAL; | |
1624 | } | |
1625 | ||
245ae5e9 CK |
1626 | r = amdgpu_sync_init(); |
1627 | if (r) | |
1628 | goto error_sync; | |
1629 | ||
1630 | r = amdgpu_fence_slab_init(); | |
1631 | if (r) | |
1632 | goto error_fence; | |
1633 | ||
d38ceaf9 | 1634 | DRM_INFO("amdgpu kernel modesetting enabled.\n"); |
d38ceaf9 | 1635 | amdgpu_register_atpx_handler(); |
03a1c08d FK |
1636 | |
1637 | /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ | |
1638 | amdgpu_amdkfd_init(); | |
1639 | ||
d38ceaf9 | 1640 | /* let modprobe override vga console setting */ |
448d1051 | 1641 | return pci_register_driver(&amdgpu_kms_pci_driver); |
245ae5e9 | 1642 | |
245ae5e9 CK |
1643 | error_fence: |
1644 | amdgpu_sync_fini(); | |
1645 | ||
1646 | error_sync: | |
1647 | return r; | |
d38ceaf9 AD |
1648 | } |
1649 | ||
1650 | static void __exit amdgpu_exit(void) | |
1651 | { | |
130e0371 | 1652 | amdgpu_amdkfd_fini(); |
448d1051 | 1653 | pci_unregister_driver(&amdgpu_kms_pci_driver); |
d38ceaf9 | 1654 | amdgpu_unregister_atpx_handler(); |
257bf15a | 1655 | amdgpu_sync_fini(); |
d573de2d | 1656 | amdgpu_fence_slab_fini(); |
c7d8b782 | 1657 | mmu_notifier_synchronize(); |
d38ceaf9 AD |
1658 | } |
1659 | ||
1660 | module_init(amdgpu_init); | |
1661 | module_exit(amdgpu_exit); | |
1662 | ||
1663 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
1664 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1665 | MODULE_LICENSE("GPL and additional rights"); |