[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>

#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "cikd.h"
#include "amdgpu_gem.h"

#include <drm/drm_fb_helper.h>

#include <linux/vga_switcheroo.h>

#include "amdgpu_display.h"

/* object hierarchy -
   this contains a helper + a amdgpu fb
   the helper contains a pointer to amdgpu framebuffer baseclass.
*/

static int
amdgpufb_open(struct fb_info *info, int user)
{
	struct amdgpu_fbdev *rfbdev = info->par;
	struct amdgpu_device *adev = rfbdev->adev;
	int ret = pm_runtime_get_sync(adev->ddev->dev);
	if (ret < 0 && ret != -EACCES) {
		pm_runtime_mark_last_busy(adev->ddev->dev);
		pm_runtime_put_autosuspend(adev->ddev->dev);
		return ret;
	}
	return 0;
}

static int
amdgpufb_release(struct fb_info *info, int user)
{
	struct amdgpu_fbdev *rfbdev = info->par;
	struct amdgpu_device *adev = rfbdev->adev;

	pm_runtime_mark_last_busy(adev->ddev->dev);
	pm_runtime_put_autosuspend(adev->ddev->dev);
	return 0;
}

static struct fb_ops amdgpufb_ops = {
	.owner = THIS_MODULE,
	DRM_FB_HELPER_DEFAULT_OPS,
	.fb_open = amdgpufb_open,
	.fb_release = amdgpufb_release,
	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	.fb_imageblit = drm_fb_helper_cfb_imageblit,
};


int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
{
	int aligned = width;
	int pitch_mask = 0;

	switch (cpp) {
	case 1:
		pitch_mask = 255;
		break;
	case 2:
		pitch_mask = 127;
		break;
	case 3:
	case 4:
		pitch_mask = 63;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned * cpp;
}

static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
	int ret;

	ret = amdgpu_bo_reserve(abo, true);
	if (likely(ret == 0)) {
		amdgpu_bo_kunmap(abo);
		amdgpu_bo_unpin(abo);
		amdgpu_bo_unreserve(abo);
	}
	drm_gem_object_put_unlocked(gobj);
}

static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
					 struct drm_mode_fb_cmd2 *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	struct amdgpu_device *adev = rfbdev->adev;
	struct drm_gem_object *gobj = NULL;
	struct amdgpu_bo *abo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0, domain;
	int ret;
	int aligned_size, size;
	int height = mode_cmd->height;
	u32 cpp;

	cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);

	/* need to align pitch with crtc limits */
	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
						  fb_tiled);
	domain = amdgpu_display_supported_domains(adev);

	height = ALIGN(mode_cmd->height, 8);
	size = mode_cmd->pitches[0] * height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
				       AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
				       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
				       AMDGPU_GEM_CREATE_VRAM_CLEARED,
				       ttm_bo_type_kernel, NULL, &gobj);
	if (ret) {
		pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
		return -ENOMEM;
	}
	abo = gem_to_amdgpu_bo(gobj);

	if (fb_tiled)
		tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);

	ret = amdgpu_bo_reserve(abo, false);
	if (unlikely(ret != 0))
		goto out_unref;

	if (tiling_flags) {
		ret = amdgpu_bo_set_tiling_flags(abo,
						 tiling_flags);
		if (ret)
			dev_err(adev->dev, "FB failed to set tiling flags\n");
	}


	ret = amdgpu_bo_pin(abo, domain);
	if (ret) {
		amdgpu_bo_unreserve(abo);
		goto out_unref;
	}

	ret = amdgpu_ttm_alloc_gart(&abo->tbo);
	if (ret) {
		amdgpu_bo_unreserve(abo);
		dev_err(adev->dev, "%p bind failed\n", abo);
		goto out_unref;
	}

	ret = amdgpu_bo_kmap(abo, NULL);
	amdgpu_bo_unreserve(abo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	amdgpufb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int amdgpufb_create(struct drm_fb_helper *helper,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
	struct amdgpu_device *adev = rfbdev->adev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd2 mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct amdgpu_bo *abo = NULL;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	if (sizes->surface_bpp == 24)
		sizes->surface_bpp = 32;

	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
							  sizes->surface_depth);

	ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	if (ret) {
		DRM_ERROR("failed to create fbcon object %d\n", ret);
		return ret;
	}

	abo = gem_to_amdgpu_bo(gobj);

	/* okay we have an object now allocate the framebuffer */
	info = drm_fb_helper_alloc_fbi(helper);
	if (IS_ERR(info)) {
		ret = PTR_ERR(info);
		goto out;
	}

	info->par = rfbdev;
	info->skip_vt_switch = true;

	ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
					      &mode_cmd, gobj);
	if (ret) {
		DRM_ERROR("failed to initialize framebuffer %d\n", ret);
		goto out;
	}

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;

	strcpy(info->fix.id, "amdgpudrmfb");

	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);

	info->fbops = &amdgpufb_ops;

	tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
	info->fix.smem_start = adev->gmc.aper_base + tmp;
	info->fix.smem_len = amdgpu_bo_size(abo);
	info->screen_base = amdgpu_bo_kptr(abo);
	info->screen_size = amdgpu_bo_size(abo);

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
	info->apertures->ranges[0].size = adev->gmc.aper_size;

	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */

	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out;
	}

	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)adev->gmc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
	DRM_INFO("fb depth is %d\n", fb->format->depth);
	DRM_INFO("   pitch is %d\n", fb->pitches[0]);

	vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
	return 0;

out:
	if (abo) {

	}
	if (fb && ret) {
		drm_gem_object_put_unlocked(gobj);
		drm_framebuffer_unregister_private(fb);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
{
	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;

	drm_fb_helper_unregister_fbi(&rfbdev->helper);

	if (rfb->base.obj[0]) {
		amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
		rfb->base.obj[0] = NULL;
		drm_framebuffer_unregister_private(&rfb->base);
		drm_framebuffer_cleanup(&rfb->base);
	}
	drm_fb_helper_fini(&rfbdev->helper);

	return 0;
}

static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
	.fb_probe = amdgpufb_create,
};

int amdgpu_fbdev_init(struct amdgpu_device *adev)
{
	struct amdgpu_fbdev *rfbdev;
	int bpp_sel = 32;
	int ret;

	/* don't init fbdev on hw without DCE */
	if (!adev->mode_info.mode_config_initialized)
		return 0;

	/* don't init fbdev if there are no connectors */
	if (list_empty(&adev->ddev->mode_config.connector_list))
		return 0;

	/* select 8 bpp console on low vram cards */
	if (adev->gmc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->adev = adev;
	adev->mode_info.rfbdev = rfbdev;

	drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
			&amdgpu_fb_helper_funcs);

	ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
				 AMDGPUFB_CONN_LIMIT);
	if (ret) {
		kfree(rfbdev);
		return ret;
	}

	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);

	/* disable all the possible outputs/crtcs before entering KMS mode */
	if (!amdgpu_device_has_dc_support(adev))
		drm_helper_disable_unused_functions(adev->ddev);

	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	return 0;
}

void amdgpu_fbdev_fini(struct amdgpu_device *adev)
{
	if (!adev->mode_info.rfbdev)
		return;

	amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
	kfree(adev->mode_info.rfbdev);
	adev->mode_info.rfbdev = NULL;
}

void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
{
	if (adev->mode_info.rfbdev)
		drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper,
						   state);
}

int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
{
	struct amdgpu_bo *robj;
	int size = 0;

	if (!adev->mode_info.rfbdev)
		return 0;

	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
	size += amdgpu_bo_size(robj);
	return size;
}

bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
{
	if (!adev->mode_info.rfbdev)
		return false;
	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
		return true;
	return false;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
	26	#include <linux/module.h>
	27	#include <linux/slab.h>
7c1fa1db	28	#include <linux/pm_runtime.h>
d38ceaf9 AD	29
	30	#include <drm/drmP.h>
	31	#include <drm/drm_crtc.h>
	32	#include <drm/drm_crtc_helper.h>
	33	#include <drm/amdgpu_drm.h>
	34	#include "amdgpu.h"
fbd76d59	35	#include "cikd.h"
2cddc50e	36	#include "amdgpu_gem.h"
d38ceaf9 AD	37
	38	#include <drm/drm_fb_helper.h>
	39
	40	#include <linux/vga_switcheroo.h>
	41
5d43be0c CK	42	#include "amdgpu_display.h"
5d43be0c CK	43
d38ceaf9 AD	44	/* object hierarchy -
	45	this contains a helper + a amdgpu fb
	46	the helper contains a pointer to amdgpu framebuffer baseclass.
	47	*/
d38ceaf9	48
7c1fa1db AD	49	static int
	50	amdgpufb_open(struct fb_info *info, int user)
	51	{
	52	struct amdgpu_fbdev *rfbdev = info->par;
	53	struct amdgpu_device *adev = rfbdev->adev;
	54	int ret = pm_runtime_get_sync(adev->ddev->dev);
	55	if (ret < 0 && ret != -EACCES) {
	56	pm_runtime_mark_last_busy(adev->ddev->dev);
	57	pm_runtime_put_autosuspend(adev->ddev->dev);
	58	return ret;
	59	}
	60	return 0;
	61	}
	62
	63	static int
	64	amdgpufb_release(struct fb_info *info, int user)
	65	{
	66	struct amdgpu_fbdev *rfbdev = info->par;
	67	struct amdgpu_device *adev = rfbdev->adev;
	68
	69	pm_runtime_mark_last_busy(adev->ddev->dev);
	70	pm_runtime_put_autosuspend(adev->ddev->dev);
	71	return 0;
	72	}
	73
d38ceaf9 AD	74	static struct fb_ops amdgpufb_ops = {
d38ceaf9 AD	75	.owner = THIS_MODULE,
ea4ffffe	76	DRM_FB_HELPER_DEFAULT_OPS,
7c1fa1db AD	77	.fb_open = amdgpufb_open,
7c1fa1db AD	78	.fb_release = amdgpufb_release,
2dbaf392 AT	79	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	80	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	81	.fb_imageblit = drm_fb_helper_cfb_imageblit,
d38ceaf9 AD	82	};
	83
	84
8e911ab7	85	int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
d38ceaf9 AD	86	{
	87	int aligned = width;
	88	int pitch_mask = 0;
	89
8e911ab7	90	switch (cpp) {
d38ceaf9 AD	91	case 1:
	92	pitch_mask = 255;
	93	break;
	94	case 2:
	95	pitch_mask = 127;
	96	break;
	97	case 3:
	98	case 4:
	99	pitch_mask = 63;
	100	break;
	101	}
	102
	103	aligned += pitch_mask;
	104	aligned &= ~pitch_mask;
8e911ab7	105	return aligned * cpp;
d38ceaf9 AD	106	}
	107
	108	static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
	109	{
765e7fbf	110	struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	111	int ret;
d38ceaf9 AD	112
c81a1a74	113	ret = amdgpu_bo_reserve(abo, true);
d38ceaf9	114	if (likely(ret == 0)) {
765e7fbf CK	115	amdgpu_bo_kunmap(abo);
	116	amdgpu_bo_unpin(abo);
	117	amdgpu_bo_unreserve(abo);
d38ceaf9	118	}
f62facc2	119	drm_gem_object_put_unlocked(gobj);
d38ceaf9 AD	120	}
	121
	122	static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
	123	struct drm_mode_fb_cmd2 *mode_cmd,
	124	struct drm_gem_object **gobj_p)
	125	{
	126	struct amdgpu_device *adev = rfbdev->adev;
	127	struct drm_gem_object *gobj = NULL;
765e7fbf	128	struct amdgpu_bo *abo = NULL;
d38ceaf9	129	bool fb_tiled = false; /* useful for testing */
5d43be0c	130	u32 tiling_flags = 0, domain;
d38ceaf9 AD	131	int ret;
	132	int aligned_size, size;
	133	int height = mode_cmd->height;
8e911ab7	134	u32 cpp;
d38ceaf9	135
8e911ab7	136	cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
d38ceaf9 AD	137
d38ceaf9 AD	138	/* need to align pitch with crtc limits */
8e911ab7 LP	139	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
8e911ab7 LP	140	fb_tiled);
1d2361e5	141	domain = amdgpu_display_supported_domains(adev);
d38ceaf9 AD	142
	143	height = ALIGN(mode_cmd->height, 8);
	144	size = mode_cmd->pitches[0] * height;
	145	aligned_size = ALIGN(size, PAGE_SIZE);
5d43be0c	146	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
03f48dd5	147	AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
cbabc8b3 PD	148	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS \|
cbabc8b3 PD	149	AMDGPU_GEM_CREATE_VRAM_CLEARED,
f8ddb39a	150	ttm_bo_type_kernel, NULL, &gobj);
d38ceaf9	151	if (ret) {
7ca85295	152	pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
d38ceaf9 AD	153	return -ENOMEM;
d38ceaf9 AD	154	}
765e7fbf	155	abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	156
d38ceaf9 AD	157	if (fb_tiled)
fbd76d59	158	tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
d38ceaf9	159
765e7fbf	160	ret = amdgpu_bo_reserve(abo, false);
d38ceaf9 AD	161	if (unlikely(ret != 0))
	162	goto out_unref;
	163
	164	if (tiling_flags) {
765e7fbf	165	ret = amdgpu_bo_set_tiling_flags(abo,
63ab1c2b	166	tiling_flags);
d38ceaf9 AD	167	if (ret)
	168	dev_err(adev->dev, "FB failed to set tiling flags\n");
	169	}
	170
	171
7b7c6c81	172	ret = amdgpu_bo_pin(abo, domain);
d38ceaf9	173	if (ret) {
765e7fbf	174	amdgpu_bo_unreserve(abo);
d38ceaf9 AD	175	goto out_unref;
d38ceaf9 AD	176	}
bb812f1e JZ	177
	178	ret = amdgpu_ttm_alloc_gart(&abo->tbo);
	179	if (ret) {
	180	amdgpu_bo_unreserve(abo);
	181	dev_err(adev->dev, "%p bind failed\n", abo);
	182	goto out_unref;
	183	}
	184
765e7fbf CK	185	ret = amdgpu_bo_kmap(abo, NULL);
765e7fbf CK	186	amdgpu_bo_unreserve(abo);
d38ceaf9 AD	187	if (ret) {
	188	goto out_unref;
	189	}
	190
	191	*gobj_p = gobj;
	192	return 0;
	193	out_unref:
	194	amdgpufb_destroy_pinned_object(gobj);
	195	*gobj_p = NULL;
	196	return ret;
	197	}
	198
	199	static int amdgpufb_create(struct drm_fb_helper *helper,
	200	struct drm_fb_helper_surface_size *sizes)
	201	{
	202	struct amdgpu_fbdev rfbdev = (struct amdgpu_fbdev )helper;
	203	struct amdgpu_device *adev = rfbdev->adev;
	204	struct fb_info *info;
	205	struct drm_framebuffer *fb = NULL;
	206	struct drm_mode_fb_cmd2 mode_cmd;
	207	struct drm_gem_object *gobj = NULL;
765e7fbf	208	struct amdgpu_bo *abo = NULL;
d38ceaf9 AD	209	int ret;
	210	unsigned long tmp;
	211
	212	mode_cmd.width = sizes->surface_width;
	213	mode_cmd.height = sizes->surface_height;
	214
	215	if (sizes->surface_bpp == 24)
	216	sizes->surface_bpp = 32;
	217
	218	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
	219	sizes->surface_depth);
	220
	221	ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	222	if (ret) {
	223	DRM_ERROR("failed to create fbcon object %d\n", ret);
	224	return ret;
	225	}
	226
765e7fbf	227	abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	228
d38ceaf9 AD	229	/* okay we have an object now allocate the framebuffer */
2dbaf392 AT	230	info = drm_fb_helper_alloc_fbi(helper);
	231	if (IS_ERR(info)) {
	232	ret = PTR_ERR(info);
da7bdda2	233	goto out;
d38ceaf9 AD	234	}
	235
	236	info->par = rfbdev;
df7989fe	237	info->skip_vt_switch = true;
d38ceaf9	238
9da3f2d9 SL	239	ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
9da3f2d9 SL	240	&mode_cmd, gobj);
d38ceaf9 AD	241	if (ret) {
d38ceaf9 AD	242	DRM_ERROR("failed to initialize framebuffer %d\n", ret);
da7bdda2	243	goto out;
d38ceaf9 AD	244	}
	245
	246	fb = &rfbdev->rfb.base;
	247
	248	/* setup helper */
	249	rfbdev->helper.fb = fb;
d38ceaf9	250
d38ceaf9 AD	251	strcpy(info->fix.id, "amdgpudrmfb");
d38ceaf9 AD	252
b00c600e	253	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
d38ceaf9	254
d38ceaf9 AD	255	info->fbops = &amdgpufb_ops;
d38ceaf9 AD	256
770d13b1 CK	257	tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
770d13b1 CK	258	info->fix.smem_start = adev->gmc.aper_base + tmp;
765e7fbf	259	info->fix.smem_len = amdgpu_bo_size(abo);
f5e1c740	260	info->screen_base = amdgpu_bo_kptr(abo);
765e7fbf	261	info->screen_size = amdgpu_bo_size(abo);
d38ceaf9 AD	262
	263	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
	264
	265	/* setup aperture base/size for vesafb takeover */
d38ceaf9	266	info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
770d13b1	267	info->apertures->ranges[0].size = adev->gmc.aper_size;
d38ceaf9 AD	268
	269	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
	270
	271	if (info->screen_base == NULL) {
	272	ret = -ENOSPC;
da7bdda2	273	goto out;
d38ceaf9 AD	274	}
	275
	276	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
770d13b1	277	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base);
765e7fbf	278	DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
b00c600e	279	DRM_INFO("fb depth is %d\n", fb->format->depth);
d38ceaf9 AD	280	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
	281
	282	vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
	283	return 0;
	284
da7bdda2	285	out:
765e7fbf	286	if (abo) {
d38ceaf9 AD	287
	288	}
	289	if (fb && ret) {
f62facc2	290	drm_gem_object_put_unlocked(gobj);
d38ceaf9 AD	291	drm_framebuffer_unregister_private(fb);
	292	drm_framebuffer_cleanup(fb);
	293	kfree(fb);
	294	}
	295	return ret;
	296	}
	297
d38ceaf9 AD	298	static int amdgpu_fbdev_destroy(struct drm_device dev, struct amdgpu_fbdev rfbdev)
d38ceaf9 AD	299	{
d38ceaf9 AD	300	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
d38ceaf9 AD	301
2dbaf392	302	drm_fb_helper_unregister_fbi(&rfbdev->helper);
d38ceaf9	303
e68d14dd DS	304	if (rfb->base.obj[0]) {
	305	amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
	306	rfb->base.obj[0] = NULL;
a072c5f8 MD	307	drm_framebuffer_unregister_private(&rfb->base);
a072c5f8 MD	308	drm_framebuffer_cleanup(&rfb->base);
d38ceaf9 AD	309	}
d38ceaf9 AD	310	drm_fb_helper_fini(&rfbdev->helper);
d38ceaf9 AD	311
	312	return 0;
	313	}
	314
d38ceaf9	315	static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
d38ceaf9 AD	316	.fb_probe = amdgpufb_create,
	317	};
	318
	319	int amdgpu_fbdev_init(struct amdgpu_device *adev)
	320	{
	321	struct amdgpu_fbdev *rfbdev;
	322	int bpp_sel = 32;
	323	int ret;
	324
	325	/* don't init fbdev on hw without DCE */
	326	if (!adev->mode_info.mode_config_initialized)
	327	return 0;
	328
f49d45c9 AD	329	/* don't init fbdev if there are no connectors */
	330	if (list_empty(&adev->ddev->mode_config.connector_list))
	331	return 0;
	332
d38ceaf9	333	/* select 8 bpp console on low vram cards */
770d13b1	334	if (adev->gmc.real_vram_size <= (3210241024))
d38ceaf9 AD	335	bpp_sel = 8;
	336
	337	rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
	338	if (!rfbdev)
	339	return -ENOMEM;
	340
	341	rfbdev->adev = adev;
	342	adev->mode_info.rfbdev = rfbdev;
	343
	344	drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
	345	&amdgpu_fb_helper_funcs);
	346
	347	ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
d38ceaf9 AD	348	AMDGPUFB_CONN_LIMIT);
	349	if (ret) {
	350	kfree(rfbdev);
	351	return ret;
	352	}
	353
	354	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	355
	356	/* disable all the possible outputs/crtcs before entering KMS mode */
93b8ca9b AG	357	if (!amdgpu_device_has_dc_support(adev))
93b8ca9b AG	358	drm_helper_disable_unused_functions(adev->ddev);
d38ceaf9 AD	359
	360	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	361	return 0;
	362	}
	363
	364	void amdgpu_fbdev_fini(struct amdgpu_device *adev)
	365	{
	366	if (!adev->mode_info.rfbdev)
	367	return;
	368
	369	amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
	370	kfree(adev->mode_info.rfbdev);
	371	adev->mode_info.rfbdev = NULL;
	372	}
	373
	374	void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
	375	{
	376	if (adev->mode_info.rfbdev)
ecb8c503 S	377	drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper,
ecb8c503 S	378	state);
d38ceaf9 AD	379	}
	380
	381	int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
	382	{
	383	struct amdgpu_bo *robj;
	384	int size = 0;
	385
	386	if (!adev->mode_info.rfbdev)
	387	return 0;
	388
e68d14dd	389	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
d38ceaf9 AD	390	size += amdgpu_bo_size(robj);
	391	return size;
	392	}
	393
	394	bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device adev, struct amdgpu_bo robj)
	395	{
	396	if (!adev->mode_info.rfbdev)
	397	return false;
e68d14dd	398	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
d38ceaf9 AD	399	return true;
	400	return false;
	401	}