[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>

#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "cikd.h"

#include <drm/drm_fb_helper.h>

#include <linux/vga_switcheroo.h>

/* object hierarchy -
   this contains a helper + a amdgpu fb
   the helper contains a pointer to amdgpu framebuffer baseclass.
*/

static int
amdgpufb_open(struct fb_info *info, int user)
{
	struct amdgpu_fbdev *rfbdev = info->par;
	struct amdgpu_device *adev = rfbdev->adev;
	int ret = pm_runtime_get_sync(adev->ddev->dev);
	if (ret < 0 && ret != -EACCES) {
		pm_runtime_mark_last_busy(adev->ddev->dev);
		pm_runtime_put_autosuspend(adev->ddev->dev);
		return ret;
	}
	return 0;
}

static int
amdgpufb_release(struct fb_info *info, int user)
{
	struct amdgpu_fbdev *rfbdev = info->par;
	struct amdgpu_device *adev = rfbdev->adev;

	pm_runtime_mark_last_busy(adev->ddev->dev);
	pm_runtime_put_autosuspend(adev->ddev->dev);
	return 0;
}

static struct fb_ops amdgpufb_ops = {
	.owner = THIS_MODULE,
	DRM_FB_HELPER_DEFAULT_OPS,
	.fb_open = amdgpufb_open,
	.fb_release = amdgpufb_release,
	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	.fb_imageblit = drm_fb_helper_cfb_imageblit,
};


int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
{
	int aligned = width;
	int pitch_mask = 0;

	switch (cpp) {
	case 1:
		pitch_mask = 255;
		break;
	case 2:
		pitch_mask = 127;
		break;
	case 3:
	case 4:
		pitch_mask = 63;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned * cpp;
}

static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
	int ret;

	ret = amdgpu_bo_reserve(abo, true);
	if (likely(ret == 0)) {
		amdgpu_bo_kunmap(abo);
		amdgpu_bo_unpin(abo);
		amdgpu_bo_unreserve(abo);
	}
	drm_gem_object_put_unlocked(gobj);
}

static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
					 struct drm_mode_fb_cmd2 *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	struct amdgpu_device *adev = rfbdev->adev;
	struct drm_gem_object *gobj = NULL;
	struct amdgpu_bo *abo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;
	int ret;
	int aligned_size, size;
	int height = mode_cmd->height;
	u32 cpp;

	cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);

	/* need to align pitch with crtc limits */
	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
						  fb_tiled);

	height = ALIGN(mode_cmd->height, 8);
	size = mode_cmd->pitches[0] * height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = amdgpu_gem_object_create(adev, aligned_size, 0,
				       AMDGPU_GEM_DOMAIN_VRAM,
				       AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
				       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
				       AMDGPU_GEM_CREATE_VRAM_CLEARED,
				       true, NULL, &gobj);
	if (ret) {
		pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
		return -ENOMEM;
	}
	abo = gem_to_amdgpu_bo(gobj);

	if (fb_tiled)
		tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);

	ret = amdgpu_bo_reserve(abo, false);
	if (unlikely(ret != 0))
		goto out_unref;

	if (tiling_flags) {
		ret = amdgpu_bo_set_tiling_flags(abo,
						 tiling_flags);
		if (ret)
			dev_err(adev->dev, "FB failed to set tiling flags\n");
	}


	ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
	if (ret) {
		amdgpu_bo_unreserve(abo);
		goto out_unref;
	}
	ret = amdgpu_bo_kmap(abo, NULL);
	amdgpu_bo_unreserve(abo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	amdgpufb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int amdgpufb_create(struct drm_fb_helper *helper,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
	struct amdgpu_device *adev = rfbdev->adev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd2 mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct amdgpu_bo *abo = NULL;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	if (sizes->surface_bpp == 24)
		sizes->surface_bpp = 32;

	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
							  sizes->surface_depth);

	ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	if (ret) {
		DRM_ERROR("failed to create fbcon object %d\n", ret);
		return ret;
	}

	abo = gem_to_amdgpu_bo(gobj);

	/* okay we have an object now allocate the framebuffer */
	info = drm_fb_helper_alloc_fbi(helper);
	if (IS_ERR(info)) {
		ret = PTR_ERR(info);
		goto out;
	}

	info->par = rfbdev;
	info->skip_vt_switch = true;

	ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
	if (ret) {
		DRM_ERROR("failed to initialize framebuffer %d\n", ret);
		goto out;
	}

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;

	strcpy(info->fix.id, "amdgpudrmfb");

	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);

	info->fbops = &amdgpufb_ops;

	tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start;
	info->fix.smem_start = adev->mc.aper_base + tmp;
	info->fix.smem_len = amdgpu_bo_size(abo);
	info->screen_base = amdgpu_bo_kptr(abo);
	info->screen_size = amdgpu_bo_size(abo);

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
	info->apertures->ranges[0].size = adev->mc.aper_size;

	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */

	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out;
	}

	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)adev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
	DRM_INFO("fb depth is %d\n", fb->format->depth);
	DRM_INFO("   pitch is %d\n", fb->pitches[0]);

	vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
	return 0;

out:
	if (abo) {

	}
	if (fb && ret) {
		drm_gem_object_put_unlocked(gobj);
		drm_framebuffer_unregister_private(fb);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
{
	if (adev->mode_info.rfbdev)
		drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
}

static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
{
	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;

	drm_fb_helper_unregister_fbi(&rfbdev->helper);

	if (rfb->obj) {
		amdgpufb_destroy_pinned_object(rfb->obj);
		rfb->obj = NULL;
		drm_framebuffer_unregister_private(&rfb->base);
		drm_framebuffer_cleanup(&rfb->base);
	}
	drm_fb_helper_fini(&rfbdev->helper);

	return 0;
}

static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
	.fb_probe = amdgpufb_create,
};

int amdgpu_fbdev_init(struct amdgpu_device *adev)
{
	struct amdgpu_fbdev *rfbdev;
	int bpp_sel = 32;
	int ret;

	/* don't init fbdev on hw without DCE */
	if (!adev->mode_info.mode_config_initialized)
		return 0;

	/* don't init fbdev if there are no connectors */
	if (list_empty(&adev->ddev->mode_config.connector_list))
		return 0;

	/* select 8 bpp console on low vram cards */
	if (adev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->adev = adev;
	adev->mode_info.rfbdev = rfbdev;

	drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
			&amdgpu_fb_helper_funcs);

	ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
				 AMDGPUFB_CONN_LIMIT);
	if (ret) {
		kfree(rfbdev);
		return ret;
	}

	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);

	/* disable all the possible outputs/crtcs before entering KMS mode */
	drm_helper_disable_unused_functions(adev->ddev);

	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	return 0;
}

void amdgpu_fbdev_fini(struct amdgpu_device *adev)
{
	if (!adev->mode_info.rfbdev)
		return;

	amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
	kfree(adev->mode_info.rfbdev);
	adev->mode_info.rfbdev = NULL;
}

void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
{
	if (adev->mode_info.rfbdev)
		drm_fb_helper_set_suspend(&adev->mode_info.rfbdev->helper,
			state);
}

int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
{
	struct amdgpu_bo *robj;
	int size = 0;

	if (!adev->mode_info.rfbdev)
		return 0;

	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
	size += amdgpu_bo_size(robj);
	return size;
}

bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
{
	if (!adev->mode_info.rfbdev)
		return false;
	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
		return true;
	return false;
}

void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
{
	struct amdgpu_fbdev *afbdev;
	struct drm_fb_helper *fb_helper;
	int ret;

	if (!adev)
		return;

	afbdev = adev->mode_info.rfbdev;

	if (!afbdev)
		return;

	fb_helper = &afbdev->helper;

	ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
	if (ret)
		DRM_DEBUG("failed to restore crtc mode\n");
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
	26	#include <linux/module.h>
	27	#include <linux/slab.h>
7c1fa1db	28	#include <linux/pm_runtime.h>
d38ceaf9 AD	29
	30	#include <drm/drmP.h>
	31	#include <drm/drm_crtc.h>
	32	#include <drm/drm_crtc_helper.h>
	33	#include <drm/amdgpu_drm.h>
	34	#include "amdgpu.h"
fbd76d59	35	#include "cikd.h"
d38ceaf9 AD	36
	37	#include <drm/drm_fb_helper.h>
	38
	39	#include <linux/vga_switcheroo.h>
	40
	41	/* object hierarchy -
	42	this contains a helper + a amdgpu fb
	43	the helper contains a pointer to amdgpu framebuffer baseclass.
	44	*/
d38ceaf9	45
7c1fa1db AD	46	static int
	47	amdgpufb_open(struct fb_info *info, int user)
	48	{
	49	struct amdgpu_fbdev *rfbdev = info->par;
	50	struct amdgpu_device *adev = rfbdev->adev;
	51	int ret = pm_runtime_get_sync(adev->ddev->dev);
	52	if (ret < 0 && ret != -EACCES) {
	53	pm_runtime_mark_last_busy(adev->ddev->dev);
	54	pm_runtime_put_autosuspend(adev->ddev->dev);
	55	return ret;
	56	}
	57	return 0;
	58	}
	59
	60	static int
	61	amdgpufb_release(struct fb_info *info, int user)
	62	{
	63	struct amdgpu_fbdev *rfbdev = info->par;
	64	struct amdgpu_device *adev = rfbdev->adev;
	65
	66	pm_runtime_mark_last_busy(adev->ddev->dev);
	67	pm_runtime_put_autosuspend(adev->ddev->dev);
	68	return 0;
	69	}
	70
d38ceaf9 AD	71	static struct fb_ops amdgpufb_ops = {
d38ceaf9 AD	72	.owner = THIS_MODULE,
ea4ffffe	73	DRM_FB_HELPER_DEFAULT_OPS,
7c1fa1db AD	74	.fb_open = amdgpufb_open,
7c1fa1db AD	75	.fb_release = amdgpufb_release,
2dbaf392 AT	76	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	77	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	78	.fb_imageblit = drm_fb_helper_cfb_imageblit,
d38ceaf9 AD	79	};
	80
	81
8e911ab7	82	int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
d38ceaf9 AD	83	{
	84	int aligned = width;
	85	int pitch_mask = 0;
	86
8e911ab7	87	switch (cpp) {
d38ceaf9 AD	88	case 1:
	89	pitch_mask = 255;
	90	break;
	91	case 2:
	92	pitch_mask = 127;
	93	break;
	94	case 3:
	95	case 4:
	96	pitch_mask = 63;
	97	break;
	98	}
	99
	100	aligned += pitch_mask;
	101	aligned &= ~pitch_mask;
8e911ab7	102	return aligned * cpp;
d38ceaf9 AD	103	}
	104
	105	static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
	106	{
765e7fbf	107	struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	108	int ret;
d38ceaf9 AD	109
c81a1a74	110	ret = amdgpu_bo_reserve(abo, true);
d38ceaf9	111	if (likely(ret == 0)) {
765e7fbf CK	112	amdgpu_bo_kunmap(abo);
	113	amdgpu_bo_unpin(abo);
	114	amdgpu_bo_unreserve(abo);
d38ceaf9	115	}
f62facc2	116	drm_gem_object_put_unlocked(gobj);
d38ceaf9 AD	117	}
	118
	119	static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
	120	struct drm_mode_fb_cmd2 *mode_cmd,
	121	struct drm_gem_object **gobj_p)
	122	{
	123	struct amdgpu_device *adev = rfbdev->adev;
	124	struct drm_gem_object *gobj = NULL;
765e7fbf	125	struct amdgpu_bo *abo = NULL;
d38ceaf9 AD	126	bool fb_tiled = false; /* useful for testing */
	127	u32 tiling_flags = 0;
	128	int ret;
	129	int aligned_size, size;
	130	int height = mode_cmd->height;
8e911ab7	131	u32 cpp;
d38ceaf9	132
8e911ab7	133	cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
d38ceaf9 AD	134
d38ceaf9 AD	135	/* need to align pitch with crtc limits */
8e911ab7 LP	136	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
8e911ab7 LP	137	fb_tiled);
d38ceaf9 AD	138
	139	height = ALIGN(mode_cmd->height, 8);
	140	size = mode_cmd->pitches[0] * height;
	141	aligned_size = ALIGN(size, PAGE_SIZE);
	142	ret = amdgpu_gem_object_create(adev, aligned_size, 0,
	143	AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5	144	AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
cbabc8b3 PD	145	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS \|
cbabc8b3 PD	146	AMDGPU_GEM_CREATE_VRAM_CLEARED,
e1eb899b	147	true, NULL, &gobj);
d38ceaf9	148	if (ret) {
7ca85295	149	pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
d38ceaf9 AD	150	return -ENOMEM;
d38ceaf9 AD	151	}
765e7fbf	152	abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	153
d38ceaf9 AD	154	if (fb_tiled)
fbd76d59	155	tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
d38ceaf9	156
765e7fbf	157	ret = amdgpu_bo_reserve(abo, false);
d38ceaf9 AD	158	if (unlikely(ret != 0))
	159	goto out_unref;
	160
	161	if (tiling_flags) {
765e7fbf	162	ret = amdgpu_bo_set_tiling_flags(abo,
63ab1c2b	163	tiling_flags);
d38ceaf9 AD	164	if (ret)
	165	dev_err(adev->dev, "FB failed to set tiling flags\n");
	166	}
	167
	168
7fe28576	169	ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
d38ceaf9	170	if (ret) {
765e7fbf	171	amdgpu_bo_unreserve(abo);
d38ceaf9 AD	172	goto out_unref;
d38ceaf9 AD	173	}
765e7fbf CK	174	ret = amdgpu_bo_kmap(abo, NULL);
765e7fbf CK	175	amdgpu_bo_unreserve(abo);
d38ceaf9 AD	176	if (ret) {
	177	goto out_unref;
	178	}
	179
	180	*gobj_p = gobj;
	181	return 0;
	182	out_unref:
	183	amdgpufb_destroy_pinned_object(gobj);
	184	*gobj_p = NULL;
	185	return ret;
	186	}
	187
	188	static int amdgpufb_create(struct drm_fb_helper *helper,
	189	struct drm_fb_helper_surface_size *sizes)
	190	{
	191	struct amdgpu_fbdev rfbdev = (struct amdgpu_fbdev )helper;
	192	struct amdgpu_device *adev = rfbdev->adev;
	193	struct fb_info *info;
	194	struct drm_framebuffer *fb = NULL;
	195	struct drm_mode_fb_cmd2 mode_cmd;
	196	struct drm_gem_object *gobj = NULL;
765e7fbf	197	struct amdgpu_bo *abo = NULL;
d38ceaf9 AD	198	int ret;
	199	unsigned long tmp;
	200
	201	mode_cmd.width = sizes->surface_width;
	202	mode_cmd.height = sizes->surface_height;
	203
	204	if (sizes->surface_bpp == 24)
	205	sizes->surface_bpp = 32;
	206
	207	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
	208	sizes->surface_depth);
	209
	210	ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	211	if (ret) {
	212	DRM_ERROR("failed to create fbcon object %d\n", ret);
	213	return ret;
	214	}
	215
765e7fbf	216	abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	217
d38ceaf9 AD	218	/* okay we have an object now allocate the framebuffer */
2dbaf392 AT	219	info = drm_fb_helper_alloc_fbi(helper);
	220	if (IS_ERR(info)) {
	221	ret = PTR_ERR(info);
da7bdda2	222	goto out;
d38ceaf9 AD	223	}
	224
	225	info->par = rfbdev;
df7989fe	226	info->skip_vt_switch = true;
d38ceaf9 AD	227
	228	ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
	229	if (ret) {
	230	DRM_ERROR("failed to initialize framebuffer %d\n", ret);
da7bdda2	231	goto out;
d38ceaf9 AD	232	}
	233
	234	fb = &rfbdev->rfb.base;
	235
	236	/* setup helper */
	237	rfbdev->helper.fb = fb;
d38ceaf9	238
d38ceaf9 AD	239	strcpy(info->fix.id, "amdgpudrmfb");
d38ceaf9 AD	240
b00c600e	241	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
d38ceaf9	242
d38ceaf9 AD	243	info->fbops = &amdgpufb_ops;
d38ceaf9 AD	244
765e7fbf	245	tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start;
d38ceaf9	246	info->fix.smem_start = adev->mc.aper_base + tmp;
765e7fbf	247	info->fix.smem_len = amdgpu_bo_size(abo);
f5e1c740	248	info->screen_base = amdgpu_bo_kptr(abo);
765e7fbf	249	info->screen_size = amdgpu_bo_size(abo);
d38ceaf9 AD	250
	251	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
	252
	253	/* setup aperture base/size for vesafb takeover */
d38ceaf9 AD	254	info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
	255	info->apertures->ranges[0].size = adev->mc.aper_size;
	256
	257	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
	258
	259	if (info->screen_base == NULL) {
	260	ret = -ENOSPC;
da7bdda2	261	goto out;
d38ceaf9 AD	262	}
	263
	264	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
	265	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base);
765e7fbf	266	DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
b00c600e	267	DRM_INFO("fb depth is %d\n", fb->format->depth);
d38ceaf9 AD	268	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
	269
	270	vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
	271	return 0;
	272
da7bdda2	273	out:
765e7fbf	274	if (abo) {
d38ceaf9 AD	275
	276	}
	277	if (fb && ret) {
f62facc2	278	drm_gem_object_put_unlocked(gobj);
d38ceaf9 AD	279	drm_framebuffer_unregister_private(fb);
	280	drm_framebuffer_cleanup(fb);
	281	kfree(fb);
	282	}
	283	return ret;
	284	}
	285
	286	void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
	287	{
	288	if (adev->mode_info.rfbdev)
	289	drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
	290	}
	291
	292	static int amdgpu_fbdev_destroy(struct drm_device dev, struct amdgpu_fbdev rfbdev)
	293	{
d38ceaf9 AD	294	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
d38ceaf9 AD	295
2dbaf392	296	drm_fb_helper_unregister_fbi(&rfbdev->helper);
d38ceaf9 AD	297
	298	if (rfb->obj) {
	299	amdgpufb_destroy_pinned_object(rfb->obj);
	300	rfb->obj = NULL;
a072c5f8 MD	301	drm_framebuffer_unregister_private(&rfb->base);
a072c5f8 MD	302	drm_framebuffer_cleanup(&rfb->base);
d38ceaf9 AD	303	}
d38ceaf9 AD	304	drm_fb_helper_fini(&rfbdev->helper);
d38ceaf9 AD	305
	306	return 0;
	307	}
	308
d38ceaf9	309	static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
d38ceaf9 AD	310	.fb_probe = amdgpufb_create,
	311	};
	312
	313	int amdgpu_fbdev_init(struct amdgpu_device *adev)
	314	{
	315	struct amdgpu_fbdev *rfbdev;
	316	int bpp_sel = 32;
	317	int ret;
	318
	319	/* don't init fbdev on hw without DCE */
	320	if (!adev->mode_info.mode_config_initialized)
	321	return 0;
	322
f49d45c9 AD	323	/* don't init fbdev if there are no connectors */
	324	if (list_empty(&adev->ddev->mode_config.connector_list))
	325	return 0;
	326
d38ceaf9 AD	327	/* select 8 bpp console on low vram cards */
	328	if (adev->mc.real_vram_size <= (3210241024))
	329	bpp_sel = 8;
	330
	331	rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
	332	if (!rfbdev)
	333	return -ENOMEM;
	334
	335	rfbdev->adev = adev;
	336	adev->mode_info.rfbdev = rfbdev;
	337
	338	drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
	339	&amdgpu_fb_helper_funcs);
	340
	341	ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
d38ceaf9 AD	342	AMDGPUFB_CONN_LIMIT);
	343	if (ret) {
	344	kfree(rfbdev);
	345	return ret;
	346	}
	347
	348	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	349
	350	/* disable all the possible outputs/crtcs before entering KMS mode */
	351	drm_helper_disable_unused_functions(adev->ddev);
	352
	353	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	354	return 0;
	355	}
	356
	357	void amdgpu_fbdev_fini(struct amdgpu_device *adev)
	358	{
	359	if (!adev->mode_info.rfbdev)
	360	return;
	361
	362	amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
	363	kfree(adev->mode_info.rfbdev);
	364	adev->mode_info.rfbdev = NULL;
	365	}
	366
	367	void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
	368	{
	369	if (adev->mode_info.rfbdev)
2dbaf392 AT	370	drm_fb_helper_set_suspend(&adev->mode_info.rfbdev->helper,
2dbaf392 AT	371	state);
d38ceaf9 AD	372	}
	373
	374	int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
	375	{
	376	struct amdgpu_bo *robj;
	377	int size = 0;
	378
	379	if (!adev->mode_info.rfbdev)
	380	return 0;
	381
	382	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
	383	size += amdgpu_bo_size(robj);
	384	return size;
	385	}
	386
	387	bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device adev, struct amdgpu_bo robj)
	388	{
	389	if (!adev->mode_info.rfbdev)
	390	return false;
	391	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
	392	return true;
	393	return false;
	394	}
8b7530b1 AD	395
	396	void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
	397	{
b62ce397	398	struct amdgpu_fbdev *afbdev;
8b7530b1 AD	399	struct drm_fb_helper *fb_helper;
	400	int ret;
	401
b62ce397 RZ	402	if (!adev)
	403	return;
	404
	405	afbdev = adev->mode_info.rfbdev;
	406
8b7530b1 AD	407	if (!afbdev)
	408	return;
	409
	410	fb_helper = &afbdev->helper;
	411
	412	ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
	413	if (ret)
	414	DRM_DEBUG("failed to restore crtc mode\n");
	415	}