[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>

#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "cikd.h"

#include <drm/drm_fb_helper.h>

#include <linux/vga_switcheroo.h>

/* object hierarchy -
   this contains a helper + a amdgpu fb
   the helper contains a pointer to amdgpu framebuffer baseclass.
*/
struct amdgpu_fbdev {
	struct drm_fb_helper helper;
	struct amdgpu_framebuffer rfb;
	struct amdgpu_device *adev;
};

static int
amdgpufb_open(struct fb_info *info, int user)
{
	struct amdgpu_fbdev *rfbdev = info->par;
	struct amdgpu_device *adev = rfbdev->adev;
	int ret = pm_runtime_get_sync(adev->ddev->dev);
	if (ret < 0 && ret != -EACCES) {
		pm_runtime_mark_last_busy(adev->ddev->dev);
		pm_runtime_put_autosuspend(adev->ddev->dev);
		return ret;
	}
	return 0;
}

static int
amdgpufb_release(struct fb_info *info, int user)
{
	struct amdgpu_fbdev *rfbdev = info->par;
	struct amdgpu_device *adev = rfbdev->adev;

	pm_runtime_mark_last_busy(adev->ddev->dev);
	pm_runtime_put_autosuspend(adev->ddev->dev);
	return 0;
}

static struct fb_ops amdgpufb_ops = {
	.owner = THIS_MODULE,
	DRM_FB_HELPER_DEFAULT_OPS,
	.fb_open = amdgpufb_open,
	.fb_release = amdgpufb_release,
	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	.fb_imageblit = drm_fb_helper_cfb_imageblit,
};


int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
{
	int aligned = width;
	int pitch_mask = 0;

	switch (cpp) {
	case 1:
		pitch_mask = 255;
		break;
	case 2:
		pitch_mask = 127;
		break;
	case 3:
	case 4:
		pitch_mask = 63;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned * cpp;
}

static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
	int ret;

	ret = amdgpu_bo_reserve(abo, true);
	if (likely(ret == 0)) {
		amdgpu_bo_kunmap(abo);
		amdgpu_bo_unpin(abo);
		amdgpu_bo_unreserve(abo);
	}
	drm_gem_object_unreference_unlocked(gobj);
}

static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
					 struct drm_mode_fb_cmd2 *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	struct amdgpu_device *adev = rfbdev->adev;
	struct drm_gem_object *gobj = NULL;
	struct amdgpu_bo *abo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;
	int ret;
	int aligned_size, size;
	int height = mode_cmd->height;
	u32 cpp;

	cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);

	/* need to align pitch with crtc limits */
	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
						  fb_tiled);

	height = ALIGN(mode_cmd->height, 8);
	size = mode_cmd->pitches[0] * height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = amdgpu_gem_object_create(adev, aligned_size, 0,
				       AMDGPU_GEM_DOMAIN_VRAM,
				       AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
				       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
				       AMDGPU_GEM_CREATE_VRAM_CLEARED,
				       true, &gobj);
	if (ret) {
		pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
		return -ENOMEM;
	}
	abo = gem_to_amdgpu_bo(gobj);

	if (fb_tiled)
		tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);

	ret = amdgpu_bo_reserve(abo, false);
	if (unlikely(ret != 0))
		goto out_unref;

	if (tiling_flags) {
		ret = amdgpu_bo_set_tiling_flags(abo,
						 tiling_flags);
		if (ret)
			dev_err(adev->dev, "FB failed to set tiling flags\n");
	}


	ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
	if (ret) {
		amdgpu_bo_unreserve(abo);
		goto out_unref;
	}
	ret = amdgpu_bo_kmap(abo, NULL);
	amdgpu_bo_unreserve(abo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	amdgpufb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int amdgpufb_create(struct drm_fb_helper *helper,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
	struct amdgpu_device *adev = rfbdev->adev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd2 mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct amdgpu_bo *abo = NULL;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	if (sizes->surface_bpp == 24)
		sizes->surface_bpp = 32;

	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
							  sizes->surface_depth);

	ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	if (ret) {
		DRM_ERROR("failed to create fbcon object %d\n", ret);
		return ret;
	}

	abo = gem_to_amdgpu_bo(gobj);

	/* okay we have an object now allocate the framebuffer */
	info = drm_fb_helper_alloc_fbi(helper);
	if (IS_ERR(info)) {
		ret = PTR_ERR(info);
		goto out;
	}

	info->par = rfbdev;
	info->skip_vt_switch = true;

	ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
	if (ret) {
		DRM_ERROR("failed to initialize framebuffer %d\n", ret);
		goto out;
	}

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;

	strcpy(info->fix.id, "amdgpudrmfb");

	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);

	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
	info->fbops = &amdgpufb_ops;

	tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start;
	info->fix.smem_start = adev->mc.aper_base + tmp;
	info->fix.smem_len = amdgpu_bo_size(abo);
	info->screen_base = abo->kptr;
	info->screen_size = amdgpu_bo_size(abo);

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
	info->apertures->ranges[0].size = adev->mc.aper_size;

	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */

	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out;
	}

	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)adev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
	DRM_INFO("fb depth is %d\n", fb->format->depth);
	DRM_INFO("   pitch is %d\n", fb->pitches[0]);

	vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
	return 0;

out:
	if (abo) {

	}
	if (fb && ret) {
		drm_gem_object_unreference_unlocked(gobj);
		drm_framebuffer_unregister_private(fb);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
{
	if (adev->mode_info.rfbdev)
		drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
}

static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
{
	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;

	drm_fb_helper_unregister_fbi(&rfbdev->helper);

	if (rfb->obj) {
		amdgpufb_destroy_pinned_object(rfb->obj);
		rfb->obj = NULL;
	}
	drm_fb_helper_fini(&rfbdev->helper);
	drm_framebuffer_unregister_private(&rfb->base);
	drm_framebuffer_cleanup(&rfb->base);

	return 0;
}

/** Sets the color ramps on behalf of fbcon */
static void amdgpu_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				      u16 blue, int regno)
{
	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	amdgpu_crtc->lut_r[regno] = red >> 6;
	amdgpu_crtc->lut_g[regno] = green >> 6;
	amdgpu_crtc->lut_b[regno] = blue >> 6;
}

/** Gets the color ramps on behalf of fbcon */
static void amdgpu_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
				      u16 *blue, int regno)
{
	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	*red = amdgpu_crtc->lut_r[regno] << 6;
	*green = amdgpu_crtc->lut_g[regno] << 6;
	*blue = amdgpu_crtc->lut_b[regno] << 6;
}

static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
	.gamma_set = amdgpu_crtc_fb_gamma_set,
	.gamma_get = amdgpu_crtc_fb_gamma_get,
	.fb_probe = amdgpufb_create,
};

int amdgpu_fbdev_init(struct amdgpu_device *adev)
{
	struct amdgpu_fbdev *rfbdev;
	int bpp_sel = 32;
	int ret;

	/* don't init fbdev on hw without DCE */
	if (!adev->mode_info.mode_config_initialized)
		return 0;

	/* don't init fbdev if there are no connectors */
	if (list_empty(&adev->ddev->mode_config.connector_list))
		return 0;

	/* select 8 bpp console on low vram cards */
	if (adev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->adev = adev;
	adev->mode_info.rfbdev = rfbdev;

	drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
			&amdgpu_fb_helper_funcs);

	ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
				 AMDGPUFB_CONN_LIMIT);
	if (ret) {
		kfree(rfbdev);
		return ret;
	}

	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);

	/* disable all the possible outputs/crtcs before entering KMS mode */
	drm_helper_disable_unused_functions(adev->ddev);

	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	return 0;
}

void amdgpu_fbdev_fini(struct amdgpu_device *adev)
{
	if (!adev->mode_info.rfbdev)
		return;

	amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
	kfree(adev->mode_info.rfbdev);
	adev->mode_info.rfbdev = NULL;
}

void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
{
	if (adev->mode_info.rfbdev)
		drm_fb_helper_set_suspend(&adev->mode_info.rfbdev->helper,
			state);
}

int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
{
	struct amdgpu_bo *robj;
	int size = 0;

	if (!adev->mode_info.rfbdev)
		return 0;

	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
	size += amdgpu_bo_size(robj);
	return size;
}

bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
{
	if (!adev->mode_info.rfbdev)
		return false;
	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
		return true;
	return false;
}

void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
{
	struct amdgpu_fbdev *afbdev;
	struct drm_fb_helper *fb_helper;
	int ret;

	if (!adev)
		return;

	afbdev = adev->mode_info.rfbdev;

	if (!afbdev)
		return;

	fb_helper = &afbdev->helper;

	ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
	if (ret)
		DRM_DEBUG("failed to restore crtc mode\n");
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
	26	#include <linux/module.h>
	27	#include <linux/slab.h>
7c1fa1db	28	#include <linux/pm_runtime.h>
d38ceaf9 AD	29
	30	#include <drm/drmP.h>
	31	#include <drm/drm_crtc.h>
	32	#include <drm/drm_crtc_helper.h>
	33	#include <drm/amdgpu_drm.h>
	34	#include "amdgpu.h"
fbd76d59	35	#include "cikd.h"
d38ceaf9 AD	36
	37	#include <drm/drm_fb_helper.h>
	38
	39	#include <linux/vga_switcheroo.h>
	40
	41	/* object hierarchy -
	42	this contains a helper + a amdgpu fb
	43	the helper contains a pointer to amdgpu framebuffer baseclass.
	44	*/
	45	struct amdgpu_fbdev {
	46	struct drm_fb_helper helper;
	47	struct amdgpu_framebuffer rfb;
d38ceaf9 AD	48	struct amdgpu_device *adev;
	49	};
	50
7c1fa1db AD	51	static int
	52	amdgpufb_open(struct fb_info *info, int user)
	53	{
	54	struct amdgpu_fbdev *rfbdev = info->par;
	55	struct amdgpu_device *adev = rfbdev->adev;
	56	int ret = pm_runtime_get_sync(adev->ddev->dev);
	57	if (ret < 0 && ret != -EACCES) {
	58	pm_runtime_mark_last_busy(adev->ddev->dev);
	59	pm_runtime_put_autosuspend(adev->ddev->dev);
	60	return ret;
	61	}
	62	return 0;
	63	}
	64
	65	static int
	66	amdgpufb_release(struct fb_info *info, int user)
	67	{
	68	struct amdgpu_fbdev *rfbdev = info->par;
	69	struct amdgpu_device *adev = rfbdev->adev;
	70
	71	pm_runtime_mark_last_busy(adev->ddev->dev);
	72	pm_runtime_put_autosuspend(adev->ddev->dev);
	73	return 0;
	74	}
	75
d38ceaf9 AD	76	static struct fb_ops amdgpufb_ops = {
d38ceaf9 AD	77	.owner = THIS_MODULE,
ea4ffffe	78	DRM_FB_HELPER_DEFAULT_OPS,
7c1fa1db AD	79	.fb_open = amdgpufb_open,
7c1fa1db AD	80	.fb_release = amdgpufb_release,
2dbaf392 AT	81	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	82	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	83	.fb_imageblit = drm_fb_helper_cfb_imageblit,
d38ceaf9 AD	84	};
	85
	86
8e911ab7	87	int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
d38ceaf9 AD	88	{
	89	int aligned = width;
	90	int pitch_mask = 0;
	91
8e911ab7	92	switch (cpp) {
d38ceaf9 AD	93	case 1:
	94	pitch_mask = 255;
	95	break;
	96	case 2:
	97	pitch_mask = 127;
	98	break;
	99	case 3:
	100	case 4:
	101	pitch_mask = 63;
	102	break;
	103	}
	104
	105	aligned += pitch_mask;
	106	aligned &= ~pitch_mask;
8e911ab7	107	return aligned * cpp;
d38ceaf9 AD	108	}
	109
	110	static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
	111	{
765e7fbf	112	struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	113	int ret;
d38ceaf9 AD	114
c81a1a74	115	ret = amdgpu_bo_reserve(abo, true);
d38ceaf9	116	if (likely(ret == 0)) {
765e7fbf CK	117	amdgpu_bo_kunmap(abo);
	118	amdgpu_bo_unpin(abo);
	119	amdgpu_bo_unreserve(abo);
d38ceaf9 AD	120	}
	121	drm_gem_object_unreference_unlocked(gobj);
	122	}
	123
	124	static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
	125	struct drm_mode_fb_cmd2 *mode_cmd,
	126	struct drm_gem_object **gobj_p)
	127	{
	128	struct amdgpu_device *adev = rfbdev->adev;
	129	struct drm_gem_object *gobj = NULL;
765e7fbf	130	struct amdgpu_bo *abo = NULL;
d38ceaf9 AD	131	bool fb_tiled = false; /* useful for testing */
	132	u32 tiling_flags = 0;
	133	int ret;
	134	int aligned_size, size;
	135	int height = mode_cmd->height;
8e911ab7	136	u32 cpp;
d38ceaf9	137
8e911ab7	138	cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
d38ceaf9 AD	139
d38ceaf9 AD	140	/* need to align pitch with crtc limits */
8e911ab7 LP	141	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
8e911ab7 LP	142	fb_tiled);
d38ceaf9 AD	143
	144	height = ALIGN(mode_cmd->height, 8);
	145	size = mode_cmd->pitches[0] * height;
	146	aligned_size = ALIGN(size, PAGE_SIZE);
	147	ret = amdgpu_gem_object_create(adev, aligned_size, 0,
	148	AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5	149	AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
cbabc8b3 PD	150	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS \|
cbabc8b3 PD	151	AMDGPU_GEM_CREATE_VRAM_CLEARED,
857d913d	152	true, &gobj);
d38ceaf9	153	if (ret) {
7ca85295	154	pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
d38ceaf9 AD	155	return -ENOMEM;
d38ceaf9 AD	156	}
765e7fbf	157	abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	158
d38ceaf9 AD	159	if (fb_tiled)
fbd76d59	160	tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
d38ceaf9	161
765e7fbf	162	ret = amdgpu_bo_reserve(abo, false);
d38ceaf9 AD	163	if (unlikely(ret != 0))
	164	goto out_unref;
	165
	166	if (tiling_flags) {
765e7fbf	167	ret = amdgpu_bo_set_tiling_flags(abo,
63ab1c2b	168	tiling_flags);
d38ceaf9 AD	169	if (ret)
	170	dev_err(adev->dev, "FB failed to set tiling flags\n");
	171	}
	172
	173
7fe28576	174	ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
d38ceaf9	175	if (ret) {
765e7fbf	176	amdgpu_bo_unreserve(abo);
d38ceaf9 AD	177	goto out_unref;
d38ceaf9 AD	178	}
765e7fbf CK	179	ret = amdgpu_bo_kmap(abo, NULL);
765e7fbf CK	180	amdgpu_bo_unreserve(abo);
d38ceaf9 AD	181	if (ret) {
	182	goto out_unref;
	183	}
	184
	185	*gobj_p = gobj;
	186	return 0;
	187	out_unref:
	188	amdgpufb_destroy_pinned_object(gobj);
	189	*gobj_p = NULL;
	190	return ret;
	191	}
	192
	193	static int amdgpufb_create(struct drm_fb_helper *helper,
	194	struct drm_fb_helper_surface_size *sizes)
	195	{
	196	struct amdgpu_fbdev rfbdev = (struct amdgpu_fbdev )helper;
	197	struct amdgpu_device *adev = rfbdev->adev;
	198	struct fb_info *info;
	199	struct drm_framebuffer *fb = NULL;
	200	struct drm_mode_fb_cmd2 mode_cmd;
	201	struct drm_gem_object *gobj = NULL;
765e7fbf	202	struct amdgpu_bo *abo = NULL;
d38ceaf9 AD	203	int ret;
	204	unsigned long tmp;
	205
	206	mode_cmd.width = sizes->surface_width;
	207	mode_cmd.height = sizes->surface_height;
	208
	209	if (sizes->surface_bpp == 24)
	210	sizes->surface_bpp = 32;
	211
	212	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
	213	sizes->surface_depth);
	214
	215	ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	216	if (ret) {
	217	DRM_ERROR("failed to create fbcon object %d\n", ret);
	218	return ret;
	219	}
	220
765e7fbf	221	abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	222
d38ceaf9 AD	223	/* okay we have an object now allocate the framebuffer */
2dbaf392 AT	224	info = drm_fb_helper_alloc_fbi(helper);
	225	if (IS_ERR(info)) {
	226	ret = PTR_ERR(info);
da7bdda2	227	goto out;
d38ceaf9 AD	228	}
	229
	230	info->par = rfbdev;
df7989fe	231	info->skip_vt_switch = true;
d38ceaf9 AD	232
	233	ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
	234	if (ret) {
	235	DRM_ERROR("failed to initialize framebuffer %d\n", ret);
da7bdda2	236	goto out;
d38ceaf9 AD	237	}
	238
	239	fb = &rfbdev->rfb.base;
	240
	241	/* setup helper */
	242	rfbdev->helper.fb = fb;
d38ceaf9	243
d38ceaf9 AD	244	strcpy(info->fix.id, "amdgpudrmfb");
d38ceaf9 AD	245
b00c600e	246	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
d38ceaf9 AD	247
	248	info->flags = FBINFO_DEFAULT \| FBINFO_CAN_FORCE_OUTPUT;
	249	info->fbops = &amdgpufb_ops;
	250
765e7fbf	251	tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start;
d38ceaf9	252	info->fix.smem_start = adev->mc.aper_base + tmp;
765e7fbf CK	253	info->fix.smem_len = amdgpu_bo_size(abo);
	254	info->screen_base = abo->kptr;
	255	info->screen_size = amdgpu_bo_size(abo);
d38ceaf9 AD	256
	257	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
	258
	259	/* setup aperture base/size for vesafb takeover */
d38ceaf9 AD	260	info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
	261	info->apertures->ranges[0].size = adev->mc.aper_size;
	262
	263	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
	264
	265	if (info->screen_base == NULL) {
	266	ret = -ENOSPC;
da7bdda2	267	goto out;
d38ceaf9 AD	268	}
	269
	270	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
	271	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base);
765e7fbf	272	DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
b00c600e	273	DRM_INFO("fb depth is %d\n", fb->format->depth);
d38ceaf9 AD	274	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
	275
	276	vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
	277	return 0;
	278
da7bdda2	279	out:
765e7fbf	280	if (abo) {
d38ceaf9 AD	281
	282	}
	283	if (fb && ret) {
a9906fde	284	drm_gem_object_unreference_unlocked(gobj);
d38ceaf9 AD	285	drm_framebuffer_unregister_private(fb);
	286	drm_framebuffer_cleanup(fb);
	287	kfree(fb);
	288	}
	289	return ret;
	290	}
	291
	292	void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
	293	{
	294	if (adev->mode_info.rfbdev)
	295	drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
	296	}
	297
	298	static int amdgpu_fbdev_destroy(struct drm_device dev, struct amdgpu_fbdev rfbdev)
	299	{
d38ceaf9 AD	300	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
d38ceaf9 AD	301
2dbaf392	302	drm_fb_helper_unregister_fbi(&rfbdev->helper);
d38ceaf9 AD	303
	304	if (rfb->obj) {
	305	amdgpufb_destroy_pinned_object(rfb->obj);
	306	rfb->obj = NULL;
	307	}
	308	drm_fb_helper_fini(&rfbdev->helper);
	309	drm_framebuffer_unregister_private(&rfb->base);
	310	drm_framebuffer_cleanup(&rfb->base);
	311
	312	return 0;
	313	}
	314
	315	/** Sets the color ramps on behalf of fbcon */
	316	static void amdgpu_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
	317	u16 blue, int regno)
	318	{
	319	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
	320
	321	amdgpu_crtc->lut_r[regno] = red >> 6;
	322	amdgpu_crtc->lut_g[regno] = green >> 6;
	323	amdgpu_crtc->lut_b[regno] = blue >> 6;
	324	}
	325
	326	/** Gets the color ramps on behalf of fbcon */
	327	static void amdgpu_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
	328	u16 *blue, int regno)
	329	{
	330	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
	331
	332	*red = amdgpu_crtc->lut_r[regno] << 6;
	333	*green = amdgpu_crtc->lut_g[regno] << 6;
	334	*blue = amdgpu_crtc->lut_b[regno] << 6;
	335	}
	336
	337	static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
	338	.gamma_set = amdgpu_crtc_fb_gamma_set,
	339	.gamma_get = amdgpu_crtc_fb_gamma_get,
	340	.fb_probe = amdgpufb_create,
	341	};
	342
	343	int amdgpu_fbdev_init(struct amdgpu_device *adev)
	344	{
	345	struct amdgpu_fbdev *rfbdev;
	346	int bpp_sel = 32;
	347	int ret;
	348
	349	/* don't init fbdev on hw without DCE */
	350	if (!adev->mode_info.mode_config_initialized)
	351	return 0;
	352
f49d45c9 AD	353	/* don't init fbdev if there are no connectors */
	354	if (list_empty(&adev->ddev->mode_config.connector_list))
	355	return 0;
	356
d38ceaf9 AD	357	/* select 8 bpp console on low vram cards */
	358	if (adev->mc.real_vram_size <= (3210241024))
	359	bpp_sel = 8;
	360
	361	rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
	362	if (!rfbdev)
	363	return -ENOMEM;
	364
	365	rfbdev->adev = adev;
	366	adev->mode_info.rfbdev = rfbdev;
	367
	368	drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
	369	&amdgpu_fb_helper_funcs);
	370
	371	ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
d38ceaf9 AD	372	AMDGPUFB_CONN_LIMIT);
	373	if (ret) {
	374	kfree(rfbdev);
	375	return ret;
	376	}
	377
	378	drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	379
	380	/* disable all the possible outputs/crtcs before entering KMS mode */
	381	drm_helper_disable_unused_functions(adev->ddev);
	382
	383	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	384	return 0;
	385	}
	386
	387	void amdgpu_fbdev_fini(struct amdgpu_device *adev)
	388	{
	389	if (!adev->mode_info.rfbdev)
	390	return;
	391
	392	amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
	393	kfree(adev->mode_info.rfbdev);
	394	adev->mode_info.rfbdev = NULL;
	395	}
	396
	397	void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
	398	{
	399	if (adev->mode_info.rfbdev)
2dbaf392 AT	400	drm_fb_helper_set_suspend(&adev->mode_info.rfbdev->helper,
2dbaf392 AT	401	state);
d38ceaf9 AD	402	}
	403
	404	int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
	405	{
	406	struct amdgpu_bo *robj;
	407	int size = 0;
	408
	409	if (!adev->mode_info.rfbdev)
	410	return 0;
	411
	412	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
	413	size += amdgpu_bo_size(robj);
	414	return size;
	415	}
	416
	417	bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device adev, struct amdgpu_bo robj)
	418	{
	419	if (!adev->mode_info.rfbdev)
	420	return false;
	421	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
	422	return true;
	423	return false;
	424	}
8b7530b1 AD	425
	426	void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
	427	{
b62ce397	428	struct amdgpu_fbdev *afbdev;
8b7530b1 AD	429	struct drm_fb_helper *fb_helper;
	430	int ret;
	431
b62ce397 RZ	432	if (!adev)
	433	return;
	434
	435	afbdev = adev->mode_info.rfbdev;
	436
8b7530b1 AD	437	if (!afbdev)
	438	return;
	439
	440	fb_helper = &afbdev->helper;
	441
	442	ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
	443	if (ret)
	444	DRM_DEBUG("failed to restore crtc mode\n");
	445	}