]>
Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/ktime.h> | |
fdf2f6c5 | 29 | #include <linux/module.h> |
568d7c76 | 30 | #include <linux/pagemap.h> |
fdf2f6c5 | 31 | #include <linux/pci.h> |
8523f887 | 32 | #include <linux/dma-buf.h> |
fdf2f6c5 | 33 | |
d38ceaf9 | 34 | #include <drm/amdgpu_drm.h> |
fdf2f6c5 SR |
35 | #include <drm/drm_debugfs.h> |
36 | ||
d38ceaf9 | 37 | #include "amdgpu.h" |
bda31a24 | 38 | #include "amdgpu_display.h" |
b4ae4fe6 | 39 | #include "amdgpu_xgmi.h" |
d38ceaf9 AD |
40 | |
41 | void amdgpu_gem_object_free(struct drm_gem_object *gobj) | |
42 | { | |
43 | struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); | |
44 | ||
45 | if (robj) { | |
9298e52f | 46 | amdgpu_mn_unregister(robj); |
d38ceaf9 AD |
47 | amdgpu_bo_unref(&robj); |
48 | } | |
49 | } | |
50 | ||
51 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, | |
e1eb899b | 52 | int alignment, u32 initial_domain, |
eab3de23 | 53 | u64 flags, enum ttm_bo_type type, |
52791eee | 54 | struct dma_resv *resv, |
e1eb899b | 55 | struct drm_gem_object **obj) |
d38ceaf9 | 56 | { |
e1eb899b | 57 | struct amdgpu_bo *bo; |
3216c6b7 | 58 | struct amdgpu_bo_param bp; |
d38ceaf9 AD |
59 | int r; |
60 | ||
3216c6b7 | 61 | memset(&bp, 0, sizeof(bp)); |
d38ceaf9 | 62 | *obj = NULL; |
d38ceaf9 | 63 | |
3216c6b7 CZ |
64 | bp.size = size; |
65 | bp.byte_align = alignment; | |
66 | bp.type = type; | |
67 | bp.resv = resv; | |
aa2b2e28 | 68 | bp.preferred_domain = initial_domain; |
08082104 | 69 | retry: |
3216c6b7 CZ |
70 | bp.flags = flags; |
71 | bp.domain = initial_domain; | |
72 | r = amdgpu_bo_create(adev, &bp, &bo); | |
d38ceaf9 | 73 | if (r) { |
08082104 CK |
74 | if (r != -ERESTARTSYS) { |
75 | if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { | |
76 | flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
77 | goto retry; | |
78 | } | |
79 | ||
80 | if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
81 | initial_domain |= AMDGPU_GEM_DOMAIN_GTT; | |
82 | goto retry; | |
83 | } | |
84 | DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", | |
85 | size, initial_domain, alignment, r); | |
86 | } | |
d38ceaf9 AD |
87 | return r; |
88 | } | |
c105de28 | 89 | *obj = &bo->tbo.base; |
d38ceaf9 | 90 | |
d38ceaf9 AD |
91 | return 0; |
92 | } | |
93 | ||
418aa0c2 | 94 | void amdgpu_gem_force_release(struct amdgpu_device *adev) |
d38ceaf9 | 95 | { |
4a580877 | 96 | struct drm_device *ddev = adev_to_drm(adev); |
418aa0c2 | 97 | struct drm_file *file; |
d38ceaf9 | 98 | |
1d2ac403 | 99 | mutex_lock(&ddev->filelist_mutex); |
418aa0c2 CK |
100 | |
101 | list_for_each_entry(file, &ddev->filelist, lhead) { | |
102 | struct drm_gem_object *gobj; | |
103 | int handle; | |
104 | ||
105 | WARN_ONCE(1, "Still active user space clients!\n"); | |
106 | spin_lock(&file->table_lock); | |
107 | idr_for_each_entry(&file->object_idr, gobj, handle) { | |
108 | WARN_ONCE(1, "And also active allocations!\n"); | |
e07ddb0c | 109 | drm_gem_object_put(gobj); |
418aa0c2 CK |
110 | } |
111 | idr_destroy(&file->object_idr); | |
112 | spin_unlock(&file->table_lock); | |
113 | } | |
114 | ||
1d2ac403 | 115 | mutex_unlock(&ddev->filelist_mutex); |
d38ceaf9 AD |
116 | } |
117 | ||
118 | /* | |
119 | * Call from drm_gem_handle_create which appear in both new and open ioctl | |
120 | * case. | |
121 | */ | |
a7d64de6 CK |
122 | int amdgpu_gem_object_open(struct drm_gem_object *obj, |
123 | struct drm_file *file_priv) | |
d38ceaf9 | 124 | { |
765e7fbf | 125 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); |
a7d64de6 | 126 | struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); |
d38ceaf9 AD |
127 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
128 | struct amdgpu_vm *vm = &fpriv->vm; | |
129 | struct amdgpu_bo_va *bo_va; | |
4f5839c5 | 130 | struct mm_struct *mm; |
d38ceaf9 | 131 | int r; |
4f5839c5 CK |
132 | |
133 | mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); | |
134 | if (mm && mm != current->mm) | |
135 | return -EPERM; | |
136 | ||
e1eb899b | 137 | if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && |
5a5011a7 | 138 | abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) |
e1eb899b CK |
139 | return -EPERM; |
140 | ||
765e7fbf | 141 | r = amdgpu_bo_reserve(abo, false); |
e98c1b0d | 142 | if (r) |
d38ceaf9 | 143 | return r; |
d38ceaf9 | 144 | |
765e7fbf | 145 | bo_va = amdgpu_vm_bo_find(vm, abo); |
d38ceaf9 | 146 | if (!bo_va) { |
765e7fbf | 147 | bo_va = amdgpu_vm_bo_add(adev, vm, abo); |
d38ceaf9 AD |
148 | } else { |
149 | ++bo_va->ref_count; | |
150 | } | |
765e7fbf | 151 | amdgpu_bo_unreserve(abo); |
d38ceaf9 AD |
152 | return 0; |
153 | } | |
154 | ||
155 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
156 | struct drm_file *file_priv) | |
157 | { | |
b5a5ec55 | 158 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); |
a7d64de6 | 159 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
d38ceaf9 AD |
160 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
161 | struct amdgpu_vm *vm = &fpriv->vm; | |
b5a5ec55 CK |
162 | |
163 | struct amdgpu_bo_list_entry vm_pd; | |
e1eb899b | 164 | struct list_head list, duplicates; |
82c416b1 | 165 | struct dma_fence *fence = NULL; |
b5a5ec55 CK |
166 | struct ttm_validate_buffer tv; |
167 | struct ww_acquire_ctx ticket; | |
d38ceaf9 | 168 | struct amdgpu_bo_va *bo_va; |
82c416b1 | 169 | long r; |
b5a5ec55 CK |
170 | |
171 | INIT_LIST_HEAD(&list); | |
e1eb899b | 172 | INIT_LIST_HEAD(&duplicates); |
b5a5ec55 CK |
173 | |
174 | tv.bo = &bo->tbo; | |
82c416b1 | 175 | tv.num_shared = 2; |
b5a5ec55 CK |
176 | list_add(&tv.head, &list); |
177 | ||
178 | amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); | |
179 | ||
9165fb87 | 180 | r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); |
d38ceaf9 AD |
181 | if (r) { |
182 | dev_err(adev->dev, "leaking bo va because " | |
82c416b1 | 183 | "we fail to reserve bo (%ld)\n", r); |
d38ceaf9 AD |
184 | return; |
185 | } | |
b5a5ec55 | 186 | bo_va = amdgpu_vm_bo_find(vm, bo); |
82c416b1 CK |
187 | if (!bo_va || --bo_va->ref_count) |
188 | goto out_unlock; | |
23e0563e | 189 | |
82c416b1 CK |
190 | amdgpu_vm_bo_rmv(adev, bo_va); |
191 | if (!amdgpu_vm_ready(vm)) | |
192 | goto out_unlock; | |
23e0563e | 193 | |
82c416b1 CK |
194 | fence = dma_resv_get_excl(bo->tbo.base.resv); |
195 | if (fence) { | |
196 | amdgpu_bo_fence(bo, fence, true); | |
197 | fence = NULL; | |
d38ceaf9 | 198 | } |
82c416b1 CK |
199 | |
200 | r = amdgpu_vm_clear_freed(adev, vm, &fence); | |
201 | if (r || !fence) | |
202 | goto out_unlock; | |
203 | ||
204 | amdgpu_bo_fence(bo, fence, true); | |
205 | dma_fence_put(fence); | |
206 | ||
207 | out_unlock: | |
208 | if (unlikely(r < 0)) | |
209 | dev_err(adev->dev, "failed to clear page " | |
210 | "tables on GEM object close (%ld)\n", r); | |
b5a5ec55 | 211 | ttm_eu_backoff_reservation(&ticket, &list); |
d38ceaf9 AD |
212 | } |
213 | ||
d38ceaf9 AD |
214 | /* |
215 | * GEM ioctls. | |
216 | */ | |
217 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
218 | struct drm_file *filp) | |
219 | { | |
1348969a | 220 | struct amdgpu_device *adev = drm_to_adev(dev); |
e1eb899b CK |
221 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
222 | struct amdgpu_vm *vm = &fpriv->vm; | |
d38ceaf9 | 223 | union drm_amdgpu_gem_create *args = data; |
6ac7defb | 224 | uint64_t flags = args->in.domain_flags; |
d38ceaf9 | 225 | uint64_t size = args->in.bo_size; |
52791eee | 226 | struct dma_resv *resv = NULL; |
d38ceaf9 AD |
227 | struct drm_gem_object *gobj; |
228 | uint32_t handle; | |
d38ceaf9 AD |
229 | int r; |
230 | ||
834e0f8a | 231 | /* reject invalid gem flags */ |
6ac7defb CK |
232 | if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
233 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
234 | AMDGPU_GEM_CREATE_CPU_GTT_USWC | | |
e1eb899b | 235 | AMDGPU_GEM_CREATE_VRAM_CLEARED | |
177ae09b | 236 | AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | |
4cd24494 AD |
237 | AMDGPU_GEM_CREATE_EXPLICIT_SYNC | |
238 | AMDGPU_GEM_CREATE_ENCRYPTED)) | |
177ae09b | 239 | |
a022c54e CK |
240 | return -EINVAL; |
241 | ||
834e0f8a | 242 | /* reject invalid gem domains */ |
3f188453 | 243 | if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) |
a022c54e | 244 | return -EINVAL; |
834e0f8a | 245 | |
11b407a7 HR |
246 | if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { |
247 | DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); | |
4cd24494 AD |
248 | return -EINVAL; |
249 | } | |
250 | ||
d38ceaf9 AD |
251 | /* create a gem object to contain this object in */ |
252 | if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | | |
253 | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { | |
ee5309d5 CZ |
254 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { |
255 | /* if gds bo is created from user space, it must be | |
256 | * passed to bo list | |
257 | */ | |
258 | DRM_ERROR("GDS bo cannot be per-vm-bo\n"); | |
259 | return -EINVAL; | |
260 | } | |
6ac7defb | 261 | flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; |
d38ceaf9 | 262 | } |
d38ceaf9 | 263 | |
e1eb899b CK |
264 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { |
265 | r = amdgpu_bo_reserve(vm->root.base.bo, false); | |
266 | if (r) | |
267 | return r; | |
268 | ||
5a5011a7 | 269 | resv = vm->root.base.bo->tbo.base.resv; |
e1eb899b CK |
270 | } |
271 | ||
d38ceaf9 AD |
272 | r = amdgpu_gem_object_create(adev, size, args->in.alignment, |
273 | (u32)(0xffffffff & args->in.domains), | |
f8ddb39a | 274 | flags, ttm_bo_type_device, resv, &gobj); |
e1eb899b CK |
275 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { |
276 | if (!r) { | |
277 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); | |
278 | ||
279 | abo->parent = amdgpu_bo_ref(vm->root.base.bo); | |
280 | } | |
281 | amdgpu_bo_unreserve(vm->root.base.bo); | |
282 | } | |
d38ceaf9 | 283 | if (r) |
a022c54e | 284 | return r; |
d38ceaf9 AD |
285 | |
286 | r = drm_gem_handle_create(filp, gobj, &handle); | |
287 | /* drop reference from allocate - handle holds it now */ | |
e07ddb0c | 288 | drm_gem_object_put(gobj); |
d38ceaf9 | 289 | if (r) |
a022c54e | 290 | return r; |
d38ceaf9 AD |
291 | |
292 | memset(args, 0, sizeof(*args)); | |
293 | args->out.handle = handle; | |
d38ceaf9 | 294 | return 0; |
d38ceaf9 AD |
295 | } |
296 | ||
297 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
298 | struct drm_file *filp) | |
299 | { | |
19be5570 | 300 | struct ttm_operation_ctx ctx = { true, false }; |
1348969a | 301 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 AD |
302 | struct drm_amdgpu_gem_userptr *args = data; |
303 | struct drm_gem_object *gobj; | |
304 | struct amdgpu_bo *bo; | |
305 | uint32_t handle; | |
306 | int r; | |
307 | ||
35f3fc87 AK |
308 | args->addr = untagged_addr(args->addr); |
309 | ||
d38ceaf9 AD |
310 | if (offset_in_page(args->addr | args->size)) |
311 | return -EINVAL; | |
312 | ||
313 | /* reject unknown flag values */ | |
314 | if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | | |
315 | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | | |
316 | AMDGPU_GEM_USERPTR_REGISTER)) | |
317 | return -EINVAL; | |
318 | ||
358c258a CK |
319 | if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && |
320 | !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { | |
d38ceaf9 | 321 | |
358c258a | 322 | /* if we want to write to it we must install a MMU notifier */ |
d38ceaf9 AD |
323 | return -EACCES; |
324 | } | |
325 | ||
d38ceaf9 | 326 | /* create a gem object to contain this object in */ |
e1eb899b | 327 | r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, |
f8ddb39a | 328 | 0, ttm_bo_type_device, NULL, &gobj); |
d38ceaf9 | 329 | if (r) |
a022c54e | 330 | return r; |
d38ceaf9 AD |
331 | |
332 | bo = gem_to_amdgpu_bo(gobj); | |
6d7d9c5a | 333 | bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; |
1ea863fd | 334 | bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; |
77f47d23 | 335 | r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); |
d38ceaf9 AD |
336 | if (r) |
337 | goto release_object; | |
338 | ||
339 | if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { | |
340 | r = amdgpu_mn_register(bo, args->addr); | |
341 | if (r) | |
342 | goto release_object; | |
343 | } | |
344 | ||
345 | if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { | |
e5eaa7cc | 346 | r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); |
2f568dbd | 347 | if (r) |
d5a480b4 | 348 | goto release_object; |
2f568dbd | 349 | |
d38ceaf9 | 350 | r = amdgpu_bo_reserve(bo, true); |
2f568dbd | 351 | if (r) |
899fbde1 | 352 | goto user_pages_done; |
d38ceaf9 | 353 | |
c704ab18 | 354 | amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); |
19be5570 | 355 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); |
d38ceaf9 | 356 | amdgpu_bo_unreserve(bo); |
d38ceaf9 | 357 | if (r) |
899fbde1 | 358 | goto user_pages_done; |
d38ceaf9 AD |
359 | } |
360 | ||
361 | r = drm_gem_handle_create(filp, gobj, &handle); | |
d38ceaf9 | 362 | if (r) |
899fbde1 | 363 | goto user_pages_done; |
d38ceaf9 AD |
364 | |
365 | args->handle = handle; | |
d38ceaf9 | 366 | |
899fbde1 PY |
367 | user_pages_done: |
368 | if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) | |
369 | amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); | |
2f568dbd | 370 | |
d38ceaf9 | 371 | release_object: |
e07ddb0c | 372 | drm_gem_object_put(gobj); |
d38ceaf9 | 373 | |
d38ceaf9 AD |
374 | return r; |
375 | } | |
376 | ||
377 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
378 | struct drm_device *dev, | |
379 | uint32_t handle, uint64_t *offset_p) | |
380 | { | |
381 | struct drm_gem_object *gobj; | |
382 | struct amdgpu_bo *robj; | |
383 | ||
a8ad0bd8 | 384 | gobj = drm_gem_object_lookup(filp, handle); |
d38ceaf9 AD |
385 | if (gobj == NULL) { |
386 | return -ENOENT; | |
387 | } | |
388 | robj = gem_to_amdgpu_bo(gobj); | |
cc325d19 | 389 | if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || |
271c8125 | 390 | (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { |
e07ddb0c | 391 | drm_gem_object_put(gobj); |
d38ceaf9 AD |
392 | return -EPERM; |
393 | } | |
394 | *offset_p = amdgpu_bo_mmap_offset(robj); | |
e07ddb0c | 395 | drm_gem_object_put(gobj); |
d38ceaf9 AD |
396 | return 0; |
397 | } | |
398 | ||
399 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
400 | struct drm_file *filp) | |
401 | { | |
402 | union drm_amdgpu_gem_mmap *args = data; | |
403 | uint32_t handle = args->in.handle; | |
404 | memset(args, 0, sizeof(*args)); | |
405 | return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); | |
406 | } | |
407 | ||
408 | /** | |
409 | * amdgpu_gem_timeout - calculate jiffies timeout from absolute value | |
410 | * | |
411 | * @timeout_ns: timeout in ns | |
412 | * | |
413 | * Calculate the timeout in jiffies from an absolute timeout in ns. | |
414 | */ | |
415 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) | |
416 | { | |
417 | unsigned long timeout_jiffies; | |
418 | ktime_t timeout; | |
419 | ||
420 | /* clamp timeout if it's to large */ | |
421 | if (((int64_t)timeout_ns) < 0) | |
422 | return MAX_SCHEDULE_TIMEOUT; | |
423 | ||
0f117704 | 424 | timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); |
d38ceaf9 AD |
425 | if (ktime_to_ns(timeout) < 0) |
426 | return 0; | |
427 | ||
428 | timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); | |
429 | /* clamp timeout to avoid unsigned-> signed overflow */ | |
430 | if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) | |
431 | return MAX_SCHEDULE_TIMEOUT - 1; | |
432 | ||
433 | return timeout_jiffies; | |
434 | } | |
435 | ||
436 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
437 | struct drm_file *filp) | |
438 | { | |
d38ceaf9 AD |
439 | union drm_amdgpu_gem_wait_idle *args = data; |
440 | struct drm_gem_object *gobj; | |
441 | struct amdgpu_bo *robj; | |
442 | uint32_t handle = args->in.handle; | |
443 | unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); | |
444 | int r = 0; | |
445 | long ret; | |
446 | ||
a8ad0bd8 | 447 | gobj = drm_gem_object_lookup(filp, handle); |
d38ceaf9 AD |
448 | if (gobj == NULL) { |
449 | return -ENOENT; | |
450 | } | |
451 | robj = gem_to_amdgpu_bo(gobj); | |
52791eee | 452 | ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, |
0fea2ed6 | 453 | timeout); |
d38ceaf9 AD |
454 | |
455 | /* ret == 0 means not signaled, | |
456 | * ret > 0 means signaled | |
457 | * ret < 0 means interrupted before timeout | |
458 | */ | |
459 | if (ret >= 0) { | |
460 | memset(args, 0, sizeof(*args)); | |
461 | args->out.status = (ret == 0); | |
462 | } else | |
463 | r = ret; | |
464 | ||
e07ddb0c | 465 | drm_gem_object_put(gobj); |
d38ceaf9 AD |
466 | return r; |
467 | } | |
468 | ||
469 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
470 | struct drm_file *filp) | |
471 | { | |
472 | struct drm_amdgpu_gem_metadata *args = data; | |
473 | struct drm_gem_object *gobj; | |
474 | struct amdgpu_bo *robj; | |
475 | int r = -1; | |
476 | ||
477 | DRM_DEBUG("%d \n", args->handle); | |
a8ad0bd8 | 478 | gobj = drm_gem_object_lookup(filp, args->handle); |
d38ceaf9 AD |
479 | if (gobj == NULL) |
480 | return -ENOENT; | |
481 | robj = gem_to_amdgpu_bo(gobj); | |
482 | ||
483 | r = amdgpu_bo_reserve(robj, false); | |
484 | if (unlikely(r != 0)) | |
485 | goto out; | |
486 | ||
487 | if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { | |
488 | amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); | |
489 | r = amdgpu_bo_get_metadata(robj, args->data.data, | |
490 | sizeof(args->data.data), | |
491 | &args->data.data_size_bytes, | |
492 | &args->data.flags); | |
493 | } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { | |
0913eab6 DC |
494 | if (args->data.data_size_bytes > sizeof(args->data.data)) { |
495 | r = -EINVAL; | |
496 | goto unreserve; | |
497 | } | |
d38ceaf9 AD |
498 | r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); |
499 | if (!r) | |
500 | r = amdgpu_bo_set_metadata(robj, args->data.data, | |
501 | args->data.data_size_bytes, | |
502 | args->data.flags); | |
503 | } | |
504 | ||
0913eab6 | 505 | unreserve: |
d38ceaf9 AD |
506 | amdgpu_bo_unreserve(robj); |
507 | out: | |
e07ddb0c | 508 | drm_gem_object_put(gobj); |
d38ceaf9 AD |
509 | return r; |
510 | } | |
511 | ||
512 | /** | |
513 | * amdgpu_gem_va_update_vm -update the bo_va in its VM | |
514 | * | |
515 | * @adev: amdgpu_device pointer | |
dc54d3d1 | 516 | * @vm: vm to update |
d38ceaf9 | 517 | * @bo_va: bo_va to update |
dc54d3d1 | 518 | * @operation: map, unmap or clear |
d38ceaf9 | 519 | * |
2ffdaafb | 520 | * Update the bo_va directly after setting its address. Errors are not |
d38ceaf9 AD |
521 | * vital here, so they are not reported back to userspace. |
522 | */ | |
523 | static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, | |
dc54d3d1 | 524 | struct amdgpu_vm *vm, |
f7da30d9 CK |
525 | struct amdgpu_bo_va *bo_va, |
526 | uint32_t operation) | |
d38ceaf9 | 527 | { |
3f3333f8 | 528 | int r; |
d38ceaf9 | 529 | |
3f3333f8 CK |
530 | if (!amdgpu_vm_ready(vm)) |
531 | return; | |
e410b5cb | 532 | |
f3467818 | 533 | r = amdgpu_vm_clear_freed(adev, vm, NULL); |
d38ceaf9 | 534 | if (r) |
2ffdaafb | 535 | goto error; |
194a3364 | 536 | |
80f95c57 | 537 | if (operation == AMDGPU_VA_OP_MAP || |
93bab704 | 538 | operation == AMDGPU_VA_OP_REPLACE) { |
05dcb5c8 | 539 | r = amdgpu_vm_bo_update(adev, bo_va, false); |
93bab704 GS |
540 | if (r) |
541 | goto error; | |
542 | } | |
d38ceaf9 | 543 | |
807e2994 | 544 | r = amdgpu_vm_update_pdes(adev, vm, false); |
0abc6878 | 545 | |
2ffdaafb | 546 | error: |
68fdd3df | 547 | if (r && r != -ERESTARTSYS) |
d38ceaf9 AD |
548 | DRM_ERROR("Couldn't update BO_VA (%d)\n", r); |
549 | } | |
550 | ||
71776b6d CK |
551 | /** |
552 | * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags | |
553 | * | |
554 | * @adev: amdgpu_device pointer | |
555 | * @flags: GEM UAPI flags | |
556 | * | |
557 | * Returns the GEM UAPI flags mapped into hardware for the ASIC. | |
558 | */ | |
559 | uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) | |
560 | { | |
561 | uint64_t pte_flag = 0; | |
562 | ||
563 | if (flags & AMDGPU_VM_PAGE_EXECUTABLE) | |
564 | pte_flag |= AMDGPU_PTE_EXECUTABLE; | |
565 | if (flags & AMDGPU_VM_PAGE_READABLE) | |
566 | pte_flag |= AMDGPU_PTE_READABLE; | |
567 | if (flags & AMDGPU_VM_PAGE_WRITEABLE) | |
568 | pte_flag |= AMDGPU_PTE_WRITEABLE; | |
569 | if (flags & AMDGPU_VM_PAGE_PRT) | |
570 | pte_flag |= AMDGPU_PTE_PRT; | |
571 | ||
572 | if (adev->gmc.gmc_funcs->map_mtype) | |
573 | pte_flag |= amdgpu_gmc_map_mtype(adev, | |
574 | flags & AMDGPU_VM_MTYPE_MASK); | |
575 | ||
576 | return pte_flag; | |
577 | } | |
578 | ||
d38ceaf9 AD |
579 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, |
580 | struct drm_file *filp) | |
581 | { | |
b85891bd JZ |
582 | const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | |
583 | AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | | |
66e02bc3 | 584 | AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; |
b85891bd JZ |
585 | const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | |
586 | AMDGPU_VM_PAGE_PRT; | |
587 | ||
34b5f6a6 | 588 | struct drm_amdgpu_gem_va *args = data; |
d38ceaf9 | 589 | struct drm_gem_object *gobj; |
1348969a | 590 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 591 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
765e7fbf | 592 | struct amdgpu_bo *abo; |
d38ceaf9 | 593 | struct amdgpu_bo_va *bo_va; |
b88c8796 CK |
594 | struct amdgpu_bo_list_entry vm_pd; |
595 | struct ttm_validate_buffer tv; | |
49b02b18 | 596 | struct ww_acquire_ctx ticket; |
e1eb899b | 597 | struct list_head list, duplicates; |
5463545b | 598 | uint64_t va_flags; |
d38ceaf9 AD |
599 | int r = 0; |
600 | ||
34b5f6a6 | 601 | if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { |
4b7f0848 | 602 | dev_dbg(&dev->pdev->dev, |
ff4cd389 CK |
603 | "va_address 0x%LX is in reserved area 0x%LX\n", |
604 | args->va_address, AMDGPU_VA_RESERVED_SIZE); | |
d38ceaf9 AD |
605 | return -EINVAL; |
606 | } | |
607 | ||
ad9a5b78 CK |
608 | if (args->va_address >= AMDGPU_GMC_HOLE_START && |
609 | args->va_address < AMDGPU_GMC_HOLE_END) { | |
bb7939b2 CK |
610 | dev_dbg(&dev->pdev->dev, |
611 | "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", | |
ad9a5b78 CK |
612 | args->va_address, AMDGPU_GMC_HOLE_START, |
613 | AMDGPU_GMC_HOLE_END); | |
bb7939b2 CK |
614 | return -EINVAL; |
615 | } | |
616 | ||
ad9a5b78 | 617 | args->va_address &= AMDGPU_GMC_HOLE_MASK; |
bb7939b2 | 618 | |
b85891bd | 619 | if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { |
4b7f0848 | 620 | dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", |
b85891bd | 621 | args->flags); |
d38ceaf9 AD |
622 | return -EINVAL; |
623 | } | |
624 | ||
34b5f6a6 | 625 | switch (args->operation) { |
d38ceaf9 AD |
626 | case AMDGPU_VA_OP_MAP: |
627 | case AMDGPU_VA_OP_UNMAP: | |
dc54d3d1 | 628 | case AMDGPU_VA_OP_CLEAR: |
80f95c57 | 629 | case AMDGPU_VA_OP_REPLACE: |
d38ceaf9 AD |
630 | break; |
631 | default: | |
4b7f0848 | 632 | dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", |
34b5f6a6 | 633 | args->operation); |
d38ceaf9 AD |
634 | return -EINVAL; |
635 | } | |
636 | ||
49b02b18 | 637 | INIT_LIST_HEAD(&list); |
e1eb899b | 638 | INIT_LIST_HEAD(&duplicates); |
dc54d3d1 CK |
639 | if ((args->operation != AMDGPU_VA_OP_CLEAR) && |
640 | !(args->flags & AMDGPU_VM_PAGE_PRT)) { | |
b85891bd JZ |
641 | gobj = drm_gem_object_lookup(filp, args->handle); |
642 | if (gobj == NULL) | |
643 | return -ENOENT; | |
644 | abo = gem_to_amdgpu_bo(gobj); | |
645 | tv.bo = &abo->tbo; | |
a9f34c70 CK |
646 | if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) |
647 | tv.num_shared = 1; | |
648 | else | |
649 | tv.num_shared = 0; | |
b85891bd JZ |
650 | list_add(&tv.head, &list); |
651 | } else { | |
652 | gobj = NULL; | |
653 | abo = NULL; | |
654 | } | |
49b02b18 | 655 | |
b88c8796 | 656 | amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); |
b5a5ec55 | 657 | |
9165fb87 | 658 | r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); |
b85891bd JZ |
659 | if (r) |
660 | goto error_unref; | |
34b5f6a6 | 661 | |
b85891bd JZ |
662 | if (abo) { |
663 | bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); | |
664 | if (!bo_va) { | |
665 | r = -ENOENT; | |
666 | goto error_backoff; | |
667 | } | |
dc54d3d1 | 668 | } else if (args->operation != AMDGPU_VA_OP_CLEAR) { |
b85891bd | 669 | bo_va = fpriv->prt_va; |
dc54d3d1 CK |
670 | } else { |
671 | bo_va = NULL; | |
d38ceaf9 AD |
672 | } |
673 | ||
34b5f6a6 | 674 | switch (args->operation) { |
d38ceaf9 | 675 | case AMDGPU_VA_OP_MAP: |
71776b6d | 676 | va_flags = amdgpu_gem_va_map_flags(adev, args->flags); |
34b5f6a6 CK |
677 | r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, |
678 | args->offset_in_bo, args->map_size, | |
9f7eb536 | 679 | va_flags); |
d38ceaf9 AD |
680 | break; |
681 | case AMDGPU_VA_OP_UNMAP: | |
34b5f6a6 | 682 | r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); |
d38ceaf9 | 683 | break; |
dc54d3d1 CK |
684 | |
685 | case AMDGPU_VA_OP_CLEAR: | |
686 | r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, | |
687 | args->va_address, | |
688 | args->map_size); | |
689 | break; | |
80f95c57 | 690 | case AMDGPU_VA_OP_REPLACE: |
71776b6d | 691 | va_flags = amdgpu_gem_va_map_flags(adev, args->flags); |
80f95c57 CK |
692 | r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, |
693 | args->offset_in_bo, args->map_size, | |
694 | va_flags); | |
695 | break; | |
d38ceaf9 AD |
696 | default: |
697 | break; | |
698 | } | |
b85891bd | 699 | if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) |
59d61be2 | 700 | amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, |
dc54d3d1 | 701 | args->operation); |
b85891bd JZ |
702 | |
703 | error_backoff: | |
2ffdaafb | 704 | ttm_eu_backoff_reservation(&ticket, &list); |
e98c1b0d | 705 | |
b85891bd | 706 | error_unref: |
e07ddb0c | 707 | drm_gem_object_put(gobj); |
d38ceaf9 AD |
708 | return r; |
709 | } | |
710 | ||
711 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
712 | struct drm_file *filp) | |
713 | { | |
1348969a | 714 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 AD |
715 | struct drm_amdgpu_gem_op *args = data; |
716 | struct drm_gem_object *gobj; | |
b4ae4fe6 | 717 | struct amdgpu_vm_bo_base *base; |
d38ceaf9 AD |
718 | struct amdgpu_bo *robj; |
719 | int r; | |
720 | ||
a8ad0bd8 | 721 | gobj = drm_gem_object_lookup(filp, args->handle); |
d38ceaf9 AD |
722 | if (gobj == NULL) { |
723 | return -ENOENT; | |
724 | } | |
725 | robj = gem_to_amdgpu_bo(gobj); | |
726 | ||
727 | r = amdgpu_bo_reserve(robj, false); | |
728 | if (unlikely(r)) | |
729 | goto out; | |
730 | ||
731 | switch (args->op) { | |
732 | case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { | |
733 | struct drm_amdgpu_gem_create_in info; | |
7ecc245a | 734 | void __user *out = u64_to_user_ptr(args->value); |
d38ceaf9 | 735 | |
c105de28 | 736 | info.bo_size = robj->tbo.base.size; |
d38ceaf9 | 737 | info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; |
6d7d9c5a | 738 | info.domains = robj->preferred_domains; |
d38ceaf9 | 739 | info.domain_flags = robj->flags; |
4c28fb0b | 740 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
741 | if (copy_to_user(out, &info, sizeof(info))) |
742 | r = -EFAULT; | |
743 | break; | |
744 | } | |
d8f65a23 | 745 | case AMDGPU_GEM_OP_SET_PLACEMENT: |
803d89ad CJHR |
746 | if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { |
747 | r = -EINVAL; | |
748 | amdgpu_bo_unreserve(robj); | |
749 | break; | |
750 | } | |
cc325d19 | 751 | if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { |
d38ceaf9 | 752 | r = -EPERM; |
4c28fb0b | 753 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
754 | break; |
755 | } | |
b4ae4fe6 | 756 | for (base = robj->vm_bo; base; base = base->next) |
757 | if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), | |
758 | amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) { | |
759 | r = -EINVAL; | |
760 | amdgpu_bo_unreserve(robj); | |
761 | goto out; | |
762 | } | |
763 | ||
764 | ||
6d7d9c5a | 765 | robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | |
1ea863fd CK |
766 | AMDGPU_GEM_DOMAIN_GTT | |
767 | AMDGPU_GEM_DOMAIN_CPU); | |
6d7d9c5a | 768 | robj->allowed_domains = robj->preferred_domains; |
1ea863fd CK |
769 | if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) |
770 | robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; | |
771 | ||
e1eb899b CK |
772 | if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) |
773 | amdgpu_vm_bo_invalidate(adev, robj, true); | |
774 | ||
4c28fb0b | 775 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
776 | break; |
777 | default: | |
4c28fb0b | 778 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
779 | r = -EINVAL; |
780 | } | |
781 | ||
d38ceaf9 | 782 | out: |
e07ddb0c | 783 | drm_gem_object_put(gobj); |
d38ceaf9 AD |
784 | return r; |
785 | } | |
786 | ||
787 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
788 | struct drm_device *dev, | |
789 | struct drm_mode_create_dumb *args) | |
790 | { | |
1348969a | 791 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 AD |
792 | struct drm_gem_object *gobj; |
793 | uint32_t handle; | |
e4c4073b AG |
794 | u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
795 | AMDGPU_GEM_CREATE_CPU_GTT_USWC; | |
84b74608 | 796 | u32 domain; |
d38ceaf9 AD |
797 | int r; |
798 | ||
46846ba2 NK |
799 | /* |
800 | * The buffer returned from this function should be cleared, but | |
801 | * it can only be done if the ring is enabled or we'll fail to | |
802 | * create the buffer. | |
803 | */ | |
804 | if (adev->mman.buffer_funcs_enabled) | |
805 | flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
806 | ||
8e911ab7 LP |
807 | args->pitch = amdgpu_align_pitch(adev, args->width, |
808 | DIV_ROUND_UP(args->bpp, 8), 0); | |
54ef0b54 | 809 | args->size = (u64)args->pitch * args->height; |
d38ceaf9 | 810 | args->size = ALIGN(args->size, PAGE_SIZE); |
84b74608 | 811 | domain = amdgpu_bo_get_preferred_pin_domain(adev, |
f2bd8a0e | 812 | amdgpu_display_supported_domains(adev, flags)); |
46846ba2 | 813 | r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, |
f8ddb39a | 814 | ttm_bo_type_device, NULL, &gobj); |
d38ceaf9 AD |
815 | if (r) |
816 | return -ENOMEM; | |
817 | ||
818 | r = drm_gem_handle_create(file_priv, gobj, &handle); | |
819 | /* drop reference from allocate - handle holds it now */ | |
e07ddb0c | 820 | drm_gem_object_put(gobj); |
d38ceaf9 AD |
821 | if (r) { |
822 | return r; | |
823 | } | |
824 | args->handle = handle; | |
825 | return 0; | |
826 | } | |
827 | ||
828 | #if defined(CONFIG_DEBUG_FS) | |
6b155d6a CK |
829 | |
830 | #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ | |
831 | if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ | |
832 | seq_printf((m), " " #flag); \ | |
833 | } | |
834 | ||
7ea23565 CK |
835 | static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) |
836 | { | |
837 | struct drm_gem_object *gobj = ptr; | |
838 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); | |
839 | struct seq_file *m = data; | |
840 | ||
b1f223c0 CK |
841 | struct dma_buf_attachment *attachment; |
842 | struct dma_buf *dma_buf; | |
7ea23565 CK |
843 | unsigned domain; |
844 | const char *placement; | |
845 | unsigned pin_count; | |
846 | ||
847 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
848 | switch (domain) { | |
849 | case AMDGPU_GEM_DOMAIN_VRAM: | |
850 | placement = "VRAM"; | |
851 | break; | |
852 | case AMDGPU_GEM_DOMAIN_GTT: | |
853 | placement = " GTT"; | |
854 | break; | |
855 | case AMDGPU_GEM_DOMAIN_CPU: | |
856 | default: | |
857 | placement = " CPU"; | |
858 | break; | |
859 | } | |
b8e0e6e1 CK |
860 | seq_printf(m, "\t0x%08x: %12ld byte %s", |
861 | id, amdgpu_bo_size(bo), placement); | |
862 | ||
6aa7de05 | 863 | pin_count = READ_ONCE(bo->pin_count); |
7ea23565 CK |
864 | if (pin_count) |
865 | seq_printf(m, " pin count %d", pin_count); | |
b1f223c0 | 866 | |
c105de28 GH |
867 | dma_buf = READ_ONCE(bo->tbo.base.dma_buf); |
868 | attachment = READ_ONCE(bo->tbo.base.import_attach); | |
b1f223c0 CK |
869 | |
870 | if (attachment) | |
8523f887 CK |
871 | seq_printf(m, " imported from %p%s", dma_buf, |
872 | attachment->peer2peer ? " P2P" : ""); | |
b1f223c0 CK |
873 | else if (dma_buf) |
874 | seq_printf(m, " exported as %p", dma_buf); | |
875 | ||
6b155d6a CK |
876 | amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); |
877 | amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); | |
878 | amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); | |
879 | amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); | |
880 | amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); | |
881 | amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); | |
882 | amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); | |
883 | amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); | |
884 | ||
7ea23565 CK |
885 | seq_printf(m, "\n"); |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
d38ceaf9 AD |
890 | static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) |
891 | { | |
892 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
893 | struct drm_device *dev = node->minor->dev; | |
7ea23565 CK |
894 | struct drm_file *file; |
895 | int r; | |
d38ceaf9 | 896 | |
1d2ac403 | 897 | r = mutex_lock_interruptible(&dev->filelist_mutex); |
7ea23565 CK |
898 | if (r) |
899 | return r; | |
900 | ||
901 | list_for_each_entry(file, &dev->filelist, lhead) { | |
902 | struct task_struct *task; | |
903 | ||
904 | /* | |
905 | * Although we have a valid reference on file->pid, that does | |
906 | * not guarantee that the task_struct who called get_pid() is | |
907 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
908 | * Therefore, we need to protect this ->comm access using RCU. | |
909 | */ | |
910 | rcu_read_lock(); | |
911 | task = pid_task(file->pid, PIDTYPE_PID); | |
912 | seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), | |
913 | task ? task->comm : "<unknown>"); | |
914 | rcu_read_unlock(); | |
915 | ||
916 | spin_lock(&file->table_lock); | |
917 | idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); | |
918 | spin_unlock(&file->table_lock); | |
d38ceaf9 | 919 | } |
7ea23565 | 920 | |
1d2ac403 | 921 | mutex_unlock(&dev->filelist_mutex); |
d38ceaf9 AD |
922 | return 0; |
923 | } | |
924 | ||
06ab6832 | 925 | static const struct drm_info_list amdgpu_debugfs_gem_list[] = { |
d38ceaf9 AD |
926 | {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, |
927 | }; | |
928 | #endif | |
929 | ||
75758255 | 930 | int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
931 | { |
932 | #if defined(CONFIG_DEBUG_FS) | |
9987d70d XY |
933 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, |
934 | ARRAY_SIZE(amdgpu_debugfs_gem_list)); | |
d38ceaf9 AD |
935 | #endif |
936 | return 0; | |
937 | } |