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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/ktime.h> | |
568d7c76 | 29 | #include <linux/pagemap.h> |
d38ceaf9 AD |
30 | #include <drm/drmP.h> |
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
33 | ||
34 | void amdgpu_gem_object_free(struct drm_gem_object *gobj) | |
35 | { | |
36 | struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); | |
37 | ||
38 | if (robj) { | |
39 | if (robj->gem_base.import_attach) | |
40 | drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); | |
9298e52f | 41 | amdgpu_mn_unregister(robj); |
d38ceaf9 AD |
42 | amdgpu_bo_unref(&robj); |
43 | } | |
44 | } | |
45 | ||
46 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, | |
e1eb899b CK |
47 | int alignment, u32 initial_domain, |
48 | u64 flags, bool kernel, | |
49 | struct reservation_object *resv, | |
50 | struct drm_gem_object **obj) | |
d38ceaf9 | 51 | { |
e1eb899b | 52 | struct amdgpu_bo *bo; |
d38ceaf9 AD |
53 | int r; |
54 | ||
55 | *obj = NULL; | |
56 | /* At least align on page size */ | |
57 | if (alignment < PAGE_SIZE) { | |
58 | alignment = PAGE_SIZE; | |
59 | } | |
60 | ||
d38ceaf9 | 61 | retry: |
72d7668b | 62 | r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, |
e1eb899b | 63 | flags, NULL, resv, 0, &bo); |
d38ceaf9 AD |
64 | if (r) { |
65 | if (r != -ERESTARTSYS) { | |
8e96e372 RH |
66 | if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { |
67 | flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
68 | goto retry; | |
69 | } | |
70 | ||
d38ceaf9 AD |
71 | if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { |
72 | initial_domain |= AMDGPU_GEM_DOMAIN_GTT; | |
73 | goto retry; | |
74 | } | |
75 | DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", | |
76 | size, initial_domain, alignment, r); | |
77 | } | |
78 | return r; | |
79 | } | |
e1eb899b | 80 | *obj = &bo->gem_base; |
d38ceaf9 | 81 | |
d38ceaf9 AD |
82 | return 0; |
83 | } | |
84 | ||
418aa0c2 | 85 | void amdgpu_gem_force_release(struct amdgpu_device *adev) |
d38ceaf9 | 86 | { |
418aa0c2 CK |
87 | struct drm_device *ddev = adev->ddev; |
88 | struct drm_file *file; | |
d38ceaf9 | 89 | |
1d2ac403 | 90 | mutex_lock(&ddev->filelist_mutex); |
418aa0c2 CK |
91 | |
92 | list_for_each_entry(file, &ddev->filelist, lhead) { | |
93 | struct drm_gem_object *gobj; | |
94 | int handle; | |
95 | ||
96 | WARN_ONCE(1, "Still active user space clients!\n"); | |
97 | spin_lock(&file->table_lock); | |
98 | idr_for_each_entry(&file->object_idr, gobj, handle) { | |
99 | WARN_ONCE(1, "And also active allocations!\n"); | |
f62facc2 | 100 | drm_gem_object_put_unlocked(gobj); |
418aa0c2 CK |
101 | } |
102 | idr_destroy(&file->object_idr); | |
103 | spin_unlock(&file->table_lock); | |
104 | } | |
105 | ||
1d2ac403 | 106 | mutex_unlock(&ddev->filelist_mutex); |
d38ceaf9 AD |
107 | } |
108 | ||
109 | /* | |
110 | * Call from drm_gem_handle_create which appear in both new and open ioctl | |
111 | * case. | |
112 | */ | |
a7d64de6 CK |
113 | int amdgpu_gem_object_open(struct drm_gem_object *obj, |
114 | struct drm_file *file_priv) | |
d38ceaf9 | 115 | { |
765e7fbf | 116 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); |
a7d64de6 | 117 | struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); |
d38ceaf9 AD |
118 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
119 | struct amdgpu_vm *vm = &fpriv->vm; | |
120 | struct amdgpu_bo_va *bo_va; | |
4f5839c5 | 121 | struct mm_struct *mm; |
d38ceaf9 | 122 | int r; |
4f5839c5 CK |
123 | |
124 | mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); | |
125 | if (mm && mm != current->mm) | |
126 | return -EPERM; | |
127 | ||
e1eb899b CK |
128 | if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && |
129 | abo->tbo.resv != vm->root.base.bo->tbo.resv) | |
130 | return -EPERM; | |
131 | ||
765e7fbf | 132 | r = amdgpu_bo_reserve(abo, false); |
e98c1b0d | 133 | if (r) |
d38ceaf9 | 134 | return r; |
d38ceaf9 | 135 | |
765e7fbf | 136 | bo_va = amdgpu_vm_bo_find(vm, abo); |
d38ceaf9 | 137 | if (!bo_va) { |
765e7fbf | 138 | bo_va = amdgpu_vm_bo_add(adev, vm, abo); |
d38ceaf9 AD |
139 | } else { |
140 | ++bo_va->ref_count; | |
141 | } | |
765e7fbf | 142 | amdgpu_bo_unreserve(abo); |
d38ceaf9 AD |
143 | return 0; |
144 | } | |
145 | ||
146 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
147 | struct drm_file *file_priv) | |
148 | { | |
b5a5ec55 | 149 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); |
a7d64de6 | 150 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
d38ceaf9 AD |
151 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
152 | struct amdgpu_vm *vm = &fpriv->vm; | |
b5a5ec55 CK |
153 | |
154 | struct amdgpu_bo_list_entry vm_pd; | |
e1eb899b | 155 | struct list_head list, duplicates; |
b5a5ec55 CK |
156 | struct ttm_validate_buffer tv; |
157 | struct ww_acquire_ctx ticket; | |
d38ceaf9 AD |
158 | struct amdgpu_bo_va *bo_va; |
159 | int r; | |
b5a5ec55 CK |
160 | |
161 | INIT_LIST_HEAD(&list); | |
e1eb899b | 162 | INIT_LIST_HEAD(&duplicates); |
b5a5ec55 CK |
163 | |
164 | tv.bo = &bo->tbo; | |
165 | tv.shared = true; | |
166 | list_add(&tv.head, &list); | |
167 | ||
168 | amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); | |
169 | ||
e1eb899b | 170 | r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); |
d38ceaf9 AD |
171 | if (r) { |
172 | dev_err(adev->dev, "leaking bo va because " | |
173 | "we fail to reserve bo (%d)\n", r); | |
174 | return; | |
175 | } | |
b5a5ec55 | 176 | bo_va = amdgpu_vm_bo_find(vm, bo); |
5a0f3b5f CK |
177 | if (bo_va && --bo_va->ref_count == 0) { |
178 | amdgpu_vm_bo_rmv(adev, bo_va); | |
179 | ||
3f3333f8 | 180 | if (amdgpu_vm_ready(vm)) { |
5a0f3b5f | 181 | struct dma_fence *fence = NULL; |
23e0563e NH |
182 | |
183 | r = amdgpu_vm_clear_freed(adev, vm, &fence); | |
184 | if (unlikely(r)) { | |
185 | dev_err(adev->dev, "failed to clear page " | |
186 | "tables on GEM object close (%d)\n", r); | |
187 | } | |
188 | ||
189 | if (fence) { | |
190 | amdgpu_bo_fence(bo, fence, true); | |
191 | dma_fence_put(fence); | |
192 | } | |
d38ceaf9 AD |
193 | } |
194 | } | |
b5a5ec55 | 195 | ttm_eu_backoff_reservation(&ticket, &list); |
d38ceaf9 AD |
196 | } |
197 | ||
d38ceaf9 AD |
198 | /* |
199 | * GEM ioctls. | |
200 | */ | |
201 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
202 | struct drm_file *filp) | |
203 | { | |
204 | struct amdgpu_device *adev = dev->dev_private; | |
e1eb899b CK |
205 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
206 | struct amdgpu_vm *vm = &fpriv->vm; | |
d38ceaf9 | 207 | union drm_amdgpu_gem_create *args = data; |
6ac7defb | 208 | uint64_t flags = args->in.domain_flags; |
d38ceaf9 | 209 | uint64_t size = args->in.bo_size; |
e1eb899b | 210 | struct reservation_object *resv = NULL; |
d38ceaf9 AD |
211 | struct drm_gem_object *gobj; |
212 | uint32_t handle; | |
d38ceaf9 AD |
213 | int r; |
214 | ||
834e0f8a | 215 | /* reject invalid gem flags */ |
6ac7defb CK |
216 | if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
217 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
218 | AMDGPU_GEM_CREATE_CPU_GTT_USWC | | |
e1eb899b | 219 | AMDGPU_GEM_CREATE_VRAM_CLEARED | |
177ae09b AR |
220 | AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | |
221 | AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) | |
222 | ||
a022c54e CK |
223 | return -EINVAL; |
224 | ||
834e0f8a AD |
225 | /* reject invalid gem domains */ |
226 | if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU | | |
227 | AMDGPU_GEM_DOMAIN_GTT | | |
228 | AMDGPU_GEM_DOMAIN_VRAM | | |
229 | AMDGPU_GEM_DOMAIN_GDS | | |
230 | AMDGPU_GEM_DOMAIN_GWS | | |
a022c54e CK |
231 | AMDGPU_GEM_DOMAIN_OA)) |
232 | return -EINVAL; | |
834e0f8a | 233 | |
d38ceaf9 AD |
234 | /* create a gem object to contain this object in */ |
235 | if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | | |
236 | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { | |
6ac7defb | 237 | flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; |
d38ceaf9 AD |
238 | if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) |
239 | size = size << AMDGPU_GDS_SHIFT; | |
240 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) | |
241 | size = size << AMDGPU_GWS_SHIFT; | |
242 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) | |
243 | size = size << AMDGPU_OA_SHIFT; | |
a022c54e CK |
244 | else |
245 | return -EINVAL; | |
d38ceaf9 AD |
246 | } |
247 | size = roundup(size, PAGE_SIZE); | |
248 | ||
e1eb899b CK |
249 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { |
250 | r = amdgpu_bo_reserve(vm->root.base.bo, false); | |
251 | if (r) | |
252 | return r; | |
253 | ||
254 | resv = vm->root.base.bo->tbo.resv; | |
255 | } | |
256 | ||
d38ceaf9 AD |
257 | r = amdgpu_gem_object_create(adev, size, args->in.alignment, |
258 | (u32)(0xffffffff & args->in.domains), | |
e1eb899b CK |
259 | flags, false, resv, &gobj); |
260 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { | |
261 | if (!r) { | |
262 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); | |
263 | ||
264 | abo->parent = amdgpu_bo_ref(vm->root.base.bo); | |
265 | } | |
266 | amdgpu_bo_unreserve(vm->root.base.bo); | |
267 | } | |
d38ceaf9 | 268 | if (r) |
a022c54e | 269 | return r; |
d38ceaf9 AD |
270 | |
271 | r = drm_gem_handle_create(filp, gobj, &handle); | |
272 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 273 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 274 | if (r) |
a022c54e | 275 | return r; |
d38ceaf9 AD |
276 | |
277 | memset(args, 0, sizeof(*args)); | |
278 | args->out.handle = handle; | |
d38ceaf9 | 279 | return 0; |
d38ceaf9 AD |
280 | } |
281 | ||
282 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
283 | struct drm_file *filp) | |
284 | { | |
285 | struct amdgpu_device *adev = dev->dev_private; | |
286 | struct drm_amdgpu_gem_userptr *args = data; | |
287 | struct drm_gem_object *gobj; | |
288 | struct amdgpu_bo *bo; | |
289 | uint32_t handle; | |
290 | int r; | |
291 | ||
292 | if (offset_in_page(args->addr | args->size)) | |
293 | return -EINVAL; | |
294 | ||
295 | /* reject unknown flag values */ | |
296 | if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | | |
297 | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | | |
298 | AMDGPU_GEM_USERPTR_REGISTER)) | |
299 | return -EINVAL; | |
300 | ||
358c258a CK |
301 | if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && |
302 | !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { | |
d38ceaf9 | 303 | |
358c258a | 304 | /* if we want to write to it we must install a MMU notifier */ |
d38ceaf9 AD |
305 | return -EACCES; |
306 | } | |
307 | ||
d38ceaf9 | 308 | /* create a gem object to contain this object in */ |
e1eb899b CK |
309 | r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, |
310 | 0, 0, NULL, &gobj); | |
d38ceaf9 | 311 | if (r) |
a022c54e | 312 | return r; |
d38ceaf9 AD |
313 | |
314 | bo = gem_to_amdgpu_bo(gobj); | |
6d7d9c5a | 315 | bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; |
1ea863fd | 316 | bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; |
d38ceaf9 AD |
317 | r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); |
318 | if (r) | |
319 | goto release_object; | |
320 | ||
321 | if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { | |
322 | r = amdgpu_mn_register(bo, args->addr); | |
323 | if (r) | |
324 | goto release_object; | |
325 | } | |
326 | ||
327 | if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { | |
2f568dbd CK |
328 | r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, |
329 | bo->tbo.ttm->pages); | |
330 | if (r) | |
d5a480b4 | 331 | goto release_object; |
2f568dbd | 332 | |
d38ceaf9 | 333 | r = amdgpu_bo_reserve(bo, true); |
2f568dbd CK |
334 | if (r) |
335 | goto free_pages; | |
d38ceaf9 AD |
336 | |
337 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); | |
338 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
339 | amdgpu_bo_unreserve(bo); | |
d38ceaf9 | 340 | if (r) |
2f568dbd | 341 | goto free_pages; |
d38ceaf9 AD |
342 | } |
343 | ||
344 | r = drm_gem_handle_create(filp, gobj, &handle); | |
345 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 346 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 347 | if (r) |
a022c54e | 348 | return r; |
d38ceaf9 AD |
349 | |
350 | args->handle = handle; | |
d38ceaf9 AD |
351 | return 0; |
352 | ||
2f568dbd | 353 | free_pages: |
c6f92f9f | 354 | release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); |
2f568dbd | 355 | |
d38ceaf9 | 356 | release_object: |
f62facc2 | 357 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 358 | |
d38ceaf9 AD |
359 | return r; |
360 | } | |
361 | ||
362 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
363 | struct drm_device *dev, | |
364 | uint32_t handle, uint64_t *offset_p) | |
365 | { | |
366 | struct drm_gem_object *gobj; | |
367 | struct amdgpu_bo *robj; | |
368 | ||
a8ad0bd8 | 369 | gobj = drm_gem_object_lookup(filp, handle); |
d38ceaf9 AD |
370 | if (gobj == NULL) { |
371 | return -ENOENT; | |
372 | } | |
373 | robj = gem_to_amdgpu_bo(gobj); | |
cc325d19 | 374 | if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || |
271c8125 | 375 | (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { |
f62facc2 | 376 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
377 | return -EPERM; |
378 | } | |
379 | *offset_p = amdgpu_bo_mmap_offset(robj); | |
f62facc2 | 380 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
381 | return 0; |
382 | } | |
383 | ||
384 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
385 | struct drm_file *filp) | |
386 | { | |
387 | union drm_amdgpu_gem_mmap *args = data; | |
388 | uint32_t handle = args->in.handle; | |
389 | memset(args, 0, sizeof(*args)); | |
390 | return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); | |
391 | } | |
392 | ||
393 | /** | |
394 | * amdgpu_gem_timeout - calculate jiffies timeout from absolute value | |
395 | * | |
396 | * @timeout_ns: timeout in ns | |
397 | * | |
398 | * Calculate the timeout in jiffies from an absolute timeout in ns. | |
399 | */ | |
400 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) | |
401 | { | |
402 | unsigned long timeout_jiffies; | |
403 | ktime_t timeout; | |
404 | ||
405 | /* clamp timeout if it's to large */ | |
406 | if (((int64_t)timeout_ns) < 0) | |
407 | return MAX_SCHEDULE_TIMEOUT; | |
408 | ||
0f117704 | 409 | timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); |
d38ceaf9 AD |
410 | if (ktime_to_ns(timeout) < 0) |
411 | return 0; | |
412 | ||
413 | timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); | |
414 | /* clamp timeout to avoid unsigned-> signed overflow */ | |
415 | if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) | |
416 | return MAX_SCHEDULE_TIMEOUT - 1; | |
417 | ||
418 | return timeout_jiffies; | |
419 | } | |
420 | ||
421 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
422 | struct drm_file *filp) | |
423 | { | |
d38ceaf9 AD |
424 | union drm_amdgpu_gem_wait_idle *args = data; |
425 | struct drm_gem_object *gobj; | |
426 | struct amdgpu_bo *robj; | |
427 | uint32_t handle = args->in.handle; | |
428 | unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); | |
429 | int r = 0; | |
430 | long ret; | |
431 | ||
a8ad0bd8 | 432 | gobj = drm_gem_object_lookup(filp, handle); |
d38ceaf9 AD |
433 | if (gobj == NULL) { |
434 | return -ENOENT; | |
435 | } | |
436 | robj = gem_to_amdgpu_bo(gobj); | |
0fea2ed6 CW |
437 | ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, |
438 | timeout); | |
d38ceaf9 AD |
439 | |
440 | /* ret == 0 means not signaled, | |
441 | * ret > 0 means signaled | |
442 | * ret < 0 means interrupted before timeout | |
443 | */ | |
444 | if (ret >= 0) { | |
445 | memset(args, 0, sizeof(*args)); | |
446 | args->out.status = (ret == 0); | |
447 | } else | |
448 | r = ret; | |
449 | ||
f62facc2 | 450 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
451 | return r; |
452 | } | |
453 | ||
454 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
455 | struct drm_file *filp) | |
456 | { | |
457 | struct drm_amdgpu_gem_metadata *args = data; | |
458 | struct drm_gem_object *gobj; | |
459 | struct amdgpu_bo *robj; | |
460 | int r = -1; | |
461 | ||
462 | DRM_DEBUG("%d \n", args->handle); | |
a8ad0bd8 | 463 | gobj = drm_gem_object_lookup(filp, args->handle); |
d38ceaf9 AD |
464 | if (gobj == NULL) |
465 | return -ENOENT; | |
466 | robj = gem_to_amdgpu_bo(gobj); | |
467 | ||
468 | r = amdgpu_bo_reserve(robj, false); | |
469 | if (unlikely(r != 0)) | |
470 | goto out; | |
471 | ||
472 | if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { | |
473 | amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); | |
474 | r = amdgpu_bo_get_metadata(robj, args->data.data, | |
475 | sizeof(args->data.data), | |
476 | &args->data.data_size_bytes, | |
477 | &args->data.flags); | |
478 | } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { | |
0913eab6 DC |
479 | if (args->data.data_size_bytes > sizeof(args->data.data)) { |
480 | r = -EINVAL; | |
481 | goto unreserve; | |
482 | } | |
d38ceaf9 AD |
483 | r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); |
484 | if (!r) | |
485 | r = amdgpu_bo_set_metadata(robj, args->data.data, | |
486 | args->data.data_size_bytes, | |
487 | args->data.flags); | |
488 | } | |
489 | ||
0913eab6 | 490 | unreserve: |
d38ceaf9 AD |
491 | amdgpu_bo_unreserve(robj); |
492 | out: | |
f62facc2 | 493 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
494 | return r; |
495 | } | |
496 | ||
497 | /** | |
498 | * amdgpu_gem_va_update_vm -update the bo_va in its VM | |
499 | * | |
500 | * @adev: amdgpu_device pointer | |
dc54d3d1 | 501 | * @vm: vm to update |
d38ceaf9 | 502 | * @bo_va: bo_va to update |
2ffdaafb | 503 | * @list: validation list |
dc54d3d1 | 504 | * @operation: map, unmap or clear |
d38ceaf9 | 505 | * |
2ffdaafb | 506 | * Update the bo_va directly after setting its address. Errors are not |
d38ceaf9 AD |
507 | * vital here, so they are not reported back to userspace. |
508 | */ | |
509 | static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, | |
dc54d3d1 | 510 | struct amdgpu_vm *vm, |
f7da30d9 | 511 | struct amdgpu_bo_va *bo_va, |
2ffdaafb | 512 | struct list_head *list, |
f7da30d9 | 513 | uint32_t operation) |
d38ceaf9 | 514 | { |
3f3333f8 | 515 | int r; |
d38ceaf9 | 516 | |
3f3333f8 CK |
517 | if (!amdgpu_vm_ready(vm)) |
518 | return; | |
e410b5cb | 519 | |
194d2161 | 520 | r = amdgpu_vm_update_directories(adev, vm); |
43c27fb5 | 521 | if (r) |
2ffdaafb | 522 | goto error; |
d38ceaf9 | 523 | |
f3467818 | 524 | r = amdgpu_vm_clear_freed(adev, vm, NULL); |
d38ceaf9 | 525 | if (r) |
2ffdaafb | 526 | goto error; |
194a3364 | 527 | |
80f95c57 CK |
528 | if (operation == AMDGPU_VA_OP_MAP || |
529 | operation == AMDGPU_VA_OP_REPLACE) | |
05dcb5c8 | 530 | r = amdgpu_vm_bo_update(adev, bo_va, false); |
d38ceaf9 | 531 | |
2ffdaafb | 532 | error: |
68fdd3df | 533 | if (r && r != -ERESTARTSYS) |
d38ceaf9 AD |
534 | DRM_ERROR("Couldn't update BO_VA (%d)\n", r); |
535 | } | |
536 | ||
d38ceaf9 AD |
537 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, |
538 | struct drm_file *filp) | |
539 | { | |
b85891bd JZ |
540 | const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | |
541 | AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | | |
66e02bc3 | 542 | AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; |
b85891bd JZ |
543 | const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | |
544 | AMDGPU_VM_PAGE_PRT; | |
545 | ||
34b5f6a6 | 546 | struct drm_amdgpu_gem_va *args = data; |
d38ceaf9 AD |
547 | struct drm_gem_object *gobj; |
548 | struct amdgpu_device *adev = dev->dev_private; | |
549 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
765e7fbf | 550 | struct amdgpu_bo *abo; |
d38ceaf9 | 551 | struct amdgpu_bo_va *bo_va; |
b88c8796 CK |
552 | struct amdgpu_bo_list_entry vm_pd; |
553 | struct ttm_validate_buffer tv; | |
49b02b18 | 554 | struct ww_acquire_ctx ticket; |
e1eb899b | 555 | struct list_head list, duplicates; |
5463545b | 556 | uint64_t va_flags; |
d38ceaf9 AD |
557 | int r = 0; |
558 | ||
34b5f6a6 | 559 | if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { |
d38ceaf9 | 560 | dev_err(&dev->pdev->dev, |
ff4cd389 CK |
561 | "va_address 0x%LX is in reserved area 0x%LX\n", |
562 | args->va_address, AMDGPU_VA_RESERVED_SIZE); | |
d38ceaf9 AD |
563 | return -EINVAL; |
564 | } | |
565 | ||
b85891bd JZ |
566 | if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { |
567 | dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n", | |
568 | args->flags); | |
d38ceaf9 AD |
569 | return -EINVAL; |
570 | } | |
571 | ||
34b5f6a6 | 572 | switch (args->operation) { |
d38ceaf9 AD |
573 | case AMDGPU_VA_OP_MAP: |
574 | case AMDGPU_VA_OP_UNMAP: | |
dc54d3d1 | 575 | case AMDGPU_VA_OP_CLEAR: |
80f95c57 | 576 | case AMDGPU_VA_OP_REPLACE: |
d38ceaf9 AD |
577 | break; |
578 | default: | |
579 | dev_err(&dev->pdev->dev, "unsupported operation %d\n", | |
34b5f6a6 | 580 | args->operation); |
d38ceaf9 AD |
581 | return -EINVAL; |
582 | } | |
583 | ||
49b02b18 | 584 | INIT_LIST_HEAD(&list); |
e1eb899b | 585 | INIT_LIST_HEAD(&duplicates); |
dc54d3d1 CK |
586 | if ((args->operation != AMDGPU_VA_OP_CLEAR) && |
587 | !(args->flags & AMDGPU_VM_PAGE_PRT)) { | |
b85891bd JZ |
588 | gobj = drm_gem_object_lookup(filp, args->handle); |
589 | if (gobj == NULL) | |
590 | return -ENOENT; | |
591 | abo = gem_to_amdgpu_bo(gobj); | |
592 | tv.bo = &abo->tbo; | |
593 | tv.shared = false; | |
594 | list_add(&tv.head, &list); | |
595 | } else { | |
596 | gobj = NULL; | |
597 | abo = NULL; | |
598 | } | |
49b02b18 | 599 | |
b88c8796 | 600 | amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); |
b5a5ec55 | 601 | |
e1eb899b | 602 | r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); |
b85891bd JZ |
603 | if (r) |
604 | goto error_unref; | |
34b5f6a6 | 605 | |
b85891bd JZ |
606 | if (abo) { |
607 | bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); | |
608 | if (!bo_va) { | |
609 | r = -ENOENT; | |
610 | goto error_backoff; | |
611 | } | |
dc54d3d1 | 612 | } else if (args->operation != AMDGPU_VA_OP_CLEAR) { |
b85891bd | 613 | bo_va = fpriv->prt_va; |
dc54d3d1 CK |
614 | } else { |
615 | bo_va = NULL; | |
d38ceaf9 AD |
616 | } |
617 | ||
34b5f6a6 | 618 | switch (args->operation) { |
d38ceaf9 | 619 | case AMDGPU_VA_OP_MAP: |
ec681545 | 620 | r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, |
663e4577 CK |
621 | args->map_size); |
622 | if (r) | |
623 | goto error_backoff; | |
5463545b | 624 | |
663e4577 | 625 | va_flags = amdgpu_vm_get_pte_flags(adev, args->flags); |
34b5f6a6 CK |
626 | r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, |
627 | args->offset_in_bo, args->map_size, | |
9f7eb536 | 628 | va_flags); |
d38ceaf9 AD |
629 | break; |
630 | case AMDGPU_VA_OP_UNMAP: | |
34b5f6a6 | 631 | r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); |
d38ceaf9 | 632 | break; |
dc54d3d1 CK |
633 | |
634 | case AMDGPU_VA_OP_CLEAR: | |
635 | r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, | |
636 | args->va_address, | |
637 | args->map_size); | |
638 | break; | |
80f95c57 | 639 | case AMDGPU_VA_OP_REPLACE: |
ec681545 | 640 | r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, |
80f95c57 CK |
641 | args->map_size); |
642 | if (r) | |
643 | goto error_backoff; | |
644 | ||
645 | va_flags = amdgpu_vm_get_pte_flags(adev, args->flags); | |
646 | r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, | |
647 | args->offset_in_bo, args->map_size, | |
648 | va_flags); | |
649 | break; | |
d38ceaf9 AD |
650 | default: |
651 | break; | |
652 | } | |
b85891bd | 653 | if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) |
dc54d3d1 CK |
654 | amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list, |
655 | args->operation); | |
b85891bd JZ |
656 | |
657 | error_backoff: | |
2ffdaafb | 658 | ttm_eu_backoff_reservation(&ticket, &list); |
e98c1b0d | 659 | |
b85891bd | 660 | error_unref: |
f62facc2 | 661 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
662 | return r; |
663 | } | |
664 | ||
665 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
666 | struct drm_file *filp) | |
667 | { | |
e1eb899b | 668 | struct amdgpu_device *adev = dev->dev_private; |
d38ceaf9 AD |
669 | struct drm_amdgpu_gem_op *args = data; |
670 | struct drm_gem_object *gobj; | |
671 | struct amdgpu_bo *robj; | |
672 | int r; | |
673 | ||
a8ad0bd8 | 674 | gobj = drm_gem_object_lookup(filp, args->handle); |
d38ceaf9 AD |
675 | if (gobj == NULL) { |
676 | return -ENOENT; | |
677 | } | |
678 | robj = gem_to_amdgpu_bo(gobj); | |
679 | ||
680 | r = amdgpu_bo_reserve(robj, false); | |
681 | if (unlikely(r)) | |
682 | goto out; | |
683 | ||
684 | switch (args->op) { | |
685 | case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { | |
686 | struct drm_amdgpu_gem_create_in info; | |
7ecc245a | 687 | void __user *out = u64_to_user_ptr(args->value); |
d38ceaf9 AD |
688 | |
689 | info.bo_size = robj->gem_base.size; | |
690 | info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; | |
6d7d9c5a | 691 | info.domains = robj->preferred_domains; |
d38ceaf9 | 692 | info.domain_flags = robj->flags; |
4c28fb0b | 693 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
694 | if (copy_to_user(out, &info, sizeof(info))) |
695 | r = -EFAULT; | |
696 | break; | |
697 | } | |
d8f65a23 | 698 | case AMDGPU_GEM_OP_SET_PLACEMENT: |
803d89ad CJHR |
699 | if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { |
700 | r = -EINVAL; | |
701 | amdgpu_bo_unreserve(robj); | |
702 | break; | |
703 | } | |
cc325d19 | 704 | if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { |
d38ceaf9 | 705 | r = -EPERM; |
4c28fb0b | 706 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
707 | break; |
708 | } | |
6d7d9c5a | 709 | robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | |
1ea863fd CK |
710 | AMDGPU_GEM_DOMAIN_GTT | |
711 | AMDGPU_GEM_DOMAIN_CPU); | |
6d7d9c5a | 712 | robj->allowed_domains = robj->preferred_domains; |
1ea863fd CK |
713 | if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) |
714 | robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; | |
715 | ||
e1eb899b CK |
716 | if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) |
717 | amdgpu_vm_bo_invalidate(adev, robj, true); | |
718 | ||
4c28fb0b | 719 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
720 | break; |
721 | default: | |
4c28fb0b | 722 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
723 | r = -EINVAL; |
724 | } | |
725 | ||
d38ceaf9 | 726 | out: |
f62facc2 | 727 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
728 | return r; |
729 | } | |
730 | ||
731 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
732 | struct drm_device *dev, | |
733 | struct drm_mode_create_dumb *args) | |
734 | { | |
735 | struct amdgpu_device *adev = dev->dev_private; | |
736 | struct drm_gem_object *gobj; | |
737 | uint32_t handle; | |
738 | int r; | |
739 | ||
8e911ab7 LP |
740 | args->pitch = amdgpu_align_pitch(adev, args->width, |
741 | DIV_ROUND_UP(args->bpp, 8), 0); | |
54ef0b54 | 742 | args->size = (u64)args->pitch * args->height; |
d38ceaf9 AD |
743 | args->size = ALIGN(args->size, PAGE_SIZE); |
744 | ||
745 | r = amdgpu_gem_object_create(adev, args->size, 0, | |
746 | AMDGPU_GEM_DOMAIN_VRAM, | |
857d913d | 747 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, |
e1eb899b | 748 | false, NULL, &gobj); |
d38ceaf9 AD |
749 | if (r) |
750 | return -ENOMEM; | |
751 | ||
752 | r = drm_gem_handle_create(file_priv, gobj, &handle); | |
753 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 754 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
755 | if (r) { |
756 | return r; | |
757 | } | |
758 | args->handle = handle; | |
759 | return 0; | |
760 | } | |
761 | ||
762 | #if defined(CONFIG_DEBUG_FS) | |
7ea23565 CK |
763 | static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) |
764 | { | |
765 | struct drm_gem_object *gobj = ptr; | |
766 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); | |
767 | struct seq_file *m = data; | |
768 | ||
769 | unsigned domain; | |
770 | const char *placement; | |
771 | unsigned pin_count; | |
b8e0e6e1 | 772 | uint64_t offset; |
7ea23565 CK |
773 | |
774 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
775 | switch (domain) { | |
776 | case AMDGPU_GEM_DOMAIN_VRAM: | |
777 | placement = "VRAM"; | |
778 | break; | |
779 | case AMDGPU_GEM_DOMAIN_GTT: | |
780 | placement = " GTT"; | |
781 | break; | |
782 | case AMDGPU_GEM_DOMAIN_CPU: | |
783 | default: | |
784 | placement = " CPU"; | |
785 | break; | |
786 | } | |
b8e0e6e1 CK |
787 | seq_printf(m, "\t0x%08x: %12ld byte %s", |
788 | id, amdgpu_bo_size(bo), placement); | |
789 | ||
6aa7de05 | 790 | offset = READ_ONCE(bo->tbo.mem.start); |
b8e0e6e1 CK |
791 | if (offset != AMDGPU_BO_INVALID_OFFSET) |
792 | seq_printf(m, " @ 0x%010Lx", offset); | |
7ea23565 | 793 | |
6aa7de05 | 794 | pin_count = READ_ONCE(bo->pin_count); |
7ea23565 CK |
795 | if (pin_count) |
796 | seq_printf(m, " pin count %d", pin_count); | |
797 | seq_printf(m, "\n"); | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
d38ceaf9 AD |
802 | static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) |
803 | { | |
804 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
805 | struct drm_device *dev = node->minor->dev; | |
7ea23565 CK |
806 | struct drm_file *file; |
807 | int r; | |
d38ceaf9 | 808 | |
1d2ac403 | 809 | r = mutex_lock_interruptible(&dev->filelist_mutex); |
7ea23565 CK |
810 | if (r) |
811 | return r; | |
812 | ||
813 | list_for_each_entry(file, &dev->filelist, lhead) { | |
814 | struct task_struct *task; | |
815 | ||
816 | /* | |
817 | * Although we have a valid reference on file->pid, that does | |
818 | * not guarantee that the task_struct who called get_pid() is | |
819 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
820 | * Therefore, we need to protect this ->comm access using RCU. | |
821 | */ | |
822 | rcu_read_lock(); | |
823 | task = pid_task(file->pid, PIDTYPE_PID); | |
824 | seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), | |
825 | task ? task->comm : "<unknown>"); | |
826 | rcu_read_unlock(); | |
827 | ||
828 | spin_lock(&file->table_lock); | |
829 | idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); | |
830 | spin_unlock(&file->table_lock); | |
d38ceaf9 | 831 | } |
7ea23565 | 832 | |
1d2ac403 | 833 | mutex_unlock(&dev->filelist_mutex); |
d38ceaf9 AD |
834 | return 0; |
835 | } | |
836 | ||
06ab6832 | 837 | static const struct drm_info_list amdgpu_debugfs_gem_list[] = { |
d38ceaf9 AD |
838 | {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, |
839 | }; | |
840 | #endif | |
841 | ||
842 | int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) | |
843 | { | |
844 | #if defined(CONFIG_DEBUG_FS) | |
845 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); | |
846 | #endif | |
847 | return 0; | |
848 | } |