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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/ktime.h> | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu.h" | |
32 | ||
33 | void amdgpu_gem_object_free(struct drm_gem_object *gobj) | |
34 | { | |
35 | struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); | |
36 | ||
37 | if (robj) { | |
38 | if (robj->gem_base.import_attach) | |
39 | drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); | |
9298e52f | 40 | amdgpu_mn_unregister(robj); |
d38ceaf9 AD |
41 | amdgpu_bo_unref(&robj); |
42 | } | |
43 | } | |
44 | ||
45 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, | |
46 | int alignment, u32 initial_domain, | |
47 | u64 flags, bool kernel, | |
48 | struct drm_gem_object **obj) | |
49 | { | |
50 | struct amdgpu_bo *robj; | |
51 | unsigned long max_size; | |
52 | int r; | |
53 | ||
54 | *obj = NULL; | |
55 | /* At least align on page size */ | |
56 | if (alignment < PAGE_SIZE) { | |
57 | alignment = PAGE_SIZE; | |
58 | } | |
59 | ||
60 | if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) { | |
61 | /* Maximum bo size is the unpinned gtt size since we use the gtt to | |
62 | * handle vram to system pool migrations. | |
63 | */ | |
64 | max_size = adev->mc.gtt_size - adev->gart_pin_size; | |
65 | if (size > max_size) { | |
66 | DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", | |
67 | size >> 20, max_size >> 20); | |
68 | return -ENOMEM; | |
69 | } | |
70 | } | |
71 | retry: | |
72d7668b CK |
72 | r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, |
73 | flags, NULL, NULL, &robj); | |
d38ceaf9 AD |
74 | if (r) { |
75 | if (r != -ERESTARTSYS) { | |
76 | if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
77 | initial_domain |= AMDGPU_GEM_DOMAIN_GTT; | |
78 | goto retry; | |
79 | } | |
80 | DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", | |
81 | size, initial_domain, alignment, r); | |
82 | } | |
83 | return r; | |
84 | } | |
85 | *obj = &robj->gem_base; | |
86 | robj->pid = task_pid_nr(current); | |
87 | ||
88 | mutex_lock(&adev->gem.mutex); | |
89 | list_add_tail(&robj->list, &adev->gem.objects); | |
90 | mutex_unlock(&adev->gem.mutex); | |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
95 | int amdgpu_gem_init(struct amdgpu_device *adev) | |
96 | { | |
97 | INIT_LIST_HEAD(&adev->gem.objects); | |
98 | return 0; | |
99 | } | |
100 | ||
101 | void amdgpu_gem_fini(struct amdgpu_device *adev) | |
102 | { | |
103 | amdgpu_bo_force_delete(adev); | |
104 | } | |
105 | ||
106 | /* | |
107 | * Call from drm_gem_handle_create which appear in both new and open ioctl | |
108 | * case. | |
109 | */ | |
110 | int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) | |
111 | { | |
112 | struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); | |
113 | struct amdgpu_device *adev = rbo->adev; | |
114 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
115 | struct amdgpu_vm *vm = &fpriv->vm; | |
116 | struct amdgpu_bo_va *bo_va; | |
117 | int r; | |
d38ceaf9 | 118 | r = amdgpu_bo_reserve(rbo, false); |
e98c1b0d | 119 | if (r) |
d38ceaf9 | 120 | return r; |
d38ceaf9 AD |
121 | |
122 | bo_va = amdgpu_vm_bo_find(vm, rbo); | |
123 | if (!bo_va) { | |
124 | bo_va = amdgpu_vm_bo_add(adev, vm, rbo); | |
125 | } else { | |
126 | ++bo_va->ref_count; | |
127 | } | |
128 | amdgpu_bo_unreserve(rbo); | |
d38ceaf9 AD |
129 | return 0; |
130 | } | |
131 | ||
132 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
133 | struct drm_file *file_priv) | |
134 | { | |
135 | struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); | |
136 | struct amdgpu_device *adev = rbo->adev; | |
137 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
138 | struct amdgpu_vm *vm = &fpriv->vm; | |
139 | struct amdgpu_bo_va *bo_va; | |
140 | int r; | |
d38ceaf9 AD |
141 | r = amdgpu_bo_reserve(rbo, true); |
142 | if (r) { | |
143 | dev_err(adev->dev, "leaking bo va because " | |
144 | "we fail to reserve bo (%d)\n", r); | |
145 | return; | |
146 | } | |
147 | bo_va = amdgpu_vm_bo_find(vm, rbo); | |
148 | if (bo_va) { | |
149 | if (--bo_va->ref_count == 0) { | |
150 | amdgpu_vm_bo_rmv(adev, bo_va); | |
151 | } | |
152 | } | |
153 | amdgpu_bo_unreserve(rbo); | |
154 | } | |
155 | ||
156 | static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) | |
157 | { | |
158 | if (r == -EDEADLK) { | |
159 | r = amdgpu_gpu_reset(adev); | |
160 | if (!r) | |
161 | r = -EAGAIN; | |
162 | } | |
163 | return r; | |
164 | } | |
165 | ||
166 | /* | |
167 | * GEM ioctls. | |
168 | */ | |
169 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
170 | struct drm_file *filp) | |
171 | { | |
172 | struct amdgpu_device *adev = dev->dev_private; | |
173 | union drm_amdgpu_gem_create *args = data; | |
174 | uint64_t size = args->in.bo_size; | |
175 | struct drm_gem_object *gobj; | |
176 | uint32_t handle; | |
177 | bool kernel = false; | |
178 | int r; | |
179 | ||
d38ceaf9 AD |
180 | /* create a gem object to contain this object in */ |
181 | if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | | |
182 | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { | |
183 | kernel = true; | |
184 | if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) | |
185 | size = size << AMDGPU_GDS_SHIFT; | |
186 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) | |
187 | size = size << AMDGPU_GWS_SHIFT; | |
188 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) | |
189 | size = size << AMDGPU_OA_SHIFT; | |
190 | else { | |
191 | r = -EINVAL; | |
192 | goto error_unlock; | |
193 | } | |
194 | } | |
195 | size = roundup(size, PAGE_SIZE); | |
196 | ||
197 | r = amdgpu_gem_object_create(adev, size, args->in.alignment, | |
198 | (u32)(0xffffffff & args->in.domains), | |
199 | args->in.domain_flags, | |
200 | kernel, &gobj); | |
201 | if (r) | |
202 | goto error_unlock; | |
203 | ||
204 | r = drm_gem_handle_create(filp, gobj, &handle); | |
205 | /* drop reference from allocate - handle holds it now */ | |
206 | drm_gem_object_unreference_unlocked(gobj); | |
207 | if (r) | |
208 | goto error_unlock; | |
209 | ||
210 | memset(args, 0, sizeof(*args)); | |
211 | args->out.handle = handle; | |
d38ceaf9 AD |
212 | return 0; |
213 | ||
214 | error_unlock: | |
d38ceaf9 AD |
215 | r = amdgpu_gem_handle_lockup(adev, r); |
216 | return r; | |
217 | } | |
218 | ||
219 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
220 | struct drm_file *filp) | |
221 | { | |
222 | struct amdgpu_device *adev = dev->dev_private; | |
223 | struct drm_amdgpu_gem_userptr *args = data; | |
224 | struct drm_gem_object *gobj; | |
225 | struct amdgpu_bo *bo; | |
226 | uint32_t handle; | |
227 | int r; | |
228 | ||
229 | if (offset_in_page(args->addr | args->size)) | |
230 | return -EINVAL; | |
231 | ||
232 | /* reject unknown flag values */ | |
233 | if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | | |
234 | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | | |
235 | AMDGPU_GEM_USERPTR_REGISTER)) | |
236 | return -EINVAL; | |
237 | ||
238 | if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) || | |
239 | !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { | |
240 | ||
241 | /* if we want to write to it we must require anonymous | |
242 | memory and install a MMU notifier */ | |
243 | return -EACCES; | |
244 | } | |
245 | ||
d38ceaf9 AD |
246 | /* create a gem object to contain this object in */ |
247 | r = amdgpu_gem_object_create(adev, args->size, 0, | |
248 | AMDGPU_GEM_DOMAIN_CPU, 0, | |
249 | 0, &gobj); | |
250 | if (r) | |
251 | goto handle_lockup; | |
252 | ||
253 | bo = gem_to_amdgpu_bo(gobj); | |
254 | r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); | |
255 | if (r) | |
256 | goto release_object; | |
257 | ||
258 | if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { | |
259 | r = amdgpu_mn_register(bo, args->addr); | |
260 | if (r) | |
261 | goto release_object; | |
262 | } | |
263 | ||
264 | if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { | |
265 | down_read(¤t->mm->mmap_sem); | |
266 | r = amdgpu_bo_reserve(bo, true); | |
267 | if (r) { | |
268 | up_read(¤t->mm->mmap_sem); | |
269 | goto release_object; | |
270 | } | |
271 | ||
272 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); | |
273 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
274 | amdgpu_bo_unreserve(bo); | |
275 | up_read(¤t->mm->mmap_sem); | |
276 | if (r) | |
277 | goto release_object; | |
278 | } | |
279 | ||
280 | r = drm_gem_handle_create(filp, gobj, &handle); | |
281 | /* drop reference from allocate - handle holds it now */ | |
282 | drm_gem_object_unreference_unlocked(gobj); | |
283 | if (r) | |
284 | goto handle_lockup; | |
285 | ||
286 | args->handle = handle; | |
d38ceaf9 AD |
287 | return 0; |
288 | ||
289 | release_object: | |
290 | drm_gem_object_unreference_unlocked(gobj); | |
291 | ||
292 | handle_lockup: | |
d38ceaf9 AD |
293 | r = amdgpu_gem_handle_lockup(adev, r); |
294 | ||
295 | return r; | |
296 | } | |
297 | ||
298 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
299 | struct drm_device *dev, | |
300 | uint32_t handle, uint64_t *offset_p) | |
301 | { | |
302 | struct drm_gem_object *gobj; | |
303 | struct amdgpu_bo *robj; | |
304 | ||
305 | gobj = drm_gem_object_lookup(dev, filp, handle); | |
306 | if (gobj == NULL) { | |
307 | return -ENOENT; | |
308 | } | |
309 | robj = gem_to_amdgpu_bo(gobj); | |
271c8125 CK |
310 | if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) || |
311 | (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { | |
d38ceaf9 AD |
312 | drm_gem_object_unreference_unlocked(gobj); |
313 | return -EPERM; | |
314 | } | |
315 | *offset_p = amdgpu_bo_mmap_offset(robj); | |
316 | drm_gem_object_unreference_unlocked(gobj); | |
317 | return 0; | |
318 | } | |
319 | ||
320 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
321 | struct drm_file *filp) | |
322 | { | |
323 | union drm_amdgpu_gem_mmap *args = data; | |
324 | uint32_t handle = args->in.handle; | |
325 | memset(args, 0, sizeof(*args)); | |
326 | return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); | |
327 | } | |
328 | ||
329 | /** | |
330 | * amdgpu_gem_timeout - calculate jiffies timeout from absolute value | |
331 | * | |
332 | * @timeout_ns: timeout in ns | |
333 | * | |
334 | * Calculate the timeout in jiffies from an absolute timeout in ns. | |
335 | */ | |
336 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) | |
337 | { | |
338 | unsigned long timeout_jiffies; | |
339 | ktime_t timeout; | |
340 | ||
341 | /* clamp timeout if it's to large */ | |
342 | if (((int64_t)timeout_ns) < 0) | |
343 | return MAX_SCHEDULE_TIMEOUT; | |
344 | ||
0f117704 | 345 | timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); |
d38ceaf9 AD |
346 | if (ktime_to_ns(timeout) < 0) |
347 | return 0; | |
348 | ||
349 | timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); | |
350 | /* clamp timeout to avoid unsigned-> signed overflow */ | |
351 | if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) | |
352 | return MAX_SCHEDULE_TIMEOUT - 1; | |
353 | ||
354 | return timeout_jiffies; | |
355 | } | |
356 | ||
357 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
358 | struct drm_file *filp) | |
359 | { | |
360 | struct amdgpu_device *adev = dev->dev_private; | |
361 | union drm_amdgpu_gem_wait_idle *args = data; | |
362 | struct drm_gem_object *gobj; | |
363 | struct amdgpu_bo *robj; | |
364 | uint32_t handle = args->in.handle; | |
365 | unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); | |
366 | int r = 0; | |
367 | long ret; | |
368 | ||
369 | gobj = drm_gem_object_lookup(dev, filp, handle); | |
370 | if (gobj == NULL) { | |
371 | return -ENOENT; | |
372 | } | |
373 | robj = gem_to_amdgpu_bo(gobj); | |
374 | if (timeout == 0) | |
375 | ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true); | |
376 | else | |
377 | ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout); | |
378 | ||
379 | /* ret == 0 means not signaled, | |
380 | * ret > 0 means signaled | |
381 | * ret < 0 means interrupted before timeout | |
382 | */ | |
383 | if (ret >= 0) { | |
384 | memset(args, 0, sizeof(*args)); | |
385 | args->out.status = (ret == 0); | |
386 | } else | |
387 | r = ret; | |
388 | ||
389 | drm_gem_object_unreference_unlocked(gobj); | |
390 | r = amdgpu_gem_handle_lockup(adev, r); | |
391 | return r; | |
392 | } | |
393 | ||
394 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
395 | struct drm_file *filp) | |
396 | { | |
397 | struct drm_amdgpu_gem_metadata *args = data; | |
398 | struct drm_gem_object *gobj; | |
399 | struct amdgpu_bo *robj; | |
400 | int r = -1; | |
401 | ||
402 | DRM_DEBUG("%d \n", args->handle); | |
403 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
404 | if (gobj == NULL) | |
405 | return -ENOENT; | |
406 | robj = gem_to_amdgpu_bo(gobj); | |
407 | ||
408 | r = amdgpu_bo_reserve(robj, false); | |
409 | if (unlikely(r != 0)) | |
410 | goto out; | |
411 | ||
412 | if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { | |
413 | amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); | |
414 | r = amdgpu_bo_get_metadata(robj, args->data.data, | |
415 | sizeof(args->data.data), | |
416 | &args->data.data_size_bytes, | |
417 | &args->data.flags); | |
418 | } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { | |
0913eab6 DC |
419 | if (args->data.data_size_bytes > sizeof(args->data.data)) { |
420 | r = -EINVAL; | |
421 | goto unreserve; | |
422 | } | |
d38ceaf9 AD |
423 | r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); |
424 | if (!r) | |
425 | r = amdgpu_bo_set_metadata(robj, args->data.data, | |
426 | args->data.data_size_bytes, | |
427 | args->data.flags); | |
428 | } | |
429 | ||
0913eab6 | 430 | unreserve: |
d38ceaf9 AD |
431 | amdgpu_bo_unreserve(robj); |
432 | out: | |
433 | drm_gem_object_unreference_unlocked(gobj); | |
434 | return r; | |
435 | } | |
436 | ||
437 | /** | |
438 | * amdgpu_gem_va_update_vm -update the bo_va in its VM | |
439 | * | |
440 | * @adev: amdgpu_device pointer | |
441 | * @bo_va: bo_va to update | |
442 | * | |
443 | * Update the bo_va directly after setting it's address. Errors are not | |
444 | * vital here, so they are not reported back to userspace. | |
445 | */ | |
446 | static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, | |
194a3364 | 447 | struct amdgpu_bo_va *bo_va, uint32_t operation) |
d38ceaf9 AD |
448 | { |
449 | struct ttm_validate_buffer tv, *entry; | |
450 | struct amdgpu_bo_list_entry *vm_bos; | |
451 | struct ww_acquire_ctx ticket; | |
bf60efd3 | 452 | struct list_head list, duplicates; |
d38ceaf9 AD |
453 | unsigned domain; |
454 | int r; | |
455 | ||
456 | INIT_LIST_HEAD(&list); | |
bf60efd3 | 457 | INIT_LIST_HEAD(&duplicates); |
d38ceaf9 AD |
458 | |
459 | tv.bo = &bo_va->bo->tbo; | |
460 | tv.shared = true; | |
461 | list_add(&tv.head, &list); | |
462 | ||
463 | vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list); | |
464 | if (!vm_bos) | |
465 | return; | |
466 | ||
bf60efd3 CK |
467 | /* Provide duplicates to avoid -EALREADY */ |
468 | r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); | |
d38ceaf9 AD |
469 | if (r) |
470 | goto error_free; | |
471 | ||
472 | list_for_each_entry(entry, &list, head) { | |
473 | domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); | |
474 | /* if anything is swapped out don't swap it in here, | |
475 | just abort and wait for the next CS */ | |
476 | if (domain == AMDGPU_GEM_DOMAIN_CPU) | |
477 | goto error_unreserve; | |
478 | } | |
43c27fb5 CZ |
479 | r = amdgpu_vm_update_page_directory(adev, bo_va->vm); |
480 | if (r) | |
481 | goto error_unreserve; | |
d38ceaf9 | 482 | |
d38ceaf9 AD |
483 | r = amdgpu_vm_clear_freed(adev, bo_va->vm); |
484 | if (r) | |
f48b2659 | 485 | goto error_unreserve; |
194a3364 | 486 | |
487 | if (operation == AMDGPU_VA_OP_MAP) | |
488 | r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); | |
d38ceaf9 | 489 | |
d38ceaf9 AD |
490 | error_unreserve: |
491 | ttm_eu_backoff_reservation(&ticket, &list); | |
492 | ||
493 | error_free: | |
494 | drm_free_large(vm_bos); | |
495 | ||
68fdd3df | 496 | if (r && r != -ERESTARTSYS) |
d38ceaf9 AD |
497 | DRM_ERROR("Couldn't update BO_VA (%d)\n", r); |
498 | } | |
499 | ||
500 | ||
501 | ||
502 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, | |
503 | struct drm_file *filp) | |
504 | { | |
34b5f6a6 | 505 | struct drm_amdgpu_gem_va *args = data; |
d38ceaf9 AD |
506 | struct drm_gem_object *gobj; |
507 | struct amdgpu_device *adev = dev->dev_private; | |
508 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
509 | struct amdgpu_bo *rbo; | |
510 | struct amdgpu_bo_va *bo_va; | |
49b02b18 CZ |
511 | struct ttm_validate_buffer tv, tv_pd; |
512 | struct ww_acquire_ctx ticket; | |
513 | struct list_head list, duplicates; | |
d38ceaf9 AD |
514 | uint32_t invalid_flags, va_flags = 0; |
515 | int r = 0; | |
516 | ||
34b5f6a6 | 517 | if (!adev->vm_manager.enabled) |
d38ceaf9 | 518 | return -ENOTTY; |
d38ceaf9 | 519 | |
34b5f6a6 | 520 | if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { |
d38ceaf9 AD |
521 | dev_err(&dev->pdev->dev, |
522 | "va_address 0x%lX is in reserved area 0x%X\n", | |
34b5f6a6 | 523 | (unsigned long)args->va_address, |
d38ceaf9 | 524 | AMDGPU_VA_RESERVED_SIZE); |
d38ceaf9 AD |
525 | return -EINVAL; |
526 | } | |
527 | ||
fc220f65 CK |
528 | invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE | |
529 | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE); | |
34b5f6a6 | 530 | if ((args->flags & invalid_flags)) { |
d38ceaf9 | 531 | dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", |
34b5f6a6 | 532 | args->flags, invalid_flags); |
d38ceaf9 AD |
533 | return -EINVAL; |
534 | } | |
535 | ||
34b5f6a6 | 536 | switch (args->operation) { |
d38ceaf9 AD |
537 | case AMDGPU_VA_OP_MAP: |
538 | case AMDGPU_VA_OP_UNMAP: | |
539 | break; | |
540 | default: | |
541 | dev_err(&dev->pdev->dev, "unsupported operation %d\n", | |
34b5f6a6 | 542 | args->operation); |
d38ceaf9 AD |
543 | return -EINVAL; |
544 | } | |
545 | ||
34b5f6a6 CK |
546 | gobj = drm_gem_object_lookup(dev, filp, args->handle); |
547 | if (gobj == NULL) | |
d38ceaf9 | 548 | return -ENOENT; |
d38ceaf9 | 549 | rbo = gem_to_amdgpu_bo(gobj); |
49b02b18 CZ |
550 | INIT_LIST_HEAD(&list); |
551 | INIT_LIST_HEAD(&duplicates); | |
552 | tv.bo = &rbo->tbo; | |
553 | tv.shared = true; | |
554 | list_add(&tv.head, &list); | |
555 | ||
556 | if (args->operation == AMDGPU_VA_OP_MAP) { | |
557 | tv_pd.bo = &fpriv->vm.page_directory->tbo; | |
558 | tv_pd.shared = true; | |
559 | list_add(&tv_pd.head, &list); | |
560 | } | |
561 | r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); | |
d38ceaf9 | 562 | if (r) { |
d38ceaf9 AD |
563 | drm_gem_object_unreference_unlocked(gobj); |
564 | return r; | |
565 | } | |
34b5f6a6 | 566 | |
d38ceaf9 AD |
567 | bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); |
568 | if (!bo_va) { | |
49b02b18 CZ |
569 | ttm_eu_backoff_reservation(&ticket, &list); |
570 | drm_gem_object_unreference_unlocked(gobj); | |
d38ceaf9 AD |
571 | return -ENOENT; |
572 | } | |
573 | ||
34b5f6a6 | 574 | switch (args->operation) { |
d38ceaf9 | 575 | case AMDGPU_VA_OP_MAP: |
34b5f6a6 | 576 | if (args->flags & AMDGPU_VM_PAGE_READABLE) |
d38ceaf9 | 577 | va_flags |= AMDGPU_PTE_READABLE; |
34b5f6a6 | 578 | if (args->flags & AMDGPU_VM_PAGE_WRITEABLE) |
d38ceaf9 | 579 | va_flags |= AMDGPU_PTE_WRITEABLE; |
34b5f6a6 | 580 | if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE) |
d38ceaf9 | 581 | va_flags |= AMDGPU_PTE_EXECUTABLE; |
34b5f6a6 CK |
582 | r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, |
583 | args->offset_in_bo, args->map_size, | |
9f7eb536 | 584 | va_flags); |
d38ceaf9 AD |
585 | break; |
586 | case AMDGPU_VA_OP_UNMAP: | |
34b5f6a6 | 587 | r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); |
d38ceaf9 AD |
588 | break; |
589 | default: | |
590 | break; | |
591 | } | |
49b02b18 | 592 | ttm_eu_backoff_reservation(&ticket, &list); |
fc220f65 | 593 | if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) |
194a3364 | 594 | amdgpu_gem_va_update_vm(adev, bo_va, args->operation); |
e98c1b0d | 595 | |
d38ceaf9 AD |
596 | drm_gem_object_unreference_unlocked(gobj); |
597 | return r; | |
598 | } | |
599 | ||
600 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
601 | struct drm_file *filp) | |
602 | { | |
603 | struct drm_amdgpu_gem_op *args = data; | |
604 | struct drm_gem_object *gobj; | |
605 | struct amdgpu_bo *robj; | |
606 | int r; | |
607 | ||
608 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
609 | if (gobj == NULL) { | |
610 | return -ENOENT; | |
611 | } | |
612 | robj = gem_to_amdgpu_bo(gobj); | |
613 | ||
614 | r = amdgpu_bo_reserve(robj, false); | |
615 | if (unlikely(r)) | |
616 | goto out; | |
617 | ||
618 | switch (args->op) { | |
619 | case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { | |
620 | struct drm_amdgpu_gem_create_in info; | |
621 | void __user *out = (void __user *)(long)args->value; | |
622 | ||
623 | info.bo_size = robj->gem_base.size; | |
624 | info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; | |
625 | info.domains = robj->initial_domain; | |
626 | info.domain_flags = robj->flags; | |
4c28fb0b | 627 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
628 | if (copy_to_user(out, &info, sizeof(info))) |
629 | r = -EFAULT; | |
630 | break; | |
631 | } | |
d8f65a23 | 632 | case AMDGPU_GEM_OP_SET_PLACEMENT: |
d38ceaf9 AD |
633 | if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) { |
634 | r = -EPERM; | |
4c28fb0b | 635 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
636 | break; |
637 | } | |
638 | robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM | | |
639 | AMDGPU_GEM_DOMAIN_GTT | | |
640 | AMDGPU_GEM_DOMAIN_CPU); | |
4c28fb0b | 641 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
642 | break; |
643 | default: | |
4c28fb0b | 644 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
645 | r = -EINVAL; |
646 | } | |
647 | ||
d38ceaf9 AD |
648 | out: |
649 | drm_gem_object_unreference_unlocked(gobj); | |
650 | return r; | |
651 | } | |
652 | ||
653 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
654 | struct drm_device *dev, | |
655 | struct drm_mode_create_dumb *args) | |
656 | { | |
657 | struct amdgpu_device *adev = dev->dev_private; | |
658 | struct drm_gem_object *gobj; | |
659 | uint32_t handle; | |
660 | int r; | |
661 | ||
662 | args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); | |
54ef0b54 | 663 | args->size = (u64)args->pitch * args->height; |
d38ceaf9 AD |
664 | args->size = ALIGN(args->size, PAGE_SIZE); |
665 | ||
666 | r = amdgpu_gem_object_create(adev, args->size, 0, | |
667 | AMDGPU_GEM_DOMAIN_VRAM, | |
857d913d AD |
668 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, |
669 | ttm_bo_type_device, | |
d38ceaf9 AD |
670 | &gobj); |
671 | if (r) | |
672 | return -ENOMEM; | |
673 | ||
674 | r = drm_gem_handle_create(file_priv, gobj, &handle); | |
675 | /* drop reference from allocate - handle holds it now */ | |
676 | drm_gem_object_unreference_unlocked(gobj); | |
677 | if (r) { | |
678 | return r; | |
679 | } | |
680 | args->handle = handle; | |
681 | return 0; | |
682 | } | |
683 | ||
684 | #if defined(CONFIG_DEBUG_FS) | |
685 | static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) | |
686 | { | |
687 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
688 | struct drm_device *dev = node->minor->dev; | |
689 | struct amdgpu_device *adev = dev->dev_private; | |
690 | struct amdgpu_bo *rbo; | |
691 | unsigned i = 0; | |
692 | ||
693 | mutex_lock(&adev->gem.mutex); | |
694 | list_for_each_entry(rbo, &adev->gem.objects, list) { | |
695 | unsigned domain; | |
696 | const char *placement; | |
697 | ||
698 | domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type); | |
699 | switch (domain) { | |
700 | case AMDGPU_GEM_DOMAIN_VRAM: | |
701 | placement = "VRAM"; | |
702 | break; | |
703 | case AMDGPU_GEM_DOMAIN_GTT: | |
704 | placement = " GTT"; | |
705 | break; | |
706 | case AMDGPU_GEM_DOMAIN_CPU: | |
707 | default: | |
708 | placement = " CPU"; | |
709 | break; | |
710 | } | |
711 | seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n", | |
712 | i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20, | |
713 | placement, (unsigned long)rbo->pid); | |
714 | i++; | |
715 | } | |
716 | mutex_unlock(&adev->gem.mutex); | |
717 | return 0; | |
718 | } | |
719 | ||
720 | static struct drm_info_list amdgpu_debugfs_gem_list[] = { | |
721 | {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, | |
722 | }; | |
723 | #endif | |
724 | ||
725 | int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) | |
726 | { | |
727 | #if defined(CONFIG_DEBUG_FS) | |
728 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); | |
729 | #endif | |
730 | return 0; | |
731 | } |