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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/ktime.h> | |
568d7c76 | 29 | #include <linux/pagemap.h> |
d38ceaf9 AD |
30 | #include <drm/drmP.h> |
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
33 | ||
34 | void amdgpu_gem_object_free(struct drm_gem_object *gobj) | |
35 | { | |
36 | struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); | |
37 | ||
38 | if (robj) { | |
9298e52f | 39 | amdgpu_mn_unregister(robj); |
d38ceaf9 AD |
40 | amdgpu_bo_unref(&robj); |
41 | } | |
42 | } | |
43 | ||
44 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, | |
e1eb899b | 45 | int alignment, u32 initial_domain, |
eab3de23 | 46 | u64 flags, enum ttm_bo_type type, |
e1eb899b CK |
47 | struct reservation_object *resv, |
48 | struct drm_gem_object **obj) | |
d38ceaf9 | 49 | { |
e1eb899b | 50 | struct amdgpu_bo *bo; |
d38ceaf9 AD |
51 | int r; |
52 | ||
53 | *obj = NULL; | |
54 | /* At least align on page size */ | |
55 | if (alignment < PAGE_SIZE) { | |
56 | alignment = PAGE_SIZE; | |
57 | } | |
58 | ||
08082104 | 59 | retry: |
eab3de23 CK |
60 | r = amdgpu_bo_create(adev, size, alignment, initial_domain, |
61 | flags, type, resv, &bo); | |
d38ceaf9 | 62 | if (r) { |
08082104 CK |
63 | if (r != -ERESTARTSYS) { |
64 | if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { | |
65 | flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
66 | goto retry; | |
67 | } | |
68 | ||
69 | if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
70 | initial_domain |= AMDGPU_GEM_DOMAIN_GTT; | |
71 | goto retry; | |
72 | } | |
73 | DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", | |
74 | size, initial_domain, alignment, r); | |
75 | } | |
d38ceaf9 AD |
76 | return r; |
77 | } | |
e1eb899b | 78 | *obj = &bo->gem_base; |
d38ceaf9 | 79 | |
d38ceaf9 AD |
80 | return 0; |
81 | } | |
82 | ||
418aa0c2 | 83 | void amdgpu_gem_force_release(struct amdgpu_device *adev) |
d38ceaf9 | 84 | { |
418aa0c2 CK |
85 | struct drm_device *ddev = adev->ddev; |
86 | struct drm_file *file; | |
d38ceaf9 | 87 | |
1d2ac403 | 88 | mutex_lock(&ddev->filelist_mutex); |
418aa0c2 CK |
89 | |
90 | list_for_each_entry(file, &ddev->filelist, lhead) { | |
91 | struct drm_gem_object *gobj; | |
92 | int handle; | |
93 | ||
94 | WARN_ONCE(1, "Still active user space clients!\n"); | |
95 | spin_lock(&file->table_lock); | |
96 | idr_for_each_entry(&file->object_idr, gobj, handle) { | |
97 | WARN_ONCE(1, "And also active allocations!\n"); | |
f62facc2 | 98 | drm_gem_object_put_unlocked(gobj); |
418aa0c2 CK |
99 | } |
100 | idr_destroy(&file->object_idr); | |
101 | spin_unlock(&file->table_lock); | |
102 | } | |
103 | ||
1d2ac403 | 104 | mutex_unlock(&ddev->filelist_mutex); |
d38ceaf9 AD |
105 | } |
106 | ||
107 | /* | |
108 | * Call from drm_gem_handle_create which appear in both new and open ioctl | |
109 | * case. | |
110 | */ | |
a7d64de6 CK |
111 | int amdgpu_gem_object_open(struct drm_gem_object *obj, |
112 | struct drm_file *file_priv) | |
d38ceaf9 | 113 | { |
765e7fbf | 114 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); |
a7d64de6 | 115 | struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); |
d38ceaf9 AD |
116 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
117 | struct amdgpu_vm *vm = &fpriv->vm; | |
118 | struct amdgpu_bo_va *bo_va; | |
4f5839c5 | 119 | struct mm_struct *mm; |
d38ceaf9 | 120 | int r; |
4f5839c5 CK |
121 | |
122 | mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); | |
123 | if (mm && mm != current->mm) | |
124 | return -EPERM; | |
125 | ||
e1eb899b CK |
126 | if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && |
127 | abo->tbo.resv != vm->root.base.bo->tbo.resv) | |
128 | return -EPERM; | |
129 | ||
765e7fbf | 130 | r = amdgpu_bo_reserve(abo, false); |
e98c1b0d | 131 | if (r) |
d38ceaf9 | 132 | return r; |
d38ceaf9 | 133 | |
765e7fbf | 134 | bo_va = amdgpu_vm_bo_find(vm, abo); |
d38ceaf9 | 135 | if (!bo_va) { |
765e7fbf | 136 | bo_va = amdgpu_vm_bo_add(adev, vm, abo); |
d38ceaf9 AD |
137 | } else { |
138 | ++bo_va->ref_count; | |
139 | } | |
765e7fbf | 140 | amdgpu_bo_unreserve(abo); |
d38ceaf9 AD |
141 | return 0; |
142 | } | |
143 | ||
144 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
145 | struct drm_file *file_priv) | |
146 | { | |
b5a5ec55 | 147 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); |
a7d64de6 | 148 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
d38ceaf9 AD |
149 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
150 | struct amdgpu_vm *vm = &fpriv->vm; | |
b5a5ec55 CK |
151 | |
152 | struct amdgpu_bo_list_entry vm_pd; | |
e1eb899b | 153 | struct list_head list, duplicates; |
b5a5ec55 CK |
154 | struct ttm_validate_buffer tv; |
155 | struct ww_acquire_ctx ticket; | |
d38ceaf9 AD |
156 | struct amdgpu_bo_va *bo_va; |
157 | int r; | |
b5a5ec55 CK |
158 | |
159 | INIT_LIST_HEAD(&list); | |
e1eb899b | 160 | INIT_LIST_HEAD(&duplicates); |
b5a5ec55 CK |
161 | |
162 | tv.bo = &bo->tbo; | |
163 | tv.shared = true; | |
164 | list_add(&tv.head, &list); | |
165 | ||
166 | amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); | |
167 | ||
e1eb899b | 168 | r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); |
d38ceaf9 AD |
169 | if (r) { |
170 | dev_err(adev->dev, "leaking bo va because " | |
171 | "we fail to reserve bo (%d)\n", r); | |
172 | return; | |
173 | } | |
b5a5ec55 | 174 | bo_va = amdgpu_vm_bo_find(vm, bo); |
5a0f3b5f CK |
175 | if (bo_va && --bo_va->ref_count == 0) { |
176 | amdgpu_vm_bo_rmv(adev, bo_va); | |
177 | ||
3f3333f8 | 178 | if (amdgpu_vm_ready(vm)) { |
5a0f3b5f | 179 | struct dma_fence *fence = NULL; |
23e0563e NH |
180 | |
181 | r = amdgpu_vm_clear_freed(adev, vm, &fence); | |
182 | if (unlikely(r)) { | |
183 | dev_err(adev->dev, "failed to clear page " | |
184 | "tables on GEM object close (%d)\n", r); | |
185 | } | |
186 | ||
187 | if (fence) { | |
188 | amdgpu_bo_fence(bo, fence, true); | |
189 | dma_fence_put(fence); | |
190 | } | |
d38ceaf9 AD |
191 | } |
192 | } | |
b5a5ec55 | 193 | ttm_eu_backoff_reservation(&ticket, &list); |
d38ceaf9 AD |
194 | } |
195 | ||
d38ceaf9 AD |
196 | /* |
197 | * GEM ioctls. | |
198 | */ | |
199 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
200 | struct drm_file *filp) | |
201 | { | |
202 | struct amdgpu_device *adev = dev->dev_private; | |
e1eb899b CK |
203 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
204 | struct amdgpu_vm *vm = &fpriv->vm; | |
d38ceaf9 | 205 | union drm_amdgpu_gem_create *args = data; |
6ac7defb | 206 | uint64_t flags = args->in.domain_flags; |
d38ceaf9 | 207 | uint64_t size = args->in.bo_size; |
e1eb899b | 208 | struct reservation_object *resv = NULL; |
d38ceaf9 AD |
209 | struct drm_gem_object *gobj; |
210 | uint32_t handle; | |
d38ceaf9 AD |
211 | int r; |
212 | ||
834e0f8a | 213 | /* reject invalid gem flags */ |
6ac7defb CK |
214 | if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
215 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
216 | AMDGPU_GEM_CREATE_CPU_GTT_USWC | | |
e1eb899b | 217 | AMDGPU_GEM_CREATE_VRAM_CLEARED | |
177ae09b AR |
218 | AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | |
219 | AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) | |
220 | ||
a022c54e CK |
221 | return -EINVAL; |
222 | ||
834e0f8a AD |
223 | /* reject invalid gem domains */ |
224 | if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU | | |
225 | AMDGPU_GEM_DOMAIN_GTT | | |
226 | AMDGPU_GEM_DOMAIN_VRAM | | |
227 | AMDGPU_GEM_DOMAIN_GDS | | |
228 | AMDGPU_GEM_DOMAIN_GWS | | |
a022c54e CK |
229 | AMDGPU_GEM_DOMAIN_OA)) |
230 | return -EINVAL; | |
834e0f8a | 231 | |
d38ceaf9 AD |
232 | /* create a gem object to contain this object in */ |
233 | if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | | |
234 | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { | |
6ac7defb | 235 | flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; |
d38ceaf9 AD |
236 | if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) |
237 | size = size << AMDGPU_GDS_SHIFT; | |
238 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) | |
239 | size = size << AMDGPU_GWS_SHIFT; | |
240 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) | |
241 | size = size << AMDGPU_OA_SHIFT; | |
a022c54e CK |
242 | else |
243 | return -EINVAL; | |
d38ceaf9 AD |
244 | } |
245 | size = roundup(size, PAGE_SIZE); | |
246 | ||
e1eb899b CK |
247 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { |
248 | r = amdgpu_bo_reserve(vm->root.base.bo, false); | |
249 | if (r) | |
250 | return r; | |
251 | ||
252 | resv = vm->root.base.bo->tbo.resv; | |
253 | } | |
254 | ||
d38ceaf9 AD |
255 | r = amdgpu_gem_object_create(adev, size, args->in.alignment, |
256 | (u32)(0xffffffff & args->in.domains), | |
e1eb899b CK |
257 | flags, false, resv, &gobj); |
258 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { | |
259 | if (!r) { | |
260 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); | |
261 | ||
262 | abo->parent = amdgpu_bo_ref(vm->root.base.bo); | |
263 | } | |
264 | amdgpu_bo_unreserve(vm->root.base.bo); | |
265 | } | |
d38ceaf9 | 266 | if (r) |
a022c54e | 267 | return r; |
d38ceaf9 AD |
268 | |
269 | r = drm_gem_handle_create(filp, gobj, &handle); | |
270 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 271 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 272 | if (r) |
a022c54e | 273 | return r; |
d38ceaf9 AD |
274 | |
275 | memset(args, 0, sizeof(*args)); | |
276 | args->out.handle = handle; | |
d38ceaf9 | 277 | return 0; |
d38ceaf9 AD |
278 | } |
279 | ||
280 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
281 | struct drm_file *filp) | |
282 | { | |
19be5570 | 283 | struct ttm_operation_ctx ctx = { true, false }; |
d38ceaf9 AD |
284 | struct amdgpu_device *adev = dev->dev_private; |
285 | struct drm_amdgpu_gem_userptr *args = data; | |
286 | struct drm_gem_object *gobj; | |
287 | struct amdgpu_bo *bo; | |
288 | uint32_t handle; | |
289 | int r; | |
290 | ||
291 | if (offset_in_page(args->addr | args->size)) | |
292 | return -EINVAL; | |
293 | ||
294 | /* reject unknown flag values */ | |
295 | if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | | |
296 | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | | |
297 | AMDGPU_GEM_USERPTR_REGISTER)) | |
298 | return -EINVAL; | |
299 | ||
358c258a CK |
300 | if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && |
301 | !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { | |
d38ceaf9 | 302 | |
358c258a | 303 | /* if we want to write to it we must install a MMU notifier */ |
d38ceaf9 AD |
304 | return -EACCES; |
305 | } | |
306 | ||
d38ceaf9 | 307 | /* create a gem object to contain this object in */ |
e1eb899b CK |
308 | r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, |
309 | 0, 0, NULL, &gobj); | |
d38ceaf9 | 310 | if (r) |
a022c54e | 311 | return r; |
d38ceaf9 AD |
312 | |
313 | bo = gem_to_amdgpu_bo(gobj); | |
6d7d9c5a | 314 | bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; |
1ea863fd | 315 | bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; |
d38ceaf9 AD |
316 | r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); |
317 | if (r) | |
318 | goto release_object; | |
319 | ||
320 | if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { | |
321 | r = amdgpu_mn_register(bo, args->addr); | |
322 | if (r) | |
323 | goto release_object; | |
324 | } | |
325 | ||
326 | if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { | |
2f568dbd CK |
327 | r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, |
328 | bo->tbo.ttm->pages); | |
329 | if (r) | |
d5a480b4 | 330 | goto release_object; |
2f568dbd | 331 | |
d38ceaf9 | 332 | r = amdgpu_bo_reserve(bo, true); |
2f568dbd CK |
333 | if (r) |
334 | goto free_pages; | |
d38ceaf9 AD |
335 | |
336 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); | |
19be5570 | 337 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); |
d38ceaf9 | 338 | amdgpu_bo_unreserve(bo); |
d38ceaf9 | 339 | if (r) |
2f568dbd | 340 | goto free_pages; |
d38ceaf9 AD |
341 | } |
342 | ||
343 | r = drm_gem_handle_create(filp, gobj, &handle); | |
344 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 345 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 346 | if (r) |
a022c54e | 347 | return r; |
d38ceaf9 AD |
348 | |
349 | args->handle = handle; | |
d38ceaf9 AD |
350 | return 0; |
351 | ||
2f568dbd | 352 | free_pages: |
c6f92f9f | 353 | release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); |
2f568dbd | 354 | |
d38ceaf9 | 355 | release_object: |
f62facc2 | 356 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 357 | |
d38ceaf9 AD |
358 | return r; |
359 | } | |
360 | ||
361 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
362 | struct drm_device *dev, | |
363 | uint32_t handle, uint64_t *offset_p) | |
364 | { | |
365 | struct drm_gem_object *gobj; | |
366 | struct amdgpu_bo *robj; | |
367 | ||
a8ad0bd8 | 368 | gobj = drm_gem_object_lookup(filp, handle); |
d38ceaf9 AD |
369 | if (gobj == NULL) { |
370 | return -ENOENT; | |
371 | } | |
372 | robj = gem_to_amdgpu_bo(gobj); | |
cc325d19 | 373 | if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || |
271c8125 | 374 | (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { |
f62facc2 | 375 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
376 | return -EPERM; |
377 | } | |
378 | *offset_p = amdgpu_bo_mmap_offset(robj); | |
f62facc2 | 379 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
380 | return 0; |
381 | } | |
382 | ||
383 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
384 | struct drm_file *filp) | |
385 | { | |
386 | union drm_amdgpu_gem_mmap *args = data; | |
387 | uint32_t handle = args->in.handle; | |
388 | memset(args, 0, sizeof(*args)); | |
389 | return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); | |
390 | } | |
391 | ||
392 | /** | |
393 | * amdgpu_gem_timeout - calculate jiffies timeout from absolute value | |
394 | * | |
395 | * @timeout_ns: timeout in ns | |
396 | * | |
397 | * Calculate the timeout in jiffies from an absolute timeout in ns. | |
398 | */ | |
399 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) | |
400 | { | |
401 | unsigned long timeout_jiffies; | |
402 | ktime_t timeout; | |
403 | ||
404 | /* clamp timeout if it's to large */ | |
405 | if (((int64_t)timeout_ns) < 0) | |
406 | return MAX_SCHEDULE_TIMEOUT; | |
407 | ||
0f117704 | 408 | timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); |
d38ceaf9 AD |
409 | if (ktime_to_ns(timeout) < 0) |
410 | return 0; | |
411 | ||
412 | timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); | |
413 | /* clamp timeout to avoid unsigned-> signed overflow */ | |
414 | if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) | |
415 | return MAX_SCHEDULE_TIMEOUT - 1; | |
416 | ||
417 | return timeout_jiffies; | |
418 | } | |
419 | ||
420 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
421 | struct drm_file *filp) | |
422 | { | |
d38ceaf9 AD |
423 | union drm_amdgpu_gem_wait_idle *args = data; |
424 | struct drm_gem_object *gobj; | |
425 | struct amdgpu_bo *robj; | |
426 | uint32_t handle = args->in.handle; | |
427 | unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); | |
428 | int r = 0; | |
429 | long ret; | |
430 | ||
a8ad0bd8 | 431 | gobj = drm_gem_object_lookup(filp, handle); |
d38ceaf9 AD |
432 | if (gobj == NULL) { |
433 | return -ENOENT; | |
434 | } | |
435 | robj = gem_to_amdgpu_bo(gobj); | |
0fea2ed6 CW |
436 | ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, |
437 | timeout); | |
d38ceaf9 AD |
438 | |
439 | /* ret == 0 means not signaled, | |
440 | * ret > 0 means signaled | |
441 | * ret < 0 means interrupted before timeout | |
442 | */ | |
443 | if (ret >= 0) { | |
444 | memset(args, 0, sizeof(*args)); | |
445 | args->out.status = (ret == 0); | |
446 | } else | |
447 | r = ret; | |
448 | ||
f62facc2 | 449 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
450 | return r; |
451 | } | |
452 | ||
453 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
454 | struct drm_file *filp) | |
455 | { | |
456 | struct drm_amdgpu_gem_metadata *args = data; | |
457 | struct drm_gem_object *gobj; | |
458 | struct amdgpu_bo *robj; | |
459 | int r = -1; | |
460 | ||
461 | DRM_DEBUG("%d \n", args->handle); | |
a8ad0bd8 | 462 | gobj = drm_gem_object_lookup(filp, args->handle); |
d38ceaf9 AD |
463 | if (gobj == NULL) |
464 | return -ENOENT; | |
465 | robj = gem_to_amdgpu_bo(gobj); | |
466 | ||
467 | r = amdgpu_bo_reserve(robj, false); | |
468 | if (unlikely(r != 0)) | |
469 | goto out; | |
470 | ||
471 | if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { | |
472 | amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); | |
473 | r = amdgpu_bo_get_metadata(robj, args->data.data, | |
474 | sizeof(args->data.data), | |
475 | &args->data.data_size_bytes, | |
476 | &args->data.flags); | |
477 | } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { | |
0913eab6 DC |
478 | if (args->data.data_size_bytes > sizeof(args->data.data)) { |
479 | r = -EINVAL; | |
480 | goto unreserve; | |
481 | } | |
d38ceaf9 AD |
482 | r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); |
483 | if (!r) | |
484 | r = amdgpu_bo_set_metadata(robj, args->data.data, | |
485 | args->data.data_size_bytes, | |
486 | args->data.flags); | |
487 | } | |
488 | ||
0913eab6 | 489 | unreserve: |
d38ceaf9 AD |
490 | amdgpu_bo_unreserve(robj); |
491 | out: | |
f62facc2 | 492 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
493 | return r; |
494 | } | |
495 | ||
496 | /** | |
497 | * amdgpu_gem_va_update_vm -update the bo_va in its VM | |
498 | * | |
499 | * @adev: amdgpu_device pointer | |
dc54d3d1 | 500 | * @vm: vm to update |
d38ceaf9 | 501 | * @bo_va: bo_va to update |
2ffdaafb | 502 | * @list: validation list |
dc54d3d1 | 503 | * @operation: map, unmap or clear |
d38ceaf9 | 504 | * |
2ffdaafb | 505 | * Update the bo_va directly after setting its address. Errors are not |
d38ceaf9 AD |
506 | * vital here, so they are not reported back to userspace. |
507 | */ | |
508 | static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, | |
dc54d3d1 | 509 | struct amdgpu_vm *vm, |
f7da30d9 | 510 | struct amdgpu_bo_va *bo_va, |
2ffdaafb | 511 | struct list_head *list, |
f7da30d9 | 512 | uint32_t operation) |
d38ceaf9 | 513 | { |
3f3333f8 | 514 | int r; |
d38ceaf9 | 515 | |
3f3333f8 CK |
516 | if (!amdgpu_vm_ready(vm)) |
517 | return; | |
e410b5cb | 518 | |
f3467818 | 519 | r = amdgpu_vm_clear_freed(adev, vm, NULL); |
d38ceaf9 | 520 | if (r) |
2ffdaafb | 521 | goto error; |
194a3364 | 522 | |
80f95c57 | 523 | if (operation == AMDGPU_VA_OP_MAP || |
93bab704 | 524 | operation == AMDGPU_VA_OP_REPLACE) { |
05dcb5c8 | 525 | r = amdgpu_vm_bo_update(adev, bo_va, false); |
93bab704 GS |
526 | if (r) |
527 | goto error; | |
528 | } | |
d38ceaf9 | 529 | |
0abc6878 | 530 | r = amdgpu_vm_update_directories(adev, vm); |
0abc6878 | 531 | |
2ffdaafb | 532 | error: |
68fdd3df | 533 | if (r && r != -ERESTARTSYS) |
d38ceaf9 AD |
534 | DRM_ERROR("Couldn't update BO_VA (%d)\n", r); |
535 | } | |
536 | ||
d38ceaf9 AD |
537 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, |
538 | struct drm_file *filp) | |
539 | { | |
b85891bd JZ |
540 | const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | |
541 | AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | | |
66e02bc3 | 542 | AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; |
b85891bd JZ |
543 | const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | |
544 | AMDGPU_VM_PAGE_PRT; | |
545 | ||
34b5f6a6 | 546 | struct drm_amdgpu_gem_va *args = data; |
d38ceaf9 AD |
547 | struct drm_gem_object *gobj; |
548 | struct amdgpu_device *adev = dev->dev_private; | |
549 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
765e7fbf | 550 | struct amdgpu_bo *abo; |
d38ceaf9 | 551 | struct amdgpu_bo_va *bo_va; |
b88c8796 CK |
552 | struct amdgpu_bo_list_entry vm_pd; |
553 | struct ttm_validate_buffer tv; | |
49b02b18 | 554 | struct ww_acquire_ctx ticket; |
e1eb899b | 555 | struct list_head list, duplicates; |
5463545b | 556 | uint64_t va_flags; |
d38ceaf9 AD |
557 | int r = 0; |
558 | ||
34b5f6a6 | 559 | if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { |
4b7f0848 | 560 | dev_dbg(&dev->pdev->dev, |
ff4cd389 CK |
561 | "va_address 0x%LX is in reserved area 0x%LX\n", |
562 | args->va_address, AMDGPU_VA_RESERVED_SIZE); | |
d38ceaf9 AD |
563 | return -EINVAL; |
564 | } | |
565 | ||
bb7939b2 CK |
566 | if (args->va_address >= AMDGPU_VA_HOLE_START && |
567 | args->va_address < AMDGPU_VA_HOLE_END) { | |
568 | dev_dbg(&dev->pdev->dev, | |
569 | "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", | |
570 | args->va_address, AMDGPU_VA_HOLE_START, | |
571 | AMDGPU_VA_HOLE_END); | |
572 | return -EINVAL; | |
573 | } | |
574 | ||
575 | args->va_address &= AMDGPU_VA_HOLE_MASK; | |
576 | ||
b85891bd | 577 | if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { |
4b7f0848 | 578 | dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", |
b85891bd | 579 | args->flags); |
d38ceaf9 AD |
580 | return -EINVAL; |
581 | } | |
582 | ||
34b5f6a6 | 583 | switch (args->operation) { |
d38ceaf9 AD |
584 | case AMDGPU_VA_OP_MAP: |
585 | case AMDGPU_VA_OP_UNMAP: | |
dc54d3d1 | 586 | case AMDGPU_VA_OP_CLEAR: |
80f95c57 | 587 | case AMDGPU_VA_OP_REPLACE: |
d38ceaf9 AD |
588 | break; |
589 | default: | |
4b7f0848 | 590 | dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", |
34b5f6a6 | 591 | args->operation); |
d38ceaf9 AD |
592 | return -EINVAL; |
593 | } | |
594 | ||
49b02b18 | 595 | INIT_LIST_HEAD(&list); |
e1eb899b | 596 | INIT_LIST_HEAD(&duplicates); |
dc54d3d1 CK |
597 | if ((args->operation != AMDGPU_VA_OP_CLEAR) && |
598 | !(args->flags & AMDGPU_VM_PAGE_PRT)) { | |
b85891bd JZ |
599 | gobj = drm_gem_object_lookup(filp, args->handle); |
600 | if (gobj == NULL) | |
601 | return -ENOENT; | |
602 | abo = gem_to_amdgpu_bo(gobj); | |
603 | tv.bo = &abo->tbo; | |
604 | tv.shared = false; | |
605 | list_add(&tv.head, &list); | |
606 | } else { | |
607 | gobj = NULL; | |
608 | abo = NULL; | |
609 | } | |
49b02b18 | 610 | |
b88c8796 | 611 | amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); |
b5a5ec55 | 612 | |
e1eb899b | 613 | r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); |
b85891bd JZ |
614 | if (r) |
615 | goto error_unref; | |
34b5f6a6 | 616 | |
b85891bd JZ |
617 | if (abo) { |
618 | bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); | |
619 | if (!bo_va) { | |
620 | r = -ENOENT; | |
621 | goto error_backoff; | |
622 | } | |
dc54d3d1 | 623 | } else if (args->operation != AMDGPU_VA_OP_CLEAR) { |
b85891bd | 624 | bo_va = fpriv->prt_va; |
dc54d3d1 CK |
625 | } else { |
626 | bo_va = NULL; | |
d38ceaf9 AD |
627 | } |
628 | ||
34b5f6a6 | 629 | switch (args->operation) { |
d38ceaf9 | 630 | case AMDGPU_VA_OP_MAP: |
ec681545 | 631 | r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, |
663e4577 CK |
632 | args->map_size); |
633 | if (r) | |
634 | goto error_backoff; | |
5463545b | 635 | |
132f34e4 | 636 | va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); |
34b5f6a6 CK |
637 | r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, |
638 | args->offset_in_bo, args->map_size, | |
9f7eb536 | 639 | va_flags); |
d38ceaf9 AD |
640 | break; |
641 | case AMDGPU_VA_OP_UNMAP: | |
34b5f6a6 | 642 | r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); |
d38ceaf9 | 643 | break; |
dc54d3d1 CK |
644 | |
645 | case AMDGPU_VA_OP_CLEAR: | |
646 | r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, | |
647 | args->va_address, | |
648 | args->map_size); | |
649 | break; | |
80f95c57 | 650 | case AMDGPU_VA_OP_REPLACE: |
ec681545 | 651 | r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, |
80f95c57 CK |
652 | args->map_size); |
653 | if (r) | |
654 | goto error_backoff; | |
655 | ||
132f34e4 | 656 | va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); |
80f95c57 CK |
657 | r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, |
658 | args->offset_in_bo, args->map_size, | |
659 | va_flags); | |
660 | break; | |
d38ceaf9 AD |
661 | default: |
662 | break; | |
663 | } | |
b85891bd | 664 | if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) |
dc54d3d1 CK |
665 | amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list, |
666 | args->operation); | |
b85891bd JZ |
667 | |
668 | error_backoff: | |
2ffdaafb | 669 | ttm_eu_backoff_reservation(&ticket, &list); |
e98c1b0d | 670 | |
b85891bd | 671 | error_unref: |
f62facc2 | 672 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
673 | return r; |
674 | } | |
675 | ||
676 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
677 | struct drm_file *filp) | |
678 | { | |
e1eb899b | 679 | struct amdgpu_device *adev = dev->dev_private; |
d38ceaf9 AD |
680 | struct drm_amdgpu_gem_op *args = data; |
681 | struct drm_gem_object *gobj; | |
682 | struct amdgpu_bo *robj; | |
683 | int r; | |
684 | ||
a8ad0bd8 | 685 | gobj = drm_gem_object_lookup(filp, args->handle); |
d38ceaf9 AD |
686 | if (gobj == NULL) { |
687 | return -ENOENT; | |
688 | } | |
689 | robj = gem_to_amdgpu_bo(gobj); | |
690 | ||
691 | r = amdgpu_bo_reserve(robj, false); | |
692 | if (unlikely(r)) | |
693 | goto out; | |
694 | ||
695 | switch (args->op) { | |
696 | case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { | |
697 | struct drm_amdgpu_gem_create_in info; | |
7ecc245a | 698 | void __user *out = u64_to_user_ptr(args->value); |
d38ceaf9 AD |
699 | |
700 | info.bo_size = robj->gem_base.size; | |
701 | info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; | |
6d7d9c5a | 702 | info.domains = robj->preferred_domains; |
d38ceaf9 | 703 | info.domain_flags = robj->flags; |
4c28fb0b | 704 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
705 | if (copy_to_user(out, &info, sizeof(info))) |
706 | r = -EFAULT; | |
707 | break; | |
708 | } | |
d8f65a23 | 709 | case AMDGPU_GEM_OP_SET_PLACEMENT: |
803d89ad CJHR |
710 | if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { |
711 | r = -EINVAL; | |
712 | amdgpu_bo_unreserve(robj); | |
713 | break; | |
714 | } | |
cc325d19 | 715 | if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { |
d38ceaf9 | 716 | r = -EPERM; |
4c28fb0b | 717 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
718 | break; |
719 | } | |
6d7d9c5a | 720 | robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | |
1ea863fd CK |
721 | AMDGPU_GEM_DOMAIN_GTT | |
722 | AMDGPU_GEM_DOMAIN_CPU); | |
6d7d9c5a | 723 | robj->allowed_domains = robj->preferred_domains; |
1ea863fd CK |
724 | if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) |
725 | robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; | |
726 | ||
e1eb899b CK |
727 | if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) |
728 | amdgpu_vm_bo_invalidate(adev, robj, true); | |
729 | ||
4c28fb0b | 730 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
731 | break; |
732 | default: | |
4c28fb0b | 733 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
734 | r = -EINVAL; |
735 | } | |
736 | ||
d38ceaf9 | 737 | out: |
f62facc2 | 738 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
739 | return r; |
740 | } | |
741 | ||
742 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
743 | struct drm_device *dev, | |
744 | struct drm_mode_create_dumb *args) | |
745 | { | |
746 | struct amdgpu_device *adev = dev->dev_private; | |
747 | struct drm_gem_object *gobj; | |
748 | uint32_t handle; | |
749 | int r; | |
750 | ||
8e911ab7 LP |
751 | args->pitch = amdgpu_align_pitch(adev, args->width, |
752 | DIV_ROUND_UP(args->bpp, 8), 0); | |
54ef0b54 | 753 | args->size = (u64)args->pitch * args->height; |
d38ceaf9 AD |
754 | args->size = ALIGN(args->size, PAGE_SIZE); |
755 | ||
756 | r = amdgpu_gem_object_create(adev, args->size, 0, | |
757 | AMDGPU_GEM_DOMAIN_VRAM, | |
857d913d | 758 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, |
e1eb899b | 759 | false, NULL, &gobj); |
d38ceaf9 AD |
760 | if (r) |
761 | return -ENOMEM; | |
762 | ||
763 | r = drm_gem_handle_create(file_priv, gobj, &handle); | |
764 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 765 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
766 | if (r) { |
767 | return r; | |
768 | } | |
769 | args->handle = handle; | |
770 | return 0; | |
771 | } | |
772 | ||
773 | #if defined(CONFIG_DEBUG_FS) | |
7ea23565 CK |
774 | static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) |
775 | { | |
776 | struct drm_gem_object *gobj = ptr; | |
777 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); | |
778 | struct seq_file *m = data; | |
779 | ||
780 | unsigned domain; | |
781 | const char *placement; | |
782 | unsigned pin_count; | |
b8e0e6e1 | 783 | uint64_t offset; |
7ea23565 CK |
784 | |
785 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
786 | switch (domain) { | |
787 | case AMDGPU_GEM_DOMAIN_VRAM: | |
788 | placement = "VRAM"; | |
789 | break; | |
790 | case AMDGPU_GEM_DOMAIN_GTT: | |
791 | placement = " GTT"; | |
792 | break; | |
793 | case AMDGPU_GEM_DOMAIN_CPU: | |
794 | default: | |
795 | placement = " CPU"; | |
796 | break; | |
797 | } | |
b8e0e6e1 CK |
798 | seq_printf(m, "\t0x%08x: %12ld byte %s", |
799 | id, amdgpu_bo_size(bo), placement); | |
800 | ||
6aa7de05 | 801 | offset = READ_ONCE(bo->tbo.mem.start); |
b8e0e6e1 CK |
802 | if (offset != AMDGPU_BO_INVALID_OFFSET) |
803 | seq_printf(m, " @ 0x%010Lx", offset); | |
7ea23565 | 804 | |
6aa7de05 | 805 | pin_count = READ_ONCE(bo->pin_count); |
7ea23565 CK |
806 | if (pin_count) |
807 | seq_printf(m, " pin count %d", pin_count); | |
808 | seq_printf(m, "\n"); | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
d38ceaf9 AD |
813 | static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) |
814 | { | |
815 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
816 | struct drm_device *dev = node->minor->dev; | |
7ea23565 CK |
817 | struct drm_file *file; |
818 | int r; | |
d38ceaf9 | 819 | |
1d2ac403 | 820 | r = mutex_lock_interruptible(&dev->filelist_mutex); |
7ea23565 CK |
821 | if (r) |
822 | return r; | |
823 | ||
824 | list_for_each_entry(file, &dev->filelist, lhead) { | |
825 | struct task_struct *task; | |
826 | ||
827 | /* | |
828 | * Although we have a valid reference on file->pid, that does | |
829 | * not guarantee that the task_struct who called get_pid() is | |
830 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
831 | * Therefore, we need to protect this ->comm access using RCU. | |
832 | */ | |
833 | rcu_read_lock(); | |
834 | task = pid_task(file->pid, PIDTYPE_PID); | |
835 | seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), | |
836 | task ? task->comm : "<unknown>"); | |
837 | rcu_read_unlock(); | |
838 | ||
839 | spin_lock(&file->table_lock); | |
840 | idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); | |
841 | spin_unlock(&file->table_lock); | |
d38ceaf9 | 842 | } |
7ea23565 | 843 | |
1d2ac403 | 844 | mutex_unlock(&dev->filelist_mutex); |
d38ceaf9 AD |
845 | return 0; |
846 | } | |
847 | ||
06ab6832 | 848 | static const struct drm_info_list amdgpu_debugfs_gem_list[] = { |
d38ceaf9 AD |
849 | {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, |
850 | }; | |
851 | #endif | |
852 | ||
75758255 | 853 | int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
854 | { |
855 | #if defined(CONFIG_DEBUG_FS) | |
856 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); | |
857 | #endif | |
858 | return 0; | |
859 | } |