]>
Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/ktime.h> | |
568d7c76 | 29 | #include <linux/pagemap.h> |
d38ceaf9 AD |
30 | #include <drm/drmP.h> |
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
bda31a24 | 33 | #include "amdgpu_display.h" |
d38ceaf9 AD |
34 | |
35 | void amdgpu_gem_object_free(struct drm_gem_object *gobj) | |
36 | { | |
37 | struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); | |
38 | ||
39 | if (robj) { | |
9298e52f | 40 | amdgpu_mn_unregister(robj); |
d38ceaf9 AD |
41 | amdgpu_bo_unref(&robj); |
42 | } | |
43 | } | |
44 | ||
45 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, | |
e1eb899b | 46 | int alignment, u32 initial_domain, |
eab3de23 | 47 | u64 flags, enum ttm_bo_type type, |
e1eb899b CK |
48 | struct reservation_object *resv, |
49 | struct drm_gem_object **obj) | |
d38ceaf9 | 50 | { |
e1eb899b | 51 | struct amdgpu_bo *bo; |
3216c6b7 | 52 | struct amdgpu_bo_param bp; |
d38ceaf9 AD |
53 | int r; |
54 | ||
3216c6b7 | 55 | memset(&bp, 0, sizeof(bp)); |
d38ceaf9 AD |
56 | *obj = NULL; |
57 | /* At least align on page size */ | |
58 | if (alignment < PAGE_SIZE) { | |
59 | alignment = PAGE_SIZE; | |
60 | } | |
61 | ||
3216c6b7 CZ |
62 | bp.size = size; |
63 | bp.byte_align = alignment; | |
64 | bp.type = type; | |
65 | bp.resv = resv; | |
aa2b2e28 | 66 | bp.preferred_domain = initial_domain; |
08082104 | 67 | retry: |
3216c6b7 CZ |
68 | bp.flags = flags; |
69 | bp.domain = initial_domain; | |
70 | r = amdgpu_bo_create(adev, &bp, &bo); | |
d38ceaf9 | 71 | if (r) { |
08082104 CK |
72 | if (r != -ERESTARTSYS) { |
73 | if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { | |
74 | flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
75 | goto retry; | |
76 | } | |
77 | ||
78 | if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
79 | initial_domain |= AMDGPU_GEM_DOMAIN_GTT; | |
80 | goto retry; | |
81 | } | |
82 | DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", | |
83 | size, initial_domain, alignment, r); | |
84 | } | |
d38ceaf9 AD |
85 | return r; |
86 | } | |
e1eb899b | 87 | *obj = &bo->gem_base; |
d38ceaf9 | 88 | |
d38ceaf9 AD |
89 | return 0; |
90 | } | |
91 | ||
418aa0c2 | 92 | void amdgpu_gem_force_release(struct amdgpu_device *adev) |
d38ceaf9 | 93 | { |
418aa0c2 CK |
94 | struct drm_device *ddev = adev->ddev; |
95 | struct drm_file *file; | |
d38ceaf9 | 96 | |
1d2ac403 | 97 | mutex_lock(&ddev->filelist_mutex); |
418aa0c2 CK |
98 | |
99 | list_for_each_entry(file, &ddev->filelist, lhead) { | |
100 | struct drm_gem_object *gobj; | |
101 | int handle; | |
102 | ||
103 | WARN_ONCE(1, "Still active user space clients!\n"); | |
104 | spin_lock(&file->table_lock); | |
105 | idr_for_each_entry(&file->object_idr, gobj, handle) { | |
106 | WARN_ONCE(1, "And also active allocations!\n"); | |
f62facc2 | 107 | drm_gem_object_put_unlocked(gobj); |
418aa0c2 CK |
108 | } |
109 | idr_destroy(&file->object_idr); | |
110 | spin_unlock(&file->table_lock); | |
111 | } | |
112 | ||
1d2ac403 | 113 | mutex_unlock(&ddev->filelist_mutex); |
d38ceaf9 AD |
114 | } |
115 | ||
116 | /* | |
117 | * Call from drm_gem_handle_create which appear in both new and open ioctl | |
118 | * case. | |
119 | */ | |
a7d64de6 CK |
120 | int amdgpu_gem_object_open(struct drm_gem_object *obj, |
121 | struct drm_file *file_priv) | |
d38ceaf9 | 122 | { |
765e7fbf | 123 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); |
a7d64de6 | 124 | struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); |
d38ceaf9 AD |
125 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
126 | struct amdgpu_vm *vm = &fpriv->vm; | |
127 | struct amdgpu_bo_va *bo_va; | |
4f5839c5 | 128 | struct mm_struct *mm; |
d38ceaf9 | 129 | int r; |
4f5839c5 CK |
130 | |
131 | mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); | |
132 | if (mm && mm != current->mm) | |
133 | return -EPERM; | |
134 | ||
e1eb899b CK |
135 | if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && |
136 | abo->tbo.resv != vm->root.base.bo->tbo.resv) | |
137 | return -EPERM; | |
138 | ||
765e7fbf | 139 | r = amdgpu_bo_reserve(abo, false); |
e98c1b0d | 140 | if (r) |
d38ceaf9 | 141 | return r; |
d38ceaf9 | 142 | |
765e7fbf | 143 | bo_va = amdgpu_vm_bo_find(vm, abo); |
d38ceaf9 | 144 | if (!bo_va) { |
765e7fbf | 145 | bo_va = amdgpu_vm_bo_add(adev, vm, abo); |
d38ceaf9 AD |
146 | } else { |
147 | ++bo_va->ref_count; | |
148 | } | |
765e7fbf | 149 | amdgpu_bo_unreserve(abo); |
d38ceaf9 AD |
150 | return 0; |
151 | } | |
152 | ||
153 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
154 | struct drm_file *file_priv) | |
155 | { | |
b5a5ec55 | 156 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); |
a7d64de6 | 157 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
d38ceaf9 AD |
158 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
159 | struct amdgpu_vm *vm = &fpriv->vm; | |
b5a5ec55 CK |
160 | |
161 | struct amdgpu_bo_list_entry vm_pd; | |
e1eb899b | 162 | struct list_head list, duplicates; |
b5a5ec55 CK |
163 | struct ttm_validate_buffer tv; |
164 | struct ww_acquire_ctx ticket; | |
d38ceaf9 AD |
165 | struct amdgpu_bo_va *bo_va; |
166 | int r; | |
b5a5ec55 CK |
167 | |
168 | INIT_LIST_HEAD(&list); | |
e1eb899b | 169 | INIT_LIST_HEAD(&duplicates); |
b5a5ec55 CK |
170 | |
171 | tv.bo = &bo->tbo; | |
172 | tv.shared = true; | |
173 | list_add(&tv.head, &list); | |
174 | ||
175 | amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); | |
176 | ||
e1eb899b | 177 | r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); |
d38ceaf9 AD |
178 | if (r) { |
179 | dev_err(adev->dev, "leaking bo va because " | |
180 | "we fail to reserve bo (%d)\n", r); | |
181 | return; | |
182 | } | |
b5a5ec55 | 183 | bo_va = amdgpu_vm_bo_find(vm, bo); |
5a0f3b5f CK |
184 | if (bo_va && --bo_va->ref_count == 0) { |
185 | amdgpu_vm_bo_rmv(adev, bo_va); | |
186 | ||
3f3333f8 | 187 | if (amdgpu_vm_ready(vm)) { |
5a0f3b5f | 188 | struct dma_fence *fence = NULL; |
23e0563e NH |
189 | |
190 | r = amdgpu_vm_clear_freed(adev, vm, &fence); | |
191 | if (unlikely(r)) { | |
192 | dev_err(adev->dev, "failed to clear page " | |
193 | "tables on GEM object close (%d)\n", r); | |
194 | } | |
195 | ||
196 | if (fence) { | |
197 | amdgpu_bo_fence(bo, fence, true); | |
198 | dma_fence_put(fence); | |
199 | } | |
d38ceaf9 AD |
200 | } |
201 | } | |
b5a5ec55 | 202 | ttm_eu_backoff_reservation(&ticket, &list); |
d38ceaf9 AD |
203 | } |
204 | ||
d38ceaf9 AD |
205 | /* |
206 | * GEM ioctls. | |
207 | */ | |
208 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
209 | struct drm_file *filp) | |
210 | { | |
211 | struct amdgpu_device *adev = dev->dev_private; | |
e1eb899b CK |
212 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
213 | struct amdgpu_vm *vm = &fpriv->vm; | |
d38ceaf9 | 214 | union drm_amdgpu_gem_create *args = data; |
6ac7defb | 215 | uint64_t flags = args->in.domain_flags; |
d38ceaf9 | 216 | uint64_t size = args->in.bo_size; |
e1eb899b | 217 | struct reservation_object *resv = NULL; |
d38ceaf9 AD |
218 | struct drm_gem_object *gobj; |
219 | uint32_t handle; | |
d38ceaf9 AD |
220 | int r; |
221 | ||
834e0f8a | 222 | /* reject invalid gem flags */ |
6ac7defb CK |
223 | if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
224 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
225 | AMDGPU_GEM_CREATE_CPU_GTT_USWC | | |
e1eb899b | 226 | AMDGPU_GEM_CREATE_VRAM_CLEARED | |
177ae09b AR |
227 | AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | |
228 | AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) | |
229 | ||
a022c54e CK |
230 | return -EINVAL; |
231 | ||
834e0f8a | 232 | /* reject invalid gem domains */ |
3f188453 | 233 | if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) |
a022c54e | 234 | return -EINVAL; |
834e0f8a | 235 | |
d38ceaf9 AD |
236 | /* create a gem object to contain this object in */ |
237 | if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | | |
238 | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { | |
6ac7defb | 239 | flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; |
d38ceaf9 AD |
240 | if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) |
241 | size = size << AMDGPU_GDS_SHIFT; | |
242 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) | |
243 | size = size << AMDGPU_GWS_SHIFT; | |
244 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) | |
245 | size = size << AMDGPU_OA_SHIFT; | |
a022c54e CK |
246 | else |
247 | return -EINVAL; | |
d38ceaf9 AD |
248 | } |
249 | size = roundup(size, PAGE_SIZE); | |
250 | ||
e1eb899b CK |
251 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { |
252 | r = amdgpu_bo_reserve(vm->root.base.bo, false); | |
253 | if (r) | |
254 | return r; | |
255 | ||
256 | resv = vm->root.base.bo->tbo.resv; | |
257 | } | |
258 | ||
d38ceaf9 AD |
259 | r = amdgpu_gem_object_create(adev, size, args->in.alignment, |
260 | (u32)(0xffffffff & args->in.domains), | |
e1eb899b CK |
261 | flags, false, resv, &gobj); |
262 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { | |
263 | if (!r) { | |
264 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); | |
265 | ||
266 | abo->parent = amdgpu_bo_ref(vm->root.base.bo); | |
267 | } | |
268 | amdgpu_bo_unreserve(vm->root.base.bo); | |
269 | } | |
d38ceaf9 | 270 | if (r) |
a022c54e | 271 | return r; |
d38ceaf9 AD |
272 | |
273 | r = drm_gem_handle_create(filp, gobj, &handle); | |
274 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 275 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 276 | if (r) |
a022c54e | 277 | return r; |
d38ceaf9 AD |
278 | |
279 | memset(args, 0, sizeof(*args)); | |
280 | args->out.handle = handle; | |
d38ceaf9 | 281 | return 0; |
d38ceaf9 AD |
282 | } |
283 | ||
284 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
285 | struct drm_file *filp) | |
286 | { | |
19be5570 | 287 | struct ttm_operation_ctx ctx = { true, false }; |
d38ceaf9 AD |
288 | struct amdgpu_device *adev = dev->dev_private; |
289 | struct drm_amdgpu_gem_userptr *args = data; | |
290 | struct drm_gem_object *gobj; | |
291 | struct amdgpu_bo *bo; | |
292 | uint32_t handle; | |
293 | int r; | |
294 | ||
295 | if (offset_in_page(args->addr | args->size)) | |
296 | return -EINVAL; | |
297 | ||
298 | /* reject unknown flag values */ | |
299 | if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | | |
300 | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | | |
301 | AMDGPU_GEM_USERPTR_REGISTER)) | |
302 | return -EINVAL; | |
303 | ||
358c258a CK |
304 | if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && |
305 | !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { | |
d38ceaf9 | 306 | |
358c258a | 307 | /* if we want to write to it we must install a MMU notifier */ |
d38ceaf9 AD |
308 | return -EACCES; |
309 | } | |
310 | ||
d38ceaf9 | 311 | /* create a gem object to contain this object in */ |
e1eb899b CK |
312 | r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, |
313 | 0, 0, NULL, &gobj); | |
d38ceaf9 | 314 | if (r) |
a022c54e | 315 | return r; |
d38ceaf9 AD |
316 | |
317 | bo = gem_to_amdgpu_bo(gobj); | |
6d7d9c5a | 318 | bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; |
1ea863fd | 319 | bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; |
d38ceaf9 AD |
320 | r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); |
321 | if (r) | |
322 | goto release_object; | |
323 | ||
324 | if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { | |
325 | r = amdgpu_mn_register(bo, args->addr); | |
326 | if (r) | |
327 | goto release_object; | |
328 | } | |
329 | ||
330 | if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { | |
2f568dbd CK |
331 | r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, |
332 | bo->tbo.ttm->pages); | |
333 | if (r) | |
d5a480b4 | 334 | goto release_object; |
2f568dbd | 335 | |
d38ceaf9 | 336 | r = amdgpu_bo_reserve(bo, true); |
2f568dbd CK |
337 | if (r) |
338 | goto free_pages; | |
d38ceaf9 AD |
339 | |
340 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); | |
19be5570 | 341 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); |
d38ceaf9 | 342 | amdgpu_bo_unreserve(bo); |
d38ceaf9 | 343 | if (r) |
2f568dbd | 344 | goto free_pages; |
d38ceaf9 AD |
345 | } |
346 | ||
347 | r = drm_gem_handle_create(filp, gobj, &handle); | |
348 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 349 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 350 | if (r) |
a022c54e | 351 | return r; |
d38ceaf9 AD |
352 | |
353 | args->handle = handle; | |
d38ceaf9 AD |
354 | return 0; |
355 | ||
2f568dbd | 356 | free_pages: |
c6f92f9f | 357 | release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); |
2f568dbd | 358 | |
d38ceaf9 | 359 | release_object: |
f62facc2 | 360 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 361 | |
d38ceaf9 AD |
362 | return r; |
363 | } | |
364 | ||
365 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
366 | struct drm_device *dev, | |
367 | uint32_t handle, uint64_t *offset_p) | |
368 | { | |
369 | struct drm_gem_object *gobj; | |
370 | struct amdgpu_bo *robj; | |
371 | ||
a8ad0bd8 | 372 | gobj = drm_gem_object_lookup(filp, handle); |
d38ceaf9 AD |
373 | if (gobj == NULL) { |
374 | return -ENOENT; | |
375 | } | |
376 | robj = gem_to_amdgpu_bo(gobj); | |
cc325d19 | 377 | if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || |
271c8125 | 378 | (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { |
f62facc2 | 379 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
380 | return -EPERM; |
381 | } | |
382 | *offset_p = amdgpu_bo_mmap_offset(robj); | |
f62facc2 | 383 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
384 | return 0; |
385 | } | |
386 | ||
387 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
388 | struct drm_file *filp) | |
389 | { | |
390 | union drm_amdgpu_gem_mmap *args = data; | |
391 | uint32_t handle = args->in.handle; | |
392 | memset(args, 0, sizeof(*args)); | |
393 | return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); | |
394 | } | |
395 | ||
396 | /** | |
397 | * amdgpu_gem_timeout - calculate jiffies timeout from absolute value | |
398 | * | |
399 | * @timeout_ns: timeout in ns | |
400 | * | |
401 | * Calculate the timeout in jiffies from an absolute timeout in ns. | |
402 | */ | |
403 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) | |
404 | { | |
405 | unsigned long timeout_jiffies; | |
406 | ktime_t timeout; | |
407 | ||
408 | /* clamp timeout if it's to large */ | |
409 | if (((int64_t)timeout_ns) < 0) | |
410 | return MAX_SCHEDULE_TIMEOUT; | |
411 | ||
0f117704 | 412 | timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); |
d38ceaf9 AD |
413 | if (ktime_to_ns(timeout) < 0) |
414 | return 0; | |
415 | ||
416 | timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); | |
417 | /* clamp timeout to avoid unsigned-> signed overflow */ | |
418 | if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) | |
419 | return MAX_SCHEDULE_TIMEOUT - 1; | |
420 | ||
421 | return timeout_jiffies; | |
422 | } | |
423 | ||
424 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
425 | struct drm_file *filp) | |
426 | { | |
d38ceaf9 AD |
427 | union drm_amdgpu_gem_wait_idle *args = data; |
428 | struct drm_gem_object *gobj; | |
429 | struct amdgpu_bo *robj; | |
430 | uint32_t handle = args->in.handle; | |
431 | unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); | |
432 | int r = 0; | |
433 | long ret; | |
434 | ||
a8ad0bd8 | 435 | gobj = drm_gem_object_lookup(filp, handle); |
d38ceaf9 AD |
436 | if (gobj == NULL) { |
437 | return -ENOENT; | |
438 | } | |
439 | robj = gem_to_amdgpu_bo(gobj); | |
0fea2ed6 CW |
440 | ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, |
441 | timeout); | |
d38ceaf9 AD |
442 | |
443 | /* ret == 0 means not signaled, | |
444 | * ret > 0 means signaled | |
445 | * ret < 0 means interrupted before timeout | |
446 | */ | |
447 | if (ret >= 0) { | |
448 | memset(args, 0, sizeof(*args)); | |
449 | args->out.status = (ret == 0); | |
450 | } else | |
451 | r = ret; | |
452 | ||
f62facc2 | 453 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
454 | return r; |
455 | } | |
456 | ||
457 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
458 | struct drm_file *filp) | |
459 | { | |
460 | struct drm_amdgpu_gem_metadata *args = data; | |
461 | struct drm_gem_object *gobj; | |
462 | struct amdgpu_bo *robj; | |
463 | int r = -1; | |
464 | ||
465 | DRM_DEBUG("%d \n", args->handle); | |
a8ad0bd8 | 466 | gobj = drm_gem_object_lookup(filp, args->handle); |
d38ceaf9 AD |
467 | if (gobj == NULL) |
468 | return -ENOENT; | |
469 | robj = gem_to_amdgpu_bo(gobj); | |
470 | ||
471 | r = amdgpu_bo_reserve(robj, false); | |
472 | if (unlikely(r != 0)) | |
473 | goto out; | |
474 | ||
475 | if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { | |
476 | amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); | |
477 | r = amdgpu_bo_get_metadata(robj, args->data.data, | |
478 | sizeof(args->data.data), | |
479 | &args->data.data_size_bytes, | |
480 | &args->data.flags); | |
481 | } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { | |
0913eab6 DC |
482 | if (args->data.data_size_bytes > sizeof(args->data.data)) { |
483 | r = -EINVAL; | |
484 | goto unreserve; | |
485 | } | |
d38ceaf9 AD |
486 | r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); |
487 | if (!r) | |
488 | r = amdgpu_bo_set_metadata(robj, args->data.data, | |
489 | args->data.data_size_bytes, | |
490 | args->data.flags); | |
491 | } | |
492 | ||
0913eab6 | 493 | unreserve: |
d38ceaf9 AD |
494 | amdgpu_bo_unreserve(robj); |
495 | out: | |
f62facc2 | 496 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
497 | return r; |
498 | } | |
499 | ||
500 | /** | |
501 | * amdgpu_gem_va_update_vm -update the bo_va in its VM | |
502 | * | |
503 | * @adev: amdgpu_device pointer | |
dc54d3d1 | 504 | * @vm: vm to update |
d38ceaf9 | 505 | * @bo_va: bo_va to update |
2ffdaafb | 506 | * @list: validation list |
dc54d3d1 | 507 | * @operation: map, unmap or clear |
d38ceaf9 | 508 | * |
2ffdaafb | 509 | * Update the bo_va directly after setting its address. Errors are not |
d38ceaf9 AD |
510 | * vital here, so they are not reported back to userspace. |
511 | */ | |
512 | static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, | |
dc54d3d1 | 513 | struct amdgpu_vm *vm, |
f7da30d9 | 514 | struct amdgpu_bo_va *bo_va, |
2ffdaafb | 515 | struct list_head *list, |
f7da30d9 | 516 | uint32_t operation) |
d38ceaf9 | 517 | { |
3f3333f8 | 518 | int r; |
d38ceaf9 | 519 | |
3f3333f8 CK |
520 | if (!amdgpu_vm_ready(vm)) |
521 | return; | |
e410b5cb | 522 | |
f3467818 | 523 | r = amdgpu_vm_clear_freed(adev, vm, NULL); |
d38ceaf9 | 524 | if (r) |
2ffdaafb | 525 | goto error; |
194a3364 | 526 | |
80f95c57 | 527 | if (operation == AMDGPU_VA_OP_MAP || |
93bab704 | 528 | operation == AMDGPU_VA_OP_REPLACE) { |
05dcb5c8 | 529 | r = amdgpu_vm_bo_update(adev, bo_va, false); |
93bab704 GS |
530 | if (r) |
531 | goto error; | |
532 | } | |
d38ceaf9 | 533 | |
0abc6878 | 534 | r = amdgpu_vm_update_directories(adev, vm); |
0abc6878 | 535 | |
2ffdaafb | 536 | error: |
68fdd3df | 537 | if (r && r != -ERESTARTSYS) |
d38ceaf9 AD |
538 | DRM_ERROR("Couldn't update BO_VA (%d)\n", r); |
539 | } | |
540 | ||
d38ceaf9 AD |
541 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, |
542 | struct drm_file *filp) | |
543 | { | |
b85891bd JZ |
544 | const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | |
545 | AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | | |
66e02bc3 | 546 | AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; |
b85891bd JZ |
547 | const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | |
548 | AMDGPU_VM_PAGE_PRT; | |
549 | ||
34b5f6a6 | 550 | struct drm_amdgpu_gem_va *args = data; |
d38ceaf9 AD |
551 | struct drm_gem_object *gobj; |
552 | struct amdgpu_device *adev = dev->dev_private; | |
553 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
765e7fbf | 554 | struct amdgpu_bo *abo; |
d38ceaf9 | 555 | struct amdgpu_bo_va *bo_va; |
b88c8796 CK |
556 | struct amdgpu_bo_list_entry vm_pd; |
557 | struct ttm_validate_buffer tv; | |
49b02b18 | 558 | struct ww_acquire_ctx ticket; |
e1eb899b | 559 | struct list_head list, duplicates; |
5463545b | 560 | uint64_t va_flags; |
d38ceaf9 AD |
561 | int r = 0; |
562 | ||
34b5f6a6 | 563 | if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { |
4b7f0848 | 564 | dev_dbg(&dev->pdev->dev, |
ff4cd389 CK |
565 | "va_address 0x%LX is in reserved area 0x%LX\n", |
566 | args->va_address, AMDGPU_VA_RESERVED_SIZE); | |
d38ceaf9 AD |
567 | return -EINVAL; |
568 | } | |
569 | ||
bb7939b2 CK |
570 | if (args->va_address >= AMDGPU_VA_HOLE_START && |
571 | args->va_address < AMDGPU_VA_HOLE_END) { | |
572 | dev_dbg(&dev->pdev->dev, | |
573 | "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", | |
574 | args->va_address, AMDGPU_VA_HOLE_START, | |
575 | AMDGPU_VA_HOLE_END); | |
576 | return -EINVAL; | |
577 | } | |
578 | ||
579 | args->va_address &= AMDGPU_VA_HOLE_MASK; | |
580 | ||
b85891bd | 581 | if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { |
4b7f0848 | 582 | dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", |
b85891bd | 583 | args->flags); |
d38ceaf9 AD |
584 | return -EINVAL; |
585 | } | |
586 | ||
34b5f6a6 | 587 | switch (args->operation) { |
d38ceaf9 AD |
588 | case AMDGPU_VA_OP_MAP: |
589 | case AMDGPU_VA_OP_UNMAP: | |
dc54d3d1 | 590 | case AMDGPU_VA_OP_CLEAR: |
80f95c57 | 591 | case AMDGPU_VA_OP_REPLACE: |
d38ceaf9 AD |
592 | break; |
593 | default: | |
4b7f0848 | 594 | dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", |
34b5f6a6 | 595 | args->operation); |
d38ceaf9 AD |
596 | return -EINVAL; |
597 | } | |
598 | ||
49b02b18 | 599 | INIT_LIST_HEAD(&list); |
e1eb899b | 600 | INIT_LIST_HEAD(&duplicates); |
dc54d3d1 CK |
601 | if ((args->operation != AMDGPU_VA_OP_CLEAR) && |
602 | !(args->flags & AMDGPU_VM_PAGE_PRT)) { | |
b85891bd JZ |
603 | gobj = drm_gem_object_lookup(filp, args->handle); |
604 | if (gobj == NULL) | |
605 | return -ENOENT; | |
606 | abo = gem_to_amdgpu_bo(gobj); | |
607 | tv.bo = &abo->tbo; | |
608 | tv.shared = false; | |
609 | list_add(&tv.head, &list); | |
610 | } else { | |
611 | gobj = NULL; | |
612 | abo = NULL; | |
613 | } | |
49b02b18 | 614 | |
b88c8796 | 615 | amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); |
b5a5ec55 | 616 | |
e1eb899b | 617 | r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); |
b85891bd JZ |
618 | if (r) |
619 | goto error_unref; | |
34b5f6a6 | 620 | |
b85891bd JZ |
621 | if (abo) { |
622 | bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); | |
623 | if (!bo_va) { | |
624 | r = -ENOENT; | |
625 | goto error_backoff; | |
626 | } | |
dc54d3d1 | 627 | } else if (args->operation != AMDGPU_VA_OP_CLEAR) { |
b85891bd | 628 | bo_va = fpriv->prt_va; |
dc54d3d1 CK |
629 | } else { |
630 | bo_va = NULL; | |
d38ceaf9 AD |
631 | } |
632 | ||
34b5f6a6 | 633 | switch (args->operation) { |
d38ceaf9 | 634 | case AMDGPU_VA_OP_MAP: |
ec681545 | 635 | r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, |
663e4577 CK |
636 | args->map_size); |
637 | if (r) | |
638 | goto error_backoff; | |
5463545b | 639 | |
132f34e4 | 640 | va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); |
34b5f6a6 CK |
641 | r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, |
642 | args->offset_in_bo, args->map_size, | |
9f7eb536 | 643 | va_flags); |
d38ceaf9 AD |
644 | break; |
645 | case AMDGPU_VA_OP_UNMAP: | |
34b5f6a6 | 646 | r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); |
d38ceaf9 | 647 | break; |
dc54d3d1 CK |
648 | |
649 | case AMDGPU_VA_OP_CLEAR: | |
650 | r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, | |
651 | args->va_address, | |
652 | args->map_size); | |
653 | break; | |
80f95c57 | 654 | case AMDGPU_VA_OP_REPLACE: |
ec681545 | 655 | r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, |
80f95c57 CK |
656 | args->map_size); |
657 | if (r) | |
658 | goto error_backoff; | |
659 | ||
132f34e4 | 660 | va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); |
80f95c57 CK |
661 | r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, |
662 | args->offset_in_bo, args->map_size, | |
663 | va_flags); | |
664 | break; | |
d38ceaf9 AD |
665 | default: |
666 | break; | |
667 | } | |
b85891bd | 668 | if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) |
dc54d3d1 CK |
669 | amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list, |
670 | args->operation); | |
b85891bd JZ |
671 | |
672 | error_backoff: | |
2ffdaafb | 673 | ttm_eu_backoff_reservation(&ticket, &list); |
e98c1b0d | 674 | |
b85891bd | 675 | error_unref: |
f62facc2 | 676 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
677 | return r; |
678 | } | |
679 | ||
680 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
681 | struct drm_file *filp) | |
682 | { | |
e1eb899b | 683 | struct amdgpu_device *adev = dev->dev_private; |
d38ceaf9 AD |
684 | struct drm_amdgpu_gem_op *args = data; |
685 | struct drm_gem_object *gobj; | |
686 | struct amdgpu_bo *robj; | |
687 | int r; | |
688 | ||
a8ad0bd8 | 689 | gobj = drm_gem_object_lookup(filp, args->handle); |
d38ceaf9 AD |
690 | if (gobj == NULL) { |
691 | return -ENOENT; | |
692 | } | |
693 | robj = gem_to_amdgpu_bo(gobj); | |
694 | ||
695 | r = amdgpu_bo_reserve(robj, false); | |
696 | if (unlikely(r)) | |
697 | goto out; | |
698 | ||
699 | switch (args->op) { | |
700 | case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { | |
701 | struct drm_amdgpu_gem_create_in info; | |
7ecc245a | 702 | void __user *out = u64_to_user_ptr(args->value); |
d38ceaf9 AD |
703 | |
704 | info.bo_size = robj->gem_base.size; | |
705 | info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; | |
6d7d9c5a | 706 | info.domains = robj->preferred_domains; |
d38ceaf9 | 707 | info.domain_flags = robj->flags; |
4c28fb0b | 708 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
709 | if (copy_to_user(out, &info, sizeof(info))) |
710 | r = -EFAULT; | |
711 | break; | |
712 | } | |
d8f65a23 | 713 | case AMDGPU_GEM_OP_SET_PLACEMENT: |
803d89ad CJHR |
714 | if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { |
715 | r = -EINVAL; | |
716 | amdgpu_bo_unreserve(robj); | |
717 | break; | |
718 | } | |
cc325d19 | 719 | if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { |
d38ceaf9 | 720 | r = -EPERM; |
4c28fb0b | 721 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
722 | break; |
723 | } | |
6d7d9c5a | 724 | robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | |
1ea863fd CK |
725 | AMDGPU_GEM_DOMAIN_GTT | |
726 | AMDGPU_GEM_DOMAIN_CPU); | |
6d7d9c5a | 727 | robj->allowed_domains = robj->preferred_domains; |
1ea863fd CK |
728 | if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) |
729 | robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; | |
730 | ||
e1eb899b CK |
731 | if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) |
732 | amdgpu_vm_bo_invalidate(adev, robj, true); | |
733 | ||
4c28fb0b | 734 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
735 | break; |
736 | default: | |
4c28fb0b | 737 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
738 | r = -EINVAL; |
739 | } | |
740 | ||
d38ceaf9 | 741 | out: |
f62facc2 | 742 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
743 | return r; |
744 | } | |
745 | ||
746 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
747 | struct drm_device *dev, | |
748 | struct drm_mode_create_dumb *args) | |
749 | { | |
750 | struct amdgpu_device *adev = dev->dev_private; | |
751 | struct drm_gem_object *gobj; | |
752 | uint32_t handle; | |
bda31a24 | 753 | u32 domain = amdgpu_display_supported_domains(adev); |
d38ceaf9 AD |
754 | int r; |
755 | ||
8e911ab7 LP |
756 | args->pitch = amdgpu_align_pitch(adev, args->width, |
757 | DIV_ROUND_UP(args->bpp, 8), 0); | |
54ef0b54 | 758 | args->size = (u64)args->pitch * args->height; |
d38ceaf9 | 759 | args->size = ALIGN(args->size, PAGE_SIZE); |
bda31a24 DS |
760 | if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { |
761 | domain = AMDGPU_GEM_DOMAIN_VRAM; | |
762 | if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) | |
763 | domain = AMDGPU_GEM_DOMAIN_GTT; | |
764 | } | |
d38ceaf9 | 765 | |
bda31a24 | 766 | r = amdgpu_gem_object_create(adev, args->size, 0, domain, |
857d913d | 767 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, |
e1eb899b | 768 | false, NULL, &gobj); |
d38ceaf9 AD |
769 | if (r) |
770 | return -ENOMEM; | |
771 | ||
772 | r = drm_gem_handle_create(file_priv, gobj, &handle); | |
773 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 774 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
775 | if (r) { |
776 | return r; | |
777 | } | |
778 | args->handle = handle; | |
779 | return 0; | |
780 | } | |
781 | ||
782 | #if defined(CONFIG_DEBUG_FS) | |
6b155d6a CK |
783 | |
784 | #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ | |
785 | if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ | |
786 | seq_printf((m), " " #flag); \ | |
787 | } | |
788 | ||
7ea23565 CK |
789 | static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) |
790 | { | |
791 | struct drm_gem_object *gobj = ptr; | |
792 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); | |
793 | struct seq_file *m = data; | |
794 | ||
b1f223c0 CK |
795 | struct dma_buf_attachment *attachment; |
796 | struct dma_buf *dma_buf; | |
7ea23565 CK |
797 | unsigned domain; |
798 | const char *placement; | |
799 | unsigned pin_count; | |
800 | ||
801 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
802 | switch (domain) { | |
803 | case AMDGPU_GEM_DOMAIN_VRAM: | |
804 | placement = "VRAM"; | |
805 | break; | |
806 | case AMDGPU_GEM_DOMAIN_GTT: | |
807 | placement = " GTT"; | |
808 | break; | |
809 | case AMDGPU_GEM_DOMAIN_CPU: | |
810 | default: | |
811 | placement = " CPU"; | |
812 | break; | |
813 | } | |
b8e0e6e1 CK |
814 | seq_printf(m, "\t0x%08x: %12ld byte %s", |
815 | id, amdgpu_bo_size(bo), placement); | |
816 | ||
6aa7de05 | 817 | pin_count = READ_ONCE(bo->pin_count); |
7ea23565 CK |
818 | if (pin_count) |
819 | seq_printf(m, " pin count %d", pin_count); | |
b1f223c0 CK |
820 | |
821 | dma_buf = READ_ONCE(bo->gem_base.dma_buf); | |
822 | attachment = READ_ONCE(bo->gem_base.import_attach); | |
823 | ||
824 | if (attachment) | |
825 | seq_printf(m, " imported from %p", dma_buf); | |
826 | else if (dma_buf) | |
827 | seq_printf(m, " exported as %p", dma_buf); | |
828 | ||
6b155d6a CK |
829 | amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); |
830 | amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); | |
831 | amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); | |
832 | amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); | |
833 | amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); | |
834 | amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); | |
835 | amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); | |
836 | amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); | |
837 | ||
7ea23565 CK |
838 | seq_printf(m, "\n"); |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
d38ceaf9 AD |
843 | static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) |
844 | { | |
845 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
846 | struct drm_device *dev = node->minor->dev; | |
7ea23565 CK |
847 | struct drm_file *file; |
848 | int r; | |
d38ceaf9 | 849 | |
1d2ac403 | 850 | r = mutex_lock_interruptible(&dev->filelist_mutex); |
7ea23565 CK |
851 | if (r) |
852 | return r; | |
853 | ||
854 | list_for_each_entry(file, &dev->filelist, lhead) { | |
855 | struct task_struct *task; | |
856 | ||
857 | /* | |
858 | * Although we have a valid reference on file->pid, that does | |
859 | * not guarantee that the task_struct who called get_pid() is | |
860 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
861 | * Therefore, we need to protect this ->comm access using RCU. | |
862 | */ | |
863 | rcu_read_lock(); | |
864 | task = pid_task(file->pid, PIDTYPE_PID); | |
865 | seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), | |
866 | task ? task->comm : "<unknown>"); | |
867 | rcu_read_unlock(); | |
868 | ||
869 | spin_lock(&file->table_lock); | |
870 | idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); | |
871 | spin_unlock(&file->table_lock); | |
d38ceaf9 | 872 | } |
7ea23565 | 873 | |
1d2ac403 | 874 | mutex_unlock(&dev->filelist_mutex); |
d38ceaf9 AD |
875 | return 0; |
876 | } | |
877 | ||
06ab6832 | 878 | static const struct drm_info_list amdgpu_debugfs_gem_list[] = { |
d38ceaf9 AD |
879 | {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, |
880 | }; | |
881 | #endif | |
882 | ||
75758255 | 883 | int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
884 | { |
885 | #if defined(CONFIG_DEBUG_FS) | |
886 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); | |
887 | #endif | |
888 | return 0; | |
889 | } |