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1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/ktime.h> | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu.h" | |
32 | ||
33 | void amdgpu_gem_object_free(struct drm_gem_object *gobj) | |
34 | { | |
35 | struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); | |
36 | ||
37 | if (robj) { | |
38 | if (robj->gem_base.import_attach) | |
39 | drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); | |
40 | amdgpu_bo_unref(&robj); | |
41 | } | |
42 | } | |
43 | ||
44 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, | |
45 | int alignment, u32 initial_domain, | |
46 | u64 flags, bool kernel, | |
47 | struct drm_gem_object **obj) | |
48 | { | |
49 | struct amdgpu_bo *robj; | |
50 | unsigned long max_size; | |
51 | int r; | |
52 | ||
53 | *obj = NULL; | |
54 | /* At least align on page size */ | |
55 | if (alignment < PAGE_SIZE) { | |
56 | alignment = PAGE_SIZE; | |
57 | } | |
58 | ||
59 | if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) { | |
60 | /* Maximum bo size is the unpinned gtt size since we use the gtt to | |
61 | * handle vram to system pool migrations. | |
62 | */ | |
63 | max_size = adev->mc.gtt_size - adev->gart_pin_size; | |
64 | if (size > max_size) { | |
65 | DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", | |
66 | size >> 20, max_size >> 20); | |
67 | return -ENOMEM; | |
68 | } | |
69 | } | |
70 | retry: | |
71 | r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, flags, NULL, &robj); | |
72 | if (r) { | |
73 | if (r != -ERESTARTSYS) { | |
74 | if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
75 | initial_domain |= AMDGPU_GEM_DOMAIN_GTT; | |
76 | goto retry; | |
77 | } | |
78 | DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", | |
79 | size, initial_domain, alignment, r); | |
80 | } | |
81 | return r; | |
82 | } | |
83 | *obj = &robj->gem_base; | |
84 | robj->pid = task_pid_nr(current); | |
85 | ||
86 | mutex_lock(&adev->gem.mutex); | |
87 | list_add_tail(&robj->list, &adev->gem.objects); | |
88 | mutex_unlock(&adev->gem.mutex); | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
93 | int amdgpu_gem_init(struct amdgpu_device *adev) | |
94 | { | |
95 | INIT_LIST_HEAD(&adev->gem.objects); | |
96 | return 0; | |
97 | } | |
98 | ||
99 | void amdgpu_gem_fini(struct amdgpu_device *adev) | |
100 | { | |
101 | amdgpu_bo_force_delete(adev); | |
102 | } | |
103 | ||
104 | /* | |
105 | * Call from drm_gem_handle_create which appear in both new and open ioctl | |
106 | * case. | |
107 | */ | |
108 | int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) | |
109 | { | |
110 | struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); | |
111 | struct amdgpu_device *adev = rbo->adev; | |
112 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
113 | struct amdgpu_vm *vm = &fpriv->vm; | |
114 | struct amdgpu_bo_va *bo_va; | |
115 | int r; | |
116 | ||
117 | r = amdgpu_bo_reserve(rbo, false); | |
118 | if (r) { | |
119 | return r; | |
120 | } | |
121 | ||
122 | bo_va = amdgpu_vm_bo_find(vm, rbo); | |
123 | if (!bo_va) { | |
124 | bo_va = amdgpu_vm_bo_add(adev, vm, rbo); | |
125 | } else { | |
126 | ++bo_va->ref_count; | |
127 | } | |
128 | amdgpu_bo_unreserve(rbo); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
134 | struct drm_file *file_priv) | |
135 | { | |
136 | struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); | |
137 | struct amdgpu_device *adev = rbo->adev; | |
138 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
139 | struct amdgpu_vm *vm = &fpriv->vm; | |
140 | struct amdgpu_bo_va *bo_va; | |
141 | int r; | |
142 | ||
143 | r = amdgpu_bo_reserve(rbo, true); | |
144 | if (r) { | |
145 | dev_err(adev->dev, "leaking bo va because " | |
146 | "we fail to reserve bo (%d)\n", r); | |
147 | return; | |
148 | } | |
149 | bo_va = amdgpu_vm_bo_find(vm, rbo); | |
150 | if (bo_va) { | |
151 | if (--bo_va->ref_count == 0) { | |
152 | amdgpu_vm_bo_rmv(adev, bo_va); | |
153 | } | |
154 | } | |
155 | amdgpu_bo_unreserve(rbo); | |
156 | } | |
157 | ||
158 | static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) | |
159 | { | |
160 | if (r == -EDEADLK) { | |
161 | r = amdgpu_gpu_reset(adev); | |
162 | if (!r) | |
163 | r = -EAGAIN; | |
164 | } | |
165 | return r; | |
166 | } | |
167 | ||
168 | /* | |
169 | * GEM ioctls. | |
170 | */ | |
171 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
172 | struct drm_file *filp) | |
173 | { | |
174 | struct amdgpu_device *adev = dev->dev_private; | |
175 | union drm_amdgpu_gem_create *args = data; | |
176 | uint64_t size = args->in.bo_size; | |
177 | struct drm_gem_object *gobj; | |
178 | uint32_t handle; | |
179 | bool kernel = false; | |
180 | int r; | |
181 | ||
182 | down_read(&adev->exclusive_lock); | |
183 | /* create a gem object to contain this object in */ | |
184 | if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | | |
185 | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { | |
186 | kernel = true; | |
187 | if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) | |
188 | size = size << AMDGPU_GDS_SHIFT; | |
189 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) | |
190 | size = size << AMDGPU_GWS_SHIFT; | |
191 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) | |
192 | size = size << AMDGPU_OA_SHIFT; | |
193 | else { | |
194 | r = -EINVAL; | |
195 | goto error_unlock; | |
196 | } | |
197 | } | |
198 | size = roundup(size, PAGE_SIZE); | |
199 | ||
200 | r = amdgpu_gem_object_create(adev, size, args->in.alignment, | |
201 | (u32)(0xffffffff & args->in.domains), | |
202 | args->in.domain_flags, | |
203 | kernel, &gobj); | |
204 | if (r) | |
205 | goto error_unlock; | |
206 | ||
207 | r = drm_gem_handle_create(filp, gobj, &handle); | |
208 | /* drop reference from allocate - handle holds it now */ | |
209 | drm_gem_object_unreference_unlocked(gobj); | |
210 | if (r) | |
211 | goto error_unlock; | |
212 | ||
213 | memset(args, 0, sizeof(*args)); | |
214 | args->out.handle = handle; | |
215 | up_read(&adev->exclusive_lock); | |
216 | return 0; | |
217 | ||
218 | error_unlock: | |
219 | up_read(&adev->exclusive_lock); | |
220 | r = amdgpu_gem_handle_lockup(adev, r); | |
221 | return r; | |
222 | } | |
223 | ||
224 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
225 | struct drm_file *filp) | |
226 | { | |
227 | struct amdgpu_device *adev = dev->dev_private; | |
228 | struct drm_amdgpu_gem_userptr *args = data; | |
229 | struct drm_gem_object *gobj; | |
230 | struct amdgpu_bo *bo; | |
231 | uint32_t handle; | |
232 | int r; | |
233 | ||
234 | if (offset_in_page(args->addr | args->size)) | |
235 | return -EINVAL; | |
236 | ||
237 | /* reject unknown flag values */ | |
238 | if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | | |
239 | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | | |
240 | AMDGPU_GEM_USERPTR_REGISTER)) | |
241 | return -EINVAL; | |
242 | ||
243 | if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) || | |
244 | !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { | |
245 | ||
246 | /* if we want to write to it we must require anonymous | |
247 | memory and install a MMU notifier */ | |
248 | return -EACCES; | |
249 | } | |
250 | ||
251 | down_read(&adev->exclusive_lock); | |
252 | ||
253 | /* create a gem object to contain this object in */ | |
254 | r = amdgpu_gem_object_create(adev, args->size, 0, | |
255 | AMDGPU_GEM_DOMAIN_CPU, 0, | |
256 | 0, &gobj); | |
257 | if (r) | |
258 | goto handle_lockup; | |
259 | ||
260 | bo = gem_to_amdgpu_bo(gobj); | |
261 | r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); | |
262 | if (r) | |
263 | goto release_object; | |
264 | ||
265 | if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { | |
266 | r = amdgpu_mn_register(bo, args->addr); | |
267 | if (r) | |
268 | goto release_object; | |
269 | } | |
270 | ||
271 | if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { | |
272 | down_read(¤t->mm->mmap_sem); | |
273 | r = amdgpu_bo_reserve(bo, true); | |
274 | if (r) { | |
275 | up_read(¤t->mm->mmap_sem); | |
276 | goto release_object; | |
277 | } | |
278 | ||
279 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); | |
280 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
281 | amdgpu_bo_unreserve(bo); | |
282 | up_read(¤t->mm->mmap_sem); | |
283 | if (r) | |
284 | goto release_object; | |
285 | } | |
286 | ||
287 | r = drm_gem_handle_create(filp, gobj, &handle); | |
288 | /* drop reference from allocate - handle holds it now */ | |
289 | drm_gem_object_unreference_unlocked(gobj); | |
290 | if (r) | |
291 | goto handle_lockup; | |
292 | ||
293 | args->handle = handle; | |
294 | up_read(&adev->exclusive_lock); | |
295 | return 0; | |
296 | ||
297 | release_object: | |
298 | drm_gem_object_unreference_unlocked(gobj); | |
299 | ||
300 | handle_lockup: | |
301 | up_read(&adev->exclusive_lock); | |
302 | r = amdgpu_gem_handle_lockup(adev, r); | |
303 | ||
304 | return r; | |
305 | } | |
306 | ||
307 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
308 | struct drm_device *dev, | |
309 | uint32_t handle, uint64_t *offset_p) | |
310 | { | |
311 | struct drm_gem_object *gobj; | |
312 | struct amdgpu_bo *robj; | |
313 | ||
314 | gobj = drm_gem_object_lookup(dev, filp, handle); | |
315 | if (gobj == NULL) { | |
316 | return -ENOENT; | |
317 | } | |
318 | robj = gem_to_amdgpu_bo(gobj); | |
319 | if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) { | |
320 | drm_gem_object_unreference_unlocked(gobj); | |
321 | return -EPERM; | |
322 | } | |
323 | *offset_p = amdgpu_bo_mmap_offset(robj); | |
324 | drm_gem_object_unreference_unlocked(gobj); | |
325 | return 0; | |
326 | } | |
327 | ||
328 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
329 | struct drm_file *filp) | |
330 | { | |
331 | union drm_amdgpu_gem_mmap *args = data; | |
332 | uint32_t handle = args->in.handle; | |
333 | memset(args, 0, sizeof(*args)); | |
334 | return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); | |
335 | } | |
336 | ||
337 | /** | |
338 | * amdgpu_gem_timeout - calculate jiffies timeout from absolute value | |
339 | * | |
340 | * @timeout_ns: timeout in ns | |
341 | * | |
342 | * Calculate the timeout in jiffies from an absolute timeout in ns. | |
343 | */ | |
344 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) | |
345 | { | |
346 | unsigned long timeout_jiffies; | |
347 | ktime_t timeout; | |
348 | ||
349 | /* clamp timeout if it's to large */ | |
350 | if (((int64_t)timeout_ns) < 0) | |
351 | return MAX_SCHEDULE_TIMEOUT; | |
352 | ||
353 | timeout = ktime_sub_ns(ktime_get(), timeout_ns); | |
354 | if (ktime_to_ns(timeout) < 0) | |
355 | return 0; | |
356 | ||
357 | timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); | |
358 | /* clamp timeout to avoid unsigned-> signed overflow */ | |
359 | if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) | |
360 | return MAX_SCHEDULE_TIMEOUT - 1; | |
361 | ||
362 | return timeout_jiffies; | |
363 | } | |
364 | ||
365 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
366 | struct drm_file *filp) | |
367 | { | |
368 | struct amdgpu_device *adev = dev->dev_private; | |
369 | union drm_amdgpu_gem_wait_idle *args = data; | |
370 | struct drm_gem_object *gobj; | |
371 | struct amdgpu_bo *robj; | |
372 | uint32_t handle = args->in.handle; | |
373 | unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); | |
374 | int r = 0; | |
375 | long ret; | |
376 | ||
377 | gobj = drm_gem_object_lookup(dev, filp, handle); | |
378 | if (gobj == NULL) { | |
379 | return -ENOENT; | |
380 | } | |
381 | robj = gem_to_amdgpu_bo(gobj); | |
382 | if (timeout == 0) | |
383 | ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true); | |
384 | else | |
385 | ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout); | |
386 | ||
387 | /* ret == 0 means not signaled, | |
388 | * ret > 0 means signaled | |
389 | * ret < 0 means interrupted before timeout | |
390 | */ | |
391 | if (ret >= 0) { | |
392 | memset(args, 0, sizeof(*args)); | |
393 | args->out.status = (ret == 0); | |
394 | } else | |
395 | r = ret; | |
396 | ||
397 | drm_gem_object_unreference_unlocked(gobj); | |
398 | r = amdgpu_gem_handle_lockup(adev, r); | |
399 | return r; | |
400 | } | |
401 | ||
402 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
403 | struct drm_file *filp) | |
404 | { | |
405 | struct drm_amdgpu_gem_metadata *args = data; | |
406 | struct drm_gem_object *gobj; | |
407 | struct amdgpu_bo *robj; | |
408 | int r = -1; | |
409 | ||
410 | DRM_DEBUG("%d \n", args->handle); | |
411 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
412 | if (gobj == NULL) | |
413 | return -ENOENT; | |
414 | robj = gem_to_amdgpu_bo(gobj); | |
415 | ||
416 | r = amdgpu_bo_reserve(robj, false); | |
417 | if (unlikely(r != 0)) | |
418 | goto out; | |
419 | ||
420 | if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { | |
421 | amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); | |
422 | r = amdgpu_bo_get_metadata(robj, args->data.data, | |
423 | sizeof(args->data.data), | |
424 | &args->data.data_size_bytes, | |
425 | &args->data.flags); | |
426 | } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { | |
427 | r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); | |
428 | if (!r) | |
429 | r = amdgpu_bo_set_metadata(robj, args->data.data, | |
430 | args->data.data_size_bytes, | |
431 | args->data.flags); | |
432 | } | |
433 | ||
434 | amdgpu_bo_unreserve(robj); | |
435 | out: | |
436 | drm_gem_object_unreference_unlocked(gobj); | |
437 | return r; | |
438 | } | |
439 | ||
440 | /** | |
441 | * amdgpu_gem_va_update_vm -update the bo_va in its VM | |
442 | * | |
443 | * @adev: amdgpu_device pointer | |
444 | * @bo_va: bo_va to update | |
445 | * | |
446 | * Update the bo_va directly after setting it's address. Errors are not | |
447 | * vital here, so they are not reported back to userspace. | |
448 | */ | |
449 | static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, | |
450 | struct amdgpu_bo_va *bo_va) | |
451 | { | |
452 | struct ttm_validate_buffer tv, *entry; | |
453 | struct amdgpu_bo_list_entry *vm_bos; | |
454 | struct ww_acquire_ctx ticket; | |
455 | struct list_head list; | |
456 | unsigned domain; | |
457 | int r; | |
458 | ||
459 | INIT_LIST_HEAD(&list); | |
460 | ||
461 | tv.bo = &bo_va->bo->tbo; | |
462 | tv.shared = true; | |
463 | list_add(&tv.head, &list); | |
464 | ||
465 | vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list); | |
466 | if (!vm_bos) | |
467 | return; | |
468 | ||
469 | r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL); | |
470 | if (r) | |
471 | goto error_free; | |
472 | ||
473 | list_for_each_entry(entry, &list, head) { | |
474 | domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); | |
475 | /* if anything is swapped out don't swap it in here, | |
476 | just abort and wait for the next CS */ | |
477 | if (domain == AMDGPU_GEM_DOMAIN_CPU) | |
478 | goto error_unreserve; | |
479 | } | |
480 | ||
481 | mutex_lock(&bo_va->vm->mutex); | |
482 | r = amdgpu_vm_clear_freed(adev, bo_va->vm); | |
483 | if (r) | |
484 | goto error_unlock; | |
485 | ||
486 | r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); | |
487 | ||
488 | error_unlock: | |
489 | mutex_unlock(&bo_va->vm->mutex); | |
490 | ||
491 | error_unreserve: | |
492 | ttm_eu_backoff_reservation(&ticket, &list); | |
493 | ||
494 | error_free: | |
495 | drm_free_large(vm_bos); | |
496 | ||
497 | if (r) | |
498 | DRM_ERROR("Couldn't update BO_VA (%d)\n", r); | |
499 | } | |
500 | ||
501 | ||
502 | ||
503 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, | |
504 | struct drm_file *filp) | |
505 | { | |
506 | union drm_amdgpu_gem_va *args = data; | |
507 | struct drm_gem_object *gobj; | |
508 | struct amdgpu_device *adev = dev->dev_private; | |
509 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
510 | struct amdgpu_bo *rbo; | |
511 | struct amdgpu_bo_va *bo_va; | |
512 | uint32_t invalid_flags, va_flags = 0; | |
513 | int r = 0; | |
514 | ||
515 | if (!adev->vm_manager.enabled) { | |
516 | memset(args, 0, sizeof(*args)); | |
517 | args->out.result = AMDGPU_VA_RESULT_ERROR; | |
518 | return -ENOTTY; | |
519 | } | |
520 | ||
521 | if (args->in.va_address < AMDGPU_VA_RESERVED_SIZE) { | |
522 | dev_err(&dev->pdev->dev, | |
523 | "va_address 0x%lX is in reserved area 0x%X\n", | |
524 | (unsigned long)args->in.va_address, | |
525 | AMDGPU_VA_RESERVED_SIZE); | |
526 | memset(args, 0, sizeof(*args)); | |
527 | args->out.result = AMDGPU_VA_RESULT_ERROR; | |
528 | return -EINVAL; | |
529 | } | |
530 | ||
531 | invalid_flags = ~(AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | | |
532 | AMDGPU_VM_PAGE_EXECUTABLE); | |
533 | if ((args->in.flags & invalid_flags)) { | |
534 | dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", | |
535 | args->in.flags, invalid_flags); | |
536 | memset(args, 0, sizeof(*args)); | |
537 | args->out.result = AMDGPU_VA_RESULT_ERROR; | |
538 | return -EINVAL; | |
539 | } | |
540 | ||
541 | switch (args->in.operation) { | |
542 | case AMDGPU_VA_OP_MAP: | |
543 | case AMDGPU_VA_OP_UNMAP: | |
544 | break; | |
545 | default: | |
546 | dev_err(&dev->pdev->dev, "unsupported operation %d\n", | |
547 | args->in.operation); | |
548 | memset(args, 0, sizeof(*args)); | |
549 | args->out.result = AMDGPU_VA_RESULT_ERROR; | |
550 | return -EINVAL; | |
551 | } | |
552 | ||
553 | gobj = drm_gem_object_lookup(dev, filp, args->in.handle); | |
554 | if (gobj == NULL) { | |
555 | memset(args, 0, sizeof(*args)); | |
556 | args->out.result = AMDGPU_VA_RESULT_ERROR; | |
557 | return -ENOENT; | |
558 | } | |
559 | rbo = gem_to_amdgpu_bo(gobj); | |
560 | r = amdgpu_bo_reserve(rbo, false); | |
561 | if (r) { | |
562 | if (r != -ERESTARTSYS) { | |
563 | memset(args, 0, sizeof(*args)); | |
564 | args->out.result = AMDGPU_VA_RESULT_ERROR; | |
565 | } | |
566 | drm_gem_object_unreference_unlocked(gobj); | |
567 | return r; | |
568 | } | |
569 | bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); | |
570 | if (!bo_va) { | |
571 | memset(args, 0, sizeof(*args)); | |
572 | args->out.result = AMDGPU_VA_RESULT_ERROR; | |
573 | drm_gem_object_unreference_unlocked(gobj); | |
574 | return -ENOENT; | |
575 | } | |
576 | ||
577 | switch (args->in.operation) { | |
578 | case AMDGPU_VA_OP_MAP: | |
579 | if (args->in.flags & AMDGPU_VM_PAGE_READABLE) | |
580 | va_flags |= AMDGPU_PTE_READABLE; | |
581 | if (args->in.flags & AMDGPU_VM_PAGE_WRITEABLE) | |
582 | va_flags |= AMDGPU_PTE_WRITEABLE; | |
583 | if (args->in.flags & AMDGPU_VM_PAGE_EXECUTABLE) | |
584 | va_flags |= AMDGPU_PTE_EXECUTABLE; | |
585 | r = amdgpu_vm_bo_map(adev, bo_va, args->in.va_address, 0, | |
586 | amdgpu_bo_size(bo_va->bo), va_flags); | |
587 | break; | |
588 | case AMDGPU_VA_OP_UNMAP: | |
589 | r = amdgpu_vm_bo_unmap(adev, bo_va, args->in.va_address); | |
590 | break; | |
591 | default: | |
592 | break; | |
593 | } | |
594 | ||
595 | if (!r) { | |
596 | amdgpu_gem_va_update_vm(adev, bo_va); | |
597 | memset(args, 0, sizeof(*args)); | |
598 | args->out.result = AMDGPU_VA_RESULT_OK; | |
599 | } else { | |
600 | memset(args, 0, sizeof(*args)); | |
601 | args->out.result = AMDGPU_VA_RESULT_ERROR; | |
602 | } | |
603 | ||
604 | drm_gem_object_unreference_unlocked(gobj); | |
605 | return r; | |
606 | } | |
607 | ||
608 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
609 | struct drm_file *filp) | |
610 | { | |
611 | struct drm_amdgpu_gem_op *args = data; | |
612 | struct drm_gem_object *gobj; | |
613 | struct amdgpu_bo *robj; | |
614 | int r; | |
615 | ||
616 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
617 | if (gobj == NULL) { | |
618 | return -ENOENT; | |
619 | } | |
620 | robj = gem_to_amdgpu_bo(gobj); | |
621 | ||
622 | r = amdgpu_bo_reserve(robj, false); | |
623 | if (unlikely(r)) | |
624 | goto out; | |
625 | ||
626 | switch (args->op) { | |
627 | case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { | |
628 | struct drm_amdgpu_gem_create_in info; | |
629 | void __user *out = (void __user *)(long)args->value; | |
630 | ||
631 | info.bo_size = robj->gem_base.size; | |
632 | info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; | |
633 | info.domains = robj->initial_domain; | |
634 | info.domain_flags = robj->flags; | |
635 | if (copy_to_user(out, &info, sizeof(info))) | |
636 | r = -EFAULT; | |
637 | break; | |
638 | } | |
639 | case AMDGPU_GEM_OP_SET_INITIAL_DOMAIN: | |
640 | if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) { | |
641 | r = -EPERM; | |
642 | break; | |
643 | } | |
644 | robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM | | |
645 | AMDGPU_GEM_DOMAIN_GTT | | |
646 | AMDGPU_GEM_DOMAIN_CPU); | |
647 | break; | |
648 | default: | |
649 | r = -EINVAL; | |
650 | } | |
651 | ||
652 | amdgpu_bo_unreserve(robj); | |
653 | out: | |
654 | drm_gem_object_unreference_unlocked(gobj); | |
655 | return r; | |
656 | } | |
657 | ||
658 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
659 | struct drm_device *dev, | |
660 | struct drm_mode_create_dumb *args) | |
661 | { | |
662 | struct amdgpu_device *adev = dev->dev_private; | |
663 | struct drm_gem_object *gobj; | |
664 | uint32_t handle; | |
665 | int r; | |
666 | ||
667 | args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); | |
668 | args->size = args->pitch * args->height; | |
669 | args->size = ALIGN(args->size, PAGE_SIZE); | |
670 | ||
671 | r = amdgpu_gem_object_create(adev, args->size, 0, | |
672 | AMDGPU_GEM_DOMAIN_VRAM, | |
673 | 0, ttm_bo_type_device, | |
674 | &gobj); | |
675 | if (r) | |
676 | return -ENOMEM; | |
677 | ||
678 | r = drm_gem_handle_create(file_priv, gobj, &handle); | |
679 | /* drop reference from allocate - handle holds it now */ | |
680 | drm_gem_object_unreference_unlocked(gobj); | |
681 | if (r) { | |
682 | return r; | |
683 | } | |
684 | args->handle = handle; | |
685 | return 0; | |
686 | } | |
687 | ||
688 | #if defined(CONFIG_DEBUG_FS) | |
689 | static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) | |
690 | { | |
691 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
692 | struct drm_device *dev = node->minor->dev; | |
693 | struct amdgpu_device *adev = dev->dev_private; | |
694 | struct amdgpu_bo *rbo; | |
695 | unsigned i = 0; | |
696 | ||
697 | mutex_lock(&adev->gem.mutex); | |
698 | list_for_each_entry(rbo, &adev->gem.objects, list) { | |
699 | unsigned domain; | |
700 | const char *placement; | |
701 | ||
702 | domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type); | |
703 | switch (domain) { | |
704 | case AMDGPU_GEM_DOMAIN_VRAM: | |
705 | placement = "VRAM"; | |
706 | break; | |
707 | case AMDGPU_GEM_DOMAIN_GTT: | |
708 | placement = " GTT"; | |
709 | break; | |
710 | case AMDGPU_GEM_DOMAIN_CPU: | |
711 | default: | |
712 | placement = " CPU"; | |
713 | break; | |
714 | } | |
715 | seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n", | |
716 | i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20, | |
717 | placement, (unsigned long)rbo->pid); | |
718 | i++; | |
719 | } | |
720 | mutex_unlock(&adev->gem.mutex); | |
721 | return 0; | |
722 | } | |
723 | ||
724 | static struct drm_info_list amdgpu_debugfs_gem_list[] = { | |
725 | {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, | |
726 | }; | |
727 | #endif | |
728 | ||
729 | int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) | |
730 | { | |
731 | #if defined(CONFIG_DEBUG_FS) | |
732 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); | |
733 | #endif | |
734 | return 0; | |
735 | } |