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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/ktime.h> | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu.h" | |
32 | ||
33 | void amdgpu_gem_object_free(struct drm_gem_object *gobj) | |
34 | { | |
35 | struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); | |
36 | ||
37 | if (robj) { | |
38 | if (robj->gem_base.import_attach) | |
39 | drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); | |
9298e52f | 40 | amdgpu_mn_unregister(robj); |
d38ceaf9 AD |
41 | amdgpu_bo_unref(&robj); |
42 | } | |
43 | } | |
44 | ||
45 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, | |
46 | int alignment, u32 initial_domain, | |
47 | u64 flags, bool kernel, | |
48 | struct drm_gem_object **obj) | |
49 | { | |
50 | struct amdgpu_bo *robj; | |
51 | unsigned long max_size; | |
52 | int r; | |
53 | ||
54 | *obj = NULL; | |
55 | /* At least align on page size */ | |
56 | if (alignment < PAGE_SIZE) { | |
57 | alignment = PAGE_SIZE; | |
58 | } | |
59 | ||
60 | if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) { | |
61 | /* Maximum bo size is the unpinned gtt size since we use the gtt to | |
62 | * handle vram to system pool migrations. | |
63 | */ | |
64 | max_size = adev->mc.gtt_size - adev->gart_pin_size; | |
65 | if (size > max_size) { | |
66 | DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", | |
67 | size >> 20, max_size >> 20); | |
68 | return -ENOMEM; | |
69 | } | |
70 | } | |
71 | retry: | |
72d7668b CK |
72 | r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, |
73 | flags, NULL, NULL, &robj); | |
d38ceaf9 AD |
74 | if (r) { |
75 | if (r != -ERESTARTSYS) { | |
76 | if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
77 | initial_domain |= AMDGPU_GEM_DOMAIN_GTT; | |
78 | goto retry; | |
79 | } | |
80 | DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", | |
81 | size, initial_domain, alignment, r); | |
82 | } | |
83 | return r; | |
84 | } | |
85 | *obj = &robj->gem_base; | |
86 | robj->pid = task_pid_nr(current); | |
87 | ||
88 | mutex_lock(&adev->gem.mutex); | |
89 | list_add_tail(&robj->list, &adev->gem.objects); | |
90 | mutex_unlock(&adev->gem.mutex); | |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
95 | int amdgpu_gem_init(struct amdgpu_device *adev) | |
96 | { | |
97 | INIT_LIST_HEAD(&adev->gem.objects); | |
98 | return 0; | |
99 | } | |
100 | ||
101 | void amdgpu_gem_fini(struct amdgpu_device *adev) | |
102 | { | |
103 | amdgpu_bo_force_delete(adev); | |
104 | } | |
105 | ||
106 | /* | |
107 | * Call from drm_gem_handle_create which appear in both new and open ioctl | |
108 | * case. | |
109 | */ | |
110 | int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) | |
111 | { | |
112 | struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); | |
113 | struct amdgpu_device *adev = rbo->adev; | |
114 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
115 | struct amdgpu_vm *vm = &fpriv->vm; | |
116 | struct amdgpu_bo_va *bo_va; | |
117 | int r; | |
f48b2659 | 118 | mutex_lock(&vm->mutex); |
d38ceaf9 AD |
119 | r = amdgpu_bo_reserve(rbo, false); |
120 | if (r) { | |
f48b2659 | 121 | mutex_unlock(&vm->mutex); |
d38ceaf9 AD |
122 | return r; |
123 | } | |
124 | ||
125 | bo_va = amdgpu_vm_bo_find(vm, rbo); | |
126 | if (!bo_va) { | |
127 | bo_va = amdgpu_vm_bo_add(adev, vm, rbo); | |
128 | } else { | |
129 | ++bo_va->ref_count; | |
130 | } | |
131 | amdgpu_bo_unreserve(rbo); | |
f48b2659 | 132 | mutex_unlock(&vm->mutex); |
d38ceaf9 AD |
133 | return 0; |
134 | } | |
135 | ||
136 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
137 | struct drm_file *file_priv) | |
138 | { | |
139 | struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); | |
140 | struct amdgpu_device *adev = rbo->adev; | |
141 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
142 | struct amdgpu_vm *vm = &fpriv->vm; | |
143 | struct amdgpu_bo_va *bo_va; | |
144 | int r; | |
f48b2659 | 145 | mutex_lock(&vm->mutex); |
d38ceaf9 AD |
146 | r = amdgpu_bo_reserve(rbo, true); |
147 | if (r) { | |
f48b2659 | 148 | mutex_unlock(&vm->mutex); |
d38ceaf9 AD |
149 | dev_err(adev->dev, "leaking bo va because " |
150 | "we fail to reserve bo (%d)\n", r); | |
151 | return; | |
152 | } | |
153 | bo_va = amdgpu_vm_bo_find(vm, rbo); | |
154 | if (bo_va) { | |
155 | if (--bo_va->ref_count == 0) { | |
156 | amdgpu_vm_bo_rmv(adev, bo_va); | |
157 | } | |
158 | } | |
159 | amdgpu_bo_unreserve(rbo); | |
f48b2659 | 160 | mutex_unlock(&vm->mutex); |
d38ceaf9 AD |
161 | } |
162 | ||
163 | static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) | |
164 | { | |
165 | if (r == -EDEADLK) { | |
166 | r = amdgpu_gpu_reset(adev); | |
167 | if (!r) | |
168 | r = -EAGAIN; | |
169 | } | |
170 | return r; | |
171 | } | |
172 | ||
173 | /* | |
174 | * GEM ioctls. | |
175 | */ | |
176 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
177 | struct drm_file *filp) | |
178 | { | |
179 | struct amdgpu_device *adev = dev->dev_private; | |
180 | union drm_amdgpu_gem_create *args = data; | |
181 | uint64_t size = args->in.bo_size; | |
182 | struct drm_gem_object *gobj; | |
183 | uint32_t handle; | |
184 | bool kernel = false; | |
185 | int r; | |
186 | ||
d38ceaf9 AD |
187 | /* create a gem object to contain this object in */ |
188 | if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | | |
189 | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { | |
190 | kernel = true; | |
191 | if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) | |
192 | size = size << AMDGPU_GDS_SHIFT; | |
193 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) | |
194 | size = size << AMDGPU_GWS_SHIFT; | |
195 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) | |
196 | size = size << AMDGPU_OA_SHIFT; | |
197 | else { | |
198 | r = -EINVAL; | |
199 | goto error_unlock; | |
200 | } | |
201 | } | |
202 | size = roundup(size, PAGE_SIZE); | |
203 | ||
204 | r = amdgpu_gem_object_create(adev, size, args->in.alignment, | |
205 | (u32)(0xffffffff & args->in.domains), | |
206 | args->in.domain_flags, | |
207 | kernel, &gobj); | |
208 | if (r) | |
209 | goto error_unlock; | |
210 | ||
211 | r = drm_gem_handle_create(filp, gobj, &handle); | |
212 | /* drop reference from allocate - handle holds it now */ | |
213 | drm_gem_object_unreference_unlocked(gobj); | |
214 | if (r) | |
215 | goto error_unlock; | |
216 | ||
217 | memset(args, 0, sizeof(*args)); | |
218 | args->out.handle = handle; | |
d38ceaf9 AD |
219 | return 0; |
220 | ||
221 | error_unlock: | |
d38ceaf9 AD |
222 | r = amdgpu_gem_handle_lockup(adev, r); |
223 | return r; | |
224 | } | |
225 | ||
226 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
227 | struct drm_file *filp) | |
228 | { | |
229 | struct amdgpu_device *adev = dev->dev_private; | |
230 | struct drm_amdgpu_gem_userptr *args = data; | |
231 | struct drm_gem_object *gobj; | |
232 | struct amdgpu_bo *bo; | |
233 | uint32_t handle; | |
234 | int r; | |
235 | ||
236 | if (offset_in_page(args->addr | args->size)) | |
237 | return -EINVAL; | |
238 | ||
239 | /* reject unknown flag values */ | |
240 | if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | | |
241 | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | | |
242 | AMDGPU_GEM_USERPTR_REGISTER)) | |
243 | return -EINVAL; | |
244 | ||
245 | if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) || | |
246 | !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { | |
247 | ||
248 | /* if we want to write to it we must require anonymous | |
249 | memory and install a MMU notifier */ | |
250 | return -EACCES; | |
251 | } | |
252 | ||
d38ceaf9 AD |
253 | /* create a gem object to contain this object in */ |
254 | r = amdgpu_gem_object_create(adev, args->size, 0, | |
255 | AMDGPU_GEM_DOMAIN_CPU, 0, | |
256 | 0, &gobj); | |
257 | if (r) | |
258 | goto handle_lockup; | |
259 | ||
260 | bo = gem_to_amdgpu_bo(gobj); | |
261 | r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); | |
262 | if (r) | |
263 | goto release_object; | |
264 | ||
265 | if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { | |
266 | r = amdgpu_mn_register(bo, args->addr); | |
267 | if (r) | |
268 | goto release_object; | |
269 | } | |
270 | ||
271 | if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { | |
272 | down_read(¤t->mm->mmap_sem); | |
273 | r = amdgpu_bo_reserve(bo, true); | |
274 | if (r) { | |
275 | up_read(¤t->mm->mmap_sem); | |
276 | goto release_object; | |
277 | } | |
278 | ||
279 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); | |
280 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
281 | amdgpu_bo_unreserve(bo); | |
282 | up_read(¤t->mm->mmap_sem); | |
283 | if (r) | |
284 | goto release_object; | |
285 | } | |
286 | ||
287 | r = drm_gem_handle_create(filp, gobj, &handle); | |
288 | /* drop reference from allocate - handle holds it now */ | |
289 | drm_gem_object_unreference_unlocked(gobj); | |
290 | if (r) | |
291 | goto handle_lockup; | |
292 | ||
293 | args->handle = handle; | |
d38ceaf9 AD |
294 | return 0; |
295 | ||
296 | release_object: | |
297 | drm_gem_object_unreference_unlocked(gobj); | |
298 | ||
299 | handle_lockup: | |
d38ceaf9 AD |
300 | r = amdgpu_gem_handle_lockup(adev, r); |
301 | ||
302 | return r; | |
303 | } | |
304 | ||
305 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
306 | struct drm_device *dev, | |
307 | uint32_t handle, uint64_t *offset_p) | |
308 | { | |
309 | struct drm_gem_object *gobj; | |
310 | struct amdgpu_bo *robj; | |
311 | ||
312 | gobj = drm_gem_object_lookup(dev, filp, handle); | |
313 | if (gobj == NULL) { | |
314 | return -ENOENT; | |
315 | } | |
316 | robj = gem_to_amdgpu_bo(gobj); | |
271c8125 CK |
317 | if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) || |
318 | (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { | |
d38ceaf9 AD |
319 | drm_gem_object_unreference_unlocked(gobj); |
320 | return -EPERM; | |
321 | } | |
322 | *offset_p = amdgpu_bo_mmap_offset(robj); | |
323 | drm_gem_object_unreference_unlocked(gobj); | |
324 | return 0; | |
325 | } | |
326 | ||
327 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
328 | struct drm_file *filp) | |
329 | { | |
330 | union drm_amdgpu_gem_mmap *args = data; | |
331 | uint32_t handle = args->in.handle; | |
332 | memset(args, 0, sizeof(*args)); | |
333 | return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); | |
334 | } | |
335 | ||
336 | /** | |
337 | * amdgpu_gem_timeout - calculate jiffies timeout from absolute value | |
338 | * | |
339 | * @timeout_ns: timeout in ns | |
340 | * | |
341 | * Calculate the timeout in jiffies from an absolute timeout in ns. | |
342 | */ | |
343 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) | |
344 | { | |
345 | unsigned long timeout_jiffies; | |
346 | ktime_t timeout; | |
347 | ||
348 | /* clamp timeout if it's to large */ | |
349 | if (((int64_t)timeout_ns) < 0) | |
350 | return MAX_SCHEDULE_TIMEOUT; | |
351 | ||
0f117704 | 352 | timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); |
d38ceaf9 AD |
353 | if (ktime_to_ns(timeout) < 0) |
354 | return 0; | |
355 | ||
356 | timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); | |
357 | /* clamp timeout to avoid unsigned-> signed overflow */ | |
358 | if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) | |
359 | return MAX_SCHEDULE_TIMEOUT - 1; | |
360 | ||
361 | return timeout_jiffies; | |
362 | } | |
363 | ||
364 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
365 | struct drm_file *filp) | |
366 | { | |
367 | struct amdgpu_device *adev = dev->dev_private; | |
368 | union drm_amdgpu_gem_wait_idle *args = data; | |
369 | struct drm_gem_object *gobj; | |
370 | struct amdgpu_bo *robj; | |
371 | uint32_t handle = args->in.handle; | |
372 | unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); | |
373 | int r = 0; | |
374 | long ret; | |
375 | ||
376 | gobj = drm_gem_object_lookup(dev, filp, handle); | |
377 | if (gobj == NULL) { | |
378 | return -ENOENT; | |
379 | } | |
380 | robj = gem_to_amdgpu_bo(gobj); | |
381 | if (timeout == 0) | |
382 | ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true); | |
383 | else | |
384 | ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout); | |
385 | ||
386 | /* ret == 0 means not signaled, | |
387 | * ret > 0 means signaled | |
388 | * ret < 0 means interrupted before timeout | |
389 | */ | |
390 | if (ret >= 0) { | |
391 | memset(args, 0, sizeof(*args)); | |
392 | args->out.status = (ret == 0); | |
393 | } else | |
394 | r = ret; | |
395 | ||
396 | drm_gem_object_unreference_unlocked(gobj); | |
397 | r = amdgpu_gem_handle_lockup(adev, r); | |
398 | return r; | |
399 | } | |
400 | ||
401 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
402 | struct drm_file *filp) | |
403 | { | |
404 | struct drm_amdgpu_gem_metadata *args = data; | |
405 | struct drm_gem_object *gobj; | |
406 | struct amdgpu_bo *robj; | |
407 | int r = -1; | |
408 | ||
409 | DRM_DEBUG("%d \n", args->handle); | |
410 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
411 | if (gobj == NULL) | |
412 | return -ENOENT; | |
413 | robj = gem_to_amdgpu_bo(gobj); | |
414 | ||
415 | r = amdgpu_bo_reserve(robj, false); | |
416 | if (unlikely(r != 0)) | |
417 | goto out; | |
418 | ||
419 | if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { | |
420 | amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); | |
421 | r = amdgpu_bo_get_metadata(robj, args->data.data, | |
422 | sizeof(args->data.data), | |
423 | &args->data.data_size_bytes, | |
424 | &args->data.flags); | |
425 | } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { | |
0913eab6 DC |
426 | if (args->data.data_size_bytes > sizeof(args->data.data)) { |
427 | r = -EINVAL; | |
428 | goto unreserve; | |
429 | } | |
d38ceaf9 AD |
430 | r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); |
431 | if (!r) | |
432 | r = amdgpu_bo_set_metadata(robj, args->data.data, | |
433 | args->data.data_size_bytes, | |
434 | args->data.flags); | |
435 | } | |
436 | ||
0913eab6 | 437 | unreserve: |
d38ceaf9 AD |
438 | amdgpu_bo_unreserve(robj); |
439 | out: | |
440 | drm_gem_object_unreference_unlocked(gobj); | |
441 | return r; | |
442 | } | |
443 | ||
444 | /** | |
445 | * amdgpu_gem_va_update_vm -update the bo_va in its VM | |
446 | * | |
447 | * @adev: amdgpu_device pointer | |
448 | * @bo_va: bo_va to update | |
449 | * | |
450 | * Update the bo_va directly after setting it's address. Errors are not | |
451 | * vital here, so they are not reported back to userspace. | |
452 | */ | |
453 | static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, | |
194a3364 | 454 | struct amdgpu_bo_va *bo_va, uint32_t operation) |
d38ceaf9 AD |
455 | { |
456 | struct ttm_validate_buffer tv, *entry; | |
457 | struct amdgpu_bo_list_entry *vm_bos; | |
458 | struct ww_acquire_ctx ticket; | |
bf60efd3 | 459 | struct list_head list, duplicates; |
d38ceaf9 AD |
460 | unsigned domain; |
461 | int r; | |
462 | ||
463 | INIT_LIST_HEAD(&list); | |
bf60efd3 | 464 | INIT_LIST_HEAD(&duplicates); |
d38ceaf9 AD |
465 | |
466 | tv.bo = &bo_va->bo->tbo; | |
467 | tv.shared = true; | |
468 | list_add(&tv.head, &list); | |
469 | ||
470 | vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list); | |
471 | if (!vm_bos) | |
472 | return; | |
473 | ||
bf60efd3 CK |
474 | /* Provide duplicates to avoid -EALREADY */ |
475 | r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); | |
d38ceaf9 AD |
476 | if (r) |
477 | goto error_free; | |
478 | ||
479 | list_for_each_entry(entry, &list, head) { | |
480 | domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); | |
481 | /* if anything is swapped out don't swap it in here, | |
482 | just abort and wait for the next CS */ | |
483 | if (domain == AMDGPU_GEM_DOMAIN_CPU) | |
484 | goto error_unreserve; | |
485 | } | |
43c27fb5 CZ |
486 | r = amdgpu_vm_update_page_directory(adev, bo_va->vm); |
487 | if (r) | |
488 | goto error_unreserve; | |
d38ceaf9 | 489 | |
d38ceaf9 AD |
490 | r = amdgpu_vm_clear_freed(adev, bo_va->vm); |
491 | if (r) | |
f48b2659 | 492 | goto error_unreserve; |
194a3364 | 493 | |
494 | if (operation == AMDGPU_VA_OP_MAP) | |
495 | r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); | |
d38ceaf9 | 496 | |
d38ceaf9 AD |
497 | error_unreserve: |
498 | ttm_eu_backoff_reservation(&ticket, &list); | |
499 | ||
500 | error_free: | |
501 | drm_free_large(vm_bos); | |
502 | ||
68fdd3df | 503 | if (r && r != -ERESTARTSYS) |
d38ceaf9 AD |
504 | DRM_ERROR("Couldn't update BO_VA (%d)\n", r); |
505 | } | |
506 | ||
507 | ||
508 | ||
509 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, | |
510 | struct drm_file *filp) | |
511 | { | |
34b5f6a6 | 512 | struct drm_amdgpu_gem_va *args = data; |
d38ceaf9 AD |
513 | struct drm_gem_object *gobj; |
514 | struct amdgpu_device *adev = dev->dev_private; | |
515 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
516 | struct amdgpu_bo *rbo; | |
517 | struct amdgpu_bo_va *bo_va; | |
518 | uint32_t invalid_flags, va_flags = 0; | |
519 | int r = 0; | |
520 | ||
34b5f6a6 | 521 | if (!adev->vm_manager.enabled) |
d38ceaf9 | 522 | return -ENOTTY; |
d38ceaf9 | 523 | |
34b5f6a6 | 524 | if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { |
d38ceaf9 AD |
525 | dev_err(&dev->pdev->dev, |
526 | "va_address 0x%lX is in reserved area 0x%X\n", | |
34b5f6a6 | 527 | (unsigned long)args->va_address, |
d38ceaf9 | 528 | AMDGPU_VA_RESERVED_SIZE); |
d38ceaf9 AD |
529 | return -EINVAL; |
530 | } | |
531 | ||
fc220f65 CK |
532 | invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE | |
533 | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE); | |
34b5f6a6 | 534 | if ((args->flags & invalid_flags)) { |
d38ceaf9 | 535 | dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", |
34b5f6a6 | 536 | args->flags, invalid_flags); |
d38ceaf9 AD |
537 | return -EINVAL; |
538 | } | |
539 | ||
34b5f6a6 | 540 | switch (args->operation) { |
d38ceaf9 AD |
541 | case AMDGPU_VA_OP_MAP: |
542 | case AMDGPU_VA_OP_UNMAP: | |
543 | break; | |
544 | default: | |
545 | dev_err(&dev->pdev->dev, "unsupported operation %d\n", | |
34b5f6a6 | 546 | args->operation); |
d38ceaf9 AD |
547 | return -EINVAL; |
548 | } | |
549 | ||
34b5f6a6 CK |
550 | gobj = drm_gem_object_lookup(dev, filp, args->handle); |
551 | if (gobj == NULL) | |
d38ceaf9 | 552 | return -ENOENT; |
f48b2659 | 553 | mutex_lock(&fpriv->vm.mutex); |
d38ceaf9 AD |
554 | rbo = gem_to_amdgpu_bo(gobj); |
555 | r = amdgpu_bo_reserve(rbo, false); | |
556 | if (r) { | |
f48b2659 | 557 | mutex_unlock(&fpriv->vm.mutex); |
d38ceaf9 AD |
558 | drm_gem_object_unreference_unlocked(gobj); |
559 | return r; | |
560 | } | |
34b5f6a6 | 561 | |
d38ceaf9 AD |
562 | bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); |
563 | if (!bo_va) { | |
34b5f6a6 | 564 | amdgpu_bo_unreserve(rbo); |
f48b2659 | 565 | mutex_unlock(&fpriv->vm.mutex); |
d38ceaf9 AD |
566 | return -ENOENT; |
567 | } | |
568 | ||
34b5f6a6 | 569 | switch (args->operation) { |
d38ceaf9 | 570 | case AMDGPU_VA_OP_MAP: |
34b5f6a6 | 571 | if (args->flags & AMDGPU_VM_PAGE_READABLE) |
d38ceaf9 | 572 | va_flags |= AMDGPU_PTE_READABLE; |
34b5f6a6 | 573 | if (args->flags & AMDGPU_VM_PAGE_WRITEABLE) |
d38ceaf9 | 574 | va_flags |= AMDGPU_PTE_WRITEABLE; |
34b5f6a6 | 575 | if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE) |
d38ceaf9 | 576 | va_flags |= AMDGPU_PTE_EXECUTABLE; |
34b5f6a6 CK |
577 | r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, |
578 | args->offset_in_bo, args->map_size, | |
9f7eb536 | 579 | va_flags); |
d38ceaf9 AD |
580 | break; |
581 | case AMDGPU_VA_OP_UNMAP: | |
34b5f6a6 | 582 | r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); |
d38ceaf9 AD |
583 | break; |
584 | default: | |
585 | break; | |
586 | } | |
587 | ||
fc220f65 | 588 | if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) |
194a3364 | 589 | amdgpu_gem_va_update_vm(adev, bo_va, args->operation); |
f48b2659 | 590 | mutex_unlock(&fpriv->vm.mutex); |
d38ceaf9 AD |
591 | drm_gem_object_unreference_unlocked(gobj); |
592 | return r; | |
593 | } | |
594 | ||
595 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
596 | struct drm_file *filp) | |
597 | { | |
598 | struct drm_amdgpu_gem_op *args = data; | |
599 | struct drm_gem_object *gobj; | |
600 | struct amdgpu_bo *robj; | |
601 | int r; | |
602 | ||
603 | gobj = drm_gem_object_lookup(dev, filp, args->handle); | |
604 | if (gobj == NULL) { | |
605 | return -ENOENT; | |
606 | } | |
607 | robj = gem_to_amdgpu_bo(gobj); | |
608 | ||
609 | r = amdgpu_bo_reserve(robj, false); | |
610 | if (unlikely(r)) | |
611 | goto out; | |
612 | ||
613 | switch (args->op) { | |
614 | case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { | |
615 | struct drm_amdgpu_gem_create_in info; | |
616 | void __user *out = (void __user *)(long)args->value; | |
617 | ||
618 | info.bo_size = robj->gem_base.size; | |
619 | info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; | |
620 | info.domains = robj->initial_domain; | |
621 | info.domain_flags = robj->flags; | |
4c28fb0b | 622 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
623 | if (copy_to_user(out, &info, sizeof(info))) |
624 | r = -EFAULT; | |
625 | break; | |
626 | } | |
d8f65a23 | 627 | case AMDGPU_GEM_OP_SET_PLACEMENT: |
d38ceaf9 AD |
628 | if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) { |
629 | r = -EPERM; | |
4c28fb0b | 630 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
631 | break; |
632 | } | |
633 | robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM | | |
634 | AMDGPU_GEM_DOMAIN_GTT | | |
635 | AMDGPU_GEM_DOMAIN_CPU); | |
4c28fb0b | 636 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
637 | break; |
638 | default: | |
4c28fb0b | 639 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
640 | r = -EINVAL; |
641 | } | |
642 | ||
d38ceaf9 AD |
643 | out: |
644 | drm_gem_object_unreference_unlocked(gobj); | |
645 | return r; | |
646 | } | |
647 | ||
648 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
649 | struct drm_device *dev, | |
650 | struct drm_mode_create_dumb *args) | |
651 | { | |
652 | struct amdgpu_device *adev = dev->dev_private; | |
653 | struct drm_gem_object *gobj; | |
654 | uint32_t handle; | |
655 | int r; | |
656 | ||
657 | args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); | |
54ef0b54 | 658 | args->size = (u64)args->pitch * args->height; |
d38ceaf9 AD |
659 | args->size = ALIGN(args->size, PAGE_SIZE); |
660 | ||
661 | r = amdgpu_gem_object_create(adev, args->size, 0, | |
662 | AMDGPU_GEM_DOMAIN_VRAM, | |
857d913d AD |
663 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, |
664 | ttm_bo_type_device, | |
d38ceaf9 AD |
665 | &gobj); |
666 | if (r) | |
667 | return -ENOMEM; | |
668 | ||
669 | r = drm_gem_handle_create(file_priv, gobj, &handle); | |
670 | /* drop reference from allocate - handle holds it now */ | |
671 | drm_gem_object_unreference_unlocked(gobj); | |
672 | if (r) { | |
673 | return r; | |
674 | } | |
675 | args->handle = handle; | |
676 | return 0; | |
677 | } | |
678 | ||
679 | #if defined(CONFIG_DEBUG_FS) | |
680 | static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) | |
681 | { | |
682 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
683 | struct drm_device *dev = node->minor->dev; | |
684 | struct amdgpu_device *adev = dev->dev_private; | |
685 | struct amdgpu_bo *rbo; | |
686 | unsigned i = 0; | |
687 | ||
688 | mutex_lock(&adev->gem.mutex); | |
689 | list_for_each_entry(rbo, &adev->gem.objects, list) { | |
690 | unsigned domain; | |
691 | const char *placement; | |
692 | ||
693 | domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type); | |
694 | switch (domain) { | |
695 | case AMDGPU_GEM_DOMAIN_VRAM: | |
696 | placement = "VRAM"; | |
697 | break; | |
698 | case AMDGPU_GEM_DOMAIN_GTT: | |
699 | placement = " GTT"; | |
700 | break; | |
701 | case AMDGPU_GEM_DOMAIN_CPU: | |
702 | default: | |
703 | placement = " CPU"; | |
704 | break; | |
705 | } | |
706 | seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n", | |
707 | i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20, | |
708 | placement, (unsigned long)rbo->pid); | |
709 | i++; | |
710 | } | |
711 | mutex_unlock(&adev->gem.mutex); | |
712 | return 0; | |
713 | } | |
714 | ||
715 | static struct drm_info_list amdgpu_debugfs_gem_list[] = { | |
716 | {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, | |
717 | }; | |
718 | #endif | |
719 | ||
720 | int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) | |
721 | { | |
722 | #if defined(CONFIG_DEBUG_FS) | |
723 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); | |
724 | #endif | |
725 | return 0; | |
726 | } |