[mirror_ubuntu-kernels.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gfx.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __AMDGPU_GFX_H__
#define __AMDGPU_GFX_H__

/*
 * GFX stuff
 */
#include "clearstate_defs.h"
#include "amdgpu_ring.h"
#include "amdgpu_rlc.h"

/* GFX current status */
#define AMDGPU_GFX_NORMAL_MODE			0x00000000L
#define AMDGPU_GFX_SAFE_MODE			0x00000001L
#define AMDGPU_GFX_PG_DISABLED_MODE		0x00000002L
#define AMDGPU_GFX_CG_DISABLED_MODE		0x00000004L
#define AMDGPU_GFX_LBPW_DISABLED_MODE		0x00000008L

#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES

struct amdgpu_mec {
	struct amdgpu_bo	*hpd_eop_obj;
	u64			hpd_eop_gpu_addr;
	struct amdgpu_bo	*mec_fw_obj;
	u64			mec_fw_gpu_addr;
	u32 num_mec;
	u32 num_pipe_per_mec;
	u32 num_queue_per_pipe;
	void			*mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];

	/* These are the resources for which amdgpu takes ownership */
	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
};

enum amdgpu_unmap_queues_action {
	PREEMPT_QUEUES = 0,
	RESET_QUEUES,
	DISABLE_PROCESS_QUEUES,
	PREEMPT_QUEUES_NO_UNMAP,
};

struct kiq_pm4_funcs {
	/* Support ASIC-specific kiq pm4 packets*/
	void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
					uint64_t queue_mask);
	void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
					struct amdgpu_ring *ring);
	void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
				 struct amdgpu_ring *ring,
				 enum amdgpu_unmap_queues_action action,
				 u64 gpu_addr, u64 seq);
	void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
					struct amdgpu_ring *ring,
					u64 addr,
					u64 seq);
	/* Packet sizes */
	int set_resources_size;
	int map_queues_size;
	int unmap_queues_size;
	int query_status_size;
};

struct amdgpu_kiq {
	u64			eop_gpu_addr;
	struct amdgpu_bo	*eop_obj;
	spinlock_t              ring_lock;
	struct amdgpu_ring	ring;
	struct amdgpu_irq_src	irq;
	const struct kiq_pm4_funcs *pmf;
};

/*
 * GPU scratch registers structures, functions & helpers
 */
struct amdgpu_scratch {
	unsigned		num_reg;
	uint32_t                reg_base;
	uint32_t		free_mask;
};

/*
 * GFX configurations
 */
#define AMDGPU_GFX_MAX_SE 4
#define AMDGPU_GFX_MAX_SH_PER_SE 2

struct amdgpu_rb_config {
	uint32_t rb_backend_disable;
	uint32_t user_rb_backend_disable;
	uint32_t raster_config;
	uint32_t raster_config_1;
};

struct gb_addr_config {
	uint16_t pipe_interleave_size;
	uint8_t num_pipes;
	uint8_t max_compress_frags;
	uint8_t num_banks;
	uint8_t num_se;
	uint8_t num_rb_per_se;
};

struct amdgpu_gfx_config {
	unsigned max_shader_engines;
	unsigned max_tile_pipes;
	unsigned max_cu_per_sh;
	unsigned max_sh_per_se;
	unsigned max_backends_per_se;
	unsigned max_texture_channel_caches;
	unsigned max_gprs;
	unsigned max_gs_threads;
	unsigned max_hw_contexts;
	unsigned sc_prim_fifo_size_frontend;
	unsigned sc_prim_fifo_size_backend;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;

	unsigned num_tile_pipes;
	unsigned backend_enable_mask;
	unsigned mem_max_burst_length_bytes;
	unsigned mem_row_size_in_kb;
	unsigned shader_engine_tile_size;
	unsigned num_gpus;
	unsigned multi_gpu_tile_size;
	unsigned mc_arb_ramcfg;
	unsigned gb_addr_config;
	unsigned num_rbs;
	unsigned gs_vgt_table_depth;
	unsigned gs_prim_buffer_depth;

	uint32_t tile_mode_array[32];
	uint32_t macrotile_mode_array[16];

	struct gb_addr_config gb_addr_config_fields;
	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];

	/* gfx configure feature */
	uint32_t double_offchip_lds_buf;
	/* cached value of DB_DEBUG2 */
	uint32_t db_debug2;
	/* gfx10 specific config */
	uint32_t num_sc_per_sh;
	uint32_t num_packer_per_sc;
	uint32_t pa_sc_tile_steering_override;
};

struct amdgpu_cu_info {
	uint32_t simd_per_cu;
	uint32_t max_waves_per_simd;
	uint32_t wave_front_size;
	uint32_t max_scratch_slots_per_cu;
	uint32_t lds_size;

	/* total active CU number */
	uint32_t number;
	uint32_t ao_cu_mask;
	uint32_t ao_cu_bitmap[4][4];
	uint32_t bitmap[4][4];
};

struct amdgpu_gfx_funcs {
	/* get the gpu clock counter */
	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
			     u32 sh_num, u32 instance);
	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
			       uint32_t wave, uint32_t *dst, int *no_fields);
	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
				uint32_t wave, uint32_t thread, uint32_t start,
				uint32_t size, uint32_t *dst);
	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
				uint32_t wave, uint32_t start, uint32_t size,
				uint32_t *dst);
	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
				 u32 queue, u32 vmid);
	int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
	int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
};

struct amdgpu_ngg_buf {
	struct amdgpu_bo	*bo;
	uint64_t		gpu_addr;
	uint32_t		size;
	uint32_t		bo_size;
};

enum {
	NGG_PRIM = 0,
	NGG_POS,
	NGG_CNTL,
	NGG_PARAM,
	NGG_BUF_MAX
};

struct amdgpu_ngg {
	struct amdgpu_ngg_buf	buf[NGG_BUF_MAX];
	uint32_t		gds_reserve_addr;
	uint32_t		gds_reserve_size;
	bool			init;
};

struct sq_work {
	struct work_struct	work;
	unsigned ih_data;
};

struct amdgpu_pfp {
	struct amdgpu_bo		*pfp_fw_obj;
	uint64_t			pfp_fw_gpu_addr;
	uint32_t			*pfp_fw_ptr;
};

struct amdgpu_ce {
	struct amdgpu_bo		*ce_fw_obj;
	uint64_t			ce_fw_gpu_addr;
	uint32_t			*ce_fw_ptr;
};

struct amdgpu_me {
	struct amdgpu_bo		*me_fw_obj;
	uint64_t			me_fw_gpu_addr;
	uint32_t			*me_fw_ptr;
	uint32_t			num_me;
	uint32_t			num_pipe_per_me;
	uint32_t			num_queue_per_pipe;
	void				*mqd_backup[AMDGPU_MAX_GFX_RINGS + 1];

	/* These are the resources for which amdgpu takes ownership */
	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
};

struct amdgpu_gfx {
	struct mutex			gpu_clock_mutex;
	struct amdgpu_gfx_config	config;
	struct amdgpu_rlc		rlc;
	struct amdgpu_pfp		pfp;
	struct amdgpu_ce		ce;
	struct amdgpu_me		me;
	struct amdgpu_mec		mec;
	struct amdgpu_kiq		kiq;
	struct amdgpu_scratch		scratch;
	const struct firmware		*me_fw;	/* ME firmware */
	uint32_t			me_fw_version;
	const struct firmware		*pfp_fw; /* PFP firmware */
	uint32_t			pfp_fw_version;
	const struct firmware		*ce_fw;	/* CE firmware */
	uint32_t			ce_fw_version;
	const struct firmware		*rlc_fw; /* RLC firmware */
	uint32_t			rlc_fw_version;
	const struct firmware		*mec_fw; /* MEC firmware */
	uint32_t			mec_fw_version;
	const struct firmware		*mec2_fw; /* MEC2 firmware */
	uint32_t			mec2_fw_version;
	uint32_t			me_feature_version;
	uint32_t			ce_feature_version;
	uint32_t			pfp_feature_version;
	uint32_t			rlc_feature_version;
	uint32_t			rlc_srlc_fw_version;
	uint32_t			rlc_srlc_feature_version;
	uint32_t			rlc_srlg_fw_version;
	uint32_t			rlc_srlg_feature_version;
	uint32_t			rlc_srls_fw_version;
	uint32_t			rlc_srls_feature_version;
	uint32_t			mec_feature_version;
	uint32_t			mec2_feature_version;
	bool				mec_fw_write_wait;
	bool				me_fw_write_wait;
	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
	unsigned			num_gfx_rings;
	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
	unsigned			num_compute_rings;
	struct amdgpu_irq_src		eop_irq;
	struct amdgpu_irq_src		priv_reg_irq;
	struct amdgpu_irq_src		priv_inst_irq;
	struct amdgpu_irq_src		cp_ecc_error_irq;
	struct amdgpu_irq_src		sq_irq;
	struct sq_work			sq_work;

	/* gfx status */
	uint32_t			gfx_current_status;
	/* ce ram size*/
	unsigned			ce_ram_size;
	struct amdgpu_cu_info		cu_info;
	const struct amdgpu_gfx_funcs	*funcs;

	/* reset mask */
	uint32_t                        grbm_soft_reset;
	uint32_t                        srbm_soft_reset;

	/* NGG */
	struct amdgpu_ngg		ngg;

	/* gfx off */
	bool                            gfx_off_state; /* true: enabled, false: disabled */
	struct mutex                    gfx_off_mutex;
	uint32_t                        gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
	struct delayed_work             gfx_off_delay_work;

	/* pipe reservation */
	struct mutex			pipe_reserve_mutex;
	DECLARE_BITMAP			(pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);

	/*ras */
	struct ras_common_if		*ras_if;
};

#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))

/**
 * amdgpu_gfx_create_bitmask - create a bitmask
 *
 * @bit_width: length of the mask
 *
 * create a variable length bit mask.
 * Returns the bitmask.
 */
static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
{
	return (u32)((1ULL << bit_width) - 1);
}

int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);

void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
				 unsigned max_sh);

int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
			     struct amdgpu_ring *ring,
			     struct amdgpu_irq_src *irq);

void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
			      struct amdgpu_irq_src *irq);

void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
			unsigned hpd_size);

int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
			   unsigned mqd_size);
void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);

void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);

int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
				int pipe, int queue);
void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
				 int *mec, int *pipe, int *queue);
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
				     int pipe, int queue);
int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
			       int pipe, int queue);
void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
				int *me, int *pipe, int *queue);
bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
				    int pipe, int queue);
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);

#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __AMDGPU_GFX_H__
	25	#define __AMDGPU_GFX_H__
	26
448fe192 HR	27	/*
	28	* GFX stuff
	29	*/
	30	#include "clearstate_defs.h"
	31	#include "amdgpu_ring.h"
88dfc9a3	32	#include "amdgpu_rlc.h"
d38ceaf9	33
448fe192 HR	34	/* GFX current status */
	35	#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
	36	#define AMDGPU_GFX_SAFE_MODE 0x00000001L
	37	#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
	38	#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
	39	#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
6f8941a2	40
cf02b03f	41	#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
448fe192 HR	42	#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
	43
	44	struct amdgpu_mec {
	45	struct amdgpu_bo *hpd_eop_obj;
	46	u64 hpd_eop_gpu_addr;
	47	struct amdgpu_bo *mec_fw_obj;
	48	u64 mec_fw_gpu_addr;
	49	u32 num_mec;
	50	u32 num_pipe_per_mec;
	51	u32 num_queue_per_pipe;
	52	void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
	53
	54	/* These are the resources for which amdgpu takes ownership */
	55	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
	56	};
	57
19191961 JX	58	enum amdgpu_unmap_queues_action {
	59	PREEMPT_QUEUES = 0,
	60	RESET_QUEUES,
	61	DISABLE_PROCESS_QUEUES,
	62	PREEMPT_QUEUES_NO_UNMAP,
	63	};
	64
bc4a6f71 RZ	65	struct kiq_pm4_funcs {
	66	/* Support ASIC-specific kiq pm4 packets*/
	67	void (kiq_set_resources)(struct amdgpu_ring kiq_ring,
	68	uint64_t queue_mask);
	69	void (kiq_map_queues)(struct amdgpu_ring kiq_ring,
	70	struct amdgpu_ring *ring);
	71	void (kiq_unmap_queues)(struct amdgpu_ring kiq_ring,
19191961 JX	72	struct amdgpu_ring *ring,
	73	enum amdgpu_unmap_queues_action action,
	74	u64 gpu_addr, u64 seq);
bc4a6f71 RZ	75	void (kiq_query_status)(struct amdgpu_ring kiq_ring,
	76	struct amdgpu_ring *ring,
	77	u64 addr,
	78	u64 seq);
	79	/* Packet sizes */
	80	int set_resources_size;
	81	int map_queues_size;
	82	int unmap_queues_size;
	83	int query_status_size;
	84	};
	85
448fe192 HR	86	struct amdgpu_kiq {
	87	u64 eop_gpu_addr;
	88	struct amdgpu_bo *eop_obj;
	89	spinlock_t ring_lock;
	90	struct amdgpu_ring ring;
	91	struct amdgpu_irq_src irq;
bc4a6f71	92	const struct kiq_pm4_funcs *pmf;
448fe192 HR	93	};
	94
	95	/*
	96	* GPU scratch registers structures, functions & helpers
	97	*/
	98	struct amdgpu_scratch {
	99	unsigned num_reg;
	100	uint32_t reg_base;
	101	uint32_t free_mask;
	102	};
	103
	104	/*
	105	* GFX configurations
	106	*/
	107	#define AMDGPU_GFX_MAX_SE 4
	108	#define AMDGPU_GFX_MAX_SH_PER_SE 2
	109
	110	struct amdgpu_rb_config {
	111	uint32_t rb_backend_disable;
	112	uint32_t user_rb_backend_disable;
	113	uint32_t raster_config;
	114	uint32_t raster_config_1;
	115	};
	116
	117	struct gb_addr_config {
	118	uint16_t pipe_interleave_size;
	119	uint8_t num_pipes;
	120	uint8_t max_compress_frags;
	121	uint8_t num_banks;
	122	uint8_t num_se;
	123	uint8_t num_rb_per_se;
	124	};
	125
	126	struct amdgpu_gfx_config {
	127	unsigned max_shader_engines;
	128	unsigned max_tile_pipes;
	129	unsigned max_cu_per_sh;
	130	unsigned max_sh_per_se;
	131	unsigned max_backends_per_se;
	132	unsigned max_texture_channel_caches;
	133	unsigned max_gprs;
	134	unsigned max_gs_threads;
	135	unsigned max_hw_contexts;
	136	unsigned sc_prim_fifo_size_frontend;
	137	unsigned sc_prim_fifo_size_backend;
	138	unsigned sc_hiz_tile_fifo_size;
	139	unsigned sc_earlyz_tile_fifo_size;
	140
	141	unsigned num_tile_pipes;
	142	unsigned backend_enable_mask;
	143	unsigned mem_max_burst_length_bytes;
	144	unsigned mem_row_size_in_kb;
	145	unsigned shader_engine_tile_size;
	146	unsigned num_gpus;
	147	unsigned multi_gpu_tile_size;
	148	unsigned mc_arb_ramcfg;
	149	unsigned gb_addr_config;
	150	unsigned num_rbs;
	151	unsigned gs_vgt_table_depth;
	152	unsigned gs_prim_buffer_depth;
	153
	154	uint32_t tile_mode_array[32];
	155	uint32_t macrotile_mode_array[16];
	156
157	struct gb_addr_config gb_addr_config_fields;
158	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
159
160	/* gfx configure feature */
161	uint32_t double_offchip_lds_buf;
162	/* cached value of DB_DEBUG2 */
163	uint32_t db_debug2;
02a9e40a HZ	164	/* gfx10 specific config */
	165	uint32_t num_sc_per_sh;
	166	uint32_t num_packer_per_sc;
3e514732	167	uint32_t pa_sc_tile_steering_override;
448fe192 HR	168	};
	169
	170	struct amdgpu_cu_info {
	171	uint32_t simd_per_cu;
	172	uint32_t max_waves_per_simd;
	173	uint32_t wave_front_size;
	174	uint32_t max_scratch_slots_per_cu;
	175	uint32_t lds_size;
	176
	177	/* total active CU number */
	178	uint32_t number;
	179	uint32_t ao_cu_mask;
	180	uint32_t ao_cu_bitmap[4][4];
	181	uint32_t bitmap[4][4];
	182	};
	183
	184	struct amdgpu_gfx_funcs {
	185	/* get the gpu clock counter */
	186	uint64_t (get_gpu_clock_counter)(struct amdgpu_device adev);
	187	void (select_se_sh)(struct amdgpu_device adev, u32 se_num,
	188	u32 sh_num, u32 instance);
	189	void (read_wave_data)(struct amdgpu_device adev, uint32_t simd,
	190	uint32_t wave, uint32_t dst, int no_fields);
	191	void (read_wave_vgprs)(struct amdgpu_device adev, uint32_t simd,
	192	uint32_t wave, uint32_t thread, uint32_t start,
	193	uint32_t size, uint32_t *dst);
	194	void (read_wave_sgprs)(struct amdgpu_device adev, uint32_t simd,
	195	uint32_t wave, uint32_t start, uint32_t size,
	196	uint32_t *dst);
	197	void (select_me_pipe_q)(struct amdgpu_device adev, u32 me, u32 pipe,
0fa4246e	198	u32 queue, u32 vmid);
2c960ea0 DL	199	int (ras_error_inject)(struct amdgpu_device adev, void *inject_if);
2c960ea0 DL	200	int (query_ras_error_count) (struct amdgpu_device adev, void *ras_error_status);
448fe192 HR	201	};
	202
	203	struct amdgpu_ngg_buf {
	204	struct amdgpu_bo *bo;
	205	uint64_t gpu_addr;
	206	uint32_t size;
	207	uint32_t bo_size;
	208	};
	209
	210	enum {
	211	NGG_PRIM = 0,
	212	NGG_POS,
	213	NGG_CNTL,
	214	NGG_PARAM,
	215	NGG_BUF_MAX
	216	};
	217
	218	struct amdgpu_ngg {
	219	struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
	220	uint32_t gds_reserve_addr;
	221	uint32_t gds_reserve_size;
	222	bool init;
	223	};
	224
	225	struct sq_work {
	226	struct work_struct work;
	227	unsigned ih_data;
	228	};
	229
068ed934 HZ	230	struct amdgpu_pfp {
	231	struct amdgpu_bo *pfp_fw_obj;
	232	uint64_t pfp_fw_gpu_addr;
	233	uint32_t *pfp_fw_ptr;
	234	};
	235
2a00bb13 HZ	236	struct amdgpu_ce {
	237	struct amdgpu_bo *ce_fw_obj;
	238	uint64_t ce_fw_gpu_addr;
	239	uint32_t *ce_fw_ptr;
	240	};
	241
8825af65 HZ	242	struct amdgpu_me {
	243	struct amdgpu_bo *me_fw_obj;
	244	uint64_t me_fw_gpu_addr;
	245	uint32_t *me_fw_ptr;
cf02b03f HZ	246	uint32_t num_me;
	247	uint32_t num_pipe_per_me;
	248	uint32_t num_queue_per_pipe;
	249	void *mqd_backup[AMDGPU_MAX_GFX_RINGS + 1];
	250
	251	/* These are the resources for which amdgpu takes ownership */
	252	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
8825af65 HZ	253	};
8825af65 HZ	254
448fe192 HR	255	struct amdgpu_gfx {
	256	struct mutex gpu_clock_mutex;
	257	struct amdgpu_gfx_config config;
	258	struct amdgpu_rlc rlc;
068ed934	259	struct amdgpu_pfp pfp;
2a00bb13	260	struct amdgpu_ce ce;
8825af65	261	struct amdgpu_me me;
448fe192 HR	262	struct amdgpu_mec mec;
	263	struct amdgpu_kiq kiq;
	264	struct amdgpu_scratch scratch;
	265	const struct firmware me_fw; / ME firmware */
	266	uint32_t me_fw_version;
	267	const struct firmware pfp_fw; / PFP firmware */
	268	uint32_t pfp_fw_version;
	269	const struct firmware ce_fw; / CE firmware */
	270	uint32_t ce_fw_version;
	271	const struct firmware rlc_fw; / RLC firmware */
	272	uint32_t rlc_fw_version;
	273	const struct firmware mec_fw; / MEC firmware */
	274	uint32_t mec_fw_version;
	275	const struct firmware mec2_fw; / MEC2 firmware */
	276	uint32_t mec2_fw_version;
	277	uint32_t me_feature_version;
	278	uint32_t ce_feature_version;
	279	uint32_t pfp_feature_version;
	280	uint32_t rlc_feature_version;
	281	uint32_t rlc_srlc_fw_version;
	282	uint32_t rlc_srlc_feature_version;
	283	uint32_t rlc_srlg_fw_version;
	284	uint32_t rlc_srlg_feature_version;
	285	uint32_t rlc_srls_fw_version;
	286	uint32_t rlc_srls_feature_version;
	287	uint32_t mec_feature_version;
	288	uint32_t mec2_feature_version;
39b62541 ED	289	bool mec_fw_write_wait;
39b62541 ED	290	bool me_fw_write_wait;
448fe192 HR	291	struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
	292	unsigned num_gfx_rings;
	293	struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
	294	unsigned num_compute_rings;
	295	struct amdgpu_irq_src eop_irq;
	296	struct amdgpu_irq_src priv_reg_irq;
	297	struct amdgpu_irq_src priv_inst_irq;
	298	struct amdgpu_irq_src cp_ecc_error_irq;
	299	struct amdgpu_irq_src sq_irq;
	300	struct sq_work sq_work;
	301
	302	/* gfx status */
	303	uint32_t gfx_current_status;
	304	/* ce ram size*/
	305	unsigned ce_ram_size;
	306	struct amdgpu_cu_info cu_info;
	307	const struct amdgpu_gfx_funcs *funcs;
	308
	309	/* reset mask */
	310	uint32_t grbm_soft_reset;
	311	uint32_t srbm_soft_reset;
44779b43	312
448fe192 HR	313	/* NGG */
	314	struct amdgpu_ngg ngg;
	315
	316	/* gfx off */
	317	bool gfx_off_state; /* true: enabled, false: disabled */
	318	struct mutex gfx_off_mutex;
	319	uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
	320	struct delayed_work gfx_off_delay_work;
	321
	322	/* pipe reservation */
	323	struct mutex pipe_reserve_mutex;
	324	DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
760a1d55 FX	325
	326	/ras /
	327	struct ras_common_if *ras_if;
448fe192 HR	328	};
	329
	330	#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
	331	#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
0fa4246e	332	#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
b9683c21	333
378506a7 AD	334	/**
	335	* amdgpu_gfx_create_bitmask - create a bitmask
	336	*
	337	* @bit_width: length of the mask
	338	*
	339	* create a variable length bit mask.
	340	* Returns the bitmask.
	341	*/
	342	static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
	343	{
	344	return (u32)((1ULL << bit_width) - 1);
	345	}
	346
448fe192 HR	347	int amdgpu_gfx_scratch_get(struct amdgpu_device adev, uint32_t reg);
448fe192 HR	348	void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
2db0cdbe	349
448fe192 HR	350	void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
448fe192 HR	351	unsigned max_sh);
2db0cdbe	352
448fe192 HR	353	int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
	354	struct amdgpu_ring *ring,
	355	struct amdgpu_irq_src *irq);
2db0cdbe	356
448fe192 HR	357	void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
448fe192 HR	358	struct amdgpu_irq_src *irq);
2db0cdbe	359
448fe192 HR	360	void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
	361	int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
	362	unsigned hpd_size);
	363
4fc6a88f HZ	364	int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
	365	unsigned mqd_size);
	366	void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
ba0c13b7	367	int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
849aca9f	368	int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
448fe192 HR	369
448fe192 HR	370	void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
e537c994 HZ	371	void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
e537c994 HZ	372
7470bfcf HZ	373	int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
	374	int pipe, int queue);
	375	void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
	376	int mec, int pipe, int *queue);
448fe192 HR	377	bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
448fe192 HR	378	int pipe, int queue);
7470bfcf HZ	379	int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
	380	int pipe, int queue);
	381	void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
	382	int me, int pipe, int *queue);
	383	bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
	384	int pipe, int queue);
c2d358d7	385	void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
2db0cdbe	386
d38ceaf9	387	#endif