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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29#include <linux/seq_file.h>
30#include <linux/slab.h>
31#include <drm/drmP.h>
32#include <drm/amdgpu_drm.h>
33#include "amdgpu.h"
34#include "atom.h"
35
36/*
37 * IB
38 * IBs (Indirect Buffers) and areas of GPU accessible memory where
39 * commands are stored. You can put a pointer to the IB in the
40 * command ring and the hw will fetch the commands from the IB
41 * and execute them. Generally userspace acceleration drivers
42 * produce command buffers which are send to the kernel and
43 * put in IBs for execution by the requested ring.
44 */
45static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
46
47/**
48 * amdgpu_ib_get - request an IB (Indirect Buffer)
49 *
50 * @ring: ring index the IB is associated with
51 * @size: requested IB size
52 * @ib: IB object returned
53 *
54 * Request an IB (all asics). IBs are allocated using the
55 * suballocator.
56 * Returns 0 on success, error on failure.
57 */
b07c60c0 58int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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59 unsigned size, struct amdgpu_ib *ib)
60{
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61 int r;
62
63 if (size) {
bbf0b345 64 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
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65 &ib->sa_bo, size, 256);
66 if (r) {
67 dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
68 return r;
69 }
70
71 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
72
73 if (!vm)
74 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
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75 }
76
d38ceaf9 77 ib->vm = vm;
4ff37a83 78 ib->vm_id = 0;
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79
80 return 0;
81}
82
83/**
84 * amdgpu_ib_free - free an IB (Indirect Buffer)
85 *
86 * @adev: amdgpu_device pointer
87 * @ib: IB object to free
88 *
89 * Free an IB (all asics).
90 */
91void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
92{
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93 amdgpu_sa_bo_free(adev, &ib->sa_bo, ib->fence);
94 fence_put(ib->fence);
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95}
96
97/**
98 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
99 *
100 * @adev: amdgpu_device pointer
101 * @num_ibs: number of IBs to schedule
102 * @ibs: IB objects to schedule
ec72b800 103 * @f: fence created during this submission
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104 *
105 * Schedule an IB on the associated ring (all asics).
106 * Returns 0 on success, error on failure.
107 *
108 * On SI, there are two parallel engines fed from the primary ring,
109 * the CE (Constant Engine) and the DE (Drawing Engine). Since
110 * resource descriptors have moved to memory, the CE allows you to
111 * prime the caches while the DE is updating register state so that
112 * the resource descriptors will be already in cache when the draw is
113 * processed. To accomplish this, the userspace driver submits two
114 * IBs, one for the CE and one for the DE. If there is a CE IB (called
115 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
116 * to SI there was just a DE IB.
117 */
b07c60c0 118int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
336d1f5e 119 struct amdgpu_ib *ibs, struct fence *last_vm_update,
ec72b800 120 struct fence **f)
d38ceaf9 121{
b07c60c0 122 struct amdgpu_device *adev = ring->adev;
d38ceaf9 123 struct amdgpu_ib *ib = &ibs[0];
3cb485f3 124 struct amdgpu_ctx *ctx, *old_ctx;
d919ad49 125 struct amdgpu_vm *vm;
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126 unsigned i;
127 int r = 0;
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128
129 if (num_ibs == 0)
130 return -EINVAL;
131
3cb485f3 132 ctx = ibs->ctx;
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133 vm = ibs->vm;
134
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135 if (!ring->ready) {
136 dev_err(adev->dev, "couldn't schedule ib\n");
137 return -EINVAL;
138 }
be86c606 139
4ff37a83 140 if (vm && !ibs->vm_id) {
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141 dev_err(adev->dev, "VM IB without ID\n");
142 return -EINVAL;
143 }
144
867d0517 145 r = amdgpu_ring_alloc(ring, 256 * num_ibs);
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146 if (r) {
147 dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
148 return r;
149 }
150
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151 if (vm) {
152 /* do context switch */
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153 amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr,
154 ib->gds_base, ib->gds_size,
155 ib->gws_base, ib->gws_size,
156 ib->oa_base, ib->oa_size);
d38ceaf9 157
e722b71a 158 if (ring->funcs->emit_hdp_flush)
159 amdgpu_ring_emit_hdp_flush(ring);
160 }
d2edb07b 161
3cb485f3 162 old_ctx = ring->current_ctx;
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163 for (i = 0; i < num_ibs; ++i) {
164 ib = &ibs[i];
165
b07c60c0 166 if (ib->ctx != ctx || ib->vm != vm) {
3cb485f3 167 ring->current_ctx = old_ctx;
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168 if (ib->vm_id)
169 amdgpu_vm_reset_id(adev, ib->vm_id);
a27de35c 170 amdgpu_ring_undo(ring);
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171 return -EINVAL;
172 }
d38ceaf9 173 amdgpu_ring_emit_ib(ring, ib);
3cb485f3 174 ring->current_ctx = ctx;
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175 }
176
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177 if (vm) {
178 if (ring->funcs->emit_hdp_invalidate)
179 amdgpu_ring_emit_hdp_invalidate(ring);
180 }
181
336d1f5e 182 r = amdgpu_fence_emit(ring, &ib->fence);
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183 if (r) {
184 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
3cb485f3 185 ring->current_ctx = old_ctx;
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186 if (ib->vm_id)
187 amdgpu_vm_reset_id(adev, ib->vm_id);
a27de35c 188 amdgpu_ring_undo(ring);
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189 return r;
190 }
191
192 /* wrap the last IB with fence */
193 if (ib->user) {
194 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
195 addr += ib->user->offset;
5430a3ff 196 amdgpu_ring_emit_fence(ring, addr, ib->sequence,
890ee23f 197 AMDGPU_FENCE_FLAG_64BIT);
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198 }
199
ec72b800 200 if (f)
364beb2c 201 *f = fence_get(ib->fence);
ec72b800 202
a27de35c 203 amdgpu_ring_commit(ring);
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204 return 0;
205}
206
207/**
208 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
209 *
210 * @adev: amdgpu_device pointer
211 *
212 * Initialize the suballocator to manage a pool of memory
213 * for use as IBs (all asics).
214 * Returns 0 on success, error on failure.
215 */
216int amdgpu_ib_pool_init(struct amdgpu_device *adev)
217{
218 int r;
219
220 if (adev->ib_pool_ready) {
221 return 0;
222 }
223 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
224 AMDGPU_IB_POOL_SIZE*64*1024,
225 AMDGPU_GPU_PAGE_SIZE,
226 AMDGPU_GEM_DOMAIN_GTT);
227 if (r) {
228 return r;
229 }
230
231 r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo);
232 if (r) {
233 return r;
234 }
235
236 adev->ib_pool_ready = true;
237 if (amdgpu_debugfs_sa_init(adev)) {
238 dev_err(adev->dev, "failed to register debugfs file for SA\n");
239 }
240 return 0;
241}
242
243/**
244 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
245 *
246 * @adev: amdgpu_device pointer
247 *
248 * Tear down the suballocator managing the pool of memory
249 * for use as IBs (all asics).
250 */
251void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
252{
253 if (adev->ib_pool_ready) {
254 amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo);
255 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
256 adev->ib_pool_ready = false;
257 }
258}
259
260/**
261 * amdgpu_ib_ring_tests - test IBs on the rings
262 *
263 * @adev: amdgpu_device pointer
264 *
265 * Test an IB (Indirect Buffer) on each ring.
266 * If the test fails, disable the ring.
267 * Returns 0 on success, error if the primary GFX ring
268 * IB test fails.
269 */
270int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
271{
272 unsigned i;
273 int r;
274
275 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
276 struct amdgpu_ring *ring = adev->rings[i];
277
278 if (!ring || !ring->ready)
279 continue;
280
281 r = amdgpu_ring_test_ib(ring);
282 if (r) {
283 ring->ready = false;
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284
285 if (ring == &adev->gfx.gfx_ring[0]) {
286 /* oh, oh, that's really bad */
287 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
288 adev->accel_working = false;
289 return r;
290
291 } else {
292 /* still not good, but we can live with it */
293 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
294 }
295 }
296 }
297 return 0;
298}
299
300/*
301 * Debugfs info
302 */
303#if defined(CONFIG_DEBUG_FS)
304
305static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
306{
307 struct drm_info_node *node = (struct drm_info_node *) m->private;
308 struct drm_device *dev = node->minor->dev;
309 struct amdgpu_device *adev = dev->dev_private;
310
311 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
312
313 return 0;
314
315}
316
317static struct drm_info_list amdgpu_debugfs_sa_list[] = {
318 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
319};
320
321#endif
322
323static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
324{
325#if defined(CONFIG_DEBUG_FS)
326 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
327#else
328 return 0;
329#endif
330}