]>
Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | * Christian König | |
28 | */ | |
29 | #include <linux/seq_file.h> | |
30 | #include <linux/slab.h> | |
31 | #include <drm/drmP.h> | |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "atom.h" | |
35 | ||
36 | /* | |
37 | * IB | |
38 | * IBs (Indirect Buffers) and areas of GPU accessible memory where | |
39 | * commands are stored. You can put a pointer to the IB in the | |
40 | * command ring and the hw will fetch the commands from the IB | |
41 | * and execute them. Generally userspace acceleration drivers | |
42 | * produce command buffers which are send to the kernel and | |
43 | * put in IBs for execution by the requested ring. | |
44 | */ | |
45 | static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); | |
46 | ||
47 | /** | |
48 | * amdgpu_ib_get - request an IB (Indirect Buffer) | |
49 | * | |
50 | * @ring: ring index the IB is associated with | |
51 | * @size: requested IB size | |
52 | * @ib: IB object returned | |
53 | * | |
54 | * Request an IB (all asics). IBs are allocated using the | |
55 | * suballocator. | |
56 | * Returns 0 on success, error on failure. | |
57 | */ | |
58 | int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, | |
59 | unsigned size, struct amdgpu_ib *ib) | |
60 | { | |
61 | struct amdgpu_device *adev = ring->adev; | |
62 | int r; | |
63 | ||
64 | if (size) { | |
bbf0b345 | 65 | r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, |
d38ceaf9 AD |
66 | &ib->sa_bo, size, 256); |
67 | if (r) { | |
68 | dev_err(adev->dev, "failed to get a new IB (%d)\n", r); | |
69 | return r; | |
70 | } | |
71 | ||
72 | ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); | |
73 | ||
74 | if (!vm) | |
75 | ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); | |
d38ceaf9 AD |
76 | } |
77 | ||
78 | amdgpu_sync_create(&ib->sync); | |
79 | ||
80 | ib->ring = ring; | |
d38ceaf9 | 81 | ib->vm = vm; |
d38ceaf9 AD |
82 | |
83 | return 0; | |
84 | } | |
85 | ||
86 | /** | |
87 | * amdgpu_ib_free - free an IB (Indirect Buffer) | |
88 | * | |
89 | * @adev: amdgpu_device pointer | |
90 | * @ib: IB object to free | |
91 | * | |
92 | * Free an IB (all asics). | |
93 | */ | |
94 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib) | |
95 | { | |
4ce9891e CZ |
96 | amdgpu_sync_free(adev, &ib->sync, &ib->fence->base); |
97 | amdgpu_sa_bo_free(adev, &ib->sa_bo, &ib->fence->base); | |
6ef68c17 CK |
98 | if (ib->fence) |
99 | fence_put(&ib->fence->base); | |
d38ceaf9 AD |
100 | } |
101 | ||
102 | /** | |
103 | * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring | |
104 | * | |
105 | * @adev: amdgpu_device pointer | |
106 | * @num_ibs: number of IBs to schedule | |
107 | * @ibs: IB objects to schedule | |
108 | * @owner: owner for creating the fences | |
109 | * | |
110 | * Schedule an IB on the associated ring (all asics). | |
111 | * Returns 0 on success, error on failure. | |
112 | * | |
113 | * On SI, there are two parallel engines fed from the primary ring, | |
114 | * the CE (Constant Engine) and the DE (Drawing Engine). Since | |
115 | * resource descriptors have moved to memory, the CE allows you to | |
116 | * prime the caches while the DE is updating register state so that | |
117 | * the resource descriptors will be already in cache when the draw is | |
118 | * processed. To accomplish this, the userspace driver submits two | |
119 | * IBs, one for the CE and one for the DE. If there is a CE IB (called | |
120 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior | |
121 | * to SI there was just a DE IB. | |
122 | */ | |
123 | int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, | |
124 | struct amdgpu_ib *ibs, void *owner) | |
125 | { | |
d38ceaf9 | 126 | struct amdgpu_ib *ib = &ibs[0]; |
d919ad49 | 127 | struct amdgpu_ring *ring; |
3cb485f3 | 128 | struct amdgpu_ctx *ctx, *old_ctx; |
d919ad49 | 129 | struct amdgpu_vm *vm; |
d38ceaf9 AD |
130 | unsigned i; |
131 | int r = 0; | |
d38ceaf9 AD |
132 | |
133 | if (num_ibs == 0) | |
134 | return -EINVAL; | |
135 | ||
136 | ring = ibs->ring; | |
3cb485f3 | 137 | ctx = ibs->ctx; |
d919ad49 CK |
138 | vm = ibs->vm; |
139 | ||
d38ceaf9 AD |
140 | if (!ring->ready) { |
141 | dev_err(adev->dev, "couldn't schedule ib\n"); | |
142 | return -EINVAL; | |
143 | } | |
be86c606 | 144 | |
8d0a7cea CK |
145 | if (vm && !ibs->grabbed_vmid) { |
146 | dev_err(adev->dev, "VM IB without ID\n"); | |
147 | return -EINVAL; | |
148 | } | |
149 | ||
d38ceaf9 AD |
150 | r = amdgpu_ring_lock(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs); |
151 | if (r) { | |
152 | dev_err(adev->dev, "scheduling IB failed (%d).\n", r); | |
153 | return r; | |
154 | } | |
155 | ||
be86c606 | 156 | r = amdgpu_sync_wait(&ibs->sync); |
d38ceaf9 AD |
157 | if (r) { |
158 | amdgpu_ring_unlock_undo(ring); | |
be86c606 | 159 | dev_err(adev->dev, "failed to sync wait (%d)\n", r); |
d38ceaf9 AD |
160 | return r; |
161 | } | |
162 | ||
163 | if (vm) { | |
164 | /* do context switch */ | |
165 | amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update); | |
d38ceaf9 | 166 | |
e722b71a | 167 | if (ring->funcs->emit_gds_switch) |
168 | amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, | |
169 | ib->gds_base, ib->gds_size, | |
170 | ib->gws_base, ib->gws_size, | |
171 | ib->oa_base, ib->oa_size); | |
d38ceaf9 | 172 | |
e722b71a | 173 | if (ring->funcs->emit_hdp_flush) |
174 | amdgpu_ring_emit_hdp_flush(ring); | |
175 | } | |
d2edb07b | 176 | |
3cb485f3 | 177 | old_ctx = ring->current_ctx; |
d38ceaf9 AD |
178 | for (i = 0; i < num_ibs; ++i) { |
179 | ib = &ibs[i]; | |
180 | ||
3cb485f3 CK |
181 | if (ib->ring != ring || ib->ctx != ctx || ib->vm != vm) { |
182 | ring->current_ctx = old_ctx; | |
d38ceaf9 AD |
183 | amdgpu_ring_unlock_undo(ring); |
184 | return -EINVAL; | |
185 | } | |
d38ceaf9 | 186 | amdgpu_ring_emit_ib(ring, ib); |
3cb485f3 | 187 | ring->current_ctx = ctx; |
d38ceaf9 AD |
188 | } |
189 | ||
190 | r = amdgpu_fence_emit(ring, owner, &ib->fence); | |
191 | if (r) { | |
192 | dev_err(adev->dev, "failed to emit fence (%d)\n", r); | |
3cb485f3 | 193 | ring->current_ctx = old_ctx; |
d38ceaf9 AD |
194 | amdgpu_ring_unlock_undo(ring); |
195 | return r; | |
196 | } | |
197 | ||
198 | /* wrap the last IB with fence */ | |
199 | if (ib->user) { | |
200 | uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); | |
201 | addr += ib->user->offset; | |
5430a3ff | 202 | amdgpu_ring_emit_fence(ring, addr, ib->sequence, |
890ee23f | 203 | AMDGPU_FENCE_FLAG_64BIT); |
d38ceaf9 AD |
204 | } |
205 | ||
d38ceaf9 AD |
206 | amdgpu_ring_unlock_commit(ring); |
207 | return 0; | |
208 | } | |
209 | ||
210 | /** | |
211 | * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool | |
212 | * | |
213 | * @adev: amdgpu_device pointer | |
214 | * | |
215 | * Initialize the suballocator to manage a pool of memory | |
216 | * for use as IBs (all asics). | |
217 | * Returns 0 on success, error on failure. | |
218 | */ | |
219 | int amdgpu_ib_pool_init(struct amdgpu_device *adev) | |
220 | { | |
221 | int r; | |
222 | ||
223 | if (adev->ib_pool_ready) { | |
224 | return 0; | |
225 | } | |
226 | r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, | |
227 | AMDGPU_IB_POOL_SIZE*64*1024, | |
228 | AMDGPU_GPU_PAGE_SIZE, | |
229 | AMDGPU_GEM_DOMAIN_GTT); | |
230 | if (r) { | |
231 | return r; | |
232 | } | |
233 | ||
234 | r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); | |
235 | if (r) { | |
236 | return r; | |
237 | } | |
238 | ||
239 | adev->ib_pool_ready = true; | |
240 | if (amdgpu_debugfs_sa_init(adev)) { | |
241 | dev_err(adev->dev, "failed to register debugfs file for SA\n"); | |
242 | } | |
243 | return 0; | |
244 | } | |
245 | ||
246 | /** | |
247 | * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool | |
248 | * | |
249 | * @adev: amdgpu_device pointer | |
250 | * | |
251 | * Tear down the suballocator managing the pool of memory | |
252 | * for use as IBs (all asics). | |
253 | */ | |
254 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev) | |
255 | { | |
256 | if (adev->ib_pool_ready) { | |
257 | amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); | |
258 | amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); | |
259 | adev->ib_pool_ready = false; | |
260 | } | |
261 | } | |
262 | ||
263 | /** | |
264 | * amdgpu_ib_ring_tests - test IBs on the rings | |
265 | * | |
266 | * @adev: amdgpu_device pointer | |
267 | * | |
268 | * Test an IB (Indirect Buffer) on each ring. | |
269 | * If the test fails, disable the ring. | |
270 | * Returns 0 on success, error if the primary GFX ring | |
271 | * IB test fails. | |
272 | */ | |
273 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev) | |
274 | { | |
275 | unsigned i; | |
276 | int r; | |
277 | ||
278 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
279 | struct amdgpu_ring *ring = adev->rings[i]; | |
280 | ||
281 | if (!ring || !ring->ready) | |
282 | continue; | |
283 | ||
284 | r = amdgpu_ring_test_ib(ring); | |
285 | if (r) { | |
286 | ring->ready = false; | |
d38ceaf9 AD |
287 | |
288 | if (ring == &adev->gfx.gfx_ring[0]) { | |
289 | /* oh, oh, that's really bad */ | |
290 | DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); | |
291 | adev->accel_working = false; | |
292 | return r; | |
293 | ||
294 | } else { | |
295 | /* still not good, but we can live with it */ | |
296 | DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); | |
297 | } | |
298 | } | |
299 | } | |
300 | return 0; | |
301 | } | |
302 | ||
303 | /* | |
304 | * Debugfs info | |
305 | */ | |
306 | #if defined(CONFIG_DEBUG_FS) | |
307 | ||
308 | static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) | |
309 | { | |
310 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
311 | struct drm_device *dev = node->minor->dev; | |
312 | struct amdgpu_device *adev = dev->dev_private; | |
313 | ||
314 | amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); | |
315 | ||
316 | return 0; | |
317 | ||
318 | } | |
319 | ||
320 | static struct drm_info_list amdgpu_debugfs_sa_list[] = { | |
321 | {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, | |
322 | }; | |
323 | ||
324 | #endif | |
325 | ||
326 | static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) | |
327 | { | |
328 | #if defined(CONFIG_DEBUG_FS) | |
329 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); | |
330 | #else | |
331 | return 0; | |
332 | #endif | |
333 | } |