[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_mn.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Christian König <christian.koenig@amd.com>
 */

/**
 * DOC: MMU Notifier
 *
 * For coherent userptr handling registers an MMU notifier to inform the driver
 * about updates on the page tables of a process.
 *
 * When somebody tries to invalidate the page tables we block the update until
 * all operations on the pages in question are completed, then those pages are
 * marked as accessed and also dirty if it wasn't a read only access.
 *
 * New command submissions using the userptrs in question are delayed until all
 * page table invalidation are completed and we once more see a coherent process
 * address space.
 */

#include <linux/firmware.h>
#include <linux/module.h>
#include <drm/drm.h>

#include "amdgpu.h"
#include "amdgpu_amdkfd.h"

/**
 * struct amdgpu_mn_node
 *
 * @it: interval node defining start-last of the affected address range
 * @bos: list of all BOs in the affected address range
 *
 * Manages all BOs which are affected of a certain range of address space.
 */
struct amdgpu_mn_node {
	struct interval_tree_node	it;
	struct list_head		bos;
};

/**
 * amdgpu_mn_destroy - destroy the HMM mirror
 *
 * @work: previously sheduled work item
 *
 * Lazy destroys the notifier from a work item
 */
static void amdgpu_mn_destroy(struct work_struct *work)
{
	struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work);
	struct amdgpu_device *adev = amn->adev;
	struct amdgpu_mn_node *node, *next_node;
	struct amdgpu_bo *bo, *next_bo;

	mutex_lock(&adev->mn_lock);
	down_write(&amn->lock);
	hash_del(&amn->node);
	rbtree_postorder_for_each_entry_safe(node, next_node,
					     &amn->objects.rb_root, it.rb) {
		list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) {
			bo->mn = NULL;
			list_del_init(&bo->mn_list);
		}
		kfree(node);
	}
	up_write(&amn->lock);
	mutex_unlock(&adev->mn_lock);

	hmm_mirror_unregister(&amn->mirror);
	kfree(amn);
}

/**
 * amdgpu_hmm_mirror_release - callback to notify about mm destruction
 *
 * @mirror: the HMM mirror (mm) this callback is about
 *
 * Shedule a work item to lazy destroy HMM mirror.
 */
static void amdgpu_hmm_mirror_release(struct hmm_mirror *mirror)
{
	struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);

	INIT_WORK(&amn->work, amdgpu_mn_destroy);
	schedule_work(&amn->work);
}

/**
 * amdgpu_mn_lock - take the write side lock for this notifier
 *
 * @mn: our notifier
 */
void amdgpu_mn_lock(struct amdgpu_mn *mn)
{
	if (mn)
		down_write(&mn->lock);
}

/**
 * amdgpu_mn_unlock - drop the write side lock for this notifier
 *
 * @mn: our notifier
 */
void amdgpu_mn_unlock(struct amdgpu_mn *mn)
{
	if (mn)
		up_write(&mn->lock);
}

/**
 * amdgpu_mn_read_lock - take the read side lock for this notifier
 *
 * @amn: our notifier
 */
static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
{
	if (blockable)
		down_read(&amn->lock);
	else if (!down_read_trylock(&amn->lock))
		return -EAGAIN;

	return 0;
}

/**
 * amdgpu_mn_read_unlock - drop the read side lock for this notifier
 *
 * @amn: our notifier
 */
static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn)
{
	up_read(&amn->lock);
}

/**
 * amdgpu_mn_invalidate_node - unmap all BOs of a node
 *
 * @node: the node with the BOs to unmap
 * @start: start of address range affected
 * @end: end of address range affected
 *
 * Block for operations on BOs to finish and mark pages as accessed and
 * potentially dirty.
 */
static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node,
				      unsigned long start,
				      unsigned long end)
{
	struct amdgpu_bo *bo;
	long r;

	list_for_each_entry(bo, &node->bos, mn_list) {

		if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
			continue;

		r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
			true, false, MAX_SCHEDULE_TIMEOUT);
		if (r <= 0)
			DRM_ERROR("(%ld) failed to wait for user bo\n", r);
	}
}

/**
 * amdgpu_mn_sync_pagetables_gfx - callback to notify about mm change
 *
 * @mirror: the hmm_mirror (mm) is about to update
 * @update: the update start, end address
 *
 * Block for operations on BOs to finish and mark pages as accessed and
 * potentially dirty.
 */
static int amdgpu_mn_sync_pagetables_gfx(struct hmm_mirror *mirror,
			const struct hmm_update *update)
{
	struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
	unsigned long start = update->start;
	unsigned long end = update->end;
	bool blockable = update->blockable;
	struct interval_tree_node *it;

	/* notification is exclusive, but interval is inclusive */
	end -= 1;

	/* TODO we should be able to split locking for interval tree and
	 * amdgpu_mn_invalidate_node
	 */
	if (amdgpu_mn_read_lock(amn, blockable))
		return -EAGAIN;

	it = interval_tree_iter_first(&amn->objects, start, end);
	while (it) {
		struct amdgpu_mn_node *node;

		if (!blockable) {
			amdgpu_mn_read_unlock(amn);
			return -EAGAIN;
		}

		node = container_of(it, struct amdgpu_mn_node, it);
		it = interval_tree_iter_next(it, start, end);

		amdgpu_mn_invalidate_node(node, start, end);
	}

	amdgpu_mn_read_unlock(amn);

	return 0;
}

/**
 * amdgpu_mn_sync_pagetables_hsa - callback to notify about mm change
 *
 * @mirror: the hmm_mirror (mm) is about to update
 * @update: the update start, end address
 *
 * We temporarily evict all BOs between start and end. This
 * necessitates evicting all user-mode queues of the process. The BOs
 * are restorted in amdgpu_mn_invalidate_range_end_hsa.
 */
static int amdgpu_mn_sync_pagetables_hsa(struct hmm_mirror *mirror,
			const struct hmm_update *update)
{
	struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
	unsigned long start = update->start;
	unsigned long end = update->end;
	bool blockable = update->blockable;
	struct interval_tree_node *it;

	/* notification is exclusive, but interval is inclusive */
	end -= 1;

	if (amdgpu_mn_read_lock(amn, blockable))
		return -EAGAIN;

	it = interval_tree_iter_first(&amn->objects, start, end);
	while (it) {
		struct amdgpu_mn_node *node;
		struct amdgpu_bo *bo;

		if (!blockable) {
			amdgpu_mn_read_unlock(amn);
			return -EAGAIN;
		}

		node = container_of(it, struct amdgpu_mn_node, it);
		it = interval_tree_iter_next(it, start, end);

		list_for_each_entry(bo, &node->bos, mn_list) {
			struct kgd_mem *mem = bo->kfd_bo;

			if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm,
							 start, end))
				amdgpu_amdkfd_evict_userptr(mem, amn->mm);
		}
	}

	amdgpu_mn_read_unlock(amn);

	return 0;
}

/* Low bits of any reasonable mm pointer will be unused due to struct
 * alignment. Use these bits to make a unique key from the mm pointer
 * and notifier type.
 */
#define AMDGPU_MN_KEY(mm, type) ((unsigned long)(mm) + (type))

static struct hmm_mirror_ops amdgpu_hmm_mirror_ops[] = {
	[AMDGPU_MN_TYPE_GFX] = {
		.sync_cpu_device_pagetables = amdgpu_mn_sync_pagetables_gfx,
		.release = amdgpu_hmm_mirror_release
	},
	[AMDGPU_MN_TYPE_HSA] = {
		.sync_cpu_device_pagetables = amdgpu_mn_sync_pagetables_hsa,
		.release = amdgpu_hmm_mirror_release
	},
};

/**
 * amdgpu_mn_get - create HMM mirror context
 *
 * @adev: amdgpu device pointer
 * @type: type of MMU notifier context
 *
 * Creates a HMM mirror context for current->mm.
 */
struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev,
				enum amdgpu_mn_type type)
{
	struct mm_struct *mm = current->mm;
	struct amdgpu_mn *amn;
	unsigned long key = AMDGPU_MN_KEY(mm, type);
	int r;

	mutex_lock(&adev->mn_lock);
	if (down_write_killable(&mm->mmap_sem)) {
		mutex_unlock(&adev->mn_lock);
		return ERR_PTR(-EINTR);
	}

	hash_for_each_possible(adev->mn_hash, amn, node, key)
		if (AMDGPU_MN_KEY(amn->mm, amn->type) == key)
			goto release_locks;

	amn = kzalloc(sizeof(*amn), GFP_KERNEL);
	if (!amn) {
		amn = ERR_PTR(-ENOMEM);
		goto release_locks;
	}

	amn->adev = adev;
	amn->mm = mm;
	init_rwsem(&amn->lock);
	amn->type = type;
	amn->objects = RB_ROOT_CACHED;

	amn->mirror.ops = &amdgpu_hmm_mirror_ops[type];
	r = hmm_mirror_register(&amn->mirror, mm);
	if (r)
		goto free_amn;

	hash_add(adev->mn_hash, &amn->node, AMDGPU_MN_KEY(mm, type));

release_locks:
	up_write(&mm->mmap_sem);
	mutex_unlock(&adev->mn_lock);

	return amn;

free_amn:
	up_write(&mm->mmap_sem);
	mutex_unlock(&adev->mn_lock);
	kfree(amn);

	return ERR_PTR(r);
}

/**
 * amdgpu_mn_register - register a BO for notifier updates
 *
 * @bo: amdgpu buffer object
 * @addr: userptr addr we should monitor
 *
 * Registers an HMM mirror for the given BO at the specified address.
 * Returns 0 on success, -ERRNO if anything goes wrong.
 */
int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
{
	unsigned long end = addr + amdgpu_bo_size(bo) - 1;
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
	enum amdgpu_mn_type type =
		bo->kfd_bo ? AMDGPU_MN_TYPE_HSA : AMDGPU_MN_TYPE_GFX;
	struct amdgpu_mn *amn;
	struct amdgpu_mn_node *node = NULL, *new_node;
	struct list_head bos;
	struct interval_tree_node *it;

	amn = amdgpu_mn_get(adev, type);
	if (IS_ERR(amn))
		return PTR_ERR(amn);

	new_node = kmalloc(sizeof(*new_node), GFP_KERNEL);
	if (!new_node)
		return -ENOMEM;

	INIT_LIST_HEAD(&bos);

	down_write(&amn->lock);

	while ((it = interval_tree_iter_first(&amn->objects, addr, end))) {
		kfree(node);
		node = container_of(it, struct amdgpu_mn_node, it);
		interval_tree_remove(&node->it, &amn->objects);
		addr = min(it->start, addr);
		end = max(it->last, end);
		list_splice(&node->bos, &bos);
	}

	if (!node)
		node = new_node;
	else
		kfree(new_node);

	bo->mn = amn;

	node->it.start = addr;
	node->it.last = end;
	INIT_LIST_HEAD(&node->bos);
	list_splice(&bos, &node->bos);
	list_add(&bo->mn_list, &node->bos);

	interval_tree_insert(&node->it, &amn->objects);

	up_write(&amn->lock);

	return 0;
}

/**
 * amdgpu_mn_unregister - unregister a BO for HMM mirror updates
 *
 * @bo: amdgpu buffer object
 *
 * Remove any registration of HMM mirror updates from the buffer object.
 */
void amdgpu_mn_unregister(struct amdgpu_bo *bo)
{
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
	struct amdgpu_mn *amn;
	struct list_head *head;

	mutex_lock(&adev->mn_lock);

	amn = bo->mn;
	if (amn == NULL) {
		mutex_unlock(&adev->mn_lock);
		return;
	}

	down_write(&amn->lock);

	/* save the next list entry for later */
	head = bo->mn_list.next;

	bo->mn = NULL;
	list_del_init(&bo->mn_list);

	if (list_empty(head)) {
		struct amdgpu_mn_node *node;

		node = container_of(head, struct amdgpu_mn_node, bos);
		interval_tree_remove(&node->it, &amn->objects);
		kfree(node);
	}

	up_write(&amn->lock);
	mutex_unlock(&adev->mn_lock);
}

/* flags used by HMM internal, not related to CPU/GPU PTE flags */
static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = {
		(1 << 0), /* HMM_PFN_VALID */
		(1 << 1), /* HMM_PFN_WRITE */
		0 /* HMM_PFN_DEVICE_PRIVATE */
};

static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = {
		0xfffffffffffffffeUL, /* HMM_PFN_ERROR */
		0, /* HMM_PFN_NONE */
		0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */
};

void amdgpu_hmm_init_range(struct hmm_range *range)
{
	if (range) {
		range->flags = hmm_range_flags;
		range->values = hmm_range_values;
		range->pfn_shift = PAGE_SHIFT;
		INIT_LIST_HEAD(&range->list);
	}
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Christian König <christian.koenig@amd.com>
	29	*/
	30
ad7f0b63 CK	31	/**
	32	* DOC: MMU Notifier
	33	*
	34	* For coherent userptr handling registers an MMU notifier to inform the driver
	35	* about updates on the page tables of a process.
	36	*
	37	* When somebody tries to invalidate the page tables we block the update until
	38	* all operations on the pages in question are completed, then those pages are
	39	* marked as accessed and also dirty if it wasn't a read only access.
	40	*
	41	* New command submissions using the userptrs in question are delayed until all
	42	* page table invalidation are completed and we once more see a coherent process
	43	* address space.
	44	*/
	45
d38ceaf9 AD	46	#include <linux/firmware.h>
d38ceaf9 AD	47	#include <linux/module.h>
d38ceaf9 AD	48	#include <drm/drm.h>
	49
	50	#include "amdgpu.h"
e52482de	51	#include "amdgpu_amdkfd.h"
d38ceaf9	52
ad7f0b63 CK	53	/**
	54	* struct amdgpu_mn_node
	55	*
	56	* @it: interval node defining start-last of the affected address range
	57	* @bos: list of all BOs in the affected address range
	58	*
	59	* Manages all BOs which are affected of a certain range of address space.
	60	*/
d38ceaf9 AD	61	struct amdgpu_mn_node {
	62	struct interval_tree_node it;
	63	struct list_head bos;
	64	};
	65
	66	/**
2c5a51f5	67	* amdgpu_mn_destroy - destroy the HMM mirror
d38ceaf9 AD	68	*
	69	* @work: previously sheduled work item
	70	*
	71	* Lazy destroys the notifier from a work item
	72	*/
	73	static void amdgpu_mn_destroy(struct work_struct *work)
	74	{
528e083d CK	75	struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work);
528e083d CK	76	struct amdgpu_device *adev = amn->adev;
d38ceaf9 AD	77	struct amdgpu_mn_node node, next_node;
	78	struct amdgpu_bo bo, next_bo;
	79
	80	mutex_lock(&adev->mn_lock);
528e083d CK	81	down_write(&amn->lock);
528e083d CK	82	hash_del(&amn->node);
f808c13f	83	rbtree_postorder_for_each_entry_safe(node, next_node,
528e083d	84	&amn->objects.rb_root, it.rb) {
d38ceaf9 AD	85	list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) {
	86	bo->mn = NULL;
	87	list_del_init(&bo->mn_list);
	88	}
	89	kfree(node);
	90	}
528e083d	91	up_write(&amn->lock);
b8ea3783	92	mutex_unlock(&adev->mn_lock);
2c5a51f5 PY	93
2c5a51f5 PY	94	hmm_mirror_unregister(&amn->mirror);
528e083d	95	kfree(amn);
d38ceaf9 AD	96	}
	97
	98	/**
2c5a51f5	99	* amdgpu_hmm_mirror_release - callback to notify about mm destruction
d38ceaf9	100	*
2c5a51f5	101	* @mirror: the HMM mirror (mm) this callback is about
d38ceaf9	102	*
2c5a51f5	103	* Shedule a work item to lazy destroy HMM mirror.
d38ceaf9	104	*/
2c5a51f5	105	static void amdgpu_hmm_mirror_release(struct hmm_mirror *mirror)
d38ceaf9	106	{
2c5a51f5	107	struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
ad7f0b63	108
528e083d CK	109	INIT_WORK(&amn->work, amdgpu_mn_destroy);
528e083d CK	110	schedule_work(&amn->work);
d38ceaf9 AD	111	}
d38ceaf9 AD	112
3fe89771	113	/**
ad7f0b63 CK	114	* amdgpu_mn_lock - take the write side lock for this notifier
	115	*
	116	* @mn: our notifier
3fe89771 CK	117	*/
	118	void amdgpu_mn_lock(struct amdgpu_mn *mn)
	119	{
	120	if (mn)
	121	down_write(&mn->lock);
	122	}
	123
	124	/**
ad7f0b63 CK	125	* amdgpu_mn_unlock - drop the write side lock for this notifier
	126	*
	127	* @mn: our notifier
3fe89771 CK	128	*/
	129	void amdgpu_mn_unlock(struct amdgpu_mn *mn)
	130	{
	131	if (mn)
	132	up_write(&mn->lock);
	133	}
	134
1ed3d256	135	/**
ad7f0b63	136	* amdgpu_mn_read_lock - take the read side lock for this notifier
1ed3d256	137	*
528e083d	138	* @amn: our notifier
1ed3d256	139	*/
93065ac7	140	static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
1ed3d256	141	{
93065ac7	142	if (blockable)
2c5a51f5 PY	143	down_read(&amn->lock);
2c5a51f5 PY	144	else if (!down_read_trylock(&amn->lock))
93065ac7 MH	145	return -EAGAIN;
93065ac7 MH	146
93065ac7	147	return 0;
1ed3d256 CK	148	}
	149
	150	/**
ad7f0b63	151	* amdgpu_mn_read_unlock - drop the read side lock for this notifier
1ed3d256	152	*
528e083d	153	* @amn: our notifier
1ed3d256	154	*/
528e083d	155	static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn)
1ed3d256	156	{
2c5a51f5	157	up_read(&amn->lock);
1ed3d256 CK	158	}
1ed3d256 CK	159
ae20f12d CK	160	/**
	161	* amdgpu_mn_invalidate_node - unmap all BOs of a node
	162	*
	163	* @node: the node with the BOs to unmap
ad7f0b63 CK	164	* @start: start of address range affected
ad7f0b63 CK	165	* @end: end of address range affected
ae20f12d	166	*
ad7f0b63 CK	167	* Block for operations on BOs to finish and mark pages as accessed and
ad7f0b63 CK	168	* potentially dirty.
ae20f12d CK	169	*/
	170	static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node,
	171	unsigned long start,
	172	unsigned long end)
	173	{
	174	struct amdgpu_bo *bo;
	175	long r;
	176
	177	list_for_each_entry(bo, &node->bos, mn_list) {
	178
	179	if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
	180	continue;
	181
ae20f12d CK	182	r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
	183	true, false, MAX_SCHEDULE_TIMEOUT);
	184	if (r <= 0)
	185	DRM_ERROR("(%ld) failed to wait for user bo\n", r);
ae20f12d CK	186	}
	187	}
	188
d38ceaf9	189	/**
2c5a51f5	190	* amdgpu_mn_sync_pagetables_gfx - callback to notify about mm change
d38ceaf9	191	*
2c5a51f5 PY	192	* @mirror: the hmm_mirror (mm) is about to update
2c5a51f5 PY	193	* @update: the update start, end address
d38ceaf9	194	*
ad7f0b63 CK	195	* Block for operations on BOs to finish and mark pages as accessed and
ad7f0b63 CK	196	* potentially dirty.
d38ceaf9	197	*/
2c5a51f5 PY	198	static int amdgpu_mn_sync_pagetables_gfx(struct hmm_mirror *mirror,
2c5a51f5 PY	199	const struct hmm_update *update)
d38ceaf9	200	{
2c5a51f5 PY	201	struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
	202	unsigned long start = update->start;
	203	unsigned long end = update->end;
	204	bool blockable = update->blockable;
d38ceaf9 AD	205	struct interval_tree_node *it;
	206
	207	/* notification is exclusive, but interval is inclusive */
2c5a51f5	208	end -= 1;
d38ceaf9	209
93065ac7 MH	210	/* TODO we should be able to split locking for interval tree and
	211	* amdgpu_mn_invalidate_node
	212	*/
2c5a51f5	213	if (amdgpu_mn_read_lock(amn, blockable))
93065ac7	214	return -EAGAIN;
0d2b42b0	215
2c5a51f5	216	it = interval_tree_iter_first(&amn->objects, start, end);
d38ceaf9 AD	217	while (it) {
d38ceaf9 AD	218	struct amdgpu_mn_node *node;
d38ceaf9	219
2c5a51f5	220	if (!blockable) {
93065ac7 MH	221	amdgpu_mn_read_unlock(amn);
	222	return -EAGAIN;
	223	}
	224
d38ceaf9	225	node = container_of(it, struct amdgpu_mn_node, it);
2c5a51f5	226	it = interval_tree_iter_next(it, start, end);
d38ceaf9	227
2c5a51f5	228	amdgpu_mn_invalidate_node(node, start, end);
d38ceaf9	229	}
93065ac7	230
2c5a51f5 PY	231	amdgpu_mn_read_unlock(amn);
2c5a51f5 PY	232
93065ac7	233	return 0;
1ed3d256	234	}
0d2b42b0	235
e52482de	236	/**
2c5a51f5	237	* amdgpu_mn_sync_pagetables_hsa - callback to notify about mm change
e52482de	238	*
2c5a51f5 PY	239	* @mirror: the hmm_mirror (mm) is about to update
2c5a51f5 PY	240	* @update: the update start, end address
e52482de FK	241	*
	242	* We temporarily evict all BOs between start and end. This
	243	* necessitates evicting all user-mode queues of the process. The BOs
	244	* are restorted in amdgpu_mn_invalidate_range_end_hsa.
	245	*/
2c5a51f5 PY	246	static int amdgpu_mn_sync_pagetables_hsa(struct hmm_mirror *mirror,
2c5a51f5 PY	247	const struct hmm_update *update)
e52482de	248	{
2c5a51f5 PY	249	struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
	250	unsigned long start = update->start;
	251	unsigned long end = update->end;
	252	bool blockable = update->blockable;
e52482de FK	253	struct interval_tree_node *it;
	254
	255	/* notification is exclusive, but interval is inclusive */
2c5a51f5	256	end -= 1;
e52482de	257
2c5a51f5	258	if (amdgpu_mn_read_lock(amn, blockable))
93065ac7	259	return -EAGAIN;
e52482de	260
2c5a51f5	261	it = interval_tree_iter_first(&amn->objects, start, end);
e52482de FK	262	while (it) {
	263	struct amdgpu_mn_node *node;
	264	struct amdgpu_bo *bo;
	265
2c5a51f5	266	if (!blockable) {
93065ac7 MH	267	amdgpu_mn_read_unlock(amn);
	268	return -EAGAIN;
	269	}
	270
e52482de	271	node = container_of(it, struct amdgpu_mn_node, it);
2c5a51f5	272	it = interval_tree_iter_next(it, start, end);
e52482de FK	273
	274	list_for_each_entry(bo, &node->bos, mn_list) {
	275	struct kgd_mem *mem = bo->kfd_bo;
	276
	277	if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm,
2c5a51f5 PY	278	start, end))
2c5a51f5 PY	279	amdgpu_amdkfd_evict_userptr(mem, amn->mm);
e52482de FK	280	}
e52482de FK	281	}
93065ac7	282
2c5a51f5 PY	283	amdgpu_mn_read_unlock(amn);
2c5a51f5 PY	284
93065ac7	285	return 0;
e52482de FK	286	}
e52482de FK	287
2c5a51f5 PY	288	/* Low bits of any reasonable mm pointer will be unused due to struct
	289	* alignment. Use these bits to make a unique key from the mm pointer
	290	* and notifier type.
1ed3d256	291	*/
2c5a51f5	292	#define AMDGPU_MN_KEY(mm, type) ((unsigned long)(mm) + (type))
d38ceaf9	293
2c5a51f5	294	static struct hmm_mirror_ops amdgpu_hmm_mirror_ops[] = {
e52482de	295	[AMDGPU_MN_TYPE_GFX] = {
2c5a51f5 PY	296	.sync_cpu_device_pagetables = amdgpu_mn_sync_pagetables_gfx,
2c5a51f5 PY	297	.release = amdgpu_hmm_mirror_release
e52482de FK	298	},
e52482de FK	299	[AMDGPU_MN_TYPE_HSA] = {
2c5a51f5 PY	300	.sync_cpu_device_pagetables = amdgpu_mn_sync_pagetables_hsa,
2c5a51f5 PY	301	.release = amdgpu_hmm_mirror_release
e52482de	302	},
d38ceaf9 AD	303	};
	304
	305	/**
2c5a51f5	306	* amdgpu_mn_get - create HMM mirror context
d38ceaf9 AD	307	*
d38ceaf9 AD	308	* @adev: amdgpu device pointer
e52482de	309	* @type: type of MMU notifier context
d38ceaf9	310	*
2c5a51f5	311	* Creates a HMM mirror context for current->mm.
d38ceaf9	312	*/
e52482de FK	313	struct amdgpu_mn amdgpu_mn_get(struct amdgpu_device adev,
e52482de FK	314	enum amdgpu_mn_type type)
d38ceaf9 AD	315	{
d38ceaf9 AD	316	struct mm_struct *mm = current->mm;
528e083d	317	struct amdgpu_mn *amn;
e52482de	318	unsigned long key = AMDGPU_MN_KEY(mm, type);
d38ceaf9 AD	319	int r;
d38ceaf9 AD	320
d38ceaf9	321	mutex_lock(&adev->mn_lock);
b5637051 MH	322	if (down_write_killable(&mm->mmap_sem)) {
	323	mutex_unlock(&adev->mn_lock);
	324	return ERR_PTR(-EINTR);
	325	}
d38ceaf9	326
528e083d CK	327	hash_for_each_possible(adev->mn_hash, amn, node, key)
528e083d CK	328	if (AMDGPU_MN_KEY(amn->mm, amn->type) == key)
d38ceaf9 AD	329	goto release_locks;
d38ceaf9 AD	330
528e083d CK	331	amn = kzalloc(sizeof(*amn), GFP_KERNEL);
	332	if (!amn) {
	333	amn = ERR_PTR(-ENOMEM);
d38ceaf9 AD	334	goto release_locks;
	335	}
	336
528e083d CK	337	amn->adev = adev;
	338	amn->mm = mm;
	339	init_rwsem(&amn->lock);
	340	amn->type = type;
528e083d	341	amn->objects = RB_ROOT_CACHED;
d38ceaf9	342
2c5a51f5 PY	343	amn->mirror.ops = &amdgpu_hmm_mirror_ops[type];
2c5a51f5 PY	344	r = hmm_mirror_register(&amn->mirror, mm);
d38ceaf9	345	if (r)
528e083d	346	goto free_amn;
d38ceaf9	347
528e083d	348	hash_add(adev->mn_hash, &amn->node, AMDGPU_MN_KEY(mm, type));
d38ceaf9 AD	349
d38ceaf9 AD	350	release_locks:
d38ceaf9	351	up_write(&mm->mmap_sem);
b8ea3783	352	mutex_unlock(&adev->mn_lock);
d38ceaf9	353
528e083d	354	return amn;
d38ceaf9	355
528e083d	356	free_amn:
d38ceaf9	357	up_write(&mm->mmap_sem);
b8ea3783	358	mutex_unlock(&adev->mn_lock);
528e083d	359	kfree(amn);
d38ceaf9 AD	360
	361	return ERR_PTR(r);
	362	}
	363
	364	/**
	365	* amdgpu_mn_register - register a BO for notifier updates
	366	*
	367	* @bo: amdgpu buffer object
	368	* @addr: userptr addr we should monitor
	369	*
2c5a51f5	370	* Registers an HMM mirror for the given BO at the specified address.
d38ceaf9 AD	371	* Returns 0 on success, -ERRNO if anything goes wrong.
	372	*/
	373	int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
	374	{
	375	unsigned long end = addr + amdgpu_bo_size(bo) - 1;
a7d64de6	376	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
e52482de FK	377	enum amdgpu_mn_type type =
e52482de FK	378	bo->kfd_bo ? AMDGPU_MN_TYPE_HSA : AMDGPU_MN_TYPE_GFX;
528e083d	379	struct amdgpu_mn *amn;
6e08e099	380	struct amdgpu_mn_node node = NULL, new_node;
d38ceaf9 AD	381	struct list_head bos;
	382	struct interval_tree_node *it;
	383
528e083d CK	384	amn = amdgpu_mn_get(adev, type);
	385	if (IS_ERR(amn))
	386	return PTR_ERR(amn);
d38ceaf9	387
6e08e099 FK	388	new_node = kmalloc(sizeof(*new_node), GFP_KERNEL);
	389	if (!new_node)
	390	return -ENOMEM;
	391
d38ceaf9 AD	392	INIT_LIST_HEAD(&bos);
d38ceaf9 AD	393
528e083d	394	down_write(&amn->lock);
d38ceaf9	395
528e083d	396	while ((it = interval_tree_iter_first(&amn->objects, addr, end))) {
d38ceaf9 AD	397	kfree(node);
d38ceaf9 AD	398	node = container_of(it, struct amdgpu_mn_node, it);
528e083d	399	interval_tree_remove(&node->it, &amn->objects);
d38ceaf9 AD	400	addr = min(it->start, addr);
	401	end = max(it->last, end);
	402	list_splice(&node->bos, &bos);
	403	}
	404
6e08e099 FK	405	if (!node)
	406	node = new_node;
	407	else
	408	kfree(new_node);
d38ceaf9	409
528e083d	410	bo->mn = amn;
d38ceaf9 AD	411
	412	node->it.start = addr;
	413	node->it.last = end;
	414	INIT_LIST_HEAD(&node->bos);
	415	list_splice(&bos, &node->bos);
	416	list_add(&bo->mn_list, &node->bos);
	417
528e083d	418	interval_tree_insert(&node->it, &amn->objects);
d38ceaf9	419
528e083d	420	up_write(&amn->lock);
d38ceaf9 AD	421
	422	return 0;
	423	}
	424
	425	/**
2c5a51f5	426	* amdgpu_mn_unregister - unregister a BO for HMM mirror updates
d38ceaf9 AD	427	*
	428	* @bo: amdgpu buffer object
	429	*
2c5a51f5	430	* Remove any registration of HMM mirror updates from the buffer object.
d38ceaf9 AD	431	*/
	432	void amdgpu_mn_unregister(struct amdgpu_bo *bo)
	433	{
a7d64de6	434	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
528e083d	435	struct amdgpu_mn *amn;
d38ceaf9 AD	436	struct list_head *head;
d38ceaf9 AD	437
b8ea3783 FK	438	mutex_lock(&adev->mn_lock);
b8ea3783 FK	439
528e083d CK	440	amn = bo->mn;
528e083d CK	441	if (amn == NULL) {
b8ea3783	442	mutex_unlock(&adev->mn_lock);
d38ceaf9	443	return;
b8ea3783	444	}
d38ceaf9	445
528e083d	446	down_write(&amn->lock);
c41d271d	447
d38ceaf9 AD	448	/* save the next list entry for later */
	449	head = bo->mn_list.next;
	450
	451	bo->mn = NULL;
68c9793d	452	list_del_init(&bo->mn_list);
d38ceaf9 AD	453
	454	if (list_empty(head)) {
	455	struct amdgpu_mn_node *node;
ad7f0b63	456
d38ceaf9	457	node = container_of(head, struct amdgpu_mn_node, bos);
528e083d	458	interval_tree_remove(&node->it, &amn->objects);
d38ceaf9 AD	459	kfree(node);
	460	}
	461
528e083d	462	up_write(&amn->lock);
b8ea3783	463	mutex_unlock(&adev->mn_lock);
d38ceaf9	464	}
3fe89771	465
899fbde1 PY	466	/* flags used by HMM internal, not related to CPU/GPU PTE flags */
	467	static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = {
	468	(1 << 0), /* HMM_PFN_VALID */
	469	(1 << 1), /* HMM_PFN_WRITE */
	470	0 /* HMM_PFN_DEVICE_PRIVATE */
	471	};
	472
	473	static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = {
	474	0xfffffffffffffffeUL, /* HMM_PFN_ERROR */
	475	0, /* HMM_PFN_NONE */
	476	0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */
	477	};
	478
	479	void amdgpu_hmm_init_range(struct hmm_range *range)
	480	{
	481	if (range) {
	482	range->flags = hmm_range_flags;
	483	range->values = hmm_range_values;
	484	range->pfn_shift = PAGE_SHIFT;
899fbde1 PY	485	INIT_LIST_HEAD(&range->list);
	486	}
	487	}