[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_mode.h

/*
 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
 *                VA Linux Systems Inc., Fremont, California.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Original Authors:
 *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
 *
 * Kernel port Author: Dave Airlie
 */

#ifndef AMDGPU_MODE_H
#define AMDGPU_MODE_H

#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/drm_encoder.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_fixed.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/hrtimer.h>
#include "amdgpu_irq.h"

#include <drm/drm_dp_mst_helper.h>
#include "modules/inc/mod_freesync.h"

struct amdgpu_bo;
struct amdgpu_device;
struct amdgpu_encoder;
struct amdgpu_router;
struct amdgpu_hpd;

#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)

#define to_dm_plane_state(x)	container_of(x, struct dm_plane_state, base)

#define AMDGPU_MAX_HPD_PINS 6
#define AMDGPU_MAX_CRTCS 6
#define AMDGPU_MAX_PLANES 6
#define AMDGPU_MAX_AFMT_BLOCKS 9

enum amdgpu_rmx_type {
	RMX_OFF,
	RMX_FULL,
	RMX_CENTER,
	RMX_ASPECT
};

enum amdgpu_underscan_type {
	UNDERSCAN_OFF,
	UNDERSCAN_ON,
	UNDERSCAN_AUTO,
};

#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10

enum amdgpu_hpd_id {
	AMDGPU_HPD_1 = 0,
	AMDGPU_HPD_2,
	AMDGPU_HPD_3,
	AMDGPU_HPD_4,
	AMDGPU_HPD_5,
	AMDGPU_HPD_6,
	AMDGPU_HPD_NONE = 0xff,
};

enum amdgpu_crtc_irq {
	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
	AMDGPU_CRTC_IRQ_VBLANK2,
	AMDGPU_CRTC_IRQ_VBLANK3,
	AMDGPU_CRTC_IRQ_VBLANK4,
	AMDGPU_CRTC_IRQ_VBLANK5,
	AMDGPU_CRTC_IRQ_VBLANK6,
	AMDGPU_CRTC_IRQ_VLINE1,
	AMDGPU_CRTC_IRQ_VLINE2,
	AMDGPU_CRTC_IRQ_VLINE3,
	AMDGPU_CRTC_IRQ_VLINE4,
	AMDGPU_CRTC_IRQ_VLINE5,
	AMDGPU_CRTC_IRQ_VLINE6,
	AMDGPU_CRTC_IRQ_NONE = 0xff
};

enum amdgpu_pageflip_irq {
	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
	AMDGPU_PAGEFLIP_IRQ_D2,
	AMDGPU_PAGEFLIP_IRQ_D3,
	AMDGPU_PAGEFLIP_IRQ_D4,
	AMDGPU_PAGEFLIP_IRQ_D5,
	AMDGPU_PAGEFLIP_IRQ_D6,
	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
};

enum amdgpu_flip_status {
	AMDGPU_FLIP_NONE,
	AMDGPU_FLIP_PENDING,
	AMDGPU_FLIP_SUBMITTED
};

#define AMDGPU_MAX_I2C_BUS 16

/* amdgpu gpio-based i2c
 * 1. "mask" reg and bits
 *    grabs the gpio pins for software use
 *    0=not held  1=held
 * 2. "a" reg and bits
 *    output pin value
 *    0=low 1=high
 * 3. "en" reg and bits
 *    sets the pin direction
 *    0=input 1=output
 * 4. "y" reg and bits
 *    input pin value
 *    0=low 1=high
 */
struct amdgpu_i2c_bus_rec {
	bool valid;
	/* id used by atom */
	uint8_t i2c_id;
	/* id used by atom */
	enum amdgpu_hpd_id hpd;
	/* can be used with hw i2c engine */
	bool hw_capable;
	/* uses multi-media i2c engine */
	bool mm_i2c;
	/* regs and bits */
	uint32_t mask_clk_reg;
	uint32_t mask_data_reg;
	uint32_t a_clk_reg;
	uint32_t a_data_reg;
	uint32_t en_clk_reg;
	uint32_t en_data_reg;
	uint32_t y_clk_reg;
	uint32_t y_data_reg;
	uint32_t mask_clk_mask;
	uint32_t mask_data_mask;
	uint32_t a_clk_mask;
	uint32_t a_data_mask;
	uint32_t en_clk_mask;
	uint32_t en_data_mask;
	uint32_t y_clk_mask;
	uint32_t y_data_mask;
};

#define AMDGPU_MAX_BIOS_CONNECTOR 16

/* pll flags */
#define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
#define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
#define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
#define AMDGPU_PLL_LEGACY               (1 << 3)
#define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
#define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
#define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
#define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
#define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
#define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
#define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
#define AMDGPU_PLL_IS_LCD               (1 << 13)
#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)

struct amdgpu_pll {
	/* reference frequency */
	uint32_t reference_freq;

	/* fixed dividers */
	uint32_t reference_div;
	uint32_t post_div;

	/* pll in/out limits */
	uint32_t pll_in_min;
	uint32_t pll_in_max;
	uint32_t pll_out_min;
	uint32_t pll_out_max;
	uint32_t lcd_pll_out_min;
	uint32_t lcd_pll_out_max;
	uint32_t best_vco;

	/* divider limits */
	uint32_t min_ref_div;
	uint32_t max_ref_div;
	uint32_t min_post_div;
	uint32_t max_post_div;
	uint32_t min_feedback_div;
	uint32_t max_feedback_div;
	uint32_t min_frac_feedback_div;
	uint32_t max_frac_feedback_div;

	/* flags for the current clock */
	uint32_t flags;

	/* pll id */
	uint32_t id;
};

struct amdgpu_i2c_chan {
	struct i2c_adapter adapter;
	struct drm_device *dev;
	struct i2c_algo_bit_data bit;
	struct amdgpu_i2c_bus_rec rec;
	struct drm_dp_aux aux;
	bool has_aux;
	struct mutex mutex;
};

struct amdgpu_fbdev;

struct amdgpu_afmt {
	bool enabled;
	int offset;
	bool last_buffer_filled_status;
	int id;
	struct amdgpu_audio_pin *pin;
};

/*
 * Audio
 */
struct amdgpu_audio_pin {
	int			channels;
	int			rate;
	int			bits_per_sample;
	u8			status_bits;
	u8			category_code;
	u32			offset;
	bool			connected;
	u32			id;
};

struct amdgpu_audio {
	bool enabled;
	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
	int num_pins;
};

struct amdgpu_display_funcs {
	/* display watermarks */
	void (*bandwidth_update)(struct amdgpu_device *adev);
	/* get frame count */
	u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
	/* set backlight level */
	void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
				    u8 level);
	/* get backlight level */
	u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
	/* hotplug detect */
	bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
	void (*hpd_set_polarity)(struct amdgpu_device *adev,
				 enum amdgpu_hpd_id hpd);
	u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
	/* pageflipping */
	void (*page_flip)(struct amdgpu_device *adev,
			  int crtc_id, u64 crtc_base, bool async);
	int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
					u32 *vbl, u32 *position);
	/* display topology setup */
	void (*add_encoder)(struct amdgpu_device *adev,
			    uint32_t encoder_enum,
			    uint32_t supported_device,
			    u16 caps);
	void (*add_connector)(struct amdgpu_device *adev,
			      uint32_t connector_id,
			      uint32_t supported_device,
			      int connector_type,
			      struct amdgpu_i2c_bus_rec *i2c_bus,
			      uint16_t connector_object_id,
			      struct amdgpu_hpd *hpd,
			      struct amdgpu_router *router);


};

struct amdgpu_framebuffer {
	struct drm_framebuffer base;

	/* caching for later use */
	uint64_t address;
};

struct amdgpu_fbdev {
	struct drm_fb_helper helper;
	struct amdgpu_framebuffer rfb;
	struct list_head fbdev_list;
	struct amdgpu_device *adev;
};

struct amdgpu_mode_info {
	struct atom_context *atom_context;
	struct card_info *atom_card_info;
	bool mode_config_initialized;
	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
	struct drm_plane *planes[AMDGPU_MAX_PLANES];
	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
	/* DVI-I properties */
	struct drm_property *coherent_mode_property;
	/* DAC enable load detect */
	struct drm_property *load_detect_property;
	/* underscan */
	struct drm_property *underscan_property;
	struct drm_property *underscan_hborder_property;
	struct drm_property *underscan_vborder_property;
	/* audio */
	struct drm_property *audio_property;
	/* FMT dithering */
	struct drm_property *dither_property;
	/* Adaptive Backlight Modulation (power feature) */
	struct drm_property *abm_level_property;
	/* hardcoded DFP edid from BIOS */
	struct edid *bios_hardcoded_edid;
	int bios_hardcoded_edid_size;

	/* pointer to fbdev info structure */
	struct amdgpu_fbdev *rfbdev;
	/* firmware flags */
	u16 firmware_flags;
	/* pointer to backlight encoder */
	struct amdgpu_encoder *bl_encoder;
	u8 bl_level; /* saved backlight level */
	struct amdgpu_audio	audio; /* audio stuff */
	int			num_crtc; /* number of crtcs */
	int			num_hpd; /* number of hpd pins */
	int			num_dig; /* number of dig blocks */
	int			disp_priority;
	const struct amdgpu_display_funcs *funcs;
	const enum drm_plane_type *plane_type;
};

#define AMDGPU_MAX_BL_LEVEL 0xFF

#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

struct amdgpu_backlight_privdata {
	struct amdgpu_encoder *encoder;
	uint8_t negative;
};

#endif

struct amdgpu_atom_ss {
	uint16_t percentage;
	uint16_t percentage_divider;
	uint8_t type;
	uint16_t step;
	uint8_t delay;
	uint8_t range;
	uint8_t refdiv;
	/* asic_ss */
	uint16_t rate;
	uint16_t amount;
};

struct amdgpu_crtc {
	struct drm_crtc base;
	int crtc_id;
	bool enabled;
	bool can_tile;
	uint32_t crtc_offset;
	struct drm_gem_object *cursor_bo;
	uint64_t cursor_addr;
	int cursor_x;
	int cursor_y;
	int cursor_hot_x;
	int cursor_hot_y;
	int cursor_width;
	int cursor_height;
	int max_cursor_width;
	int max_cursor_height;
	enum amdgpu_rmx_type rmx_type;
	u8 h_border;
	u8 v_border;
	fixed20_12 vsc;
	fixed20_12 hsc;
	struct drm_display_mode native_mode;
	u32 pll_id;
	/* page flipping */
	struct amdgpu_flip_work *pflip_works;
	enum amdgpu_flip_status pflip_status;
	int deferred_flip_completion;
	u32 last_flip_vblank;
	/* pll sharing */
	struct amdgpu_atom_ss ss;
	bool ss_enabled;
	u32 adjusted_clock;
	int bpc;
	u32 pll_reference_div;
	u32 pll_post_div;
	u32 pll_flags;
	struct drm_encoder *encoder;
	struct drm_connector *connector;
	/* for dpm */
	u32 line_time;
	u32 wm_low;
	u32 wm_high;
	u32 lb_vblank_lead_lines;
	struct drm_display_mode hw_mode;
	/* for virtual dce */
	struct hrtimer vblank_timer;
	enum amdgpu_interrupt_state vsync_timer_enabled;

	int otg_inst;
	struct drm_pending_vblank_event *event;
};

struct amdgpu_encoder_atom_dig {
	bool linkb;
	/* atom dig */
	bool coherent_mode;
	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
	/* atom lvds/edp */
	uint32_t lcd_misc;
	uint16_t panel_pwr_delay;
	uint32_t lcd_ss_id;
	/* panel mode */
	struct drm_display_mode native_mode;
	struct backlight_device *bl_dev;
	int dpms_mode;
	uint8_t backlight_level;
	int panel_mode;
	struct amdgpu_afmt *afmt;
};

struct amdgpu_encoder {
	struct drm_encoder base;
	uint32_t encoder_enum;
	uint32_t encoder_id;
	uint32_t devices;
	uint32_t active_device;
	uint32_t flags;
	uint32_t pixel_clock;
	enum amdgpu_rmx_type rmx_type;
	enum amdgpu_underscan_type underscan_type;
	uint32_t underscan_hborder;
	uint32_t underscan_vborder;
	struct drm_display_mode native_mode;
	void *enc_priv;
	int audio_polling_active;
	bool is_ext_encoder;
	u16 caps;
};

struct amdgpu_connector_atom_dig {
	/* displayport */
	u8 dpcd[DP_RECEIVER_CAP_SIZE];
	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
	u8 dp_sink_type;
	int dp_clock;
	int dp_lane_count;
	bool edp_on;
};

struct amdgpu_gpio_rec {
	bool valid;
	u8 id;
	u32 reg;
	u32 mask;
	u32 shift;
};

struct amdgpu_hpd {
	enum amdgpu_hpd_id hpd;
	u8 plugged_state;
	struct amdgpu_gpio_rec gpio;
};

struct amdgpu_router {
	u32 router_id;
	struct amdgpu_i2c_bus_rec i2c_info;
	u8 i2c_addr;
	/* i2c mux */
	bool ddc_valid;
	u8 ddc_mux_type;
	u8 ddc_mux_control_pin;
	u8 ddc_mux_state;
	/* clock/data mux */
	bool cd_valid;
	u8 cd_mux_type;
	u8 cd_mux_control_pin;
	u8 cd_mux_state;
};

enum amdgpu_connector_audio {
	AMDGPU_AUDIO_DISABLE = 0,
	AMDGPU_AUDIO_ENABLE = 1,
	AMDGPU_AUDIO_AUTO = 2
};

enum amdgpu_connector_dither {
	AMDGPU_FMT_DITHER_DISABLE = 0,
	AMDGPU_FMT_DITHER_ENABLE = 1,
};

struct amdgpu_dm_dp_aux {
	struct drm_dp_aux aux;
	struct ddc_service *ddc_service;
};

struct amdgpu_i2c_adapter {
	struct i2c_adapter base;

	struct ddc_service *ddc_service;
};

#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)

struct amdgpu_connector {
	struct drm_connector base;
	uint32_t connector_id;
	uint32_t devices;
	struct amdgpu_i2c_chan *ddc_bus;
	/* some systems have an hdmi and vga port with a shared ddc line */
	bool shared_ddc;
	bool use_digital;
	/* we need to mind the EDID between detect
	   and get modes due to analog/digital/tvencoder */
	struct edid *edid;
	void *con_priv;
	bool dac_load_detect;
	bool detected_by_load; /* if the connection status was determined by load */
	uint16_t connector_object_id;
	struct amdgpu_hpd hpd;
	struct amdgpu_router router;
	struct amdgpu_i2c_chan *router_bus;
	enum amdgpu_connector_audio audio;
	enum amdgpu_connector_dither dither;
	unsigned pixelclock_for_modeset;
};

/* TODO: start to use this struct and remove same field from base one */
struct amdgpu_mst_connector {
	struct amdgpu_connector base;

	struct drm_dp_mst_topology_mgr mst_mgr;
	struct amdgpu_dm_dp_aux dm_dp_aux;
	struct drm_dp_mst_port *port;
	struct amdgpu_connector *mst_port;
	bool is_mst_connector;
	struct amdgpu_encoder *mst_encoder;
};

#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
				((em) == ATOM_ENCODER_MODE_DP_MST))

/* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
#define DRM_SCANOUTPOS_VALID        (1 << 0)
#define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
#define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
#define USE_REAL_VBLANKSTART		(1 << 30)
#define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)

void amdgpu_link_encoder_connector(struct drm_device *dev);

struct drm_connector *
amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
struct drm_connector *
amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
				    u32 pixel_clock);

u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);

bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
			      bool use_aux);

void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);

int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
			unsigned int pipe, unsigned int flags, int *vpos,
			int *hpos, ktime_t *stime, ktime_t *etime,
			const struct drm_display_mode *mode);

int amdgpu_display_framebuffer_init(struct drm_device *dev,
				    struct amdgpu_framebuffer *rfb,
				    const struct drm_mode_fb_cmd2 *mode_cmd,
				    struct drm_gem_object *obj);

int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);

void amdgpu_enc_destroy(struct drm_encoder *encoder);
void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
				const struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode);
void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
			     struct drm_display_mode *adjusted_mode);
int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);

bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
			bool in_vblank_irq, int *vpos,
			int *hpos, ktime_t *stime, ktime_t *etime,
			const struct drm_display_mode *mode);

/* fbdev layer */
int amdgpu_fbdev_init(struct amdgpu_device *adev);
void amdgpu_fbdev_fini(struct amdgpu_device *adev);
void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);

int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);

/* amdgpu_display.c */
void amdgpu_display_print_display_setup(struct drm_device *dev);
int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
				   struct drm_modeset_acquire_ctx *ctx);
int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
				struct drm_framebuffer *fb,
				struct drm_pending_vblank_event *event,
				uint32_t page_flip_flags, uint32_t target,
				struct drm_modeset_acquire_ctx *ctx);
extern const struct drm_mode_config_funcs amdgpu_mode_funcs;

#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
	3	* VA Linux Systems Inc., Fremont, California.
	4	* Copyright 2008 Red Hat Inc.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Original Authors:
	25	* Kevin E. Martin, Rickard E. Faith, Alan Hourihane
	26	*
	27	* Kernel port Author: Dave Airlie
	28	*/
	29
	30	#ifndef AMDGPU_MODE_H
	31	#define AMDGPU_MODE_H
	32
	33	#include <drm/drm_crtc.h>
	34	#include <drm/drm_edid.h>
9338203c	35	#include <drm/drm_encoder.h>
d38ceaf9 AD	36	#include <drm/drm_dp_helper.h>
	37	#include <drm/drm_fixed.h>
	38	#include <drm/drm_crtc_helper.h>
b516a9ef	39	#include <drm/drm_fb_helper.h>
d38ceaf9	40	#include <drm/drm_plane_helper.h>
fcd70cd3	41	#include <drm/drm_probe_helper.h>
d38ceaf9 AD	42	#include <linux/i2c.h>
d38ceaf9 AD	43	#include <linux/i2c-algo-bit.h>
46ac3622 ED	44	#include <linux/hrtimer.h>
46ac3622 ED	45	#include "amdgpu_irq.h"
d38ceaf9	46
4562236b HW	47	#include <drm/drm_dp_mst_helper.h>
	48	#include "modules/inc/mod_freesync.h"
	49
d38ceaf9 AD	50	struct amdgpu_bo;
	51	struct amdgpu_device;
	52	struct amdgpu_encoder;
	53	struct amdgpu_router;
	54	struct amdgpu_hpd;
	55
	56	#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
	57	#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
	58	#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
	59	#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
	60
3d12beb3	61	#define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base)
0604b36c	62
d38ceaf9 AD	63	#define AMDGPU_MAX_HPD_PINS 6
d38ceaf9 AD	64	#define AMDGPU_MAX_CRTCS 6
d4e13b0d	65	#define AMDGPU_MAX_PLANES 6
22384459	66	#define AMDGPU_MAX_AFMT_BLOCKS 9
d38ceaf9 AD	67
	68	enum amdgpu_rmx_type {
	69	RMX_OFF,
	70	RMX_FULL,
	71	RMX_CENTER,
	72	RMX_ASPECT
	73	};
	74
	75	enum amdgpu_underscan_type {
	76	UNDERSCAN_OFF,
	77	UNDERSCAN_ON,
	78	UNDERSCAN_AUTO,
	79	};
	80
	81	#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
	82	#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
	83
	84	enum amdgpu_hpd_id {
	85	AMDGPU_HPD_1 = 0,
	86	AMDGPU_HPD_2,
	87	AMDGPU_HPD_3,
	88	AMDGPU_HPD_4,
	89	AMDGPU_HPD_5,
	90	AMDGPU_HPD_6,
d38ceaf9 AD	91	AMDGPU_HPD_NONE = 0xff,
	92	};
	93
	94	enum amdgpu_crtc_irq {
	95	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
	96	AMDGPU_CRTC_IRQ_VBLANK2,
	97	AMDGPU_CRTC_IRQ_VBLANK3,
	98	AMDGPU_CRTC_IRQ_VBLANK4,
	99	AMDGPU_CRTC_IRQ_VBLANK5,
	100	AMDGPU_CRTC_IRQ_VBLANK6,
	101	AMDGPU_CRTC_IRQ_VLINE1,
	102	AMDGPU_CRTC_IRQ_VLINE2,
	103	AMDGPU_CRTC_IRQ_VLINE3,
	104	AMDGPU_CRTC_IRQ_VLINE4,
	105	AMDGPU_CRTC_IRQ_VLINE5,
	106	AMDGPU_CRTC_IRQ_VLINE6,
d38ceaf9 AD	107	AMDGPU_CRTC_IRQ_NONE = 0xff
	108	};
	109
	110	enum amdgpu_pageflip_irq {
	111	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
	112	AMDGPU_PAGEFLIP_IRQ_D2,
	113	AMDGPU_PAGEFLIP_IRQ_D3,
	114	AMDGPU_PAGEFLIP_IRQ_D4,
	115	AMDGPU_PAGEFLIP_IRQ_D5,
	116	AMDGPU_PAGEFLIP_IRQ_D6,
d38ceaf9 AD	117	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
	118	};
	119
	120	enum amdgpu_flip_status {
	121	AMDGPU_FLIP_NONE,
	122	AMDGPU_FLIP_PENDING,
	123	AMDGPU_FLIP_SUBMITTED
	124	};
	125
	126	#define AMDGPU_MAX_I2C_BUS 16
	127
	128	/* amdgpu gpio-based i2c
	129	* 1. "mask" reg and bits
	130	* grabs the gpio pins for software use
	131	* 0=not held 1=held
	132	* 2. "a" reg and bits
	133	* output pin value
	134	* 0=low 1=high
	135	* 3. "en" reg and bits
	136	* sets the pin direction
	137	* 0=input 1=output
	138	* 4. "y" reg and bits
	139	* input pin value
	140	* 0=low 1=high
	141	*/
	142	struct amdgpu_i2c_bus_rec {
	143	bool valid;
	144	/* id used by atom */
	145	uint8_t i2c_id;
	146	/* id used by atom */
	147	enum amdgpu_hpd_id hpd;
	148	/* can be used with hw i2c engine */
	149	bool hw_capable;
	150	/* uses multi-media i2c engine */
	151	bool mm_i2c;
	152	/* regs and bits */
	153	uint32_t mask_clk_reg;
	154	uint32_t mask_data_reg;
	155	uint32_t a_clk_reg;
	156	uint32_t a_data_reg;
	157	uint32_t en_clk_reg;
	158	uint32_t en_data_reg;
	159	uint32_t y_clk_reg;
	160	uint32_t y_data_reg;
	161	uint32_t mask_clk_mask;
	162	uint32_t mask_data_mask;
	163	uint32_t a_clk_mask;
	164	uint32_t a_data_mask;
	165	uint32_t en_clk_mask;
	166	uint32_t en_data_mask;
	167	uint32_t y_clk_mask;
	168	uint32_t y_data_mask;
	169	};
	170
	171	#define AMDGPU_MAX_BIOS_CONNECTOR 16
	172
	173	/* pll flags */
	174	#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
	175	#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
	176	#define AMDGPU_PLL_USE_REF_DIV (1 << 2)
	177	#define AMDGPU_PLL_LEGACY (1 << 3)
	178	#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
	179	#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
	180	#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
181	#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
182	#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
183	#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
184	#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
185	#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
186	#define AMDGPU_PLL_USE_POST_DIV (1 << 12)
187	#define AMDGPU_PLL_IS_LCD (1 << 13)
188	#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
189
190	struct amdgpu_pll {
191	/* reference frequency */
192	uint32_t reference_freq;
193
194	/* fixed dividers */
195	uint32_t reference_div;
196	uint32_t post_div;
197
198	/* pll in/out limits */
199	uint32_t pll_in_min;
200	uint32_t pll_in_max;
201	uint32_t pll_out_min;
202	uint32_t pll_out_max;
203	uint32_t lcd_pll_out_min;
204	uint32_t lcd_pll_out_max;
205	uint32_t best_vco;
206
207	/* divider limits */
208	uint32_t min_ref_div;
209	uint32_t max_ref_div;
210	uint32_t min_post_div;
211	uint32_t max_post_div;
212	uint32_t min_feedback_div;
213	uint32_t max_feedback_div;
214	uint32_t min_frac_feedback_div;
215	uint32_t max_frac_feedback_div;
216
217	/* flags for the current clock */
218	uint32_t flags;
219
220	/* pll id */
221	uint32_t id;
222	};
223
224	struct amdgpu_i2c_chan {
225	struct i2c_adapter adapter;
226	struct drm_device *dev;
227	struct i2c_algo_bit_data bit;
228	struct amdgpu_i2c_bus_rec rec;
229	struct drm_dp_aux aux;
230	bool has_aux;
231	struct mutex mutex;
232	};
233
234	struct amdgpu_fbdev;
235
236	struct amdgpu_afmt {
237	bool enabled;
238	int offset;
239	bool last_buffer_filled_status;
240	int id;
241	struct amdgpu_audio_pin *pin;
242	};
243
244	/*
245	* Audio
246	*/
247	struct amdgpu_audio_pin {
248	int channels;
249	int rate;
250	int bits_per_sample;
251	u8 status_bits;
252	u8 category_code;
253	u32 offset;
254	bool connected;
255	u32 id;
256	};
257
258	struct amdgpu_audio {
259	bool enabled;
260	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
261	int num_pins;
262	};
263
d38ceaf9	264	struct amdgpu_display_funcs {
d38ceaf9 AD	265	/* display watermarks */
	266	void (bandwidth_update)(struct amdgpu_device adev);
	267	/* get frame count */
	268	u32 (vblank_get_counter)(struct amdgpu_device adev, int crtc);
d38ceaf9 AD	269	/* set backlight level */
	270	void (backlight_set_level)(struct amdgpu_encoder amdgpu_encoder,
	271	u8 level);
	272	/* get backlight level */
	273	u8 (backlight_get_level)(struct amdgpu_encoder amdgpu_encoder);
	274	/* hotplug detect */
	275	bool (hpd_sense)(struct amdgpu_device adev, enum amdgpu_hpd_id hpd);
	276	void (hpd_set_polarity)(struct amdgpu_device adev,
	277	enum amdgpu_hpd_id hpd);
	278	u32 (hpd_get_gpio_reg)(struct amdgpu_device adev);
	279	/* pageflipping */
	280	void (page_flip)(struct amdgpu_device adev,
cb9e59d7	281	int crtc_id, u64 crtc_base, bool async);
d38ceaf9 AD	282	int (page_flip_get_scanoutpos)(struct amdgpu_device adev, int crtc,
	283	u32 vbl, u32 position);
	284	/* display topology setup */
	285	void (add_encoder)(struct amdgpu_device adev,
	286	uint32_t encoder_enum,
	287	uint32_t supported_device,
	288	u16 caps);
	289	void (add_connector)(struct amdgpu_device adev,
	290	uint32_t connector_id,
	291	uint32_t supported_device,
	292	int connector_type,
	293	struct amdgpu_i2c_bus_rec *i2c_bus,
	294	uint16_t connector_object_id,
	295	struct amdgpu_hpd *hpd,
	296	struct amdgpu_router *router);
4562236b HW	297
	298
	299	};
	300
	301	struct amdgpu_framebuffer {
	302	struct drm_framebuffer base;
dd55d12c AG	303
	304	/* caching for later use */
	305	uint64_t address;
4562236b HW	306	};
	307
	308	struct amdgpu_fbdev {
	309	struct drm_fb_helper helper;
	310	struct amdgpu_framebuffer rfb;
	311	struct list_head fbdev_list;
	312	struct amdgpu_device *adev;
d38ceaf9 AD	313	};
	314
	315	struct amdgpu_mode_info {
	316	struct atom_context *atom_context;
	317	struct card_info *atom_card_info;
	318	bool mode_config_initialized;
f195038c	319	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
f180b4bc	320	struct drm_plane *planes[AMDGPU_MAX_PLANES];
f195038c	321	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
d38ceaf9 AD	322	/* DVI-I properties */
	323	struct drm_property *coherent_mode_property;
	324	/* DAC enable load detect */
	325	struct drm_property *load_detect_property;
	326	/* underscan */
	327	struct drm_property *underscan_property;
	328	struct drm_property *underscan_hborder_property;
	329	struct drm_property *underscan_vborder_property;
	330	/* audio */
	331	struct drm_property *audio_property;
	332	/* FMT dithering */
	333	struct drm_property *dither_property;
c1ee92f9 DF	334	/* Adaptive Backlight Modulation (power feature) */
c1ee92f9 DF	335	struct drm_property *abm_level_property;
d38ceaf9 AD	336	/* hardcoded DFP edid from BIOS */
	337	struct edid *bios_hardcoded_edid;
	338	int bios_hardcoded_edid_size;
	339
	340	/* pointer to fbdev info structure */
	341	struct amdgpu_fbdev *rfbdev;
	342	/* firmware flags */
	343	u16 firmware_flags;
	344	/* pointer to backlight encoder */
	345	struct amdgpu_encoder *bl_encoder;
a59b3c80	346	u8 bl_level; /* saved backlight level */
d38ceaf9 AD	347	struct amdgpu_audio audio; /* audio stuff */
	348	int num_crtc; /* number of crtcs */
	349	int num_hpd; /* number of hpd pins */
	350	int num_dig; /* number of dig blocks */
	351	int disp_priority;
	352	const struct amdgpu_display_funcs *funcs;
e04a6123	353	const enum drm_plane_type *plane_type;
d38ceaf9 AD	354	};
	355
	356	#define AMDGPU_MAX_BL_LEVEL 0xFF
	357
	358	#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) \|\| defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
	359
	360	struct amdgpu_backlight_privdata {
	361	struct amdgpu_encoder *encoder;
	362	uint8_t negative;
	363	};
	364
	365	#endif
	366
	367	struct amdgpu_atom_ss {
	368	uint16_t percentage;
	369	uint16_t percentage_divider;
	370	uint8_t type;
	371	uint16_t step;
	372	uint8_t delay;
	373	uint8_t range;
	374	uint8_t refdiv;
	375	/* asic_ss */
	376	uint16_t rate;
	377	uint16_t amount;
	378	};
	379
	380	struct amdgpu_crtc {
	381	struct drm_crtc base;
	382	int crtc_id;
d38ceaf9 AD	383	bool enabled;
	384	bool can_tile;
	385	uint32_t crtc_offset;
	386	struct drm_gem_object *cursor_bo;
	387	uint64_t cursor_addr;
29275a9b AD	388	int cursor_x;
	389	int cursor_y;
	390	int cursor_hot_x;
	391	int cursor_hot_y;
d38ceaf9 AD	392	int cursor_width;
	393	int cursor_height;
	394	int max_cursor_width;
	395	int max_cursor_height;
	396	enum amdgpu_rmx_type rmx_type;
	397	u8 h_border;
	398	u8 v_border;
	399	fixed20_12 vsc;
	400	fixed20_12 hsc;
	401	struct drm_display_mode native_mode;
	402	u32 pll_id;
	403	/* page flipping */
d38ceaf9 AD	404	struct amdgpu_flip_work *pflip_works;
	405	enum amdgpu_flip_status pflip_status;
	406	int deferred_flip_completion;
fdd1fe57	407	u32 last_flip_vblank;
d38ceaf9 AD	408	/* pll sharing */
	409	struct amdgpu_atom_ss ss;
	410	bool ss_enabled;
	411	u32 adjusted_clock;
	412	int bpc;
	413	u32 pll_reference_div;
	414	u32 pll_post_div;
	415	u32 pll_flags;
	416	struct drm_encoder *encoder;
	417	struct drm_connector *connector;
	418	/* for dpm */
	419	u32 line_time;
	420	u32 wm_low;
	421	u32 wm_high;
8e36f9d3	422	u32 lb_vblank_lead_lines;
d38ceaf9	423	struct drm_display_mode hw_mode;
0f66356d ED	424	/* for virtual dce */
	425	struct hrtimer vblank_timer;
	426	enum amdgpu_interrupt_state vsync_timer_enabled;
4562236b HW	427
4562236b HW	428	int otg_inst;
dd55d12c	429	struct drm_pending_vblank_event *event;
d38ceaf9 AD	430	};
	431
	432	struct amdgpu_encoder_atom_dig {
	433	bool linkb;
	434	/* atom dig */
	435	bool coherent_mode;
	436	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
	437	/* atom lvds/edp */
	438	uint32_t lcd_misc;
	439	uint16_t panel_pwr_delay;
	440	uint32_t lcd_ss_id;
	441	/* panel mode */
	442	struct drm_display_mode native_mode;
	443	struct backlight_device *bl_dev;
	444	int dpms_mode;
	445	uint8_t backlight_level;
	446	int panel_mode;
	447	struct amdgpu_afmt *afmt;
	448	};
	449
	450	struct amdgpu_encoder {
	451	struct drm_encoder base;
	452	uint32_t encoder_enum;
	453	uint32_t encoder_id;
	454	uint32_t devices;
	455	uint32_t active_device;
	456	uint32_t flags;
	457	uint32_t pixel_clock;
	458	enum amdgpu_rmx_type rmx_type;
	459	enum amdgpu_underscan_type underscan_type;
	460	uint32_t underscan_hborder;
	461	uint32_t underscan_vborder;
	462	struct drm_display_mode native_mode;
	463	void *enc_priv;
	464	int audio_polling_active;
	465	bool is_ext_encoder;
	466	u16 caps;
	467	};
	468
	469	struct amdgpu_connector_atom_dig {
	470	/* displayport */
	471	u8 dpcd[DP_RECEIVER_CAP_SIZE];
65bf2cf9	472	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
d38ceaf9 AD	473	u8 dp_sink_type;
	474	int dp_clock;
	475	int dp_lane_count;
	476	bool edp_on;
	477	};
	478
	479	struct amdgpu_gpio_rec {
	480	bool valid;
	481	u8 id;
	482	u32 reg;
	483	u32 mask;
	484	u32 shift;
	485	};
	486
	487	struct amdgpu_hpd {
	488	enum amdgpu_hpd_id hpd;
	489	u8 plugged_state;
	490	struct amdgpu_gpio_rec gpio;
	491	};
	492
	493	struct amdgpu_router {
	494	u32 router_id;
	495	struct amdgpu_i2c_bus_rec i2c_info;
	496	u8 i2c_addr;
	497	/* i2c mux */
	498	bool ddc_valid;
	499	u8 ddc_mux_type;
	500	u8 ddc_mux_control_pin;
	501	u8 ddc_mux_state;
	502	/* clock/data mux */
	503	bool cd_valid;
	504	u8 cd_mux_type;
	505	u8 cd_mux_control_pin;
	506	u8 cd_mux_state;
	507	};
	508
	509	enum amdgpu_connector_audio {
	510	AMDGPU_AUDIO_DISABLE = 0,
	511	AMDGPU_AUDIO_ENABLE = 1,
	512	AMDGPU_AUDIO_AUTO = 2
	513	};
	514
	515	enum amdgpu_connector_dither {
	516	AMDGPU_FMT_DITHER_DISABLE = 0,
	517	AMDGPU_FMT_DITHER_ENABLE = 1,
	518	};
	519
4562236b HW	520	struct amdgpu_dm_dp_aux {
4562236b HW	521	struct drm_dp_aux aux;
46df790c	522	struct ddc_service *ddc_service;
4562236b HW	523	};
	524
	525	struct amdgpu_i2c_adapter {
	526	struct i2c_adapter base;
46df790c AG	527
46df790c AG	528	struct ddc_service *ddc_service;
4562236b HW	529	};
	530
	531	#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
	532
d38ceaf9 AD	533	struct amdgpu_connector {
	534	struct drm_connector base;
	535	uint32_t connector_id;
	536	uint32_t devices;
	537	struct amdgpu_i2c_chan *ddc_bus;
	538	/* some systems have an hdmi and vga port with a shared ddc line */
	539	bool shared_ddc;
	540	bool use_digital;
	541	/* we need to mind the EDID between detect
	542	and get modes due to analog/digital/tvencoder */
	543	struct edid *edid;
	544	void *con_priv;
	545	bool dac_load_detect;
	546	bool detected_by_load; /* if the connection status was determined by load */
	547	uint16_t connector_object_id;
	548	struct amdgpu_hpd hpd;
	549	struct amdgpu_router router;
	550	struct amdgpu_i2c_chan *router_bus;
	551	enum amdgpu_connector_audio audio;
	552	enum amdgpu_connector_dither dither;
	553	unsigned pixelclock_for_modeset;
	554	};
	555
4562236b HW	556	/* TODO: start to use this struct and remove same field from base one */
	557	struct amdgpu_mst_connector {
	558	struct amdgpu_connector base;
	559
	560	struct drm_dp_mst_topology_mgr mst_mgr;
	561	struct amdgpu_dm_dp_aux dm_dp_aux;
	562	struct drm_dp_mst_port *port;
	563	struct amdgpu_connector *mst_port;
	564	bool is_mst_connector;
	565	struct amdgpu_encoder *mst_encoder;
d38ceaf9 AD	566	};
	567
	568	#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) \|\| \
	569	((em) == ATOM_ENCODER_MODE_DP_MST))
	570
aa8e286a	571	/* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
1bf6ad62 DV	572	#define DRM_SCANOUTPOS_VALID (1 << 0)
	573	#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
	574	#define DRM_SCANOUTPOS_ACCURATE (1 << 2)
edf600da	575	#define USE_REAL_VBLANKSTART (1 << 30)
8e36f9d3 AD	576	#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
8e36f9d3 AD	577
d38ceaf9 AD	578	void amdgpu_link_encoder_connector(struct drm_device *dev);
	579
	580	struct drm_connector *
	581	amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
	582	struct drm_connector *
	583	amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
	584	bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
	585	u32 pixel_clock);
	586
	587	u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
	588	struct drm_encoder amdgpu_get_external_encoder(struct drm_encoder encoder);
	589
e0b5b5ec SL	590	bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
e0b5b5ec SL	591	bool use_aux);
d38ceaf9 AD	592
	593	void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
	594
aa8e286a SL	595	int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
	596	unsigned int pipe, unsigned int flags, int *vpos,
	597	int hpos, ktime_t stime, ktime_t *etime,
	598	const struct drm_display_mode *mode);
d38ceaf9	599
9da3f2d9 SL	600	int amdgpu_display_framebuffer_init(struct drm_device *dev,
	601	struct amdgpu_framebuffer *rfb,
	602	const struct drm_mode_fb_cmd2 *mode_cmd,
	603	struct drm_gem_object *obj);
d38ceaf9 AD	604
	605	int amdgpufb_remove(struct drm_device dev, struct drm_framebuffer fb);
	606
	607	void amdgpu_enc_destroy(struct drm_encoder *encoder);
	608	void amdgpu_copy_fb(struct drm_device dev, struct drm_gem_object dst_obj);
0c16443a SL	609	bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
	610	const struct drm_display_mode *mode,
	611	struct drm_display_mode *adjusted_mode);
d38ceaf9 AD	612	void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
d38ceaf9 AD	613	struct drm_display_mode *adjusted_mode);
734dd01d	614	int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
d38ceaf9	615
ea702333 TZ	616	bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
	617	bool in_vblank_irq, int *vpos,
	618	int hpos, ktime_t stime, ktime_t *etime,
	619	const struct drm_display_mode *mode);
	620
d38ceaf9 AD	621	/* fbdev layer */
	622	int amdgpu_fbdev_init(struct amdgpu_device *adev);
	623	void amdgpu_fbdev_fini(struct amdgpu_device *adev);
	624	void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
	625	int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
	626	bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device adev, struct amdgpu_bo robj);
d38ceaf9 AD	627
	628	int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
	629
	630	/* amdgpu_display.c */
50af9193	631	void amdgpu_display_print_display_setup(struct drm_device *dev);
3dc9b1ce	632	int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
775a8364 SL	633	int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
775a8364 SL	634	struct drm_modeset_acquire_ctx *ctx);
0cd11932 SL	635	int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
	636	struct drm_framebuffer *fb,
	637	struct drm_pending_vblank_event *event,
	638	uint32_t page_flip_flags, uint32_t target,
	639	struct drm_modeset_acquire_ctx *ctx);
d38ceaf9 AD	640	extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
	641
	642	#endif