[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_mode.h

/*
 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
 *                VA Linux Systems Inc., Fremont, California.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Original Authors:
 *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
 *
 * Kernel port Author: Dave Airlie
 */

#ifndef AMDGPU_MODE_H
#define AMDGPU_MODE_H

#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/drm_encoder.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_fixed.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_fb_helper.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/hrtimer.h>
#include "amdgpu_irq.h"

#include <drm/drm_dp_mst_helper.h>
#include "modules/inc/mod_freesync.h"

struct amdgpu_bo;
struct amdgpu_device;
struct amdgpu_encoder;
struct amdgpu_router;
struct amdgpu_hpd;

#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
#define to_amdgpu_plane(x)	container_of(x, struct amdgpu_plane, base)

#define AMDGPU_MAX_HPD_PINS 6
#define AMDGPU_MAX_CRTCS 6
#define AMDGPU_MAX_PLANES 6
#define AMDGPU_MAX_AFMT_BLOCKS 9

enum amdgpu_rmx_type {
	RMX_OFF,
	RMX_FULL,
	RMX_CENTER,
	RMX_ASPECT
};

enum amdgpu_underscan_type {
	UNDERSCAN_OFF,
	UNDERSCAN_ON,
	UNDERSCAN_AUTO,
};

#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10

enum amdgpu_hpd_id {
	AMDGPU_HPD_1 = 0,
	AMDGPU_HPD_2,
	AMDGPU_HPD_3,
	AMDGPU_HPD_4,
	AMDGPU_HPD_5,
	AMDGPU_HPD_6,
	AMDGPU_HPD_LAST,
	AMDGPU_HPD_NONE = 0xff,
};

enum amdgpu_crtc_irq {
	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
	AMDGPU_CRTC_IRQ_VBLANK2,
	AMDGPU_CRTC_IRQ_VBLANK3,
	AMDGPU_CRTC_IRQ_VBLANK4,
	AMDGPU_CRTC_IRQ_VBLANK5,
	AMDGPU_CRTC_IRQ_VBLANK6,
	AMDGPU_CRTC_IRQ_VLINE1,
	AMDGPU_CRTC_IRQ_VLINE2,
	AMDGPU_CRTC_IRQ_VLINE3,
	AMDGPU_CRTC_IRQ_VLINE4,
	AMDGPU_CRTC_IRQ_VLINE5,
	AMDGPU_CRTC_IRQ_VLINE6,
	AMDGPU_CRTC_IRQ_LAST,
	AMDGPU_CRTC_IRQ_NONE = 0xff
};

enum amdgpu_pageflip_irq {
	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
	AMDGPU_PAGEFLIP_IRQ_D2,
	AMDGPU_PAGEFLIP_IRQ_D3,
	AMDGPU_PAGEFLIP_IRQ_D4,
	AMDGPU_PAGEFLIP_IRQ_D5,
	AMDGPU_PAGEFLIP_IRQ_D6,
	AMDGPU_PAGEFLIP_IRQ_LAST,
	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
};

enum amdgpu_flip_status {
	AMDGPU_FLIP_NONE,
	AMDGPU_FLIP_PENDING,
	AMDGPU_FLIP_SUBMITTED
};

#define AMDGPU_MAX_I2C_BUS 16

/* amdgpu gpio-based i2c
 * 1. "mask" reg and bits
 *    grabs the gpio pins for software use
 *    0=not held  1=held
 * 2. "a" reg and bits
 *    output pin value
 *    0=low 1=high
 * 3. "en" reg and bits
 *    sets the pin direction
 *    0=input 1=output
 * 4. "y" reg and bits
 *    input pin value
 *    0=low 1=high
 */
struct amdgpu_i2c_bus_rec {
	bool valid;
	/* id used by atom */
	uint8_t i2c_id;
	/* id used by atom */
	enum amdgpu_hpd_id hpd;
	/* can be used with hw i2c engine */
	bool hw_capable;
	/* uses multi-media i2c engine */
	bool mm_i2c;
	/* regs and bits */
	uint32_t mask_clk_reg;
	uint32_t mask_data_reg;
	uint32_t a_clk_reg;
	uint32_t a_data_reg;
	uint32_t en_clk_reg;
	uint32_t en_data_reg;
	uint32_t y_clk_reg;
	uint32_t y_data_reg;
	uint32_t mask_clk_mask;
	uint32_t mask_data_mask;
	uint32_t a_clk_mask;
	uint32_t a_data_mask;
	uint32_t en_clk_mask;
	uint32_t en_data_mask;
	uint32_t y_clk_mask;
	uint32_t y_data_mask;
};

#define AMDGPU_MAX_BIOS_CONNECTOR 16

/* pll flags */
#define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
#define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
#define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
#define AMDGPU_PLL_LEGACY               (1 << 3)
#define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
#define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
#define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
#define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
#define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
#define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
#define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
#define AMDGPU_PLL_IS_LCD               (1 << 13)
#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)

struct amdgpu_pll {
	/* reference frequency */
	uint32_t reference_freq;

	/* fixed dividers */
	uint32_t reference_div;
	uint32_t post_div;

	/* pll in/out limits */
	uint32_t pll_in_min;
	uint32_t pll_in_max;
	uint32_t pll_out_min;
	uint32_t pll_out_max;
	uint32_t lcd_pll_out_min;
	uint32_t lcd_pll_out_max;
	uint32_t best_vco;

	/* divider limits */
	uint32_t min_ref_div;
	uint32_t max_ref_div;
	uint32_t min_post_div;
	uint32_t max_post_div;
	uint32_t min_feedback_div;
	uint32_t max_feedback_div;
	uint32_t min_frac_feedback_div;
	uint32_t max_frac_feedback_div;

	/* flags for the current clock */
	uint32_t flags;

	/* pll id */
	uint32_t id;
};

struct amdgpu_i2c_chan {
	struct i2c_adapter adapter;
	struct drm_device *dev;
	struct i2c_algo_bit_data bit;
	struct amdgpu_i2c_bus_rec rec;
	struct drm_dp_aux aux;
	bool has_aux;
	struct mutex mutex;
};

struct amdgpu_fbdev;

struct amdgpu_afmt {
	bool enabled;
	int offset;
	bool last_buffer_filled_status;
	int id;
	struct amdgpu_audio_pin *pin;
};

/*
 * Audio
 */
struct amdgpu_audio_pin {
	int			channels;
	int			rate;
	int			bits_per_sample;
	u8			status_bits;
	u8			category_code;
	u32			offset;
	bool			connected;
	u32			id;
};

struct amdgpu_audio {
	bool enabled;
	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
	int num_pins;
};

struct amdgpu_display_funcs {
	/* display watermarks */
	void (*bandwidth_update)(struct amdgpu_device *adev);
	/* get frame count */
	u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
	/* wait for vblank */
	void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
	/* set backlight level */
	void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
				    u8 level);
	/* get backlight level */
	u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
	/* hotplug detect */
	bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
	void (*hpd_set_polarity)(struct amdgpu_device *adev,
				 enum amdgpu_hpd_id hpd);
	u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
	/* pageflipping */
	void (*page_flip)(struct amdgpu_device *adev,
			  int crtc_id, u64 crtc_base, bool async);
	int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
					u32 *vbl, u32 *position);
	/* display topology setup */
	void (*add_encoder)(struct amdgpu_device *adev,
			    uint32_t encoder_enum,
			    uint32_t supported_device,
			    u16 caps);
	void (*add_connector)(struct amdgpu_device *adev,
			      uint32_t connector_id,
			      uint32_t supported_device,
			      int connector_type,
			      struct amdgpu_i2c_bus_rec *i2c_bus,
			      uint16_t connector_object_id,
			      struct amdgpu_hpd *hpd,
			      struct amdgpu_router *router);
	/* it is used to enter or exit into free sync mode */
	int (*notify_freesync)(struct drm_device *dev, void *data,
			       struct drm_file *filp);
	/* it is used to allow enablement of freesync mode */
	int (*set_freesync_property)(struct drm_connector *connector,
				     struct drm_property *property,
				     uint64_t val);


};

struct amdgpu_framebuffer {
	struct drm_framebuffer base;
	struct drm_gem_object *obj;

	/* caching for later use */
	uint64_t address;
};

struct amdgpu_fbdev {
	struct drm_fb_helper helper;
	struct amdgpu_framebuffer rfb;
	struct list_head fbdev_list;
	struct amdgpu_device *adev;
};

struct amdgpu_mode_info {
	struct atom_context *atom_context;
	struct card_info *atom_card_info;
	bool mode_config_initialized;
	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
	struct amdgpu_plane *planes[AMDGPU_MAX_PLANES];
	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
	/* DVI-I properties */
	struct drm_property *coherent_mode_property;
	/* DAC enable load detect */
	struct drm_property *load_detect_property;
	/* underscan */
	struct drm_property *underscan_property;
	struct drm_property *underscan_hborder_property;
	struct drm_property *underscan_vborder_property;
	/* audio */
	struct drm_property *audio_property;
	/* FMT dithering */
	struct drm_property *dither_property;
	/* hardcoded DFP edid from BIOS */
	struct edid *bios_hardcoded_edid;
	int bios_hardcoded_edid_size;

	/* pointer to fbdev info structure */
	struct amdgpu_fbdev *rfbdev;
	/* firmware flags */
	u16 firmware_flags;
	/* pointer to backlight encoder */
	struct amdgpu_encoder *bl_encoder;
	struct amdgpu_audio	audio; /* audio stuff */
	int			num_crtc; /* number of crtcs */
	int			num_hpd; /* number of hpd pins */
	int			num_dig; /* number of dig blocks */
	int			disp_priority;
	const struct amdgpu_display_funcs *funcs;
	enum drm_plane_type *plane_type;
};

#define AMDGPU_MAX_BL_LEVEL 0xFF

#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

struct amdgpu_backlight_privdata {
	struct amdgpu_encoder *encoder;
	uint8_t negative;
};

#endif

struct amdgpu_atom_ss {
	uint16_t percentage;
	uint16_t percentage_divider;
	uint8_t type;
	uint16_t step;
	uint8_t delay;
	uint8_t range;
	uint8_t refdiv;
	/* asic_ss */
	uint16_t rate;
	uint16_t amount;
};

struct amdgpu_crtc {
	struct drm_crtc base;
	int crtc_id;
	bool enabled;
	bool can_tile;
	uint32_t crtc_offset;
	struct drm_gem_object *cursor_bo;
	uint64_t cursor_addr;
	int cursor_x;
	int cursor_y;
	int cursor_hot_x;
	int cursor_hot_y;
	int cursor_width;
	int cursor_height;
	int max_cursor_width;
	int max_cursor_height;
	enum amdgpu_rmx_type rmx_type;
	u8 h_border;
	u8 v_border;
	fixed20_12 vsc;
	fixed20_12 hsc;
	struct drm_display_mode native_mode;
	u32 pll_id;
	/* page flipping */
	struct amdgpu_flip_work *pflip_works;
	enum amdgpu_flip_status pflip_status;
	int deferred_flip_completion;
	/* pll sharing */
	struct amdgpu_atom_ss ss;
	bool ss_enabled;
	u32 adjusted_clock;
	int bpc;
	u32 pll_reference_div;
	u32 pll_post_div;
	u32 pll_flags;
	struct drm_encoder *encoder;
	struct drm_connector *connector;
	/* for dpm */
	u32 line_time;
	u32 wm_low;
	u32 wm_high;
	u32 lb_vblank_lead_lines;
	struct drm_display_mode hw_mode;
	/* for virtual dce */
	struct hrtimer vblank_timer;
	enum amdgpu_interrupt_state vsync_timer_enabled;

	int otg_inst;
	uint32_t flip_flags;
	/* After Set Mode stream will be non-NULL */
	const struct dc_stream *stream;
	struct drm_pending_vblank_event *event;
};

struct amdgpu_drm_plane_state {
	struct drm_plane_state base;
	unsigned int h_ratio;
	unsigned int v_ratio;
};

static inline struct amdgpu_drm_plane_state *
to_amdgpu_plane_state(struct drm_plane_state *state)
{
	return container_of(state, struct amdgpu_drm_plane_state, base);
}

struct amdgpu_plane {
	struct drm_plane base;
	enum drm_plane_type plane_type;
};

struct amdgpu_encoder_atom_dig {
	bool linkb;
	/* atom dig */
	bool coherent_mode;
	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
	/* atom lvds/edp */
	uint32_t lcd_misc;
	uint16_t panel_pwr_delay;
	uint32_t lcd_ss_id;
	/* panel mode */
	struct drm_display_mode native_mode;
	struct backlight_device *bl_dev;
	int dpms_mode;
	uint8_t backlight_level;
	int panel_mode;
	struct amdgpu_afmt *afmt;
};

struct amdgpu_encoder {
	struct drm_encoder base;
	uint32_t encoder_enum;
	uint32_t encoder_id;
	uint32_t devices;
	uint32_t active_device;
	uint32_t flags;
	uint32_t pixel_clock;
	enum amdgpu_rmx_type rmx_type;
	enum amdgpu_underscan_type underscan_type;
	uint32_t underscan_hborder;
	uint32_t underscan_vborder;
	struct drm_display_mode native_mode;
	void *enc_priv;
	int audio_polling_active;
	bool is_ext_encoder;
	u16 caps;
};

struct amdgpu_connector_atom_dig {
	/* displayport */
	u8 dpcd[DP_RECEIVER_CAP_SIZE];
	u8 dp_sink_type;
	int dp_clock;
	int dp_lane_count;
	bool edp_on;
};

struct amdgpu_gpio_rec {
	bool valid;
	u8 id;
	u32 reg;
	u32 mask;
	u32 shift;
};

struct amdgpu_hpd {
	enum amdgpu_hpd_id hpd;
	u8 plugged_state;
	struct amdgpu_gpio_rec gpio;
};

struct amdgpu_router {
	u32 router_id;
	struct amdgpu_i2c_bus_rec i2c_info;
	u8 i2c_addr;
	/* i2c mux */
	bool ddc_valid;
	u8 ddc_mux_type;
	u8 ddc_mux_control_pin;
	u8 ddc_mux_state;
	/* clock/data mux */
	bool cd_valid;
	u8 cd_mux_type;
	u8 cd_mux_control_pin;
	u8 cd_mux_state;
};

enum amdgpu_connector_audio {
	AMDGPU_AUDIO_DISABLE = 0,
	AMDGPU_AUDIO_ENABLE = 1,
	AMDGPU_AUDIO_AUTO = 2
};

enum amdgpu_connector_dither {
	AMDGPU_FMT_DITHER_DISABLE = 0,
	AMDGPU_FMT_DITHER_ENABLE = 1,
};

struct amdgpu_dm_dp_aux {
	struct drm_dp_aux aux;
	uint32_t link_index;
};

struct amdgpu_i2c_adapter {
	struct i2c_adapter base;
	struct amdgpu_display_manager *dm;
	uint32_t link_index;
};

#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)

struct amdgpu_connector {
	struct drm_connector base;
	uint32_t connector_id;
	uint32_t devices;
	struct amdgpu_i2c_chan *ddc_bus;
	/* some systems have an hdmi and vga port with a shared ddc line */
	bool shared_ddc;
	bool use_digital;
	/* we need to mind the EDID between detect
	   and get modes due to analog/digital/tvencoder */
	struct edid *edid;
	/* number of modes generated from EDID at 'dc_sink' */
	int num_modes;
	/* The 'old' sink - before an HPD.
	 * The 'current' sink is in dc_link->sink. */
	const struct dc_sink *dc_sink;
	const struct dc_link *dc_link;
	const struct dc_sink *dc_em_sink;
	const struct dc_stream *stream;
	void *con_priv;
	bool dac_load_detect;
	bool detected_by_load; /* if the connection status was determined by load */
	uint16_t connector_object_id;
	struct amdgpu_hpd hpd;
	struct amdgpu_router router;
	struct amdgpu_i2c_chan *router_bus;
	enum amdgpu_connector_audio audio;
	enum amdgpu_connector_dither dither;
	unsigned pixelclock_for_modeset;

	struct drm_dp_mst_topology_mgr mst_mgr;
	struct amdgpu_dm_dp_aux dm_dp_aux;
	struct drm_dp_mst_port *port;
	struct amdgpu_connector *mst_port;
	struct amdgpu_encoder *mst_encoder;
	struct semaphore mst_sem;

	/* TODO see if we can merge with ddc_bus or make a dm_connector */
	struct amdgpu_i2c_adapter *i2c;

	/* Monitor range limits */
	int min_vfreq ;
	int max_vfreq ;
	int pixel_clock_mhz;

	/*freesync caps*/
	struct mod_freesync_caps caps;

	struct mutex hpd_lock;

};

/* TODO: start to use this struct and remove same field from base one */
struct amdgpu_mst_connector {
	struct amdgpu_connector base;

	struct drm_dp_mst_topology_mgr mst_mgr;
	struct amdgpu_dm_dp_aux dm_dp_aux;
	struct drm_dp_mst_port *port;
	struct amdgpu_connector *mst_port;
	bool is_mst_connector;
	struct amdgpu_encoder *mst_encoder;
};

#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
				((em) == ATOM_ENCODER_MODE_DP_MST))

/* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
#define DRM_SCANOUTPOS_VALID        (1 << 0)
#define DRM_SCANOUTPOS_IN_VBLANK    (1 << 1)
#define DRM_SCANOUTPOS_ACCURATE     (1 << 2)
#define USE_REAL_VBLANKSTART		(1 << 30)
#define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)

void amdgpu_link_encoder_connector(struct drm_device *dev);

struct drm_connector *
amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
struct drm_connector *
amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
				    u32 pixel_clock);

u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);

bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);

void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);

int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
			       unsigned int flags, int *vpos, int *hpos,
			       ktime_t *stime, ktime_t *etime,
			       const struct drm_display_mode *mode);

int amdgpu_framebuffer_init(struct drm_device *dev,
			     struct amdgpu_framebuffer *rfb,
			     const struct drm_mode_fb_cmd2 *mode_cmd,
			     struct drm_gem_object *obj);

int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);

void amdgpu_enc_destroy(struct drm_encoder *encoder);
void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
					const struct drm_display_mode *mode,
					struct drm_display_mode *adjusted_mode);
void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
			     struct drm_display_mode *adjusted_mode);
int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);

/* fbdev layer */
int amdgpu_fbdev_init(struct amdgpu_device *adev);
void amdgpu_fbdev_fini(struct amdgpu_device *adev);
void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);

void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);


int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);

/* amdgpu_display.c */
void amdgpu_print_display_setup(struct drm_device *dev);
int amdgpu_modeset_create_props(struct amdgpu_device *adev);
int amdgpu_crtc_set_config(struct drm_mode_set *set,
			   struct drm_modeset_acquire_ctx *ctx);
int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_pending_vblank_event *event,
				 uint32_t page_flip_flags, uint32_t target,
				 struct drm_modeset_acquire_ctx *ctx);
extern const struct drm_mode_config_funcs amdgpu_mode_funcs;

#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
	3	* VA Linux Systems Inc., Fremont, California.
	4	* Copyright 2008 Red Hat Inc.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Original Authors:
	25	* Kevin E. Martin, Rickard E. Faith, Alan Hourihane
	26	*
	27	* Kernel port Author: Dave Airlie
	28	*/
	29
	30	#ifndef AMDGPU_MODE_H
	31	#define AMDGPU_MODE_H
	32
	33	#include <drm/drm_crtc.h>
	34	#include <drm/drm_edid.h>
9338203c	35	#include <drm/drm_encoder.h>
d38ceaf9 AD	36	#include <drm/drm_dp_helper.h>
	37	#include <drm/drm_fixed.h>
	38	#include <drm/drm_crtc_helper.h>
b516a9ef	39	#include <drm/drm_fb_helper.h>
d38ceaf9	40	#include <drm/drm_plane_helper.h>
4562236b	41	#include <drm/drm_fb_helper.h>
d38ceaf9 AD	42	#include <linux/i2c.h>
d38ceaf9 AD	43	#include <linux/i2c-algo-bit.h>
46ac3622 ED	44	#include <linux/hrtimer.h>
46ac3622 ED	45	#include "amdgpu_irq.h"
d38ceaf9	46
4562236b HW	47	#include <drm/drm_dp_mst_helper.h>
	48	#include "modules/inc/mod_freesync.h"
	49
d38ceaf9 AD	50	struct amdgpu_bo;
	51	struct amdgpu_device;
	52	struct amdgpu_encoder;
	53	struct amdgpu_router;
	54	struct amdgpu_hpd;
	55
	56	#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
	57	#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
	58	#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
	59	#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
64d8b780	60	#define to_amdgpu_plane(x) container_of(x, struct amdgpu_plane, base)
d38ceaf9 AD	61
	62	#define AMDGPU_MAX_HPD_PINS 6
	63	#define AMDGPU_MAX_CRTCS 6
d4e13b0d	64	#define AMDGPU_MAX_PLANES 6
22384459	65	#define AMDGPU_MAX_AFMT_BLOCKS 9
d38ceaf9 AD	66
	67	enum amdgpu_rmx_type {
	68	RMX_OFF,
	69	RMX_FULL,
	70	RMX_CENTER,
	71	RMX_ASPECT
	72	};
	73
	74	enum amdgpu_underscan_type {
	75	UNDERSCAN_OFF,
	76	UNDERSCAN_ON,
	77	UNDERSCAN_AUTO,
	78	};
	79
	80	#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
	81	#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
	82
	83	enum amdgpu_hpd_id {
	84	AMDGPU_HPD_1 = 0,
	85	AMDGPU_HPD_2,
	86	AMDGPU_HPD_3,
	87	AMDGPU_HPD_4,
	88	AMDGPU_HPD_5,
	89	AMDGPU_HPD_6,
	90	AMDGPU_HPD_LAST,
	91	AMDGPU_HPD_NONE = 0xff,
	92	};
	93
	94	enum amdgpu_crtc_irq {
	95	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
	96	AMDGPU_CRTC_IRQ_VBLANK2,
	97	AMDGPU_CRTC_IRQ_VBLANK3,
	98	AMDGPU_CRTC_IRQ_VBLANK4,
	99	AMDGPU_CRTC_IRQ_VBLANK5,
	100	AMDGPU_CRTC_IRQ_VBLANK6,
	101	AMDGPU_CRTC_IRQ_VLINE1,
	102	AMDGPU_CRTC_IRQ_VLINE2,
	103	AMDGPU_CRTC_IRQ_VLINE3,
	104	AMDGPU_CRTC_IRQ_VLINE4,
	105	AMDGPU_CRTC_IRQ_VLINE5,
	106	AMDGPU_CRTC_IRQ_VLINE6,
	107	AMDGPU_CRTC_IRQ_LAST,
	108	AMDGPU_CRTC_IRQ_NONE = 0xff
	109	};
	110
	111	enum amdgpu_pageflip_irq {
	112	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
	113	AMDGPU_PAGEFLIP_IRQ_D2,
	114	AMDGPU_PAGEFLIP_IRQ_D3,
	115	AMDGPU_PAGEFLIP_IRQ_D4,
	116	AMDGPU_PAGEFLIP_IRQ_D5,
	117	AMDGPU_PAGEFLIP_IRQ_D6,
	118	AMDGPU_PAGEFLIP_IRQ_LAST,
	119	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
	120	};
	121
	122	enum amdgpu_flip_status {
	123	AMDGPU_FLIP_NONE,
	124	AMDGPU_FLIP_PENDING,
	125	AMDGPU_FLIP_SUBMITTED
	126	};
	127
	128	#define AMDGPU_MAX_I2C_BUS 16
	129
130	/* amdgpu gpio-based i2c
131	* 1. "mask" reg and bits
132	* grabs the gpio pins for software use
133	* 0=not held 1=held
134	* 2. "a" reg and bits
135	* output pin value
136	* 0=low 1=high
137	* 3. "en" reg and bits
138	* sets the pin direction
139	* 0=input 1=output
140	* 4. "y" reg and bits
141	* input pin value
142	* 0=low 1=high
143	*/
144	struct amdgpu_i2c_bus_rec {
145	bool valid;
146	/* id used by atom */
147	uint8_t i2c_id;
148	/* id used by atom */
149	enum amdgpu_hpd_id hpd;
150	/* can be used with hw i2c engine */
151	bool hw_capable;
152	/* uses multi-media i2c engine */
153	bool mm_i2c;
154	/* regs and bits */
155	uint32_t mask_clk_reg;
156	uint32_t mask_data_reg;
157	uint32_t a_clk_reg;
158	uint32_t a_data_reg;
159	uint32_t en_clk_reg;
160	uint32_t en_data_reg;
161	uint32_t y_clk_reg;
162	uint32_t y_data_reg;
163	uint32_t mask_clk_mask;
164	uint32_t mask_data_mask;
165	uint32_t a_clk_mask;
166	uint32_t a_data_mask;
167	uint32_t en_clk_mask;
168	uint32_t en_data_mask;
169	uint32_t y_clk_mask;
170	uint32_t y_data_mask;
171	};
172
173	#define AMDGPU_MAX_BIOS_CONNECTOR 16
174
175	/* pll flags */
176	#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
177	#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
178	#define AMDGPU_PLL_USE_REF_DIV (1 << 2)
179	#define AMDGPU_PLL_LEGACY (1 << 3)
180	#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
181	#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
182	#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
183	#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
184	#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
185	#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
186	#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
187	#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
188	#define AMDGPU_PLL_USE_POST_DIV (1 << 12)
189	#define AMDGPU_PLL_IS_LCD (1 << 13)
190	#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
191
192	struct amdgpu_pll {
193	/* reference frequency */
194	uint32_t reference_freq;
195
196	/* fixed dividers */
197	uint32_t reference_div;
198	uint32_t post_div;
199
200	/* pll in/out limits */
201	uint32_t pll_in_min;
202	uint32_t pll_in_max;
203	uint32_t pll_out_min;
204	uint32_t pll_out_max;
205	uint32_t lcd_pll_out_min;
206	uint32_t lcd_pll_out_max;
207	uint32_t best_vco;
208
209	/* divider limits */
210	uint32_t min_ref_div;
211	uint32_t max_ref_div;
212	uint32_t min_post_div;
213	uint32_t max_post_div;
214	uint32_t min_feedback_div;
215	uint32_t max_feedback_div;
216	uint32_t min_frac_feedback_div;
217	uint32_t max_frac_feedback_div;
218
219	/* flags for the current clock */
220	uint32_t flags;
221
222	/* pll id */
223	uint32_t id;
224	};
225
226	struct amdgpu_i2c_chan {
227	struct i2c_adapter adapter;
228	struct drm_device *dev;
229	struct i2c_algo_bit_data bit;
230	struct amdgpu_i2c_bus_rec rec;
231	struct drm_dp_aux aux;
232	bool has_aux;
233	struct mutex mutex;
234	};
235
236	struct amdgpu_fbdev;
237
238	struct amdgpu_afmt {
239	bool enabled;
240	int offset;
241	bool last_buffer_filled_status;
242	int id;
243	struct amdgpu_audio_pin *pin;
244	};
245
246	/*
247	* Audio
248	*/
249	struct amdgpu_audio_pin {
250	int channels;
251	int rate;
252	int bits_per_sample;
253	u8 status_bits;
254	u8 category_code;
255	u32 offset;
256	bool connected;
257	u32 id;
258	};
259
260	struct amdgpu_audio {
261	bool enabled;
262	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
263	int num_pins;
264	};
265
d38ceaf9	266	struct amdgpu_display_funcs {
d38ceaf9 AD	267	/* display watermarks */
	268	void (bandwidth_update)(struct amdgpu_device adev);
	269	/* get frame count */
	270	u32 (vblank_get_counter)(struct amdgpu_device adev, int crtc);
	271	/* wait for vblank */
	272	void (vblank_wait)(struct amdgpu_device adev, int crtc);
d38ceaf9 AD	273	/* set backlight level */
	274	void (backlight_set_level)(struct amdgpu_encoder amdgpu_encoder,
	275	u8 level);
	276	/* get backlight level */
	277	u8 (backlight_get_level)(struct amdgpu_encoder amdgpu_encoder);
	278	/* hotplug detect */
	279	bool (hpd_sense)(struct amdgpu_device adev, enum amdgpu_hpd_id hpd);
	280	void (hpd_set_polarity)(struct amdgpu_device adev,
	281	enum amdgpu_hpd_id hpd);
	282	u32 (hpd_get_gpio_reg)(struct amdgpu_device adev);
	283	/* pageflipping */
	284	void (page_flip)(struct amdgpu_device adev,
cb9e59d7	285	int crtc_id, u64 crtc_base, bool async);
d38ceaf9 AD	286	int (page_flip_get_scanoutpos)(struct amdgpu_device adev, int crtc,
	287	u32 vbl, u32 position);
	288	/* display topology setup */
	289	void (add_encoder)(struct amdgpu_device adev,
	290	uint32_t encoder_enum,
	291	uint32_t supported_device,
	292	u16 caps);
	293	void (add_connector)(struct amdgpu_device adev,
	294	uint32_t connector_id,
	295	uint32_t supported_device,
	296	int connector_type,
	297	struct amdgpu_i2c_bus_rec *i2c_bus,
	298	uint16_t connector_object_id,
	299	struct amdgpu_hpd *hpd,
	300	struct amdgpu_router *router);
4562236b HW	301	/* it is used to enter or exit into free sync mode */
	302	int (notify_freesync)(struct drm_device dev, void *data,
	303	struct drm_file *filp);
	304	/* it is used to allow enablement of freesync mode */
	305	int (set_freesync_property)(struct drm_connector connector,
	306	struct drm_property *property,
	307	uint64_t val);
	308
	309
	310	};
	311
	312	struct amdgpu_framebuffer {
	313	struct drm_framebuffer base;
	314	struct drm_gem_object *obj;
dd55d12c AG	315
	316	/* caching for later use */
	317	uint64_t address;
4562236b HW	318	};
	319
	320	struct amdgpu_fbdev {
	321	struct drm_fb_helper helper;
	322	struct amdgpu_framebuffer rfb;
	323	struct list_head fbdev_list;
	324	struct amdgpu_device *adev;
d38ceaf9 AD	325	};
	326
	327	struct amdgpu_mode_info {
	328	struct atom_context *atom_context;
	329	struct card_info *atom_card_info;
	330	bool mode_config_initialized;
f195038c	331	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
d4e13b0d	332	struct amdgpu_plane *planes[AMDGPU_MAX_PLANES];
f195038c	333	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
d38ceaf9 AD	334	/* DVI-I properties */
	335	struct drm_property *coherent_mode_property;
	336	/* DAC enable load detect */
	337	struct drm_property *load_detect_property;
	338	/* underscan */
	339	struct drm_property *underscan_property;
	340	struct drm_property *underscan_hborder_property;
	341	struct drm_property *underscan_vborder_property;
	342	/* audio */
	343	struct drm_property *audio_property;
	344	/* FMT dithering */
	345	struct drm_property *dither_property;
	346	/* hardcoded DFP edid from BIOS */
	347	struct edid *bios_hardcoded_edid;
	348	int bios_hardcoded_edid_size;
	349
	350	/* pointer to fbdev info structure */
	351	struct amdgpu_fbdev *rfbdev;
	352	/* firmware flags */
	353	u16 firmware_flags;
	354	/* pointer to backlight encoder */
	355	struct amdgpu_encoder *bl_encoder;
	356	struct amdgpu_audio audio; /* audio stuff */
	357	int num_crtc; /* number of crtcs */
	358	int num_hpd; /* number of hpd pins */
	359	int num_dig; /* number of dig blocks */
	360	int disp_priority;
	361	const struct amdgpu_display_funcs *funcs;
d4e13b0d	362	enum drm_plane_type *plane_type;
d38ceaf9 AD	363	};
	364
	365	#define AMDGPU_MAX_BL_LEVEL 0xFF
	366
	367	#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) \|\| defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
	368
	369	struct amdgpu_backlight_privdata {
	370	struct amdgpu_encoder *encoder;
	371	uint8_t negative;
	372	};
	373
	374	#endif
	375
	376	struct amdgpu_atom_ss {
	377	uint16_t percentage;
	378	uint16_t percentage_divider;
	379	uint8_t type;
	380	uint16_t step;
	381	uint8_t delay;
	382	uint8_t range;
	383	uint8_t refdiv;
	384	/* asic_ss */
	385	uint16_t rate;
	386	uint16_t amount;
	387	};
	388
	389	struct amdgpu_crtc {
	390	struct drm_crtc base;
	391	int crtc_id;
d38ceaf9 AD	392	bool enabled;
	393	bool can_tile;
	394	uint32_t crtc_offset;
	395	struct drm_gem_object *cursor_bo;
	396	uint64_t cursor_addr;
29275a9b AD	397	int cursor_x;
	398	int cursor_y;
	399	int cursor_hot_x;
	400	int cursor_hot_y;
d38ceaf9 AD	401	int cursor_width;
	402	int cursor_height;
	403	int max_cursor_width;
	404	int max_cursor_height;
	405	enum amdgpu_rmx_type rmx_type;
	406	u8 h_border;
	407	u8 v_border;
	408	fixed20_12 vsc;
	409	fixed20_12 hsc;
	410	struct drm_display_mode native_mode;
	411	u32 pll_id;
	412	/* page flipping */
d38ceaf9 AD	413	struct amdgpu_flip_work *pflip_works;
	414	enum amdgpu_flip_status pflip_status;
	415	int deferred_flip_completion;
	416	/* pll sharing */
	417	struct amdgpu_atom_ss ss;
	418	bool ss_enabled;
	419	u32 adjusted_clock;
	420	int bpc;
	421	u32 pll_reference_div;
	422	u32 pll_post_div;
	423	u32 pll_flags;
	424	struct drm_encoder *encoder;
	425	struct drm_connector *connector;
	426	/* for dpm */
	427	u32 line_time;
	428	u32 wm_low;
	429	u32 wm_high;
8e36f9d3	430	u32 lb_vblank_lead_lines;
d38ceaf9	431	struct drm_display_mode hw_mode;
0f66356d ED	432	/* for virtual dce */
	433	struct hrtimer vblank_timer;
	434	enum amdgpu_interrupt_state vsync_timer_enabled;
4562236b HW	435
	436	int otg_inst;
	437	uint32_t flip_flags;
ab2541b6 AC	438	/* After Set Mode stream will be non-NULL */
ab2541b6 AC	439	const struct dc_stream *stream;
dd55d12c	440	struct drm_pending_vblank_event *event;
d38ceaf9 AD	441	};
d38ceaf9 AD	442
64d8b780 S	443	struct amdgpu_drm_plane_state {
	444	struct drm_plane_state base;
	445	unsigned int h_ratio;
	446	unsigned int v_ratio;
	447	};
	448
	449	static inline struct amdgpu_drm_plane_state *
	450	to_amdgpu_plane_state(struct drm_plane_state *state)
	451	{
	452	return container_of(state, struct amdgpu_drm_plane_state, base);
	453	}
	454
d4e13b0d AD	455	struct amdgpu_plane {
	456	struct drm_plane base;
	457	enum drm_plane_type plane_type;
	458	};
	459
d38ceaf9 AD	460	struct amdgpu_encoder_atom_dig {
	461	bool linkb;
	462	/* atom dig */
	463	bool coherent_mode;
	464	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
	465	/* atom lvds/edp */
	466	uint32_t lcd_misc;
	467	uint16_t panel_pwr_delay;
	468	uint32_t lcd_ss_id;
	469	/* panel mode */
	470	struct drm_display_mode native_mode;
	471	struct backlight_device *bl_dev;
	472	int dpms_mode;
	473	uint8_t backlight_level;
	474	int panel_mode;
	475	struct amdgpu_afmt *afmt;
	476	};
	477
	478	struct amdgpu_encoder {
	479	struct drm_encoder base;
	480	uint32_t encoder_enum;
	481	uint32_t encoder_id;
	482	uint32_t devices;
	483	uint32_t active_device;
	484	uint32_t flags;
	485	uint32_t pixel_clock;
	486	enum amdgpu_rmx_type rmx_type;
	487	enum amdgpu_underscan_type underscan_type;
	488	uint32_t underscan_hborder;
	489	uint32_t underscan_vborder;
	490	struct drm_display_mode native_mode;
	491	void *enc_priv;
	492	int audio_polling_active;
	493	bool is_ext_encoder;
	494	u16 caps;
	495	};
	496
	497	struct amdgpu_connector_atom_dig {
	498	/* displayport */
	499	u8 dpcd[DP_RECEIVER_CAP_SIZE];
	500	u8 dp_sink_type;
	501	int dp_clock;
	502	int dp_lane_count;
	503	bool edp_on;
	504	};
	505
	506	struct amdgpu_gpio_rec {
	507	bool valid;
	508	u8 id;
	509	u32 reg;
	510	u32 mask;
	511	u32 shift;
	512	};
	513
	514	struct amdgpu_hpd {
	515	enum amdgpu_hpd_id hpd;
	516	u8 plugged_state;
	517	struct amdgpu_gpio_rec gpio;
	518	};
	519
	520	struct amdgpu_router {
	521	u32 router_id;
	522	struct amdgpu_i2c_bus_rec i2c_info;
	523	u8 i2c_addr;
524	/* i2c mux */
525	bool ddc_valid;
526	u8 ddc_mux_type;
527	u8 ddc_mux_control_pin;
528	u8 ddc_mux_state;
529	/* clock/data mux */
530	bool cd_valid;
531	u8 cd_mux_type;
532	u8 cd_mux_control_pin;
533	u8 cd_mux_state;
534	};
535
536	enum amdgpu_connector_audio {
537	AMDGPU_AUDIO_DISABLE = 0,
538	AMDGPU_AUDIO_ENABLE = 1,
539	AMDGPU_AUDIO_AUTO = 2
540	};
541
542	enum amdgpu_connector_dither {
543	AMDGPU_FMT_DITHER_DISABLE = 0,
544	AMDGPU_FMT_DITHER_ENABLE = 1,
545	};
546
4562236b HW	547	struct amdgpu_dm_dp_aux {
	548	struct drm_dp_aux aux;
	549	uint32_t link_index;
	550	};
	551
	552	struct amdgpu_i2c_adapter {
	553	struct i2c_adapter base;
	554	struct amdgpu_display_manager *dm;
	555	uint32_t link_index;
	556	};
	557
	558	#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
	559
d38ceaf9 AD	560	struct amdgpu_connector {
	561	struct drm_connector base;
	562	uint32_t connector_id;
	563	uint32_t devices;
	564	struct amdgpu_i2c_chan *ddc_bus;
	565	/* some systems have an hdmi and vga port with a shared ddc line */
	566	bool shared_ddc;
	567	bool use_digital;
	568	/* we need to mind the EDID between detect
	569	and get modes due to analog/digital/tvencoder */
	570	struct edid *edid;
4562236b HW	571	/* number of modes generated from EDID at 'dc_sink' */
	572	int num_modes;
	573	/* The 'old' sink - before an HPD.
	574	* The 'current' sink is in dc_link->sink. */
	575	const struct dc_sink *dc_sink;
	576	const struct dc_link *dc_link;
	577	const struct dc_sink *dc_em_sink;
ab2541b6	578	const struct dc_stream *stream;
d38ceaf9 AD	579	void *con_priv;
	580	bool dac_load_detect;
	581	bool detected_by_load; /* if the connection status was determined by load */
	582	uint16_t connector_object_id;
	583	struct amdgpu_hpd hpd;
	584	struct amdgpu_router router;
	585	struct amdgpu_i2c_chan *router_bus;
	586	enum amdgpu_connector_audio audio;
	587	enum amdgpu_connector_dither dither;
	588	unsigned pixelclock_for_modeset;
4562236b HW	589
	590	struct drm_dp_mst_topology_mgr mst_mgr;
	591	struct amdgpu_dm_dp_aux dm_dp_aux;
	592	struct drm_dp_mst_port *port;
	593	struct amdgpu_connector *mst_port;
	594	struct amdgpu_encoder *mst_encoder;
	595	struct semaphore mst_sem;
	596
	597	/* TODO see if we can merge with ddc_bus or make a dm_connector */
	598	struct amdgpu_i2c_adapter *i2c;
	599
	600	/* Monitor range limits */
	601	int min_vfreq ;
	602	int max_vfreq ;
	603	int pixel_clock_mhz;
	604
	605	/freesync caps/
	606	struct mod_freesync_caps caps;
	607
	608	struct mutex hpd_lock;
	609
d38ceaf9 AD	610	};
d38ceaf9 AD	611
4562236b HW	612	/* TODO: start to use this struct and remove same field from base one */
	613	struct amdgpu_mst_connector {
	614	struct amdgpu_connector base;
	615
	616	struct drm_dp_mst_topology_mgr mst_mgr;
	617	struct amdgpu_dm_dp_aux dm_dp_aux;
	618	struct drm_dp_mst_port *port;
	619	struct amdgpu_connector *mst_port;
	620	bool is_mst_connector;
	621	struct amdgpu_encoder *mst_encoder;
d38ceaf9 AD	622	};
	623
	624	#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) \|\| \
	625	((em) == ATOM_ENCODER_MODE_DP_MST))
	626
8e36f9d3	627	/* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
1bf6ad62 DV	628	#define DRM_SCANOUTPOS_VALID (1 << 0)
	629	#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
	630	#define DRM_SCANOUTPOS_ACCURATE (1 << 2)
edf600da	631	#define USE_REAL_VBLANKSTART (1 << 30)
8e36f9d3 AD	632	#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
8e36f9d3 AD	633
d38ceaf9 AD	634	void amdgpu_link_encoder_connector(struct drm_device *dev);
	635
	636	struct drm_connector *
	637	amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
	638	struct drm_connector *
	639	amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
	640	bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
	641	u32 pixel_clock);
	642
	643	u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
	644	struct drm_encoder amdgpu_get_external_encoder(struct drm_encoder encoder);
	645
	646	bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
	647
	648	void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
	649
88e72717 TR	650	int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
	651	unsigned int flags, int vpos, int hpos,
	652	ktime_t stime, ktime_t etime,
	653	const struct drm_display_mode *mode);
d38ceaf9 AD	654
	655	int amdgpu_framebuffer_init(struct drm_device *dev,
	656	struct amdgpu_framebuffer *rfb,
1eb83451	657	const struct drm_mode_fb_cmd2 *mode_cmd,
d38ceaf9 AD	658	struct drm_gem_object *obj);
	659
	660	int amdgpufb_remove(struct drm_device dev, struct drm_framebuffer fb);
	661
	662	void amdgpu_enc_destroy(struct drm_encoder *encoder);
	663	void amdgpu_copy_fb(struct drm_device dev, struct drm_gem_object dst_obj);
	664	bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
	665	const struct drm_display_mode *mode,
	666	struct drm_display_mode *adjusted_mode);
	667	void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
	668	struct drm_display_mode *adjusted_mode);
	669	int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
	670
	671	/* fbdev layer */
	672	int amdgpu_fbdev_init(struct amdgpu_device *adev);
	673	void amdgpu_fbdev_fini(struct amdgpu_device *adev);
	674	void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
	675	int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
	676	bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device adev, struct amdgpu_bo robj);
8b7530b1	677	void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);
d38ceaf9 AD	678
	679	void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
	680
	681
	682	int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
	683
	684	/* amdgpu_display.c */
	685	void amdgpu_print_display_setup(struct drm_device *dev);
	686	int amdgpu_modeset_create_props(struct amdgpu_device *adev);
a4eff9aa DV	687	int amdgpu_crtc_set_config(struct drm_mode_set *set,
a4eff9aa DV	688	struct drm_modeset_acquire_ctx *ctx);
325cbba1 MD	689	int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
	690	struct drm_framebuffer *fb,
	691	struct drm_pending_vblank_event *event,
41292b1f DV	692	uint32_t page_flip_flags, uint32_t target,
41292b1f DV	693	struct drm_modeset_acquire_ctx *ctx);
d38ceaf9 AD	694	extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
	695
	696	#endif