[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_object.h

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __AMDGPU_OBJECT_H__
#define __AMDGPU_OBJECT_H__

#include <drm/amdgpu_drm.h>
#include "amdgpu.h"

#define AMDGPU_BO_INVALID_OFFSET	LONG_MAX

/* bo virtual addresses in a vm */
struct amdgpu_bo_va_mapping {
	struct list_head		list;
	struct rb_node			rb;
	uint64_t			start;
	uint64_t			last;
	uint64_t			__subtree_last;
	uint64_t			offset;
	uint64_t			flags;
};

/* User space allocated BO in a VM */
struct amdgpu_bo_va {
	struct amdgpu_vm_bo_base	base;

	/* protected by bo being reserved */
	struct dma_fence	        *last_pt_update;
	unsigned			ref_count;

	/* mappings for this bo_va */
	struct list_head		invalids;
	struct list_head		valids;
};

struct amdgpu_bo {
	/* Protected by tbo.reserved */
	u32				preferred_domains;
	u32				allowed_domains;
	struct ttm_place		placements[AMDGPU_GEM_DOMAIN_MAX + 1];
	struct ttm_placement		placement;
	struct ttm_buffer_object	tbo;
	struct ttm_bo_kmap_obj		kmap;
	u64				flags;
	unsigned			pin_count;
	u64				tiling_flags;
	u64				metadata_flags;
	void				*metadata;
	u32				metadata_size;
	unsigned			prime_shared_count;
	/* list of all virtual address to which this bo is associated to */
	struct list_head		va;
	/* Constant after initialization */
	struct drm_gem_object		gem_base;
	struct amdgpu_bo		*parent;
	struct amdgpu_bo		*shadow;

	struct ttm_bo_kmap_obj		dma_buf_vmap;
	struct amdgpu_mn		*mn;

	union {
		struct list_head	mn_list;
		struct list_head	shadow_list;
	};
};

/**
 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
 * @mem_type:	ttm memory type
 *
 * Returns corresponding domain of the ttm mem_type
 */
static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
{
	switch (mem_type) {
	case TTM_PL_VRAM:
		return AMDGPU_GEM_DOMAIN_VRAM;
	case TTM_PL_TT:
		return AMDGPU_GEM_DOMAIN_GTT;
	case TTM_PL_SYSTEM:
		return AMDGPU_GEM_DOMAIN_CPU;
	case AMDGPU_PL_GDS:
		return AMDGPU_GEM_DOMAIN_GDS;
	case AMDGPU_PL_GWS:
		return AMDGPU_GEM_DOMAIN_GWS;
	case AMDGPU_PL_OA:
		return AMDGPU_GEM_DOMAIN_OA;
	default:
		break;
	}
	return 0;
}

/**
 * amdgpu_bo_reserve - reserve bo
 * @bo:		bo structure
 * @no_intr:	don't return -ERESTARTSYS on pending signal
 *
 * Returns:
 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 * a signal. Release all buffer reservations and return to user-space.
 */
static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
{
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
	int r;

	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
	if (unlikely(r != 0)) {
		if (r != -ERESTARTSYS)
			dev_err(adev->dev, "%p reserve failed\n", bo);
		return r;
	}
	return 0;
}

static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
{
	ttm_bo_unreserve(&bo->tbo);
}

static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
{
	return bo->tbo.num_pages << PAGE_SHIFT;
}

static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
{
	return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
}

static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
{
	return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
}

/**
 * amdgpu_bo_mmap_offset - return mmap offset of bo
 * @bo:	amdgpu object for which we query the offset
 *
 * Returns mmap offset of the object.
 */
static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
{
	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
}

/**
 * amdgpu_bo_gpu_accessible - return whether the bo is currently in memory that
 * is accessible to the GPU.
 */
static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
{
	switch (bo->tbo.mem.mem_type) {
	case TTM_PL_TT: return amdgpu_ttm_is_bound(bo->tbo.ttm);
	case TTM_PL_VRAM: return true;
	default: return false;
	}
}

int amdgpu_bo_create(struct amdgpu_device *adev,
			    unsigned long size, int byte_align,
			    bool kernel, u32 domain, u64 flags,
			    struct sg_table *sg,
			    struct reservation_object *resv,
			    uint64_t init_value,
			    struct amdgpu_bo **bo_ptr);
int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
				unsigned long size, int byte_align,
				bool kernel, u32 domain, u64 flags,
				struct sg_table *sg,
				struct ttm_placement *placement,
			        struct reservation_object *resv,
				uint64_t init_value,
				struct amdgpu_bo **bo_ptr);
int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
			      unsigned long size, int align,
			      u32 domain, struct amdgpu_bo **bo_ptr,
			      u64 *gpu_addr, void **cpu_addr);
int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
			    unsigned long size, int align,
			    u32 domain, struct amdgpu_bo **bo_ptr,
			    u64 *gpu_addr, void **cpu_addr);
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
			   void **cpu_addr);
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
void amdgpu_bo_unref(struct amdgpu_bo **bo);
int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
			     u64 min_offset, u64 max_offset,
			     u64 *gpu_addr);
int amdgpu_bo_unpin(struct amdgpu_bo *bo);
int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
int amdgpu_bo_init(struct amdgpu_device *adev);
void amdgpu_bo_fini(struct amdgpu_device *adev);
int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
				struct vm_area_struct *vma);
int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
			    uint32_t metadata_size, uint64_t flags);
int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
			   size_t buffer_size, uint32_t *metadata_size,
			   uint64_t *flags);
void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
			   bool evict,
			   struct ttm_mem_reg *new_mem);
int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
		     bool shared);
u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
			       struct amdgpu_ring *ring,
			       struct amdgpu_bo *bo,
			       struct reservation_object *resv,
			       struct dma_fence **fence, bool direct);
int amdgpu_bo_validate(struct amdgpu_bo *bo);
int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
				  struct amdgpu_ring *ring,
				  struct amdgpu_bo *bo,
				  struct reservation_object *resv,
				  struct dma_fence **fence,
				  bool direct);


/*
 * sub allocation
 */

static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
{
	return sa_bo->manager->gpu_addr + sa_bo->soffset;
}

static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
{
	return sa_bo->manager->cpu_ptr + sa_bo->soffset;
}

int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
				     struct amdgpu_sa_manager *sa_manager,
				     unsigned size, u32 align, u32 domain);
void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
				      struct amdgpu_sa_manager *sa_manager);
int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
				      struct amdgpu_sa_manager *sa_manager);
int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
					struct amdgpu_sa_manager *sa_manager);
int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
		     struct amdgpu_sa_bo **sa_bo,
		     unsigned size, unsigned align);
void amdgpu_sa_bo_free(struct amdgpu_device *adev,
			      struct amdgpu_sa_bo **sa_bo,
			      struct dma_fence *fence);
#if defined(CONFIG_DEBUG_FS)
void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
					 struct seq_file *m);
#endif


#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#ifndef __AMDGPU_OBJECT_H__
	29	#define __AMDGPU_OBJECT_H__
	30
	31	#include <drm/amdgpu_drm.h>
	32	#include "amdgpu.h"
	33
9702d40d CK	34	#define AMDGPU_BO_INVALID_OFFSET LONG_MAX
9702d40d CK	35
ec681545	36	/* bo virtual addresses in a vm */
9124a398 CK	37	struct amdgpu_bo_va_mapping {
	38	struct list_head list;
	39	struct rb_node rb;
	40	uint64_t start;
	41	uint64_t last;
	42	uint64_t __subtree_last;
	43	uint64_t offset;
	44	uint64_t flags;
	45	};
	46
ec681545	47	/* User space allocated BO in a VM */
9124a398	48	struct amdgpu_bo_va {
ec681545 CK	49	struct amdgpu_vm_bo_base base;
ec681545 CK	50
9124a398	51	/* protected by bo being reserved */
9124a398 CK	52	struct dma_fence *last_pt_update;
	53	unsigned ref_count;
	54
9124a398 CK	55	/* mappings for this bo_va */
	56	struct list_head invalids;
	57	struct list_head valids;
9124a398 CK	58	};
9124a398 CK	59
9124a398 CK	60	struct amdgpu_bo {
9124a398 CK	61	/* Protected by tbo.reserved */
6d7d9c5a	62	u32 preferred_domains;
9124a398 CK	63	u32 allowed_domains;
	64	struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
	65	struct ttm_placement placement;
	66	struct ttm_buffer_object tbo;
	67	struct ttm_bo_kmap_obj kmap;
	68	u64 flags;
	69	unsigned pin_count;
	70	u64 tiling_flags;
	71	u64 metadata_flags;
	72	void *metadata;
	73	u32 metadata_size;
	74	unsigned prime_shared_count;
	75	/* list of all virtual address to which this bo is associated to */
	76	struct list_head va;
	77	/* Constant after initialization */
	78	struct drm_gem_object gem_base;
	79	struct amdgpu_bo *parent;
	80	struct amdgpu_bo *shadow;
	81
	82	struct ttm_bo_kmap_obj dma_buf_vmap;
	83	struct amdgpu_mn *mn;
ed5b89c6 CK	84
	85	union {
	86	struct list_head mn_list;
	87	struct list_head shadow_list;
	88	};
9124a398 CK	89	};
9124a398 CK	90
d38ceaf9 AD	91	/**
	92	* amdgpu_mem_type_to_domain - return domain corresponding to mem_type
	93	* @mem_type: ttm memory type
	94	*
	95	* Returns corresponding domain of the ttm mem_type
	96	*/
	97	static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
	98	{
	99	switch (mem_type) {
	100	case TTM_PL_VRAM:
	101	return AMDGPU_GEM_DOMAIN_VRAM;
	102	case TTM_PL_TT:
	103	return AMDGPU_GEM_DOMAIN_GTT;
	104	case TTM_PL_SYSTEM:
	105	return AMDGPU_GEM_DOMAIN_CPU;
	106	case AMDGPU_PL_GDS:
	107	return AMDGPU_GEM_DOMAIN_GDS;
	108	case AMDGPU_PL_GWS:
	109	return AMDGPU_GEM_DOMAIN_GWS;
	110	case AMDGPU_PL_OA:
	111	return AMDGPU_GEM_DOMAIN_OA;
	112	default:
	113	break;
	114	}
	115	return 0;
	116	}
	117
	118	/**
	119	* amdgpu_bo_reserve - reserve bo
	120	* @bo: bo structure
	121	* @no_intr: don't return -ERESTARTSYS on pending signal
	122	*
	123	* Returns:
	124	* -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
	125	* a signal. Release all buffer reservations and return to user-space.
	126	*/
	127	static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
	128	{
a7d64de6	129	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
d38ceaf9 AD	130	int r;
d38ceaf9 AD	131
dfd5e50e	132	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
d38ceaf9 AD	133	if (unlikely(r != 0)) {
d38ceaf9 AD	134	if (r != -ERESTARTSYS)
a7d64de6	135	dev_err(adev->dev, "%p reserve failed\n", bo);
d38ceaf9 AD	136	return r;
	137	}
	138	return 0;
	139	}
	140
	141	static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
	142	{
	143	ttm_bo_unreserve(&bo->tbo);
	144	}
	145
d38ceaf9 AD	146	static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
	147	{
	148	return bo->tbo.num_pages << PAGE_SHIFT;
	149	}
	150
	151	static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
	152	{
	153	return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
	154	}
	155
	156	static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
	157	{
	158	return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
	159	}
	160
	161	/**
	162	* amdgpu_bo_mmap_offset - return mmap offset of bo
	163	* @bo: amdgpu object for which we query the offset
	164	*
	165	* Returns mmap offset of the object.
	166	*/
	167	static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
	168	{
	169	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
	170	}
	171
b99f3103 NH	172	/**
	173	* amdgpu_bo_gpu_accessible - return whether the bo is currently in memory that
	174	* is accessible to the GPU.
	175	*/
	176	static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
	177	{
9d63c034 CK	178	switch (bo->tbo.mem.mem_type) {
	179	case TTM_PL_TT: return amdgpu_ttm_is_bound(bo->tbo.ttm);
	180	case TTM_PL_VRAM: return true;
	181	default: return false;
	182	}
b99f3103 NH	183	}
b99f3103 NH	184
d38ceaf9 AD	185	int amdgpu_bo_create(struct amdgpu_device *adev,
	186	unsigned long size, int byte_align,
	187	bool kernel, u32 domain, u64 flags,
	188	struct sg_table *sg,
72d7668b	189	struct reservation_object *resv,
2046d46d	190	uint64_t init_value,
d38ceaf9	191	struct amdgpu_bo **bo_ptr);
7e5a547f CZ	192	int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
	193	unsigned long size, int byte_align,
	194	bool kernel, u32 domain, u64 flags,
	195	struct sg_table *sg,
	196	struct ttm_placement *placement,
72d7668b	197	struct reservation_object *resv,
2046d46d	198	uint64_t init_value,
7e5a547f	199	struct amdgpu_bo **bo_ptr);
9d903cbd CK	200	int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
	201	unsigned long size, int align,
	202	u32 domain, struct amdgpu_bo **bo_ptr,
	203	u64 gpu_addr, void *cpu_addr);
7c204889 CK	204	int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
	205	unsigned long size, int align,
	206	u32 domain, struct amdgpu_bo **bo_ptr,
	207	u64 gpu_addr, void *cpu_addr);
aa1d562e JZ	208	void amdgpu_bo_free_kernel(struct amdgpu_bo *bo, u64 gpu_addr,
aa1d562e JZ	209	void **cpu_addr);
d38ceaf9	210	int amdgpu_bo_kmap(struct amdgpu_bo bo, void *ptr);
f5e1c740	211	void amdgpu_bo_kptr(struct amdgpu_bo bo);
d38ceaf9 AD	212	void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
	213	struct amdgpu_bo amdgpu_bo_ref(struct amdgpu_bo bo);
	214	void amdgpu_bo_unref(struct amdgpu_bo **bo);
	215	int amdgpu_bo_pin(struct amdgpu_bo bo, u32 domain, u64 gpu_addr);
	216	int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
7e5a547f CZ	217	u64 min_offset, u64 max_offset,
7e5a547f CZ	218	u64 *gpu_addr);
d38ceaf9 AD	219	int amdgpu_bo_unpin(struct amdgpu_bo *bo);
d38ceaf9 AD	220	int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
d38ceaf9 AD	221	int amdgpu_bo_init(struct amdgpu_device *adev);
	222	void amdgpu_bo_fini(struct amdgpu_device *adev);
	223	int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
	224	struct vm_area_struct *vma);
	225	int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
	226	void amdgpu_bo_get_tiling_flags(struct amdgpu_bo bo, u64 tiling_flags);
	227	int amdgpu_bo_set_metadata (struct amdgpu_bo bo, void metadata,
	228	uint32_t metadata_size, uint64_t flags);
	229	int amdgpu_bo_get_metadata(struct amdgpu_bo bo, void buffer,
	230	size_t buffer_size, uint32_t *metadata_size,
	231	uint64_t *flags);
	232	void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
66257db7 NH	233	bool evict,
66257db7 NH	234	struct ttm_mem_reg *new_mem);
d38ceaf9	235	int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
f54d1867	236	void amdgpu_bo_fence(struct amdgpu_bo bo, struct dma_fence fence,
d38ceaf9	237	bool shared);
cdb7e8f2	238	u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
20f4eff1 CZ	239	int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
	240	struct amdgpu_ring *ring,
	241	struct amdgpu_bo *bo,
	242	struct reservation_object *resv,
f54d1867	243	struct dma_fence **fence, bool direct);
82521316	244	int amdgpu_bo_validate(struct amdgpu_bo *bo);
20f4eff1 CZ	245	int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
	246	struct amdgpu_ring *ring,
	247	struct amdgpu_bo *bo,
	248	struct reservation_object *resv,
f54d1867	249	struct dma_fence **fence,
20f4eff1 CZ	250	bool direct);
20f4eff1 CZ	251
d38ceaf9 AD	252
	253	/*
	254	* sub allocation
	255	*/
	256
	257	static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
	258	{
	259	return sa_bo->manager->gpu_addr + sa_bo->soffset;
	260	}
	261
	262	static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
	263	{
	264	return sa_bo->manager->cpu_ptr + sa_bo->soffset;
	265	}
	266
	267	int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
	268	struct amdgpu_sa_manager *sa_manager,
	269	unsigned size, u32 align, u32 domain);
	270	void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
	271	struct amdgpu_sa_manager *sa_manager);
	272	int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
	273	struct amdgpu_sa_manager *sa_manager);
	274	int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
	275	struct amdgpu_sa_manager *sa_manager);
bbf0b345 JZ	276	int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
	277	struct amdgpu_sa_bo **sa_bo,
	278	unsigned size, unsigned align);
d38ceaf9 AD	279	void amdgpu_sa_bo_free(struct amdgpu_device *adev,
d38ceaf9 AD	280	struct amdgpu_sa_bo **sa_bo,
f54d1867	281	struct dma_fence *fence);
d38ceaf9 AD	282	#if defined(CONFIG_DEBUG_FS)
	283	void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
	284	struct seq_file *m);
	285	#endif
	286
	287
	288	#endif