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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __AMDGPU_OBJECT_H__ | |
29 | #define __AMDGPU_OBJECT_H__ | |
30 | ||
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
33 | ||
9702d40d CK |
34 | #define AMDGPU_BO_INVALID_OFFSET LONG_MAX |
35 | ||
9124a398 CK |
36 | struct amdgpu_bo_va_mapping { |
37 | struct list_head list; | |
38 | struct rb_node rb; | |
39 | uint64_t start; | |
40 | uint64_t last; | |
41 | uint64_t __subtree_last; | |
42 | uint64_t offset; | |
43 | uint64_t flags; | |
44 | }; | |
45 | ||
46 | /* bo virtual addresses in a specific vm */ | |
47 | struct amdgpu_bo_va { | |
48 | /* protected by bo being reserved */ | |
49 | struct list_head bo_list; | |
50 | struct dma_fence *last_pt_update; | |
51 | unsigned ref_count; | |
52 | ||
53 | /* protected by vm mutex and spinlock */ | |
54 | struct list_head vm_status; | |
55 | ||
56 | /* mappings for this bo_va */ | |
57 | struct list_head invalids; | |
58 | struct list_head valids; | |
59 | ||
60 | /* constant after initialization */ | |
61 | struct amdgpu_vm *vm; | |
62 | struct amdgpu_bo *bo; | |
63 | }; | |
64 | ||
65 | ||
66 | struct amdgpu_bo { | |
67 | /* Protected by tbo.reserved */ | |
6d7d9c5a | 68 | u32 preferred_domains; |
9124a398 CK |
69 | u32 allowed_domains; |
70 | struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; | |
71 | struct ttm_placement placement; | |
72 | struct ttm_buffer_object tbo; | |
73 | struct ttm_bo_kmap_obj kmap; | |
74 | u64 flags; | |
75 | unsigned pin_count; | |
76 | u64 tiling_flags; | |
77 | u64 metadata_flags; | |
78 | void *metadata; | |
79 | u32 metadata_size; | |
80 | unsigned prime_shared_count; | |
81 | /* list of all virtual address to which this bo is associated to */ | |
82 | struct list_head va; | |
83 | /* Constant after initialization */ | |
84 | struct drm_gem_object gem_base; | |
85 | struct amdgpu_bo *parent; | |
86 | struct amdgpu_bo *shadow; | |
87 | ||
88 | struct ttm_bo_kmap_obj dma_buf_vmap; | |
89 | struct amdgpu_mn *mn; | |
ed5b89c6 CK |
90 | |
91 | union { | |
92 | struct list_head mn_list; | |
93 | struct list_head shadow_list; | |
94 | }; | |
9124a398 CK |
95 | }; |
96 | ||
d38ceaf9 AD |
97 | /** |
98 | * amdgpu_mem_type_to_domain - return domain corresponding to mem_type | |
99 | * @mem_type: ttm memory type | |
100 | * | |
101 | * Returns corresponding domain of the ttm mem_type | |
102 | */ | |
103 | static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) | |
104 | { | |
105 | switch (mem_type) { | |
106 | case TTM_PL_VRAM: | |
107 | return AMDGPU_GEM_DOMAIN_VRAM; | |
108 | case TTM_PL_TT: | |
109 | return AMDGPU_GEM_DOMAIN_GTT; | |
110 | case TTM_PL_SYSTEM: | |
111 | return AMDGPU_GEM_DOMAIN_CPU; | |
112 | case AMDGPU_PL_GDS: | |
113 | return AMDGPU_GEM_DOMAIN_GDS; | |
114 | case AMDGPU_PL_GWS: | |
115 | return AMDGPU_GEM_DOMAIN_GWS; | |
116 | case AMDGPU_PL_OA: | |
117 | return AMDGPU_GEM_DOMAIN_OA; | |
118 | default: | |
119 | break; | |
120 | } | |
121 | return 0; | |
122 | } | |
123 | ||
124 | /** | |
125 | * amdgpu_bo_reserve - reserve bo | |
126 | * @bo: bo structure | |
127 | * @no_intr: don't return -ERESTARTSYS on pending signal | |
128 | * | |
129 | * Returns: | |
130 | * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by | |
131 | * a signal. Release all buffer reservations and return to user-space. | |
132 | */ | |
133 | static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) | |
134 | { | |
a7d64de6 | 135 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
d38ceaf9 AD |
136 | int r; |
137 | ||
dfd5e50e | 138 | r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); |
d38ceaf9 AD |
139 | if (unlikely(r != 0)) { |
140 | if (r != -ERESTARTSYS) | |
a7d64de6 | 141 | dev_err(adev->dev, "%p reserve failed\n", bo); |
d38ceaf9 AD |
142 | return r; |
143 | } | |
144 | return 0; | |
145 | } | |
146 | ||
147 | static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo) | |
148 | { | |
149 | ttm_bo_unreserve(&bo->tbo); | |
150 | } | |
151 | ||
d38ceaf9 AD |
152 | static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo) |
153 | { | |
154 | return bo->tbo.num_pages << PAGE_SHIFT; | |
155 | } | |
156 | ||
157 | static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) | |
158 | { | |
159 | return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; | |
160 | } | |
161 | ||
162 | static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) | |
163 | { | |
164 | return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; | |
165 | } | |
166 | ||
167 | /** | |
168 | * amdgpu_bo_mmap_offset - return mmap offset of bo | |
169 | * @bo: amdgpu object for which we query the offset | |
170 | * | |
171 | * Returns mmap offset of the object. | |
172 | */ | |
173 | static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) | |
174 | { | |
175 | return drm_vma_node_offset_addr(&bo->tbo.vma_node); | |
176 | } | |
177 | ||
b99f3103 NH |
178 | /** |
179 | * amdgpu_bo_gpu_accessible - return whether the bo is currently in memory that | |
180 | * is accessible to the GPU. | |
181 | */ | |
182 | static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo) | |
183 | { | |
9d63c034 CK |
184 | switch (bo->tbo.mem.mem_type) { |
185 | case TTM_PL_TT: return amdgpu_ttm_is_bound(bo->tbo.ttm); | |
186 | case TTM_PL_VRAM: return true; | |
187 | default: return false; | |
188 | } | |
b99f3103 NH |
189 | } |
190 | ||
d38ceaf9 AD |
191 | int amdgpu_bo_create(struct amdgpu_device *adev, |
192 | unsigned long size, int byte_align, | |
193 | bool kernel, u32 domain, u64 flags, | |
194 | struct sg_table *sg, | |
72d7668b | 195 | struct reservation_object *resv, |
2046d46d | 196 | uint64_t init_value, |
d38ceaf9 | 197 | struct amdgpu_bo **bo_ptr); |
7e5a547f CZ |
198 | int amdgpu_bo_create_restricted(struct amdgpu_device *adev, |
199 | unsigned long size, int byte_align, | |
200 | bool kernel, u32 domain, u64 flags, | |
201 | struct sg_table *sg, | |
202 | struct ttm_placement *placement, | |
72d7668b | 203 | struct reservation_object *resv, |
2046d46d | 204 | uint64_t init_value, |
7e5a547f | 205 | struct amdgpu_bo **bo_ptr); |
9d903cbd CK |
206 | int amdgpu_bo_create_reserved(struct amdgpu_device *adev, |
207 | unsigned long size, int align, | |
208 | u32 domain, struct amdgpu_bo **bo_ptr, | |
209 | u64 *gpu_addr, void **cpu_addr); | |
7c204889 CK |
210 | int amdgpu_bo_create_kernel(struct amdgpu_device *adev, |
211 | unsigned long size, int align, | |
212 | u32 domain, struct amdgpu_bo **bo_ptr, | |
213 | u64 *gpu_addr, void **cpu_addr); | |
aa1d562e JZ |
214 | void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, |
215 | void **cpu_addr); | |
d38ceaf9 | 216 | int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); |
f5e1c740 | 217 | void *amdgpu_bo_kptr(struct amdgpu_bo *bo); |
d38ceaf9 AD |
218 | void amdgpu_bo_kunmap(struct amdgpu_bo *bo); |
219 | struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); | |
220 | void amdgpu_bo_unref(struct amdgpu_bo **bo); | |
221 | int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr); | |
222 | int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, | |
7e5a547f CZ |
223 | u64 min_offset, u64 max_offset, |
224 | u64 *gpu_addr); | |
d38ceaf9 AD |
225 | int amdgpu_bo_unpin(struct amdgpu_bo *bo); |
226 | int amdgpu_bo_evict_vram(struct amdgpu_device *adev); | |
d38ceaf9 AD |
227 | int amdgpu_bo_init(struct amdgpu_device *adev); |
228 | void amdgpu_bo_fini(struct amdgpu_device *adev); | |
229 | int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, | |
230 | struct vm_area_struct *vma); | |
231 | int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); | |
232 | void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); | |
233 | int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, | |
234 | uint32_t metadata_size, uint64_t flags); | |
235 | int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, | |
236 | size_t buffer_size, uint32_t *metadata_size, | |
237 | uint64_t *flags); | |
238 | void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, | |
66257db7 NH |
239 | bool evict, |
240 | struct ttm_mem_reg *new_mem); | |
d38ceaf9 | 241 | int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); |
f54d1867 | 242 | void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, |
d38ceaf9 | 243 | bool shared); |
cdb7e8f2 | 244 | u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); |
20f4eff1 CZ |
245 | int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev, |
246 | struct amdgpu_ring *ring, | |
247 | struct amdgpu_bo *bo, | |
248 | struct reservation_object *resv, | |
f54d1867 | 249 | struct dma_fence **fence, bool direct); |
82521316 | 250 | int amdgpu_bo_validate(struct amdgpu_bo *bo); |
20f4eff1 CZ |
251 | int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev, |
252 | struct amdgpu_ring *ring, | |
253 | struct amdgpu_bo *bo, | |
254 | struct reservation_object *resv, | |
f54d1867 | 255 | struct dma_fence **fence, |
20f4eff1 CZ |
256 | bool direct); |
257 | ||
d38ceaf9 AD |
258 | |
259 | /* | |
260 | * sub allocation | |
261 | */ | |
262 | ||
263 | static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo) | |
264 | { | |
265 | return sa_bo->manager->gpu_addr + sa_bo->soffset; | |
266 | } | |
267 | ||
268 | static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo) | |
269 | { | |
270 | return sa_bo->manager->cpu_ptr + sa_bo->soffset; | |
271 | } | |
272 | ||
273 | int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, | |
274 | struct amdgpu_sa_manager *sa_manager, | |
275 | unsigned size, u32 align, u32 domain); | |
276 | void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, | |
277 | struct amdgpu_sa_manager *sa_manager); | |
278 | int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, | |
279 | struct amdgpu_sa_manager *sa_manager); | |
280 | int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev, | |
281 | struct amdgpu_sa_manager *sa_manager); | |
bbf0b345 JZ |
282 | int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, |
283 | struct amdgpu_sa_bo **sa_bo, | |
284 | unsigned size, unsigned align); | |
d38ceaf9 AD |
285 | void amdgpu_sa_bo_free(struct amdgpu_device *adev, |
286 | struct amdgpu_sa_bo **sa_bo, | |
f54d1867 | 287 | struct dma_fence *fence); |
d38ceaf9 AD |
288 | #if defined(CONFIG_DEBUG_FS) |
289 | void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, | |
290 | struct seq_file *m); | |
291 | #endif | |
292 | ||
293 | ||
294 | #endif |