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d38ceaf9 | 1 | /* |
bf93b448 AD |
2 | * Copyright 2017 Advanced Micro Devices, Inc. |
3 | * | |
d38ceaf9 AD |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Rafał Miłecki <zajec5@gmail.com> | |
23 | * Alex Deucher <alexdeucher@gmail.com> | |
24 | */ | |
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_drv.h" | |
28 | #include "amdgpu_pm.h" | |
29 | #include "amdgpu_dpm.h" | |
30 | #include "atom.h" | |
31 | #include <linux/power_supply.h> | |
32 | #include <linux/hwmon.h> | |
33 | #include <linux/hwmon-sysfs.h> | |
d66e9a0b | 34 | #include <linux/nospec.h> |
d38ceaf9 | 35 | |
1b5708ff RZ |
36 | #include "amd_powerplay.h" |
37 | ||
d38ceaf9 AD |
38 | static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev); |
39 | ||
a8503b15 HR |
40 | static const struct cg_flag_name clocks[] = { |
41 | {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, | |
42 | {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, | |
43 | {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, | |
44 | {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, | |
54170226 | 45 | {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, |
a8503b15 HR |
46 | {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, |
47 | {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, | |
48 | {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, | |
12ad27fa HR |
49 | {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, |
50 | {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, | |
a8503b15 HR |
51 | {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, |
52 | {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, | |
53 | {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, | |
54 | {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, | |
e96487a6 | 55 | {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, |
a8503b15 HR |
56 | {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, |
57 | {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, | |
58 | {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, | |
59 | {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, | |
60 | {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, | |
f9abe35c HR |
61 | {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, |
62 | {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, | |
a8503b15 | 63 | {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, |
f9abe35c | 64 | {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, |
a8503b15 HR |
65 | {0, NULL}, |
66 | }; | |
67 | ||
d38ceaf9 AD |
68 | void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) |
69 | { | |
70 | if (adev->pm.dpm_enabled) { | |
71 | mutex_lock(&adev->pm.mutex); | |
72 | if (power_supply_is_system_supplied() > 0) | |
73 | adev->pm.dpm.ac_power = true; | |
74 | else | |
75 | adev->pm.dpm.ac_power = false; | |
cd4d7464 | 76 | if (adev->powerplay.pp_funcs->enable_bapm) |
d38ceaf9 AD |
77 | amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power); |
78 | mutex_unlock(&adev->pm.mutex); | |
79 | } | |
80 | } | |
81 | ||
82 | static ssize_t amdgpu_get_dpm_state(struct device *dev, | |
83 | struct device_attribute *attr, | |
84 | char *buf) | |
85 | { | |
86 | struct drm_device *ddev = dev_get_drvdata(dev); | |
87 | struct amdgpu_device *adev = ddev->dev_private; | |
1b5708ff RZ |
88 | enum amd_pm_state_type pm; |
89 | ||
cd4d7464 | 90 | if (adev->powerplay.pp_funcs->get_current_power_state) |
1b5708ff | 91 | pm = amdgpu_dpm_get_current_power_state(adev); |
cd4d7464 | 92 | else |
1b5708ff | 93 | pm = adev->pm.dpm.user_state; |
d38ceaf9 AD |
94 | |
95 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
96 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : | |
97 | (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); | |
98 | } | |
99 | ||
100 | static ssize_t amdgpu_set_dpm_state(struct device *dev, | |
101 | struct device_attribute *attr, | |
102 | const char *buf, | |
103 | size_t count) | |
104 | { | |
105 | struct drm_device *ddev = dev_get_drvdata(dev); | |
106 | struct amdgpu_device *adev = ddev->dev_private; | |
1b5708ff | 107 | enum amd_pm_state_type state; |
d38ceaf9 | 108 | |
d38ceaf9 | 109 | if (strncmp("battery", buf, strlen("battery")) == 0) |
1b5708ff | 110 | state = POWER_STATE_TYPE_BATTERY; |
d38ceaf9 | 111 | else if (strncmp("balanced", buf, strlen("balanced")) == 0) |
1b5708ff | 112 | state = POWER_STATE_TYPE_BALANCED; |
d38ceaf9 | 113 | else if (strncmp("performance", buf, strlen("performance")) == 0) |
1b5708ff | 114 | state = POWER_STATE_TYPE_PERFORMANCE; |
d38ceaf9 | 115 | else { |
d38ceaf9 AD |
116 | count = -EINVAL; |
117 | goto fail; | |
118 | } | |
d38ceaf9 | 119 | |
6d07fe7b | 120 | if (adev->powerplay.pp_funcs->dispatch_tasks) { |
df1e6394 | 121 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL); |
1b5708ff RZ |
122 | } else { |
123 | mutex_lock(&adev->pm.mutex); | |
124 | adev->pm.dpm.user_state = state; | |
125 | mutex_unlock(&adev->pm.mutex); | |
126 | ||
127 | /* Can't set dpm state when the card is off */ | |
128 | if (!(adev->flags & AMD_IS_PX) || | |
129 | (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) | |
130 | amdgpu_pm_compute_clocks(adev); | |
131 | } | |
d38ceaf9 AD |
132 | fail: |
133 | return count; | |
134 | } | |
135 | ||
136 | static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev, | |
1b5708ff RZ |
137 | struct device_attribute *attr, |
138 | char *buf) | |
d38ceaf9 AD |
139 | { |
140 | struct drm_device *ddev = dev_get_drvdata(dev); | |
141 | struct amdgpu_device *adev = ddev->dev_private; | |
cd4d7464 | 142 | enum amd_dpm_forced_level level = 0xff; |
d38ceaf9 | 143 | |
0c67df48 AD |
144 | if ((adev->flags & AMD_IS_PX) && |
145 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) | |
146 | return snprintf(buf, PAGE_SIZE, "off\n"); | |
147 | ||
cd4d7464 RZ |
148 | if (adev->powerplay.pp_funcs->get_performance_level) |
149 | level = amdgpu_dpm_get_performance_level(adev); | |
150 | else | |
151 | level = adev->pm.dpm.forced_level; | |
152 | ||
e5d03ac2 | 153 | return snprintf(buf, PAGE_SIZE, "%s\n", |
570272d2 RZ |
154 | (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : |
155 | (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : | |
156 | (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : | |
157 | (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : | |
158 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : | |
159 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : | |
160 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : | |
161 | (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : | |
162 | "unknown"); | |
d38ceaf9 AD |
163 | } |
164 | ||
165 | static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev, | |
166 | struct device_attribute *attr, | |
167 | const char *buf, | |
168 | size_t count) | |
169 | { | |
170 | struct drm_device *ddev = dev_get_drvdata(dev); | |
171 | struct amdgpu_device *adev = ddev->dev_private; | |
e5d03ac2 | 172 | enum amd_dpm_forced_level level; |
cd4d7464 | 173 | enum amd_dpm_forced_level current_level = 0xff; |
d38ceaf9 AD |
174 | int ret = 0; |
175 | ||
0c67df48 AD |
176 | /* Can't force performance level when the card is off */ |
177 | if ((adev->flags & AMD_IS_PX) && | |
178 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) | |
179 | return -EINVAL; | |
180 | ||
cd4d7464 RZ |
181 | if (adev->powerplay.pp_funcs->get_performance_level) |
182 | current_level = amdgpu_dpm_get_performance_level(adev); | |
3bd58979 | 183 | |
d38ceaf9 | 184 | if (strncmp("low", buf, strlen("low")) == 0) { |
e5d03ac2 | 185 | level = AMD_DPM_FORCED_LEVEL_LOW; |
d38ceaf9 | 186 | } else if (strncmp("high", buf, strlen("high")) == 0) { |
e5d03ac2 | 187 | level = AMD_DPM_FORCED_LEVEL_HIGH; |
d38ceaf9 | 188 | } else if (strncmp("auto", buf, strlen("auto")) == 0) { |
e5d03ac2 | 189 | level = AMD_DPM_FORCED_LEVEL_AUTO; |
f3898ea1 | 190 | } else if (strncmp("manual", buf, strlen("manual")) == 0) { |
e5d03ac2 | 191 | level = AMD_DPM_FORCED_LEVEL_MANUAL; |
570272d2 RZ |
192 | } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { |
193 | level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; | |
194 | } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { | |
195 | level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; | |
196 | } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { | |
197 | level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; | |
198 | } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { | |
199 | level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; | |
200 | } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { | |
201 | level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; | |
202 | } else { | |
d38ceaf9 AD |
203 | count = -EINVAL; |
204 | goto fail; | |
205 | } | |
1b5708ff | 206 | |
3bd58979 | 207 | if (current_level == level) |
8e7afd34 | 208 | return count; |
3bd58979 | 209 | |
cd4d7464 | 210 | if (adev->powerplay.pp_funcs->force_performance_level) { |
1b5708ff | 211 | mutex_lock(&adev->pm.mutex); |
d38ceaf9 AD |
212 | if (adev->pm.dpm.thermal_active) { |
213 | count = -EINVAL; | |
10f950f6 | 214 | mutex_unlock(&adev->pm.mutex); |
d38ceaf9 AD |
215 | goto fail; |
216 | } | |
217 | ret = amdgpu_dpm_force_performance_level(adev, level); | |
218 | if (ret) | |
219 | count = -EINVAL; | |
1b5708ff RZ |
220 | else |
221 | adev->pm.dpm.forced_level = level; | |
222 | mutex_unlock(&adev->pm.mutex); | |
d38ceaf9 | 223 | } |
570272d2 | 224 | |
d38ceaf9 | 225 | fail: |
d38ceaf9 AD |
226 | return count; |
227 | } | |
228 | ||
f3898ea1 EH |
229 | static ssize_t amdgpu_get_pp_num_states(struct device *dev, |
230 | struct device_attribute *attr, | |
231 | char *buf) | |
232 | { | |
233 | struct drm_device *ddev = dev_get_drvdata(dev); | |
234 | struct amdgpu_device *adev = ddev->dev_private; | |
235 | struct pp_states_info data; | |
236 | int i, buf_len; | |
237 | ||
cd4d7464 | 238 | if (adev->powerplay.pp_funcs->get_pp_num_states) |
f3898ea1 EH |
239 | amdgpu_dpm_get_pp_num_states(adev, &data); |
240 | ||
241 | buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums); | |
242 | for (i = 0; i < data.nums; i++) | |
243 | buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i, | |
244 | (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : | |
245 | (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : | |
246 | (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : | |
247 | (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); | |
248 | ||
249 | return buf_len; | |
250 | } | |
251 | ||
252 | static ssize_t amdgpu_get_pp_cur_state(struct device *dev, | |
253 | struct device_attribute *attr, | |
254 | char *buf) | |
255 | { | |
256 | struct drm_device *ddev = dev_get_drvdata(dev); | |
257 | struct amdgpu_device *adev = ddev->dev_private; | |
258 | struct pp_states_info data; | |
259 | enum amd_pm_state_type pm = 0; | |
260 | int i = 0; | |
261 | ||
cd4d7464 RZ |
262 | if (adev->powerplay.pp_funcs->get_current_power_state |
263 | && adev->powerplay.pp_funcs->get_pp_num_states) { | |
f3898ea1 EH |
264 | pm = amdgpu_dpm_get_current_power_state(adev); |
265 | amdgpu_dpm_get_pp_num_states(adev, &data); | |
266 | ||
267 | for (i = 0; i < data.nums; i++) { | |
268 | if (pm == data.states[i]) | |
269 | break; | |
270 | } | |
271 | ||
272 | if (i == data.nums) | |
273 | i = -EINVAL; | |
274 | } | |
275 | ||
276 | return snprintf(buf, PAGE_SIZE, "%d\n", i); | |
277 | } | |
278 | ||
279 | static ssize_t amdgpu_get_pp_force_state(struct device *dev, | |
280 | struct device_attribute *attr, | |
281 | char *buf) | |
282 | { | |
283 | struct drm_device *ddev = dev_get_drvdata(dev); | |
284 | struct amdgpu_device *adev = ddev->dev_private; | |
f3898ea1 | 285 | |
cd4d7464 RZ |
286 | if (adev->pp_force_state_enabled) |
287 | return amdgpu_get_pp_cur_state(dev, attr, buf); | |
288 | else | |
f3898ea1 EH |
289 | return snprintf(buf, PAGE_SIZE, "\n"); |
290 | } | |
291 | ||
292 | static ssize_t amdgpu_set_pp_force_state(struct device *dev, | |
293 | struct device_attribute *attr, | |
294 | const char *buf, | |
295 | size_t count) | |
296 | { | |
297 | struct drm_device *ddev = dev_get_drvdata(dev); | |
298 | struct amdgpu_device *adev = ddev->dev_private; | |
299 | enum amd_pm_state_type state = 0; | |
041bf022 | 300 | unsigned long idx; |
f3898ea1 EH |
301 | int ret; |
302 | ||
303 | if (strlen(buf) == 1) | |
304 | adev->pp_force_state_enabled = false; | |
6d07fe7b RZ |
305 | else if (adev->powerplay.pp_funcs->dispatch_tasks && |
306 | adev->powerplay.pp_funcs->get_pp_num_states) { | |
041bf022 | 307 | struct pp_states_info data; |
f3898ea1 | 308 | |
041bf022 DC |
309 | ret = kstrtoul(buf, 0, &idx); |
310 | if (ret || idx >= ARRAY_SIZE(data.states)) { | |
f3898ea1 EH |
311 | count = -EINVAL; |
312 | goto fail; | |
313 | } | |
d66e9a0b | 314 | idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); |
f3898ea1 | 315 | |
041bf022 DC |
316 | amdgpu_dpm_get_pp_num_states(adev, &data); |
317 | state = data.states[idx]; | |
318 | /* only set user selected power states */ | |
319 | if (state != POWER_STATE_TYPE_INTERNAL_BOOT && | |
320 | state != POWER_STATE_TYPE_DEFAULT) { | |
321 | amdgpu_dpm_dispatch_task(adev, | |
df1e6394 | 322 | AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL); |
041bf022 | 323 | adev->pp_force_state_enabled = true; |
f3898ea1 EH |
324 | } |
325 | } | |
326 | fail: | |
327 | return count; | |
328 | } | |
329 | ||
330 | static ssize_t amdgpu_get_pp_table(struct device *dev, | |
331 | struct device_attribute *attr, | |
332 | char *buf) | |
333 | { | |
334 | struct drm_device *ddev = dev_get_drvdata(dev); | |
335 | struct amdgpu_device *adev = ddev->dev_private; | |
336 | char *table = NULL; | |
1684d3ba | 337 | int size; |
f3898ea1 | 338 | |
cd4d7464 | 339 | if (adev->powerplay.pp_funcs->get_pp_table) |
f3898ea1 EH |
340 | size = amdgpu_dpm_get_pp_table(adev, &table); |
341 | else | |
342 | return 0; | |
343 | ||
344 | if (size >= PAGE_SIZE) | |
345 | size = PAGE_SIZE - 1; | |
346 | ||
1684d3ba | 347 | memcpy(buf, table, size); |
f3898ea1 EH |
348 | |
349 | return size; | |
350 | } | |
351 | ||
352 | static ssize_t amdgpu_set_pp_table(struct device *dev, | |
353 | struct device_attribute *attr, | |
354 | const char *buf, | |
355 | size_t count) | |
356 | { | |
357 | struct drm_device *ddev = dev_get_drvdata(dev); | |
358 | struct amdgpu_device *adev = ddev->dev_private; | |
359 | ||
cd4d7464 | 360 | if (adev->powerplay.pp_funcs->set_pp_table) |
f3898ea1 EH |
361 | amdgpu_dpm_set_pp_table(adev, buf, count); |
362 | ||
363 | return count; | |
364 | } | |
365 | ||
366 | static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, | |
367 | struct device_attribute *attr, | |
368 | char *buf) | |
369 | { | |
370 | struct drm_device *ddev = dev_get_drvdata(dev); | |
371 | struct amdgpu_device *adev = ddev->dev_private; | |
f3898ea1 | 372 | |
cd4d7464 RZ |
373 | if (adev->powerplay.pp_funcs->print_clock_levels) |
374 | return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf); | |
375 | else | |
376 | return snprintf(buf, PAGE_SIZE, "\n"); | |
f3898ea1 EH |
377 | } |
378 | ||
379 | static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, | |
380 | struct device_attribute *attr, | |
381 | const char *buf, | |
382 | size_t count) | |
383 | { | |
384 | struct drm_device *ddev = dev_get_drvdata(dev); | |
385 | struct amdgpu_device *adev = ddev->dev_private; | |
386 | int ret; | |
387 | long level; | |
5632708f EH |
388 | uint32_t i, mask = 0; |
389 | char sub_str[2]; | |
f3898ea1 | 390 | |
14b33074 EH |
391 | for (i = 0; i < strlen(buf); i++) { |
392 | if (*(buf + i) == '\n') | |
393 | continue; | |
5632708f EH |
394 | sub_str[0] = *(buf + i); |
395 | sub_str[1] = '\0'; | |
396 | ret = kstrtol(sub_str, 0, &level); | |
f3898ea1 | 397 | |
5632708f EH |
398 | if (ret) { |
399 | count = -EINVAL; | |
400 | goto fail; | |
401 | } | |
402 | mask |= 1 << level; | |
f3898ea1 EH |
403 | } |
404 | ||
cd4d7464 | 405 | if (adev->powerplay.pp_funcs->force_clock_level) |
5632708f | 406 | amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); |
cd4d7464 | 407 | |
f3898ea1 EH |
408 | fail: |
409 | return count; | |
410 | } | |
411 | ||
412 | static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, | |
413 | struct device_attribute *attr, | |
414 | char *buf) | |
415 | { | |
416 | struct drm_device *ddev = dev_get_drvdata(dev); | |
417 | struct amdgpu_device *adev = ddev->dev_private; | |
f3898ea1 | 418 | |
cd4d7464 RZ |
419 | if (adev->powerplay.pp_funcs->print_clock_levels) |
420 | return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf); | |
421 | else | |
422 | return snprintf(buf, PAGE_SIZE, "\n"); | |
f3898ea1 EH |
423 | } |
424 | ||
425 | static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, | |
426 | struct device_attribute *attr, | |
427 | const char *buf, | |
428 | size_t count) | |
429 | { | |
430 | struct drm_device *ddev = dev_get_drvdata(dev); | |
431 | struct amdgpu_device *adev = ddev->dev_private; | |
432 | int ret; | |
433 | long level; | |
5632708f EH |
434 | uint32_t i, mask = 0; |
435 | char sub_str[2]; | |
f3898ea1 | 436 | |
14b33074 EH |
437 | for (i = 0; i < strlen(buf); i++) { |
438 | if (*(buf + i) == '\n') | |
439 | continue; | |
5632708f EH |
440 | sub_str[0] = *(buf + i); |
441 | sub_str[1] = '\0'; | |
442 | ret = kstrtol(sub_str, 0, &level); | |
f3898ea1 | 443 | |
5632708f EH |
444 | if (ret) { |
445 | count = -EINVAL; | |
446 | goto fail; | |
447 | } | |
448 | mask |= 1 << level; | |
f3898ea1 | 449 | } |
cd4d7464 | 450 | if (adev->powerplay.pp_funcs->force_clock_level) |
5632708f | 451 | amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask); |
cd4d7464 | 452 | |
f3898ea1 EH |
453 | fail: |
454 | return count; | |
455 | } | |
456 | ||
457 | static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, | |
458 | struct device_attribute *attr, | |
459 | char *buf) | |
460 | { | |
461 | struct drm_device *ddev = dev_get_drvdata(dev); | |
462 | struct amdgpu_device *adev = ddev->dev_private; | |
f3898ea1 | 463 | |
cd4d7464 RZ |
464 | if (adev->powerplay.pp_funcs->print_clock_levels) |
465 | return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf); | |
466 | else | |
467 | return snprintf(buf, PAGE_SIZE, "\n"); | |
f3898ea1 EH |
468 | } |
469 | ||
470 | static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, | |
471 | struct device_attribute *attr, | |
472 | const char *buf, | |
473 | size_t count) | |
474 | { | |
475 | struct drm_device *ddev = dev_get_drvdata(dev); | |
476 | struct amdgpu_device *adev = ddev->dev_private; | |
477 | int ret; | |
478 | long level; | |
5632708f EH |
479 | uint32_t i, mask = 0; |
480 | char sub_str[2]; | |
f3898ea1 | 481 | |
14b33074 EH |
482 | for (i = 0; i < strlen(buf); i++) { |
483 | if (*(buf + i) == '\n') | |
484 | continue; | |
5632708f EH |
485 | sub_str[0] = *(buf + i); |
486 | sub_str[1] = '\0'; | |
487 | ret = kstrtol(sub_str, 0, &level); | |
f3898ea1 | 488 | |
5632708f EH |
489 | if (ret) { |
490 | count = -EINVAL; | |
491 | goto fail; | |
492 | } | |
493 | mask |= 1 << level; | |
f3898ea1 | 494 | } |
cd4d7464 | 495 | if (adev->powerplay.pp_funcs->force_clock_level) |
5632708f | 496 | amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask); |
cd4d7464 | 497 | |
f3898ea1 EH |
498 | fail: |
499 | return count; | |
500 | } | |
501 | ||
428bafa8 EH |
502 | static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, |
503 | struct device_attribute *attr, | |
504 | char *buf) | |
505 | { | |
506 | struct drm_device *ddev = dev_get_drvdata(dev); | |
507 | struct amdgpu_device *adev = ddev->dev_private; | |
508 | uint32_t value = 0; | |
509 | ||
cd4d7464 | 510 | if (adev->powerplay.pp_funcs->get_sclk_od) |
428bafa8 EH |
511 | value = amdgpu_dpm_get_sclk_od(adev); |
512 | ||
513 | return snprintf(buf, PAGE_SIZE, "%d\n", value); | |
514 | } | |
515 | ||
516 | static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, | |
517 | struct device_attribute *attr, | |
518 | const char *buf, | |
519 | size_t count) | |
520 | { | |
521 | struct drm_device *ddev = dev_get_drvdata(dev); | |
522 | struct amdgpu_device *adev = ddev->dev_private; | |
523 | int ret; | |
524 | long int value; | |
525 | ||
526 | ret = kstrtol(buf, 0, &value); | |
527 | ||
528 | if (ret) { | |
529 | count = -EINVAL; | |
530 | goto fail; | |
531 | } | |
cd4d7464 RZ |
532 | if (adev->powerplay.pp_funcs->set_sclk_od) |
533 | amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); | |
428bafa8 | 534 | |
6d07fe7b | 535 | if (adev->powerplay.pp_funcs->dispatch_tasks) { |
df1e6394 | 536 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL); |
cd4d7464 | 537 | } else { |
8b2e574d EH |
538 | adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; |
539 | amdgpu_pm_compute_clocks(adev); | |
540 | } | |
428bafa8 EH |
541 | |
542 | fail: | |
543 | return count; | |
544 | } | |
545 | ||
f2bdc05f EH |
546 | static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, |
547 | struct device_attribute *attr, | |
548 | char *buf) | |
549 | { | |
550 | struct drm_device *ddev = dev_get_drvdata(dev); | |
551 | struct amdgpu_device *adev = ddev->dev_private; | |
552 | uint32_t value = 0; | |
553 | ||
cd4d7464 | 554 | if (adev->powerplay.pp_funcs->get_mclk_od) |
f2bdc05f | 555 | value = amdgpu_dpm_get_mclk_od(adev); |
f2bdc05f EH |
556 | |
557 | return snprintf(buf, PAGE_SIZE, "%d\n", value); | |
558 | } | |
559 | ||
560 | static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, | |
561 | struct device_attribute *attr, | |
562 | const char *buf, | |
563 | size_t count) | |
564 | { | |
565 | struct drm_device *ddev = dev_get_drvdata(dev); | |
566 | struct amdgpu_device *adev = ddev->dev_private; | |
567 | int ret; | |
568 | long int value; | |
569 | ||
570 | ret = kstrtol(buf, 0, &value); | |
571 | ||
572 | if (ret) { | |
573 | count = -EINVAL; | |
574 | goto fail; | |
575 | } | |
cd4d7464 RZ |
576 | if (adev->powerplay.pp_funcs->set_mclk_od) |
577 | amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); | |
f2bdc05f | 578 | |
6d07fe7b | 579 | if (adev->powerplay.pp_funcs->dispatch_tasks) { |
df1e6394 | 580 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL); |
cd4d7464 | 581 | } else { |
f2bdc05f EH |
582 | adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; |
583 | amdgpu_pm_compute_clocks(adev); | |
584 | } | |
585 | ||
586 | fail: | |
587 | return count; | |
588 | } | |
589 | ||
34bb2734 EH |
590 | static ssize_t amdgpu_get_pp_power_profile(struct device *dev, |
591 | char *buf, struct amd_pp_profile *query) | |
592 | { | |
593 | struct drm_device *ddev = dev_get_drvdata(dev); | |
594 | struct amdgpu_device *adev = ddev->dev_private; | |
cd4d7464 | 595 | int ret = 0xff; |
34bb2734 | 596 | |
cd4d7464 | 597 | if (adev->powerplay.pp_funcs->get_power_profile_state) |
34bb2734 EH |
598 | ret = amdgpu_dpm_get_power_profile_state( |
599 | adev, query); | |
34bb2734 EH |
600 | |
601 | if (ret) | |
602 | return ret; | |
603 | ||
604 | return snprintf(buf, PAGE_SIZE, | |
605 | "%d %d %d %d %d\n", | |
606 | query->min_sclk / 100, | |
607 | query->min_mclk / 100, | |
608 | query->activity_threshold, | |
609 | query->up_hyst, | |
610 | query->down_hyst); | |
611 | } | |
612 | ||
613 | static ssize_t amdgpu_get_pp_gfx_power_profile(struct device *dev, | |
614 | struct device_attribute *attr, | |
615 | char *buf) | |
616 | { | |
617 | struct amd_pp_profile query = {0}; | |
618 | ||
619 | query.type = AMD_PP_GFX_PROFILE; | |
620 | ||
621 | return amdgpu_get_pp_power_profile(dev, buf, &query); | |
622 | } | |
623 | ||
624 | static ssize_t amdgpu_get_pp_compute_power_profile(struct device *dev, | |
625 | struct device_attribute *attr, | |
626 | char *buf) | |
627 | { | |
628 | struct amd_pp_profile query = {0}; | |
629 | ||
630 | query.type = AMD_PP_COMPUTE_PROFILE; | |
631 | ||
632 | return amdgpu_get_pp_power_profile(dev, buf, &query); | |
633 | } | |
634 | ||
635 | static ssize_t amdgpu_set_pp_power_profile(struct device *dev, | |
636 | const char *buf, | |
637 | size_t count, | |
638 | struct amd_pp_profile *request) | |
639 | { | |
640 | struct drm_device *ddev = dev_get_drvdata(dev); | |
641 | struct amdgpu_device *adev = ddev->dev_private; | |
642 | uint32_t loop = 0; | |
643 | char *sub_str, buf_cpy[128], *tmp_str; | |
644 | const char delimiter[3] = {' ', '\n', '\0'}; | |
645 | long int value; | |
cd4d7464 | 646 | int ret = 0xff; |
34bb2734 EH |
647 | |
648 | if (strncmp("reset", buf, strlen("reset")) == 0) { | |
cd4d7464 | 649 | if (adev->powerplay.pp_funcs->reset_power_profile_state) |
34bb2734 EH |
650 | ret = amdgpu_dpm_reset_power_profile_state( |
651 | adev, request); | |
34bb2734 EH |
652 | if (ret) { |
653 | count = -EINVAL; | |
654 | goto fail; | |
655 | } | |
656 | return count; | |
657 | } | |
658 | ||
659 | if (strncmp("set", buf, strlen("set")) == 0) { | |
cd4d7464 | 660 | if (adev->powerplay.pp_funcs->set_power_profile_state) |
34bb2734 EH |
661 | ret = amdgpu_dpm_set_power_profile_state( |
662 | adev, request); | |
cd4d7464 | 663 | |
34bb2734 EH |
664 | if (ret) { |
665 | count = -EINVAL; | |
666 | goto fail; | |
667 | } | |
668 | return count; | |
669 | } | |
670 | ||
671 | if (count + 1 >= 128) { | |
672 | count = -EINVAL; | |
673 | goto fail; | |
674 | } | |
675 | ||
676 | memcpy(buf_cpy, buf, count + 1); | |
677 | tmp_str = buf_cpy; | |
678 | ||
679 | while (tmp_str[0]) { | |
680 | sub_str = strsep(&tmp_str, delimiter); | |
681 | ret = kstrtol(sub_str, 0, &value); | |
682 | if (ret) { | |
683 | count = -EINVAL; | |
684 | goto fail; | |
685 | } | |
686 | ||
687 | switch (loop) { | |
688 | case 0: | |
689 | /* input unit MHz convert to dpm table unit 10KHz*/ | |
690 | request->min_sclk = (uint32_t)value * 100; | |
691 | break; | |
692 | case 1: | |
693 | /* input unit MHz convert to dpm table unit 10KHz*/ | |
694 | request->min_mclk = (uint32_t)value * 100; | |
695 | break; | |
696 | case 2: | |
697 | request->activity_threshold = (uint16_t)value; | |
698 | break; | |
699 | case 3: | |
700 | request->up_hyst = (uint8_t)value; | |
701 | break; | |
702 | case 4: | |
703 | request->down_hyst = (uint8_t)value; | |
704 | break; | |
705 | default: | |
706 | break; | |
707 | } | |
708 | ||
709 | loop++; | |
710 | } | |
cd4d7464 RZ |
711 | if (adev->powerplay.pp_funcs->set_power_profile_state) |
712 | ret = amdgpu_dpm_set_power_profile_state(adev, request); | |
34bb2734 EH |
713 | |
714 | if (ret) | |
715 | count = -EINVAL; | |
716 | ||
717 | fail: | |
718 | return count; | |
719 | } | |
720 | ||
721 | static ssize_t amdgpu_set_pp_gfx_power_profile(struct device *dev, | |
722 | struct device_attribute *attr, | |
723 | const char *buf, | |
724 | size_t count) | |
725 | { | |
726 | struct amd_pp_profile request = {0}; | |
727 | ||
728 | request.type = AMD_PP_GFX_PROFILE; | |
729 | ||
730 | return amdgpu_set_pp_power_profile(dev, buf, count, &request); | |
731 | } | |
732 | ||
733 | static ssize_t amdgpu_set_pp_compute_power_profile(struct device *dev, | |
734 | struct device_attribute *attr, | |
735 | const char *buf, | |
736 | size_t count) | |
737 | { | |
738 | struct amd_pp_profile request = {0}; | |
739 | ||
740 | request.type = AMD_PP_COMPUTE_PROFILE; | |
741 | ||
742 | return amdgpu_set_pp_power_profile(dev, buf, count, &request); | |
743 | } | |
744 | ||
d38ceaf9 AD |
745 | static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state); |
746 | static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, | |
747 | amdgpu_get_dpm_forced_performance_level, | |
748 | amdgpu_set_dpm_forced_performance_level); | |
f3898ea1 EH |
749 | static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL); |
750 | static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL); | |
751 | static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR, | |
752 | amdgpu_get_pp_force_state, | |
753 | amdgpu_set_pp_force_state); | |
754 | static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR, | |
755 | amdgpu_get_pp_table, | |
756 | amdgpu_set_pp_table); | |
757 | static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR, | |
758 | amdgpu_get_pp_dpm_sclk, | |
759 | amdgpu_set_pp_dpm_sclk); | |
760 | static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR, | |
761 | amdgpu_get_pp_dpm_mclk, | |
762 | amdgpu_set_pp_dpm_mclk); | |
763 | static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR, | |
764 | amdgpu_get_pp_dpm_pcie, | |
765 | amdgpu_set_pp_dpm_pcie); | |
428bafa8 EH |
766 | static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR, |
767 | amdgpu_get_pp_sclk_od, | |
768 | amdgpu_set_pp_sclk_od); | |
f2bdc05f EH |
769 | static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR, |
770 | amdgpu_get_pp_mclk_od, | |
771 | amdgpu_set_pp_mclk_od); | |
34bb2734 EH |
772 | static DEVICE_ATTR(pp_gfx_power_profile, S_IRUGO | S_IWUSR, |
773 | amdgpu_get_pp_gfx_power_profile, | |
774 | amdgpu_set_pp_gfx_power_profile); | |
775 | static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR, | |
776 | amdgpu_get_pp_compute_power_profile, | |
777 | amdgpu_set_pp_compute_power_profile); | |
d38ceaf9 AD |
778 | |
779 | static ssize_t amdgpu_hwmon_show_temp(struct device *dev, | |
780 | struct device_attribute *attr, | |
781 | char *buf) | |
782 | { | |
783 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
0c67df48 | 784 | struct drm_device *ddev = adev->ddev; |
d38ceaf9 AD |
785 | int temp; |
786 | ||
0c67df48 AD |
787 | /* Can't get temperature when the card is off */ |
788 | if ((adev->flags & AMD_IS_PX) && | |
789 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) | |
790 | return -EINVAL; | |
791 | ||
cd4d7464 | 792 | if (!adev->powerplay.pp_funcs->get_temperature) |
d38ceaf9 | 793 | temp = 0; |
8804b8d5 RZ |
794 | else |
795 | temp = amdgpu_dpm_get_temperature(adev); | |
d38ceaf9 AD |
796 | |
797 | return snprintf(buf, PAGE_SIZE, "%d\n", temp); | |
798 | } | |
799 | ||
800 | static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, | |
801 | struct device_attribute *attr, | |
802 | char *buf) | |
803 | { | |
804 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
805 | int hyst = to_sensor_dev_attr(attr)->index; | |
806 | int temp; | |
807 | ||
808 | if (hyst) | |
809 | temp = adev->pm.dpm.thermal.min_temp; | |
810 | else | |
811 | temp = adev->pm.dpm.thermal.max_temp; | |
812 | ||
813 | return snprintf(buf, PAGE_SIZE, "%d\n", temp); | |
814 | } | |
815 | ||
816 | static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, | |
817 | struct device_attribute *attr, | |
818 | char *buf) | |
819 | { | |
820 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
821 | u32 pwm_mode = 0; | |
822 | ||
cd4d7464 | 823 | if (!adev->powerplay.pp_funcs->get_fan_control_mode) |
8804b8d5 RZ |
824 | return -EINVAL; |
825 | ||
826 | pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); | |
d38ceaf9 | 827 | |
aad22ca4 | 828 | return sprintf(buf, "%i\n", pwm_mode); |
d38ceaf9 AD |
829 | } |
830 | ||
831 | static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, | |
832 | struct device_attribute *attr, | |
833 | const char *buf, | |
834 | size_t count) | |
835 | { | |
836 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
837 | int err; | |
838 | int value; | |
839 | ||
cd4d7464 | 840 | if (!adev->powerplay.pp_funcs->set_fan_control_mode) |
d38ceaf9 AD |
841 | return -EINVAL; |
842 | ||
843 | err = kstrtoint(buf, 10, &value); | |
844 | if (err) | |
845 | return err; | |
846 | ||
aad22ca4 | 847 | amdgpu_dpm_set_fan_control_mode(adev, value); |
d38ceaf9 AD |
848 | |
849 | return count; | |
850 | } | |
851 | ||
852 | static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, | |
853 | struct device_attribute *attr, | |
854 | char *buf) | |
855 | { | |
856 | return sprintf(buf, "%i\n", 0); | |
857 | } | |
858 | ||
859 | static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, | |
860 | struct device_attribute *attr, | |
861 | char *buf) | |
862 | { | |
863 | return sprintf(buf, "%i\n", 255); | |
864 | } | |
865 | ||
866 | static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, | |
867 | struct device_attribute *attr, | |
868 | const char *buf, size_t count) | |
869 | { | |
870 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
871 | int err; | |
872 | u32 value; | |
873 | ||
874 | err = kstrtou32(buf, 10, &value); | |
875 | if (err) | |
876 | return err; | |
877 | ||
878 | value = (value * 100) / 255; | |
879 | ||
cd4d7464 RZ |
880 | if (adev->powerplay.pp_funcs->set_fan_speed_percent) { |
881 | err = amdgpu_dpm_set_fan_speed_percent(adev, value); | |
882 | if (err) | |
883 | return err; | |
884 | } | |
d38ceaf9 AD |
885 | |
886 | return count; | |
887 | } | |
888 | ||
889 | static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, | |
890 | struct device_attribute *attr, | |
891 | char *buf) | |
892 | { | |
893 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
894 | int err; | |
cd4d7464 | 895 | u32 speed = 0; |
d38ceaf9 | 896 | |
cd4d7464 RZ |
897 | if (adev->powerplay.pp_funcs->get_fan_speed_percent) { |
898 | err = amdgpu_dpm_get_fan_speed_percent(adev, &speed); | |
899 | if (err) | |
900 | return err; | |
901 | } | |
d38ceaf9 AD |
902 | |
903 | speed = (speed * 255) / 100; | |
904 | ||
905 | return sprintf(buf, "%i\n", speed); | |
906 | } | |
907 | ||
81c1514b GI |
908 | static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, |
909 | struct device_attribute *attr, | |
910 | char *buf) | |
911 | { | |
912 | struct amdgpu_device *adev = dev_get_drvdata(dev); | |
913 | int err; | |
cd4d7464 | 914 | u32 speed = 0; |
81c1514b | 915 | |
cd4d7464 RZ |
916 | if (adev->powerplay.pp_funcs->get_fan_speed_rpm) { |
917 | err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); | |
918 | if (err) | |
919 | return err; | |
920 | } | |
81c1514b GI |
921 | |
922 | return sprintf(buf, "%i\n", speed); | |
923 | } | |
924 | ||
d38ceaf9 AD |
925 | static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); |
926 | static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); | |
927 | static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); | |
928 | static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); | |
929 | static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); | |
930 | static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); | |
931 | static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); | |
81c1514b | 932 | static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); |
d38ceaf9 AD |
933 | |
934 | static struct attribute *hwmon_attributes[] = { | |
935 | &sensor_dev_attr_temp1_input.dev_attr.attr, | |
936 | &sensor_dev_attr_temp1_crit.dev_attr.attr, | |
937 | &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, | |
938 | &sensor_dev_attr_pwm1.dev_attr.attr, | |
939 | &sensor_dev_attr_pwm1_enable.dev_attr.attr, | |
940 | &sensor_dev_attr_pwm1_min.dev_attr.attr, | |
941 | &sensor_dev_attr_pwm1_max.dev_attr.attr, | |
81c1514b | 942 | &sensor_dev_attr_fan1_input.dev_attr.attr, |
d38ceaf9 AD |
943 | NULL |
944 | }; | |
945 | ||
946 | static umode_t hwmon_attributes_visible(struct kobject *kobj, | |
947 | struct attribute *attr, int index) | |
948 | { | |
cc29ec87 | 949 | struct device *dev = kobj_to_dev(kobj); |
d38ceaf9 AD |
950 | struct amdgpu_device *adev = dev_get_drvdata(dev); |
951 | umode_t effective_mode = attr->mode; | |
952 | ||
135f9711 AD |
953 | /* no skipping for powerplay */ |
954 | if (adev->powerplay.cgs_device) | |
955 | return effective_mode; | |
956 | ||
1b5708ff | 957 | /* Skip limit attributes if DPM is not enabled */ |
d38ceaf9 AD |
958 | if (!adev->pm.dpm_enabled && |
959 | (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || | |
27100735 AD |
960 | attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || |
961 | attr == &sensor_dev_attr_pwm1.dev_attr.attr || | |
962 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || | |
963 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || | |
964 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) | |
d38ceaf9 AD |
965 | return 0; |
966 | ||
967 | /* Skip fan attributes if fan is not present */ | |
968 | if (adev->pm.no_fan && | |
969 | (attr == &sensor_dev_attr_pwm1.dev_attr.attr || | |
970 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || | |
971 | attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || | |
972 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) | |
973 | return 0; | |
974 | ||
975 | /* mask fan attributes if we have no bindings for this asic to expose */ | |
cd4d7464 | 976 | if ((!adev->powerplay.pp_funcs->get_fan_speed_percent && |
d38ceaf9 | 977 | attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ |
cd4d7464 | 978 | (!adev->powerplay.pp_funcs->get_fan_control_mode && |
d38ceaf9 AD |
979 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ |
980 | effective_mode &= ~S_IRUGO; | |
981 | ||
cd4d7464 | 982 | if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && |
d38ceaf9 | 983 | attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ |
cd4d7464 | 984 | (!adev->powerplay.pp_funcs->set_fan_control_mode && |
d38ceaf9 AD |
985 | attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ |
986 | effective_mode &= ~S_IWUSR; | |
987 | ||
988 | /* hide max/min values if we can't both query and manage the fan */ | |
cd4d7464 RZ |
989 | if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && |
990 | !adev->powerplay.pp_funcs->get_fan_speed_percent) && | |
d38ceaf9 AD |
991 | (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || |
992 | attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) | |
993 | return 0; | |
994 | ||
81c1514b GI |
995 | /* requires powerplay */ |
996 | if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr) | |
997 | return 0; | |
998 | ||
d38ceaf9 AD |
999 | return effective_mode; |
1000 | } | |
1001 | ||
1002 | static const struct attribute_group hwmon_attrgroup = { | |
1003 | .attrs = hwmon_attributes, | |
1004 | .is_visible = hwmon_attributes_visible, | |
1005 | }; | |
1006 | ||
1007 | static const struct attribute_group *hwmon_groups[] = { | |
1008 | &hwmon_attrgroup, | |
1009 | NULL | |
1010 | }; | |
1011 | ||
1012 | void amdgpu_dpm_thermal_work_handler(struct work_struct *work) | |
1013 | { | |
1014 | struct amdgpu_device *adev = | |
1015 | container_of(work, struct amdgpu_device, | |
1016 | pm.dpm.thermal.work); | |
1017 | /* switch to the thermal state */ | |
3a2c788d | 1018 | enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; |
d38ceaf9 AD |
1019 | |
1020 | if (!adev->pm.dpm_enabled) | |
1021 | return; | |
1022 | ||
cd4d7464 | 1023 | if (adev->powerplay.pp_funcs->get_temperature) { |
d38ceaf9 AD |
1024 | int temp = amdgpu_dpm_get_temperature(adev); |
1025 | ||
1026 | if (temp < adev->pm.dpm.thermal.min_temp) | |
1027 | /* switch back the user state */ | |
1028 | dpm_state = adev->pm.dpm.user_state; | |
1029 | } else { | |
1030 | if (adev->pm.dpm.thermal.high_to_low) | |
1031 | /* switch back the user state */ | |
1032 | dpm_state = adev->pm.dpm.user_state; | |
1033 | } | |
1034 | mutex_lock(&adev->pm.mutex); | |
1035 | if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) | |
1036 | adev->pm.dpm.thermal_active = true; | |
1037 | else | |
1038 | adev->pm.dpm.thermal_active = false; | |
1039 | adev->pm.dpm.state = dpm_state; | |
1040 | mutex_unlock(&adev->pm.mutex); | |
1041 | ||
1042 | amdgpu_pm_compute_clocks(adev); | |
1043 | } | |
1044 | ||
1045 | static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev, | |
3a2c788d | 1046 | enum amd_pm_state_type dpm_state) |
d38ceaf9 AD |
1047 | { |
1048 | int i; | |
1049 | struct amdgpu_ps *ps; | |
1050 | u32 ui_class; | |
1051 | bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? | |
1052 | true : false; | |
1053 | ||
1054 | /* check if the vblank period is too short to adjust the mclk */ | |
cd4d7464 | 1055 | if (single_display && adev->powerplay.pp_funcs->vblank_too_short) { |
d38ceaf9 AD |
1056 | if (amdgpu_dpm_vblank_too_short(adev)) |
1057 | single_display = false; | |
1058 | } | |
1059 | ||
1060 | /* certain older asics have a separare 3D performance state, | |
1061 | * so try that first if the user selected performance | |
1062 | */ | |
1063 | if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) | |
1064 | dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; | |
1065 | /* balanced states don't exist at the moment */ | |
1066 | if (dpm_state == POWER_STATE_TYPE_BALANCED) | |
1067 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; | |
1068 | ||
1069 | restart_search: | |
1070 | /* Pick the best power state based on current conditions */ | |
1071 | for (i = 0; i < adev->pm.dpm.num_ps; i++) { | |
1072 | ps = &adev->pm.dpm.ps[i]; | |
1073 | ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; | |
1074 | switch (dpm_state) { | |
1075 | /* user states */ | |
1076 | case POWER_STATE_TYPE_BATTERY: | |
1077 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { | |
1078 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { | |
1079 | if (single_display) | |
1080 | return ps; | |
1081 | } else | |
1082 | return ps; | |
1083 | } | |
1084 | break; | |
1085 | case POWER_STATE_TYPE_BALANCED: | |
1086 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { | |
1087 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { | |
1088 | if (single_display) | |
1089 | return ps; | |
1090 | } else | |
1091 | return ps; | |
1092 | } | |
1093 | break; | |
1094 | case POWER_STATE_TYPE_PERFORMANCE: | |
1095 | if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { | |
1096 | if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { | |
1097 | if (single_display) | |
1098 | return ps; | |
1099 | } else | |
1100 | return ps; | |
1101 | } | |
1102 | break; | |
1103 | /* internal states */ | |
1104 | case POWER_STATE_TYPE_INTERNAL_UVD: | |
1105 | if (adev->pm.dpm.uvd_ps) | |
1106 | return adev->pm.dpm.uvd_ps; | |
1107 | else | |
1108 | break; | |
1109 | case POWER_STATE_TYPE_INTERNAL_UVD_SD: | |
1110 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) | |
1111 | return ps; | |
1112 | break; | |
1113 | case POWER_STATE_TYPE_INTERNAL_UVD_HD: | |
1114 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) | |
1115 | return ps; | |
1116 | break; | |
1117 | case POWER_STATE_TYPE_INTERNAL_UVD_HD2: | |
1118 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) | |
1119 | return ps; | |
1120 | break; | |
1121 | case POWER_STATE_TYPE_INTERNAL_UVD_MVC: | |
1122 | if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) | |
1123 | return ps; | |
1124 | break; | |
1125 | case POWER_STATE_TYPE_INTERNAL_BOOT: | |
1126 | return adev->pm.dpm.boot_ps; | |
1127 | case POWER_STATE_TYPE_INTERNAL_THERMAL: | |
1128 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) | |
1129 | return ps; | |
1130 | break; | |
1131 | case POWER_STATE_TYPE_INTERNAL_ACPI: | |
1132 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) | |
1133 | return ps; | |
1134 | break; | |
1135 | case POWER_STATE_TYPE_INTERNAL_ULV: | |
1136 | if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) | |
1137 | return ps; | |
1138 | break; | |
1139 | case POWER_STATE_TYPE_INTERNAL_3DPERF: | |
1140 | if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) | |
1141 | return ps; | |
1142 | break; | |
1143 | default: | |
1144 | break; | |
1145 | } | |
1146 | } | |
1147 | /* use a fallback state if we didn't match */ | |
1148 | switch (dpm_state) { | |
1149 | case POWER_STATE_TYPE_INTERNAL_UVD_SD: | |
1150 | dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; | |
1151 | goto restart_search; | |
1152 | case POWER_STATE_TYPE_INTERNAL_UVD_HD: | |
1153 | case POWER_STATE_TYPE_INTERNAL_UVD_HD2: | |
1154 | case POWER_STATE_TYPE_INTERNAL_UVD_MVC: | |
1155 | if (adev->pm.dpm.uvd_ps) { | |
1156 | return adev->pm.dpm.uvd_ps; | |
1157 | } else { | |
1158 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; | |
1159 | goto restart_search; | |
1160 | } | |
1161 | case POWER_STATE_TYPE_INTERNAL_THERMAL: | |
1162 | dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; | |
1163 | goto restart_search; | |
1164 | case POWER_STATE_TYPE_INTERNAL_ACPI: | |
1165 | dpm_state = POWER_STATE_TYPE_BATTERY; | |
1166 | goto restart_search; | |
1167 | case POWER_STATE_TYPE_BATTERY: | |
1168 | case POWER_STATE_TYPE_BALANCED: | |
1169 | case POWER_STATE_TYPE_INTERNAL_3DPERF: | |
1170 | dpm_state = POWER_STATE_TYPE_PERFORMANCE; | |
1171 | goto restart_search; | |
1172 | default: | |
1173 | break; | |
1174 | } | |
1175 | ||
1176 | return NULL; | |
1177 | } | |
1178 | ||
1179 | static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) | |
1180 | { | |
d38ceaf9 | 1181 | struct amdgpu_ps *ps; |
3a2c788d | 1182 | enum amd_pm_state_type dpm_state; |
d38ceaf9 | 1183 | int ret; |
cd4d7464 | 1184 | bool equal = false; |
d38ceaf9 AD |
1185 | |
1186 | /* if dpm init failed */ | |
1187 | if (!adev->pm.dpm_enabled) | |
1188 | return; | |
1189 | ||
1190 | if (adev->pm.dpm.user_state != adev->pm.dpm.state) { | |
1191 | /* add other state override checks here */ | |
1192 | if ((!adev->pm.dpm.thermal_active) && | |
1193 | (!adev->pm.dpm.uvd_active)) | |
1194 | adev->pm.dpm.state = adev->pm.dpm.user_state; | |
1195 | } | |
1196 | dpm_state = adev->pm.dpm.state; | |
1197 | ||
1198 | ps = amdgpu_dpm_pick_power_state(adev, dpm_state); | |
1199 | if (ps) | |
1200 | adev->pm.dpm.requested_ps = ps; | |
1201 | else | |
1202 | return; | |
1203 | ||
cd4d7464 | 1204 | if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) { |
d38ceaf9 AD |
1205 | printk("switching from power state:\n"); |
1206 | amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); | |
1207 | printk("switching to power state:\n"); | |
1208 | amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps); | |
1209 | } | |
1210 | ||
d38ceaf9 AD |
1211 | /* update whether vce is active */ |
1212 | ps->vce_active = adev->pm.dpm.vce_active; | |
cd4d7464 RZ |
1213 | if (adev->powerplay.pp_funcs->display_configuration_changed) |
1214 | amdgpu_dpm_display_configuration_changed(adev); | |
5e876c62 | 1215 | |
d38ceaf9 AD |
1216 | ret = amdgpu_dpm_pre_set_power_state(adev); |
1217 | if (ret) | |
a27de35c | 1218 | return; |
d38ceaf9 | 1219 | |
cd4d7464 RZ |
1220 | if (adev->powerplay.pp_funcs->check_state_equal) { |
1221 | if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal)) | |
1222 | equal = false; | |
1223 | } | |
d38ceaf9 | 1224 | |
5e876c62 RZ |
1225 | if (equal) |
1226 | return; | |
d38ceaf9 | 1227 | |
d38ceaf9 | 1228 | amdgpu_dpm_set_power_state(adev); |
d38ceaf9 AD |
1229 | amdgpu_dpm_post_set_power_state(adev); |
1230 | ||
eda1d1cf AD |
1231 | adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; |
1232 | adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; | |
1233 | ||
cd4d7464 | 1234 | if (adev->powerplay.pp_funcs->force_performance_level) { |
d38ceaf9 | 1235 | if (adev->pm.dpm.thermal_active) { |
e5d03ac2 | 1236 | enum amd_dpm_forced_level level = adev->pm.dpm.forced_level; |
d38ceaf9 | 1237 | /* force low perf level for thermal */ |
e5d03ac2 | 1238 | amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW); |
d38ceaf9 AD |
1239 | /* save the user's level */ |
1240 | adev->pm.dpm.forced_level = level; | |
1241 | } else { | |
1242 | /* otherwise, user selected level */ | |
1243 | amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level); | |
1244 | } | |
1245 | } | |
d38ceaf9 AD |
1246 | } |
1247 | ||
1248 | void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) | |
1249 | { | |
cd4d7464 | 1250 | if (adev->powerplay.pp_funcs->powergate_uvd) { |
e95a14a9 TSD |
1251 | /* enable/disable UVD */ |
1252 | mutex_lock(&adev->pm.mutex); | |
d38ceaf9 | 1253 | amdgpu_dpm_powergate_uvd(adev, !enable); |
e95a14a9 TSD |
1254 | mutex_unlock(&adev->pm.mutex); |
1255 | } else { | |
1256 | if (enable) { | |
d38ceaf9 | 1257 | mutex_lock(&adev->pm.mutex); |
e95a14a9 TSD |
1258 | adev->pm.dpm.uvd_active = true; |
1259 | adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; | |
d38ceaf9 AD |
1260 | mutex_unlock(&adev->pm.mutex); |
1261 | } else { | |
e95a14a9 TSD |
1262 | mutex_lock(&adev->pm.mutex); |
1263 | adev->pm.dpm.uvd_active = false; | |
1264 | mutex_unlock(&adev->pm.mutex); | |
d38ceaf9 | 1265 | } |
e95a14a9 | 1266 | amdgpu_pm_compute_clocks(adev); |
d38ceaf9 AD |
1267 | } |
1268 | } | |
1269 | ||
1270 | void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) | |
1271 | { | |
cd4d7464 | 1272 | if (adev->powerplay.pp_funcs->powergate_vce) { |
e95a14a9 TSD |
1273 | /* enable/disable VCE */ |
1274 | mutex_lock(&adev->pm.mutex); | |
b7a07769 | 1275 | amdgpu_dpm_powergate_vce(adev, !enable); |
e95a14a9 TSD |
1276 | mutex_unlock(&adev->pm.mutex); |
1277 | } else { | |
1278 | if (enable) { | |
b7a07769 | 1279 | mutex_lock(&adev->pm.mutex); |
e95a14a9 TSD |
1280 | adev->pm.dpm.vce_active = true; |
1281 | /* XXX select vce level based on ring/task */ | |
0d8de7ca | 1282 | adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; |
b7a07769 | 1283 | mutex_unlock(&adev->pm.mutex); |
beeea981 RZ |
1284 | amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, |
1285 | AMD_CG_STATE_UNGATE); | |
03a5f1df RZ |
1286 | amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, |
1287 | AMD_PG_STATE_UNGATE); | |
1288 | amdgpu_pm_compute_clocks(adev); | |
b7a07769 | 1289 | } else { |
beeea981 RZ |
1290 | amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, |
1291 | AMD_PG_STATE_GATE); | |
1292 | amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, | |
1293 | AMD_CG_STATE_GATE); | |
e95a14a9 TSD |
1294 | mutex_lock(&adev->pm.mutex); |
1295 | adev->pm.dpm.vce_active = false; | |
1296 | mutex_unlock(&adev->pm.mutex); | |
beeea981 | 1297 | amdgpu_pm_compute_clocks(adev); |
b7a07769 | 1298 | } |
beeea981 | 1299 | |
b7a07769 | 1300 | } |
d38ceaf9 AD |
1301 | } |
1302 | ||
1303 | void amdgpu_pm_print_power_states(struct amdgpu_device *adev) | |
1304 | { | |
1305 | int i; | |
1306 | ||
cd4d7464 | 1307 | if (adev->powerplay.pp_funcs->print_power_state == NULL) |
1b5708ff RZ |
1308 | return; |
1309 | ||
1310 | for (i = 0; i < adev->pm.dpm.num_ps; i++) | |
d38ceaf9 | 1311 | amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); |
1b5708ff | 1312 | |
d38ceaf9 AD |
1313 | } |
1314 | ||
1315 | int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) | |
1316 | { | |
1317 | int ret; | |
1318 | ||
c86f5ebf AD |
1319 | if (adev->pm.sysfs_initialized) |
1320 | return 0; | |
1321 | ||
d2f52ac8 RZ |
1322 | if (adev->pm.dpm_enabled == 0) |
1323 | return 0; | |
1324 | ||
cd4d7464 RZ |
1325 | if (adev->powerplay.pp_funcs->get_temperature == NULL) |
1326 | return 0; | |
1b5708ff | 1327 | |
d38ceaf9 AD |
1328 | adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, |
1329 | DRIVER_NAME, adev, | |
1330 | hwmon_groups); | |
1331 | if (IS_ERR(adev->pm.int_hwmon_dev)) { | |
1332 | ret = PTR_ERR(adev->pm.int_hwmon_dev); | |
1333 | dev_err(adev->dev, | |
1334 | "Unable to register hwmon device: %d\n", ret); | |
1335 | return ret; | |
1336 | } | |
1337 | ||
1338 | ret = device_create_file(adev->dev, &dev_attr_power_dpm_state); | |
1339 | if (ret) { | |
1340 | DRM_ERROR("failed to create device file for dpm state\n"); | |
1341 | return ret; | |
1342 | } | |
1343 | ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level); | |
1344 | if (ret) { | |
1345 | DRM_ERROR("failed to create device file for dpm state\n"); | |
1346 | return ret; | |
1347 | } | |
f3898ea1 | 1348 | |
6d07fe7b RZ |
1349 | |
1350 | ret = device_create_file(adev->dev, &dev_attr_pp_num_states); | |
1351 | if (ret) { | |
1352 | DRM_ERROR("failed to create device file pp_num_states\n"); | |
1353 | return ret; | |
1354 | } | |
1355 | ret = device_create_file(adev->dev, &dev_attr_pp_cur_state); | |
1356 | if (ret) { | |
1357 | DRM_ERROR("failed to create device file pp_cur_state\n"); | |
1358 | return ret; | |
1359 | } | |
1360 | ret = device_create_file(adev->dev, &dev_attr_pp_force_state); | |
1361 | if (ret) { | |
1362 | DRM_ERROR("failed to create device file pp_force_state\n"); | |
1363 | return ret; | |
1364 | } | |
1365 | ret = device_create_file(adev->dev, &dev_attr_pp_table); | |
1366 | if (ret) { | |
1367 | DRM_ERROR("failed to create device file pp_table\n"); | |
1368 | return ret; | |
f3898ea1 | 1369 | } |
c85e299f EH |
1370 | |
1371 | ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk); | |
1372 | if (ret) { | |
1373 | DRM_ERROR("failed to create device file pp_dpm_sclk\n"); | |
1374 | return ret; | |
1375 | } | |
1376 | ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk); | |
1377 | if (ret) { | |
1378 | DRM_ERROR("failed to create device file pp_dpm_mclk\n"); | |
1379 | return ret; | |
1380 | } | |
1381 | ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie); | |
1382 | if (ret) { | |
1383 | DRM_ERROR("failed to create device file pp_dpm_pcie\n"); | |
1384 | return ret; | |
1385 | } | |
8b2e574d EH |
1386 | ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od); |
1387 | if (ret) { | |
1388 | DRM_ERROR("failed to create device file pp_sclk_od\n"); | |
1389 | return ret; | |
1390 | } | |
f2bdc05f EH |
1391 | ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od); |
1392 | if (ret) { | |
1393 | DRM_ERROR("failed to create device file pp_mclk_od\n"); | |
1394 | return ret; | |
1395 | } | |
34bb2734 EH |
1396 | ret = device_create_file(adev->dev, |
1397 | &dev_attr_pp_gfx_power_profile); | |
1398 | if (ret) { | |
1399 | DRM_ERROR("failed to create device file " | |
1400 | "pp_gfx_power_profile\n"); | |
1401 | return ret; | |
1402 | } | |
1403 | ret = device_create_file(adev->dev, | |
1404 | &dev_attr_pp_compute_power_profile); | |
1405 | if (ret) { | |
1406 | DRM_ERROR("failed to create device file " | |
1407 | "pp_compute_power_profile\n"); | |
1408 | return ret; | |
1409 | } | |
c85e299f | 1410 | |
d38ceaf9 AD |
1411 | ret = amdgpu_debugfs_pm_init(adev); |
1412 | if (ret) { | |
1413 | DRM_ERROR("Failed to register debugfs file for dpm!\n"); | |
1414 | return ret; | |
1415 | } | |
1416 | ||
c86f5ebf AD |
1417 | adev->pm.sysfs_initialized = true; |
1418 | ||
d38ceaf9 AD |
1419 | return 0; |
1420 | } | |
1421 | ||
1422 | void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) | |
1423 | { | |
d2f52ac8 RZ |
1424 | if (adev->pm.dpm_enabled == 0) |
1425 | return; | |
1426 | ||
d38ceaf9 AD |
1427 | if (adev->pm.int_hwmon_dev) |
1428 | hwmon_device_unregister(adev->pm.int_hwmon_dev); | |
1429 | device_remove_file(adev->dev, &dev_attr_power_dpm_state); | |
1430 | device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level); | |
6d07fe7b RZ |
1431 | |
1432 | device_remove_file(adev->dev, &dev_attr_pp_num_states); | |
1433 | device_remove_file(adev->dev, &dev_attr_pp_cur_state); | |
1434 | device_remove_file(adev->dev, &dev_attr_pp_force_state); | |
1435 | device_remove_file(adev->dev, &dev_attr_pp_table); | |
1436 | ||
c85e299f EH |
1437 | device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk); |
1438 | device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk); | |
1439 | device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie); | |
8b2e574d | 1440 | device_remove_file(adev->dev, &dev_attr_pp_sclk_od); |
f2bdc05f | 1441 | device_remove_file(adev->dev, &dev_attr_pp_mclk_od); |
34bb2734 EH |
1442 | device_remove_file(adev->dev, |
1443 | &dev_attr_pp_gfx_power_profile); | |
1444 | device_remove_file(adev->dev, | |
1445 | &dev_attr_pp_compute_power_profile); | |
d38ceaf9 AD |
1446 | } |
1447 | ||
1448 | void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) | |
1449 | { | |
1450 | struct drm_device *ddev = adev->ddev; | |
1451 | struct drm_crtc *crtc; | |
1452 | struct amdgpu_crtc *amdgpu_crtc; | |
5e876c62 | 1453 | int i = 0; |
d38ceaf9 AD |
1454 | |
1455 | if (!adev->pm.dpm_enabled) | |
1456 | return; | |
1457 | ||
c10c8f7c AD |
1458 | if (adev->mode_info.num_crtc) |
1459 | amdgpu_display_bandwidth_update(adev); | |
1b5708ff | 1460 | |
5e876c62 RZ |
1461 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { |
1462 | struct amdgpu_ring *ring = adev->rings[i]; | |
1463 | if (ring && ring->ready) | |
1464 | amdgpu_fence_wait_empty(ring); | |
1465 | } | |
d38ceaf9 | 1466 | |
6d07fe7b | 1467 | if (adev->powerplay.pp_funcs->dispatch_tasks) { |
df1e6394 | 1468 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL, NULL); |
1b5708ff RZ |
1469 | } else { |
1470 | mutex_lock(&adev->pm.mutex); | |
1471 | adev->pm.dpm.new_active_crtcs = 0; | |
1472 | adev->pm.dpm.new_active_crtc_count = 0; | |
1473 | if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { | |
1474 | list_for_each_entry(crtc, | |
1475 | &ddev->mode_config.crtc_list, head) { | |
1476 | amdgpu_crtc = to_amdgpu_crtc(crtc); | |
4562236b | 1477 | if (amdgpu_crtc->enabled) { |
1b5708ff RZ |
1478 | adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); |
1479 | adev->pm.dpm.new_active_crtc_count++; | |
1480 | } | |
d38ceaf9 AD |
1481 | } |
1482 | } | |
1b5708ff RZ |
1483 | /* update battery/ac status */ |
1484 | if (power_supply_is_system_supplied() > 0) | |
1485 | adev->pm.dpm.ac_power = true; | |
1486 | else | |
1487 | adev->pm.dpm.ac_power = false; | |
d38ceaf9 | 1488 | |
1b5708ff | 1489 | amdgpu_dpm_change_power_state_locked(adev); |
d38ceaf9 | 1490 | |
1b5708ff RZ |
1491 | mutex_unlock(&adev->pm.mutex); |
1492 | } | |
d38ceaf9 AD |
1493 | } |
1494 | ||
1495 | /* | |
1496 | * Debugfs info | |
1497 | */ | |
1498 | #if defined(CONFIG_DEBUG_FS) | |
1499 | ||
3de4ec57 TSD |
1500 | static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) |
1501 | { | |
cd7b0c66 | 1502 | uint32_t value; |
4f9afc9b | 1503 | struct pp_gpu_power query = {0}; |
9f8df7d7 | 1504 | int size; |
3de4ec57 TSD |
1505 | |
1506 | /* sanity check PP is enabled */ | |
1507 | if (!(adev->powerplay.pp_funcs && | |
1508 | adev->powerplay.pp_funcs->read_sensor)) | |
1509 | return -EINVAL; | |
1510 | ||
1511 | /* GPU Clocks */ | |
9f8df7d7 | 1512 | size = sizeof(value); |
3de4ec57 | 1513 | seq_printf(m, "GFX Clocks and Power:\n"); |
9f8df7d7 | 1514 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) |
3de4ec57 | 1515 | seq_printf(m, "\t%u MHz (MCLK)\n", value/100); |
9f8df7d7 | 1516 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) |
3de4ec57 | 1517 | seq_printf(m, "\t%u MHz (SCLK)\n", value/100); |
9f8df7d7 | 1518 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) |
3de4ec57 | 1519 | seq_printf(m, "\t%u mV (VDDGFX)\n", value); |
9f8df7d7 | 1520 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) |
3de4ec57 | 1521 | seq_printf(m, "\t%u mV (VDDNB)\n", value); |
9f8df7d7 TSD |
1522 | size = sizeof(query); |
1523 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) { | |
4f9afc9b EH |
1524 | seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8, |
1525 | query.vddc_power & 0xff); | |
1526 | seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8, | |
1527 | query.vddci_power & 0xff); | |
1528 | seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8, | |
1529 | query.max_gpu_power & 0xff); | |
1530 | seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8, | |
1531 | query.average_gpu_power & 0xff); | |
1532 | } | |
9f8df7d7 | 1533 | size = sizeof(value); |
3de4ec57 TSD |
1534 | seq_printf(m, "\n"); |
1535 | ||
1536 | /* GPU Temp */ | |
9f8df7d7 | 1537 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) |
3de4ec57 TSD |
1538 | seq_printf(m, "GPU Temperature: %u C\n", value/1000); |
1539 | ||
1540 | /* GPU Load */ | |
9f8df7d7 | 1541 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) |
3de4ec57 TSD |
1542 | seq_printf(m, "GPU Load: %u %%\n", value); |
1543 | seq_printf(m, "\n"); | |
1544 | ||
1545 | /* UVD clocks */ | |
9f8df7d7 | 1546 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { |
3de4ec57 TSD |
1547 | if (!value) { |
1548 | seq_printf(m, "UVD: Disabled\n"); | |
1549 | } else { | |
1550 | seq_printf(m, "UVD: Enabled\n"); | |
9f8df7d7 | 1551 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) |
3de4ec57 | 1552 | seq_printf(m, "\t%u MHz (DCLK)\n", value/100); |
9f8df7d7 | 1553 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) |
3de4ec57 TSD |
1554 | seq_printf(m, "\t%u MHz (VCLK)\n", value/100); |
1555 | } | |
1556 | } | |
1557 | seq_printf(m, "\n"); | |
1558 | ||
1559 | /* VCE clocks */ | |
9f8df7d7 | 1560 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { |
3de4ec57 TSD |
1561 | if (!value) { |
1562 | seq_printf(m, "VCE: Disabled\n"); | |
1563 | } else { | |
1564 | seq_printf(m, "VCE: Enabled\n"); | |
9f8df7d7 | 1565 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) |
3de4ec57 TSD |
1566 | seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); |
1567 | } | |
1568 | } | |
1569 | ||
1570 | return 0; | |
1571 | } | |
1572 | ||
a8503b15 HR |
1573 | static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags) |
1574 | { | |
1575 | int i; | |
1576 | ||
1577 | for (i = 0; clocks[i].flag; i++) | |
1578 | seq_printf(m, "\t%s: %s\n", clocks[i].name, | |
1579 | (flags & clocks[i].flag) ? "On" : "Off"); | |
1580 | } | |
1581 | ||
d38ceaf9 AD |
1582 | static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) |
1583 | { | |
1584 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1585 | struct drm_device *dev = node->minor->dev; | |
1586 | struct amdgpu_device *adev = dev->dev_private; | |
0c67df48 | 1587 | struct drm_device *ddev = adev->ddev; |
6cb2d4e4 HR |
1588 | u32 flags = 0; |
1589 | ||
1590 | amdgpu_get_clockgating_state(adev, &flags); | |
1591 | seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags); | |
a8503b15 HR |
1592 | amdgpu_parse_cg_state(m, flags); |
1593 | seq_printf(m, "\n"); | |
d38ceaf9 | 1594 | |
1b5708ff RZ |
1595 | if (!adev->pm.dpm_enabled) { |
1596 | seq_printf(m, "dpm not enabled\n"); | |
1597 | return 0; | |
1598 | } | |
0c67df48 AD |
1599 | if ((adev->flags & AMD_IS_PX) && |
1600 | (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { | |
1601 | seq_printf(m, "PX asic powered off\n"); | |
6d07fe7b | 1602 | } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) { |
d38ceaf9 | 1603 | mutex_lock(&adev->pm.mutex); |
cd4d7464 RZ |
1604 | if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) |
1605 | adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m); | |
d38ceaf9 AD |
1606 | else |
1607 | seq_printf(m, "Debugfs support not implemented for this asic\n"); | |
1608 | mutex_unlock(&adev->pm.mutex); | |
6d07fe7b RZ |
1609 | } else { |
1610 | return amdgpu_debugfs_pm_info_pp(m, adev); | |
d38ceaf9 AD |
1611 | } |
1612 | ||
1613 | return 0; | |
1614 | } | |
1615 | ||
06ab6832 | 1616 | static const struct drm_info_list amdgpu_pm_info_list[] = { |
d38ceaf9 AD |
1617 | {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL}, |
1618 | }; | |
1619 | #endif | |
1620 | ||
1621 | static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev) | |
1622 | { | |
1623 | #if defined(CONFIG_DEBUG_FS) | |
1624 | return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list)); | |
1625 | #else | |
1626 | return 0; | |
1627 | #endif | |
1628 | } |