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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2012 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * based on nouveau_prime.c | |
23 | * | |
24 | * Authors: Alex Deucher | |
25 | */ | |
26 | #include <drm/drmP.h> | |
27 | ||
28 | #include "amdgpu.h" | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include <linux/dma-buf.h> | |
31 | ||
32 | struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj) | |
33 | { | |
34 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); | |
35 | int npages = bo->tbo.num_pages; | |
36 | ||
37 | return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages); | |
38 | } | |
39 | ||
40 | void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj) | |
41 | { | |
42 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); | |
43 | int ret; | |
44 | ||
45 | ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, | |
46 | &bo->dma_buf_vmap); | |
47 | if (ret) | |
48 | return ERR_PTR(ret); | |
49 | ||
50 | return bo->dma_buf_vmap.virtual; | |
51 | } | |
52 | ||
53 | void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr) | |
54 | { | |
55 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); | |
56 | ||
57 | ttm_bo_kunmap(&bo->dma_buf_vmap); | |
58 | } | |
59 | ||
dfced2e4 SL |
60 | int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) |
61 | { | |
62 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); | |
63 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); | |
64 | unsigned asize = amdgpu_bo_size(bo); | |
65 | int ret; | |
66 | ||
67 | if (!vma->vm_file) | |
68 | return -ENODEV; | |
69 | ||
70 | if (adev == NULL) | |
71 | return -ENODEV; | |
72 | ||
73 | /* Check for valid size. */ | |
74 | if (asize < vma->vm_end - vma->vm_start) | |
75 | return -EINVAL; | |
76 | ||
77 | if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || | |
78 | (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { | |
79 | return -EPERM; | |
80 | } | |
81 | vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT; | |
82 | ||
83 | /* prime mmap does not need to check access, so allow here */ | |
84 | ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data); | |
85 | if (ret) | |
86 | return ret; | |
87 | ||
88 | ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev); | |
89 | drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data); | |
90 | ||
91 | return ret; | |
92 | } | |
93 | ||
4d9c514d CK |
94 | struct drm_gem_object * |
95 | amdgpu_gem_prime_import_sg_table(struct drm_device *dev, | |
96 | struct dma_buf_attachment *attach, | |
97 | struct sg_table *sg) | |
d38ceaf9 | 98 | { |
72d7668b | 99 | struct reservation_object *resv = attach->dmabuf->resv; |
d38ceaf9 AD |
100 | struct amdgpu_device *adev = dev->dev_private; |
101 | struct amdgpu_bo *bo; | |
102 | int ret; | |
103 | ||
72d7668b | 104 | ww_mutex_lock(&resv->lock, NULL); |
d38ceaf9 | 105 | ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE, false, |
2046d46d | 106 | AMDGPU_GEM_DOMAIN_GTT, 0, sg, resv, 0, &bo); |
72d7668b | 107 | ww_mutex_unlock(&resv->lock); |
d38ceaf9 AD |
108 | if (ret) |
109 | return ERR_PTR(ret); | |
110 | ||
8e94a46c | 111 | bo->prime_shared_count = 1; |
d38ceaf9 AD |
112 | return &bo->gem_base; |
113 | } | |
114 | ||
115 | int amdgpu_gem_prime_pin(struct drm_gem_object *obj) | |
116 | { | |
117 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); | |
8e94a46c | 118 | long ret = 0; |
d38ceaf9 AD |
119 | |
120 | ret = amdgpu_bo_reserve(bo, false); | |
121 | if (unlikely(ret != 0)) | |
122 | return ret; | |
123 | ||
8e94a46c MK |
124 | /* |
125 | * Wait for all shared fences to complete before we switch to future | |
126 | * use of exclusive fence on this prime shared bo. | |
127 | */ | |
128 | ret = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false, | |
129 | MAX_SCHEDULE_TIMEOUT); | |
130 | if (unlikely(ret < 0)) { | |
131 | DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); | |
132 | amdgpu_bo_unreserve(bo); | |
133 | return ret; | |
134 | } | |
135 | ||
d38ceaf9 AD |
136 | /* pin buffer into GTT */ |
137 | ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL); | |
8e94a46c MK |
138 | if (likely(ret == 0)) |
139 | bo->prime_shared_count++; | |
140 | ||
d38ceaf9 AD |
141 | amdgpu_bo_unreserve(bo); |
142 | return ret; | |
143 | } | |
144 | ||
145 | void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) | |
146 | { | |
147 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); | |
148 | int ret = 0; | |
149 | ||
c81a1a74 | 150 | ret = amdgpu_bo_reserve(bo, true); |
d38ceaf9 AD |
151 | if (unlikely(ret != 0)) |
152 | return; | |
153 | ||
154 | amdgpu_bo_unpin(bo); | |
8e94a46c MK |
155 | if (bo->prime_shared_count) |
156 | bo->prime_shared_count--; | |
d38ceaf9 AD |
157 | amdgpu_bo_unreserve(bo); |
158 | } | |
159 | ||
160 | struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj) | |
161 | { | |
162 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); | |
163 | ||
164 | return bo->tbo.resv; | |
165 | } | |
166 | ||
167 | struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, | |
168 | struct drm_gem_object *gobj, | |
169 | int flags) | |
170 | { | |
171 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); | |
172 | ||
e1eb899b CK |
173 | if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || |
174 | bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) | |
d38ceaf9 AD |
175 | return ERR_PTR(-EPERM); |
176 | ||
177 | return drm_gem_prime_export(dev, gobj, flags); | |
178 | } |