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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b SR |
27 | #include <linux/uaccess.h> |
28 | ||
c030f2e4 | 29 | #include "amdgpu.h" |
30 | #include "amdgpu_ras.h" | |
b404ae82 | 31 | #include "amdgpu_atomfirmware.h" |
c030f2e4 | 32 | |
c030f2e4 | 33 | const char *ras_error_string[] = { |
34 | "none", | |
35 | "parity", | |
36 | "single_correctable", | |
37 | "multi_uncorrectable", | |
38 | "poison", | |
39 | }; | |
40 | ||
41 | const char *ras_block_string[] = { | |
42 | "umc", | |
43 | "sdma", | |
44 | "gfx", | |
45 | "mmhub", | |
46 | "athub", | |
47 | "pcie_bif", | |
48 | "hdp", | |
49 | "xgmi_wafl", | |
50 | "df", | |
51 | "smn", | |
52 | "sem", | |
53 | "mp0", | |
54 | "mp1", | |
55 | "fuse", | |
56 | }; | |
57 | ||
58 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
59 | #define ras_block_str(i) (ras_block_string[i]) | |
60 | ||
a564808e | 61 | #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS 1 |
62 | #define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2 | |
108c6a63 | 63 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
64 | ||
7cdc2ee3 TZ |
65 | /* inject address is 52 bits */ |
66 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
67 | ||
efb426d5 | 68 | static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev, |
69 | uint64_t offset, uint64_t size, | |
70 | struct amdgpu_bo **bo_ptr); | |
71 | static int amdgpu_ras_release_vram(struct amdgpu_device *adev, | |
72 | struct amdgpu_bo **bo_ptr); | |
73 | ||
c030f2e4 | 74 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
75 | size_t size, loff_t *pos) | |
76 | { | |
77 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
78 | struct ras_query_if info = { | |
79 | .head = obj->head, | |
80 | }; | |
81 | ssize_t s; | |
82 | char val[128]; | |
83 | ||
84 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
85 | return -EINVAL; | |
86 | ||
87 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
88 | "ue", info.ue_count, | |
89 | "ce", info.ce_count); | |
90 | if (*pos >= s) | |
91 | return 0; | |
92 | ||
93 | s -= *pos; | |
94 | s = min_t(u64, s, size); | |
95 | ||
96 | ||
97 | if (copy_to_user(buf, &val[*pos], s)) | |
98 | return -EINVAL; | |
99 | ||
100 | *pos += s; | |
101 | ||
102 | return s; | |
103 | } | |
104 | ||
c030f2e4 | 105 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
106 | .owner = THIS_MODULE, | |
107 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 108 | .write = NULL, |
c030f2e4 | 109 | .llseek = default_llseek |
110 | }; | |
111 | ||
96ebb307 | 112 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
113 | { | |
114 | int i; | |
115 | ||
116 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
117 | *block_id = i; | |
118 | if (strcmp(name, ras_block_str(i)) == 0) | |
119 | return 0; | |
120 | } | |
121 | return -EINVAL; | |
122 | } | |
123 | ||
124 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
125 | const char __user *buf, size_t size, | |
126 | loff_t *pos, struct ras_debug_if *data) | |
127 | { | |
128 | ssize_t s = min_t(u64, 64, size); | |
129 | char str[65]; | |
130 | char block_name[33]; | |
131 | char err[9] = "ue"; | |
132 | int op = -1; | |
133 | int block_id; | |
134 | u64 address, value; | |
135 | ||
136 | if (*pos) | |
137 | return -EINVAL; | |
138 | *pos = size; | |
139 | ||
140 | memset(str, 0, sizeof(str)); | |
141 | memset(data, 0, sizeof(*data)); | |
142 | ||
143 | if (copy_from_user(str, buf, s)) | |
144 | return -EINVAL; | |
145 | ||
146 | if (sscanf(str, "disable %32s", block_name) == 1) | |
147 | op = 0; | |
148 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
149 | op = 1; | |
150 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
151 | op = 2; | |
b076296b | 152 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 153 | /* ascii string, but commands are not matched. */ |
154 | return -EINVAL; | |
155 | ||
156 | if (op != -1) { | |
157 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) | |
158 | return -EINVAL; | |
159 | ||
160 | data->head.block = block_id; | |
e1063493 TZ |
161 | /* only ue and ce errors are supported */ |
162 | if (!memcmp("ue", err, 2)) | |
163 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
164 | else if (!memcmp("ce", err, 2)) | |
165 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
166 | else | |
167 | return -EINVAL; | |
168 | ||
96ebb307 | 169 | data->op = op; |
170 | ||
171 | if (op == 2) { | |
172 | if (sscanf(str, "%*s %*s %*s %llu %llu", | |
173 | &address, &value) != 2) | |
174 | if (sscanf(str, "%*s %*s %*s 0x%llx 0x%llx", | |
175 | &address, &value) != 2) | |
176 | return -EINVAL; | |
177 | data->inject.address = address; | |
178 | data->inject.value = value; | |
179 | } | |
180 | } else { | |
73aa8e1a | 181 | if (size < sizeof(*data)) |
96ebb307 | 182 | return -EINVAL; |
183 | ||
184 | if (copy_from_user(data, buf, sizeof(*data))) | |
185 | return -EINVAL; | |
186 | } | |
187 | ||
188 | return 0; | |
189 | } | |
74abc221 TSD |
190 | /** |
191 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 192 | * |
193 | * It accepts struct ras_debug_if who has two members. | |
194 | * | |
195 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 196 | * |
197 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 198 | * |
199 | * head has four members, they are block, type, sub_block_index, name. | |
200 | * block: which IP will be under control. | |
201 | * type: what kind of error will be enabled/disabled/injected. | |
202 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
203 | * name: the name of IP. | |
204 | * | |
205 | * inject has two more members than head, they are address, value. | |
206 | * As their names indicate, inject operation will write the | |
207 | * value to the address. | |
208 | * | |
209 | * Second member: struct ras_debug_if::op. | |
210 | * It has three kinds of operations. | |
211 | * 0: disable RAS on the block. Take ::head as its data. | |
212 | * 1: enable RAS on the block. Take ::head as its data. | |
213 | * 2: inject errors on the block. Take ::inject as its data. | |
214 | * | |
96ebb307 | 215 | * How to use the interface? |
216 | * programs: | |
217 | * copy the struct ras_debug_if in your codes and initialize it. | |
218 | * write the struct to the control node. | |
219 | * | |
220 | * bash: | |
221 | * echo op block [error [address value]] > .../ras/ras_ctrl | |
222 | * op: disable, enable, inject | |
223 | * disable: only block is needed | |
224 | * enable: block and error are needed | |
225 | * inject: error, address, value are needed | |
226 | * block: umc, smda, gfx, ......... | |
227 | * see ras_block_string[] for details | |
228 | * error: ue, ce | |
229 | * ue: multi_uncorrectable | |
230 | * ce: single_correctable | |
231 | * | |
232 | * here are some examples for bash commands, | |
233 | * echo inject umc ue 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
234 | * echo inject umc ce 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
235 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
236 | * | |
36ea1bd2 | 237 | * How to check the result? |
238 | * | |
239 | * For disable/enable, please check ras features at | |
240 | * /sys/class/drm/card[0/1/2...]/device/ras/features | |
241 | * | |
242 | * For inject, please check corresponding err count at | |
243 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count | |
244 | * | |
245 | * NOTE: operation is only allowed on blocks which are supported. | |
246 | * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask | |
247 | */ | |
248 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
249 | size_t size, loff_t *pos) | |
250 | { | |
251 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
252 | struct ras_debug_if data; | |
253 | int ret = 0; | |
254 | ||
96ebb307 | 255 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
256 | if (ret) | |
36ea1bd2 | 257 | return -EINVAL; |
258 | ||
36ea1bd2 | 259 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
260 | return -EINVAL; | |
261 | ||
262 | switch (data.op) { | |
263 | case 0: | |
264 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
265 | break; | |
266 | case 1: | |
267 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
268 | break; | |
269 | case 2: | |
7cdc2ee3 TZ |
270 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
271 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
272 | ret = -EINVAL; | |
273 | break; | |
274 | } | |
275 | ||
276 | /* data.inject.address is offset instead of absolute gpu address */ | |
36ea1bd2 | 277 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
278 | break; | |
96ebb307 | 279 | default: |
280 | ret = -EINVAL; | |
281 | break; | |
36ea1bd2 | 282 | }; |
283 | ||
284 | if (ret) | |
285 | return -EINVAL; | |
286 | ||
287 | return size; | |
288 | } | |
289 | ||
290 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { | |
291 | .owner = THIS_MODULE, | |
292 | .read = NULL, | |
293 | .write = amdgpu_ras_debugfs_ctrl_write, | |
294 | .llseek = default_llseek | |
295 | }; | |
296 | ||
c030f2e4 | 297 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
298 | struct device_attribute *attr, char *buf) | |
299 | { | |
300 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
301 | struct ras_query_if info = { | |
302 | .head = obj->head, | |
303 | }; | |
304 | ||
305 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
306 | return -EINVAL; | |
307 | ||
308 | return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", | |
309 | "ue", info.ue_count, | |
310 | "ce", info.ce_count); | |
311 | } | |
312 | ||
313 | /* obj begin */ | |
314 | ||
315 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
316 | #define alive_obj(obj) ((obj)->use) | |
317 | ||
318 | static inline void put_obj(struct ras_manager *obj) | |
319 | { | |
320 | if (obj && --obj->use == 0) | |
321 | list_del(&obj->node); | |
322 | if (obj && obj->use < 0) { | |
323 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
324 | } | |
325 | } | |
326 | ||
327 | /* make one obj and return it. */ | |
328 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
329 | struct ras_common_if *head) | |
330 | { | |
331 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
332 | struct ras_manager *obj; | |
333 | ||
334 | if (!con) | |
335 | return NULL; | |
336 | ||
337 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
338 | return NULL; | |
339 | ||
340 | obj = &con->objs[head->block]; | |
341 | /* already exist. return obj? */ | |
342 | if (alive_obj(obj)) | |
343 | return NULL; | |
344 | ||
345 | obj->head = *head; | |
346 | obj->adev = adev; | |
347 | list_add(&obj->node, &con->head); | |
348 | get_obj(obj); | |
349 | ||
350 | return obj; | |
351 | } | |
352 | ||
353 | /* return an obj equal to head, or the first when head is NULL */ | |
354 | static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, | |
355 | struct ras_common_if *head) | |
356 | { | |
357 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
358 | struct ras_manager *obj; | |
359 | int i; | |
360 | ||
361 | if (!con) | |
362 | return NULL; | |
363 | ||
364 | if (head) { | |
365 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
366 | return NULL; | |
367 | ||
368 | obj = &con->objs[head->block]; | |
369 | ||
370 | if (alive_obj(obj)) { | |
371 | WARN_ON(head->block != obj->head.block); | |
372 | return obj; | |
373 | } | |
374 | } else { | |
375 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
376 | obj = &con->objs[i]; | |
377 | if (alive_obj(obj)) { | |
378 | WARN_ON(i != obj->head.block); | |
379 | return obj; | |
380 | } | |
381 | } | |
382 | } | |
383 | ||
384 | return NULL; | |
385 | } | |
386 | /* obj end */ | |
387 | ||
388 | /* feature ctl begin */ | |
389 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
390 | struct ras_common_if *head) | |
391 | { | |
5caf466a | 392 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
393 | ||
394 | return con->hw_supported & BIT(head->block); | |
c030f2e4 | 395 | } |
396 | ||
397 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
398 | struct ras_common_if *head) | |
399 | { | |
400 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
401 | ||
402 | return con->features & BIT(head->block); | |
403 | } | |
404 | ||
405 | /* | |
406 | * if obj is not created, then create one. | |
407 | * set feature enable flag. | |
408 | */ | |
409 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
410 | struct ras_common_if *head, int enable) | |
411 | { | |
412 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
413 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
414 | ||
5caf466a | 415 | /* If hardware does not support ras, then do not create obj. |
416 | * But if hardware support ras, we can create the obj. | |
417 | * Ras framework checks con->hw_supported to see if it need do | |
418 | * corresponding initialization. | |
419 | * IP checks con->support to see if it need disable ras. | |
420 | */ | |
c030f2e4 | 421 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
422 | return 0; | |
423 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
424 | return 0; | |
425 | ||
426 | if (enable) { | |
427 | if (!obj) { | |
428 | obj = amdgpu_ras_create_obj(adev, head); | |
429 | if (!obj) | |
430 | return -EINVAL; | |
431 | } else { | |
432 | /* In case we create obj somewhere else */ | |
433 | get_obj(obj); | |
434 | } | |
435 | con->features |= BIT(head->block); | |
436 | } else { | |
437 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
438 | con->features &= ~BIT(head->block); | |
439 | put_obj(obj); | |
440 | } | |
441 | } | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
446 | /* wrapper of psp_ras_enable_features */ | |
447 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
448 | struct ras_common_if *head, bool enable) | |
449 | { | |
450 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
451 | union ta_ras_cmd_input info; | |
452 | int ret; | |
453 | ||
454 | if (!con) | |
455 | return -EINVAL; | |
456 | ||
457 | if (!enable) { | |
458 | info.disable_features = (struct ta_ras_disable_features_input) { | |
828cfa29 | 459 | .block_id = amdgpu_ras_block_to_ta(head->block), |
460 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 461 | }; |
462 | } else { | |
463 | info.enable_features = (struct ta_ras_enable_features_input) { | |
828cfa29 | 464 | .block_id = amdgpu_ras_block_to_ta(head->block), |
465 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 466 | }; |
467 | } | |
468 | ||
469 | /* Do not enable if it is not allowed. */ | |
470 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
471 | /* Are we alerady in that state we are going to set? */ | |
472 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
473 | return 0; | |
474 | ||
475 | ret = psp_ras_enable_features(&adev->psp, &info, enable); | |
476 | if (ret) { | |
477 | DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n", | |
478 | enable ? "enable":"disable", | |
479 | ras_block_str(head->block), | |
480 | ret); | |
7af23ebe | 481 | if (ret == TA_RAS_STATUS__RESET_NEEDED) |
482 | return -EAGAIN; | |
c030f2e4 | 483 | return -EINVAL; |
484 | } | |
485 | ||
486 | /* setup the obj */ | |
487 | __amdgpu_ras_feature_enable(adev, head, enable); | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
77de502b | 492 | /* Only used in device probe stage and called only once. */ |
493 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
494 | struct ras_common_if *head, bool enable) | |
495 | { | |
496 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
497 | int ret; | |
498 | ||
499 | if (!con) | |
500 | return -EINVAL; | |
501 | ||
502 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 503 | if (enable) { |
504 | /* There is no harm to issue a ras TA cmd regardless of | |
505 | * the currecnt ras state. | |
506 | * If current state == target state, it will do nothing | |
507 | * But sometimes it requests driver to reset and repost | |
508 | * with error code -EAGAIN. | |
509 | */ | |
510 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
511 | /* With old ras TA, we might fail to enable ras. | |
512 | * Log it and just setup the object. | |
513 | * TODO need remove this WA in the future. | |
514 | */ | |
515 | if (ret == -EINVAL) { | |
516 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
517 | if (!ret) | |
518 | DRM_INFO("RAS INFO: %s setup object\n", | |
519 | ras_block_str(head->block)); | |
520 | } | |
521 | } else { | |
522 | /* setup the object then issue a ras TA disable cmd.*/ | |
523 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
524 | if (ret) | |
525 | return ret; | |
77de502b | 526 | |
77de502b | 527 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
7af23ebe | 528 | } |
77de502b | 529 | } else |
530 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
531 | ||
532 | return ret; | |
533 | } | |
534 | ||
c030f2e4 | 535 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
536 | bool bypass) | |
537 | { | |
538 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
539 | struct ras_manager *obj, *tmp; | |
540 | ||
541 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
542 | /* bypass psp. | |
543 | * aka just release the obj and corresponding flags | |
544 | */ | |
545 | if (bypass) { | |
546 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
547 | break; | |
548 | } else { | |
549 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
550 | break; | |
551 | } | |
289d513b | 552 | } |
c030f2e4 | 553 | |
554 | return con->features; | |
555 | } | |
556 | ||
557 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
558 | bool bypass) | |
559 | { | |
560 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
561 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
562 | int i; | |
191051a1 | 563 | const enum amdgpu_ras_error_type default_ras_type = |
564 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 565 | |
566 | for (i = 0; i < ras_block_count; i++) { | |
567 | struct ras_common_if head = { | |
568 | .block = i, | |
191051a1 | 569 | .type = default_ras_type, |
c030f2e4 | 570 | .sub_block_index = 0, |
571 | }; | |
572 | strcpy(head.name, ras_block_str(i)); | |
573 | if (bypass) { | |
574 | /* | |
575 | * bypass psp. vbios enable ras for us. | |
576 | * so just create the obj | |
577 | */ | |
578 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
579 | break; | |
580 | } else { | |
581 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
582 | break; | |
583 | } | |
289d513b | 584 | } |
c030f2e4 | 585 | |
586 | return con->features; | |
587 | } | |
588 | /* feature ctl end */ | |
589 | ||
590 | /* query/inject/cure begin */ | |
591 | int amdgpu_ras_error_query(struct amdgpu_device *adev, | |
592 | struct ras_query_if *info) | |
593 | { | |
594 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 595 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 596 | |
597 | if (!obj) | |
598 | return -EINVAL; | |
c030f2e4 | 599 | |
939e2258 HZ |
600 | switch (info->head.block) { |
601 | case AMDGPU_RAS_BLOCK__UMC: | |
045c0216 TZ |
602 | if (adev->umc.funcs->query_ras_error_count) |
603 | adev->umc.funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
604 | /* umc query_ras_error_address is also responsible for clearing |
605 | * error status | |
606 | */ | |
607 | if (adev->umc.funcs->query_ras_error_address) | |
608 | adev->umc.funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 609 | break; |
83b0582c DL |
610 | case AMDGPU_RAS_BLOCK__GFX: |
611 | if (adev->gfx.funcs->query_ras_error_count) | |
612 | adev->gfx.funcs->query_ras_error_count(adev, &err_data); | |
613 | break; | |
939e2258 HZ |
614 | default: |
615 | break; | |
616 | } | |
05a58345 TZ |
617 | |
618 | obj->err_data.ue_count += err_data.ue_count; | |
619 | obj->err_data.ce_count += err_data.ce_count; | |
620 | ||
c030f2e4 | 621 | info->ue_count = obj->err_data.ue_count; |
622 | info->ce_count = obj->err_data.ce_count; | |
623 | ||
05a58345 TZ |
624 | if (err_data.ce_count) |
625 | dev_info(adev->dev, "%ld correctable errors detected in %s block\n", | |
626 | obj->err_data.ce_count, ras_block_str(info->head.block)); | |
627 | if (err_data.ue_count) | |
628 | dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n", | |
629 | obj->err_data.ue_count, ras_block_str(info->head.block)); | |
630 | ||
c030f2e4 | 631 | return 0; |
632 | } | |
633 | ||
634 | /* wrapper of psp_ras_trigger_error */ | |
635 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
636 | struct ras_inject_if *info) | |
637 | { | |
638 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
639 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 640 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
641 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 642 | .sub_block_index = info->head.sub_block_index, |
643 | .address = info->address, | |
644 | .value = info->value, | |
645 | }; | |
646 | int ret = 0; | |
647 | ||
648 | if (!obj) | |
649 | return -EINVAL; | |
650 | ||
83b0582c DL |
651 | switch (info->head.block) { |
652 | case AMDGPU_RAS_BLOCK__GFX: | |
653 | if (adev->gfx.funcs->ras_error_inject) | |
654 | ret = adev->gfx.funcs->ras_error_inject(adev, info); | |
655 | else | |
656 | ret = -EINVAL; | |
657 | break; | |
658 | case AMDGPU_RAS_BLOCK__UMC: | |
659 | ret = psp_ras_trigger_error(&adev->psp, &block_info); | |
660 | break; | |
661 | default: | |
a5dd40ca HZ |
662 | DRM_INFO("%s error injection is not supported yet\n", |
663 | ras_block_str(info->head.block)); | |
83b0582c | 664 | ret = -EINVAL; |
a5dd40ca HZ |
665 | } |
666 | ||
c030f2e4 | 667 | if (ret) |
668 | DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n", | |
669 | ras_block_str(info->head.block), | |
670 | ret); | |
671 | ||
672 | return ret; | |
673 | } | |
674 | ||
675 | int amdgpu_ras_error_cure(struct amdgpu_device *adev, | |
676 | struct ras_cure_if *info) | |
677 | { | |
678 | /* psp fw has no cure interface for now. */ | |
679 | return 0; | |
680 | } | |
681 | ||
682 | /* get the total error counts on all IPs */ | |
683 | int amdgpu_ras_query_error_count(struct amdgpu_device *adev, | |
684 | bool is_ce) | |
685 | { | |
686 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
687 | struct ras_manager *obj; | |
688 | struct ras_err_data data = {0, 0}; | |
689 | ||
690 | if (!con) | |
691 | return -EINVAL; | |
692 | ||
693 | list_for_each_entry(obj, &con->head, node) { | |
694 | struct ras_query_if info = { | |
695 | .head = obj->head, | |
696 | }; | |
697 | ||
698 | if (amdgpu_ras_error_query(adev, &info)) | |
699 | return -EINVAL; | |
700 | ||
701 | data.ce_count += info.ce_count; | |
702 | data.ue_count += info.ue_count; | |
703 | } | |
704 | ||
705 | return is_ce ? data.ce_count : data.ue_count; | |
706 | } | |
707 | /* query/inject/cure end */ | |
708 | ||
709 | ||
710 | /* sysfs begin */ | |
711 | ||
466b1793 | 712 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
713 | struct ras_badpage **bps, unsigned int *count); | |
714 | ||
715 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
716 | { | |
717 | switch (flags) { | |
718 | case 0: | |
719 | return "R"; | |
720 | case 1: | |
721 | return "P"; | |
722 | case 2: | |
723 | default: | |
724 | return "F"; | |
725 | }; | |
726 | } | |
727 | ||
728 | /* | |
729 | * DOC: ras sysfs gpu_vram_bad_pages interface | |
730 | * | |
731 | * It allows user to read the bad pages of vram on the gpu through | |
732 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
733 | * | |
734 | * It outputs multiple lines, and each line stands for one gpu page. | |
735 | * | |
736 | * The format of one line is below, | |
737 | * gpu pfn : gpu page size : flags | |
738 | * | |
739 | * gpu pfn and gpu page size are printed in hex format. | |
740 | * flags can be one of below character, | |
741 | * R: reserved, this gpu page is reserved and not able to use. | |
742 | * P: pending for reserve, this gpu page is marked as bad, will be reserved | |
743 | * in next window of page_reserve. | |
744 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. | |
745 | * | |
746 | * examples: | |
747 | * 0x00000001 : 0x00001000 : R | |
748 | * 0x00000002 : 0x00001000 : P | |
749 | */ | |
750 | ||
751 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
752 | struct kobject *kobj, struct bin_attribute *attr, | |
753 | char *buf, loff_t ppos, size_t count) | |
754 | { | |
755 | struct amdgpu_ras *con = | |
756 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
757 | struct amdgpu_device *adev = con->adev; | |
758 | const unsigned int element_size = | |
759 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
760 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
761 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 762 | ssize_t s = 0; |
763 | struct ras_badpage *bps = NULL; | |
764 | unsigned int bps_count = 0; | |
765 | ||
766 | memset(buf, 0, count); | |
767 | ||
768 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
769 | return 0; | |
770 | ||
771 | for (; start < end && start < bps_count; start++) | |
772 | s += scnprintf(&buf[s], element_size + 1, | |
773 | "0x%08x : 0x%08x : %1s\n", | |
774 | bps[start].bp, | |
775 | bps[start].size, | |
776 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
777 | ||
778 | kfree(bps); | |
779 | ||
780 | return s; | |
781 | } | |
782 | ||
c030f2e4 | 783 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
784 | struct device_attribute *attr, char *buf) | |
785 | { | |
786 | struct amdgpu_ras *con = | |
787 | container_of(attr, struct amdgpu_ras, features_attr); | |
788 | struct drm_device *ddev = dev_get_drvdata(dev); | |
789 | struct amdgpu_device *adev = ddev->dev_private; | |
790 | struct ras_common_if head; | |
791 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
2a3c7ff6 | 792 | int i, enabled; |
c030f2e4 | 793 | ssize_t s; |
c030f2e4 | 794 | |
795 | s = scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); | |
796 | ||
797 | for (i = 0; i < ras_block_count; i++) { | |
798 | head.block = i; | |
2a3c7ff6 | 799 | enabled = amdgpu_ras_is_feature_enabled(adev, &head); |
c030f2e4 | 800 | |
2a3c7ff6 TZ |
801 | s += scnprintf(&buf[s], PAGE_SIZE - s, |
802 | "%s ras feature mask: %s\n", | |
803 | ras_block_str(i), enabled?"on":"off"); | |
c030f2e4 | 804 | } |
805 | ||
806 | return s; | |
807 | } | |
808 | ||
809 | static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev) | |
810 | { | |
811 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
812 | struct attribute *attrs[] = { | |
813 | &con->features_attr.attr, | |
814 | NULL | |
815 | }; | |
466b1793 | 816 | struct bin_attribute *bin_attrs[] = { |
817 | &con->badpages_attr, | |
818 | NULL | |
819 | }; | |
c030f2e4 | 820 | struct attribute_group group = { |
821 | .name = "ras", | |
822 | .attrs = attrs, | |
466b1793 | 823 | .bin_attrs = bin_attrs, |
c030f2e4 | 824 | }; |
825 | ||
826 | con->features_attr = (struct device_attribute) { | |
827 | .attr = { | |
828 | .name = "features", | |
829 | .mode = S_IRUGO, | |
830 | }, | |
831 | .show = amdgpu_ras_sysfs_features_read, | |
832 | }; | |
466b1793 | 833 | |
834 | con->badpages_attr = (struct bin_attribute) { | |
835 | .attr = { | |
836 | .name = "gpu_vram_bad_pages", | |
837 | .mode = S_IRUGO, | |
838 | }, | |
839 | .size = 0, | |
840 | .private = NULL, | |
841 | .read = amdgpu_ras_sysfs_badpages_read, | |
842 | }; | |
843 | ||
163def43 | 844 | sysfs_attr_init(attrs[0]); |
466b1793 | 845 | sysfs_bin_attr_init(bin_attrs[0]); |
c030f2e4 | 846 | |
847 | return sysfs_create_group(&adev->dev->kobj, &group); | |
848 | } | |
849 | ||
850 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) | |
851 | { | |
852 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
853 | struct attribute *attrs[] = { | |
854 | &con->features_attr.attr, | |
855 | NULL | |
856 | }; | |
466b1793 | 857 | struct bin_attribute *bin_attrs[] = { |
858 | &con->badpages_attr, | |
859 | NULL | |
860 | }; | |
c030f2e4 | 861 | struct attribute_group group = { |
862 | .name = "ras", | |
863 | .attrs = attrs, | |
466b1793 | 864 | .bin_attrs = bin_attrs, |
c030f2e4 | 865 | }; |
866 | ||
867 | sysfs_remove_group(&adev->dev->kobj, &group); | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
872 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
873 | struct ras_fs_if *head) | |
874 | { | |
875 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
876 | ||
877 | if (!obj || obj->attr_inuse) | |
878 | return -EINVAL; | |
879 | ||
880 | get_obj(obj); | |
881 | ||
882 | memcpy(obj->fs_data.sysfs_name, | |
883 | head->sysfs_name, | |
884 | sizeof(obj->fs_data.sysfs_name)); | |
885 | ||
886 | obj->sysfs_attr = (struct device_attribute){ | |
887 | .attr = { | |
888 | .name = obj->fs_data.sysfs_name, | |
889 | .mode = S_IRUGO, | |
890 | }, | |
891 | .show = amdgpu_ras_sysfs_read, | |
892 | }; | |
163def43 | 893 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 894 | |
895 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
896 | &obj->sysfs_attr.attr, | |
897 | "ras")) { | |
898 | put_obj(obj); | |
899 | return -EINVAL; | |
900 | } | |
901 | ||
902 | obj->attr_inuse = 1; | |
903 | ||
904 | return 0; | |
905 | } | |
906 | ||
907 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
908 | struct ras_common_if *head) | |
909 | { | |
910 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
911 | ||
912 | if (!obj || !obj->attr_inuse) | |
913 | return -EINVAL; | |
914 | ||
915 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
916 | &obj->sysfs_attr.attr, | |
917 | "ras"); | |
918 | obj->attr_inuse = 0; | |
919 | put_obj(obj); | |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
924 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
925 | { | |
926 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
927 | struct ras_manager *obj, *tmp; | |
928 | ||
929 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
930 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
931 | } | |
932 | ||
933 | amdgpu_ras_sysfs_remove_feature_node(adev); | |
934 | ||
935 | return 0; | |
936 | } | |
937 | /* sysfs end */ | |
938 | ||
939 | /* debugfs begin */ | |
450f30ea | 940 | static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 941 | { |
942 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
943 | struct drm_minor *minor = adev->ddev->primary; | |
36ea1bd2 | 944 | |
450f30ea GKH |
945 | con->dir = debugfs_create_dir("ras", minor->debugfs_root); |
946 | con->ent = debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir, | |
947 | adev, &amdgpu_ras_debugfs_ctrl_ops); | |
36ea1bd2 | 948 | } |
949 | ||
450f30ea | 950 | void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
c030f2e4 | 951 | struct ras_fs_if *head) |
952 | { | |
953 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
954 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
c030f2e4 | 955 | |
956 | if (!obj || obj->ent) | |
450f30ea | 957 | return; |
c030f2e4 | 958 | |
959 | get_obj(obj); | |
960 | ||
961 | memcpy(obj->fs_data.debugfs_name, | |
962 | head->debugfs_name, | |
963 | sizeof(obj->fs_data.debugfs_name)); | |
964 | ||
450f30ea GKH |
965 | obj->ent = debugfs_create_file(obj->fs_data.debugfs_name, |
966 | S_IWUGO | S_IRUGO, con->dir, obj, | |
967 | &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 968 | } |
969 | ||
450f30ea | 970 | void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, |
c030f2e4 | 971 | struct ras_common_if *head) |
972 | { | |
973 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
974 | ||
975 | if (!obj || !obj->ent) | |
450f30ea | 976 | return; |
c030f2e4 | 977 | |
978 | debugfs_remove(obj->ent); | |
979 | obj->ent = NULL; | |
980 | put_obj(obj); | |
c030f2e4 | 981 | } |
982 | ||
450f30ea | 983 | static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) |
c030f2e4 | 984 | { |
985 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
986 | struct ras_manager *obj, *tmp; | |
987 | ||
988 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
989 | amdgpu_ras_debugfs_remove(adev, &obj->head); | |
990 | } | |
991 | ||
36ea1bd2 | 992 | debugfs_remove(con->ent); |
c030f2e4 | 993 | debugfs_remove(con->dir); |
994 | con->dir = NULL; | |
36ea1bd2 | 995 | con->ent = NULL; |
c030f2e4 | 996 | } |
997 | /* debugfs end */ | |
998 | ||
999 | /* ras fs */ | |
1000 | ||
1001 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) | |
1002 | { | |
c030f2e4 | 1003 | amdgpu_ras_sysfs_create_feature_node(adev); |
36ea1bd2 | 1004 | amdgpu_ras_debugfs_create_ctrl_node(adev); |
c030f2e4 | 1005 | |
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1010 | { | |
1011 | amdgpu_ras_debugfs_remove_all(adev); | |
1012 | amdgpu_ras_sysfs_remove_all(adev); | |
1013 | return 0; | |
1014 | } | |
1015 | /* ras fs end */ | |
1016 | ||
1017 | /* ih begin */ | |
1018 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1019 | { | |
1020 | struct ras_ih_data *data = &obj->ih_data; | |
1021 | struct amdgpu_iv_entry entry; | |
1022 | int ret; | |
cf04dfd0 | 1023 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1024 | |
1025 | while (data->rptr != data->wptr) { | |
1026 | rmb(); | |
1027 | memcpy(&entry, &data->ring[data->rptr], | |
1028 | data->element_size); | |
1029 | ||
1030 | wmb(); | |
1031 | data->rptr = (data->aligned_element_size + | |
1032 | data->rptr) % data->ring_size; | |
1033 | ||
1034 | /* Let IP handle its data, maybe we need get the output | |
1035 | * from the callback to udpate the error type/count, etc | |
1036 | */ | |
1037 | if (data->cb) { | |
cf04dfd0 | 1038 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1039 | /* ue will trigger an interrupt, and in that case |
1040 | * we need do a reset to recovery the whole system. | |
1041 | * But leave IP do that recovery, here we just dispatch | |
1042 | * the error. | |
1043 | */ | |
bd2280da | 1044 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1045 | /* these counts could be left as 0 if |
1046 | * some blocks do not count error number | |
1047 | */ | |
cf04dfd0 | 1048 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1049 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1050 | } |
c030f2e4 | 1051 | } |
1052 | } | |
1053 | } | |
1054 | ||
1055 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1056 | { | |
1057 | struct ras_ih_data *data = | |
1058 | container_of(work, struct ras_ih_data, ih_work); | |
1059 | struct ras_manager *obj = | |
1060 | container_of(data, struct ras_manager, ih_data); | |
1061 | ||
1062 | amdgpu_ras_interrupt_handler(obj); | |
1063 | } | |
1064 | ||
1065 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1066 | struct ras_dispatch_if *info) | |
1067 | { | |
1068 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1069 | struct ras_ih_data *data = &obj->ih_data; | |
1070 | ||
1071 | if (!obj) | |
1072 | return -EINVAL; | |
1073 | ||
1074 | if (data->inuse == 0) | |
1075 | return 0; | |
1076 | ||
1077 | /* Might be overflow... */ | |
1078 | memcpy(&data->ring[data->wptr], info->entry, | |
1079 | data->element_size); | |
1080 | ||
1081 | wmb(); | |
1082 | data->wptr = (data->aligned_element_size + | |
1083 | data->wptr) % data->ring_size; | |
1084 | ||
1085 | schedule_work(&data->ih_work); | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
1090 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1091 | struct ras_ih_if *info) | |
1092 | { | |
1093 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1094 | struct ras_ih_data *data; | |
1095 | ||
1096 | if (!obj) | |
1097 | return -EINVAL; | |
1098 | ||
1099 | data = &obj->ih_data; | |
1100 | if (data->inuse == 0) | |
1101 | return 0; | |
1102 | ||
1103 | cancel_work_sync(&data->ih_work); | |
1104 | ||
1105 | kfree(data->ring); | |
1106 | memset(data, 0, sizeof(*data)); | |
1107 | put_obj(obj); | |
1108 | ||
1109 | return 0; | |
1110 | } | |
1111 | ||
1112 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1113 | struct ras_ih_if *info) | |
1114 | { | |
1115 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1116 | struct ras_ih_data *data; | |
1117 | ||
1118 | if (!obj) { | |
1119 | /* in case we registe the IH before enable ras feature */ | |
1120 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1121 | if (!obj) | |
1122 | return -EINVAL; | |
1123 | } else | |
1124 | get_obj(obj); | |
1125 | ||
1126 | data = &obj->ih_data; | |
1127 | /* add the callback.etc */ | |
1128 | *data = (struct ras_ih_data) { | |
1129 | .inuse = 0, | |
1130 | .cb = info->cb, | |
1131 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1132 | .rptr = 0, | |
1133 | .wptr = 0, | |
1134 | }; | |
1135 | ||
1136 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1137 | ||
1138 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1139 | /* the ring can store 64 iv entries. */ | |
1140 | data->ring_size = 64 * data->aligned_element_size; | |
1141 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1142 | if (!data->ring) { | |
1143 | put_obj(obj); | |
1144 | return -ENOMEM; | |
1145 | } | |
1146 | ||
1147 | /* IH is ready */ | |
1148 | data->inuse = 1; | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1154 | { | |
1155 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1156 | struct ras_manager *obj, *tmp; | |
1157 | ||
1158 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1159 | struct ras_ih_if info = { | |
1160 | .head = obj->head, | |
1161 | }; | |
1162 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1163 | } | |
1164 | ||
1165 | return 0; | |
1166 | } | |
1167 | /* ih end */ | |
1168 | ||
1169 | /* recovery begin */ | |
466b1793 | 1170 | |
1171 | /* return 0 on success. | |
1172 | * caller need free bps. | |
1173 | */ | |
1174 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1175 | struct ras_badpage **bps, unsigned int *count) | |
1176 | { | |
1177 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1178 | struct ras_err_handler_data *data; | |
1179 | int i = 0; | |
1180 | int ret = 0; | |
1181 | ||
1182 | if (!con || !con->eh_data || !bps || !count) | |
1183 | return -EINVAL; | |
1184 | ||
1185 | mutex_lock(&con->recovery_lock); | |
1186 | data = con->eh_data; | |
1187 | if (!data || data->count == 0) { | |
1188 | *bps = NULL; | |
1189 | goto out; | |
1190 | } | |
1191 | ||
1192 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1193 | if (!*bps) { | |
1194 | ret = -ENOMEM; | |
1195 | goto out; | |
1196 | } | |
1197 | ||
1198 | for (; i < data->count; i++) { | |
1199 | (*bps)[i] = (struct ras_badpage){ | |
1200 | .bp = data->bps[i].bp, | |
1201 | .size = AMDGPU_GPU_PAGE_SIZE, | |
1202 | .flags = 0, | |
1203 | }; | |
1204 | ||
1205 | if (data->last_reserved <= i) | |
1206 | (*bps)[i].flags = 1; | |
1207 | else if (data->bps[i].bo == NULL) | |
1208 | (*bps)[i].flags = 2; | |
1209 | } | |
1210 | ||
1211 | *count = data->count; | |
1212 | out: | |
1213 | mutex_unlock(&con->recovery_lock); | |
1214 | return ret; | |
1215 | } | |
1216 | ||
c030f2e4 | 1217 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1218 | { | |
1219 | struct amdgpu_ras *ras = | |
1220 | container_of(work, struct amdgpu_ras, recovery_work); | |
1221 | ||
1222 | amdgpu_device_gpu_recover(ras->adev, 0); | |
1223 | atomic_set(&ras->in_recovery, 0); | |
1224 | } | |
1225 | ||
1226 | static int amdgpu_ras_release_vram(struct amdgpu_device *adev, | |
1227 | struct amdgpu_bo **bo_ptr) | |
1228 | { | |
1229 | /* no need to free it actually. */ | |
1230 | amdgpu_bo_free_kernel(bo_ptr, NULL, NULL); | |
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | /* reserve vram with size@offset */ | |
1235 | static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev, | |
1236 | uint64_t offset, uint64_t size, | |
1237 | struct amdgpu_bo **bo_ptr) | |
1238 | { | |
1239 | struct ttm_operation_ctx ctx = { false, false }; | |
1240 | struct amdgpu_bo_param bp; | |
1241 | int r = 0; | |
1242 | int i; | |
1243 | struct amdgpu_bo *bo; | |
1244 | ||
1245 | if (bo_ptr) | |
1246 | *bo_ptr = NULL; | |
1247 | memset(&bp, 0, sizeof(bp)); | |
1248 | bp.size = size; | |
1249 | bp.byte_align = PAGE_SIZE; | |
1250 | bp.domain = AMDGPU_GEM_DOMAIN_VRAM; | |
1251 | bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
1252 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS; | |
1253 | bp.type = ttm_bo_type_kernel; | |
1254 | bp.resv = NULL; | |
1255 | ||
1256 | r = amdgpu_bo_create(adev, &bp, &bo); | |
1257 | if (r) | |
1258 | return -EINVAL; | |
1259 | ||
1260 | r = amdgpu_bo_reserve(bo, false); | |
1261 | if (r) | |
1262 | goto error_reserve; | |
1263 | ||
1264 | offset = ALIGN(offset, PAGE_SIZE); | |
1265 | for (i = 0; i < bo->placement.num_placement; ++i) { | |
1266 | bo->placements[i].fpfn = offset >> PAGE_SHIFT; | |
1267 | bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; | |
1268 | } | |
1269 | ||
1270 | ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem); | |
1271 | r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem, &ctx); | |
1272 | if (r) | |
1273 | goto error_pin; | |
1274 | ||
1275 | r = amdgpu_bo_pin_restricted(bo, | |
1276 | AMDGPU_GEM_DOMAIN_VRAM, | |
1277 | offset, | |
1278 | offset + size); | |
1279 | if (r) | |
1280 | goto error_pin; | |
1281 | ||
1282 | if (bo_ptr) | |
1283 | *bo_ptr = bo; | |
1284 | ||
1285 | amdgpu_bo_unreserve(bo); | |
1286 | return r; | |
1287 | ||
1288 | error_pin: | |
1289 | amdgpu_bo_unreserve(bo); | |
1290 | error_reserve: | |
1291 | amdgpu_bo_unref(&bo); | |
1292 | return r; | |
1293 | } | |
1294 | ||
1295 | /* alloc/realloc bps array */ | |
1296 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1297 | struct ras_err_handler_data *data, int pages) | |
1298 | { | |
1299 | unsigned int old_space = data->count + data->space_left; | |
1300 | unsigned int new_space = old_space + pages; | |
1301 | unsigned int align_space = ALIGN(new_space, 1024); | |
1302 | void *tmp = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
1303 | ||
1304 | if (!tmp) | |
1305 | return -ENOMEM; | |
1306 | ||
1307 | if (data->bps) { | |
1308 | memcpy(tmp, data->bps, | |
1309 | data->count * sizeof(*data->bps)); | |
1310 | kfree(data->bps); | |
1311 | } | |
1312 | ||
1313 | data->bps = tmp; | |
1314 | data->space_left += align_space - old_space; | |
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | /* it deal with vram only. */ | |
1319 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
1320 | unsigned long *bps, int pages) | |
1321 | { | |
1322 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1323 | struct ras_err_handler_data *data; |
c030f2e4 | 1324 | int i = pages; |
1325 | int ret = 0; | |
1326 | ||
73aa8e1a | 1327 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1328 | return 0; |
1329 | ||
1330 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1331 | data = con->eh_data; |
c030f2e4 | 1332 | if (!data) |
1333 | goto out; | |
1334 | ||
1335 | if (data->space_left <= pages) | |
1336 | if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) { | |
1337 | ret = -ENOMEM; | |
1338 | goto out; | |
1339 | } | |
1340 | ||
1341 | while (i--) | |
1342 | data->bps[data->count++].bp = bps[i]; | |
1343 | ||
1344 | data->space_left -= pages; | |
1345 | out: | |
1346 | mutex_unlock(&con->recovery_lock); | |
1347 | ||
1348 | return ret; | |
1349 | } | |
1350 | ||
1351 | /* called in gpu recovery/init */ | |
1352 | int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev) | |
1353 | { | |
1354 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1355 | struct ras_err_handler_data *data; |
c030f2e4 | 1356 | uint64_t bp; |
1357 | struct amdgpu_bo *bo; | |
1358 | int i; | |
1359 | ||
73aa8e1a | 1360 | if (!con || !con->eh_data) |
c030f2e4 | 1361 | return 0; |
1362 | ||
1363 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1364 | data = con->eh_data; |
1365 | if (!data) | |
1366 | goto out; | |
c030f2e4 | 1367 | /* reserve vram at driver post stage. */ |
1368 | for (i = data->last_reserved; i < data->count; i++) { | |
1369 | bp = data->bps[i].bp; | |
1370 | ||
1371 | if (amdgpu_ras_reserve_vram(adev, bp << PAGE_SHIFT, | |
1372 | PAGE_SIZE, &bo)) | |
1373 | DRM_ERROR("RAS ERROR: reserve vram %llx fail\n", bp); | |
1374 | ||
1375 | data->bps[i].bo = bo; | |
1376 | data->last_reserved = i + 1; | |
1377 | } | |
73aa8e1a | 1378 | out: |
c030f2e4 | 1379 | mutex_unlock(&con->recovery_lock); |
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | /* called when driver unload */ | |
1384 | static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev) | |
1385 | { | |
1386 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1387 | struct ras_err_handler_data *data; |
c030f2e4 | 1388 | struct amdgpu_bo *bo; |
1389 | int i; | |
1390 | ||
73aa8e1a | 1391 | if (!con || !con->eh_data) |
c030f2e4 | 1392 | return 0; |
1393 | ||
1394 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1395 | data = con->eh_data; |
1396 | if (!data) | |
1397 | goto out; | |
1398 | ||
c030f2e4 | 1399 | for (i = data->last_reserved - 1; i >= 0; i--) { |
1400 | bo = data->bps[i].bo; | |
1401 | ||
1402 | amdgpu_ras_release_vram(adev, &bo); | |
1403 | ||
1404 | data->bps[i].bo = bo; | |
1405 | data->last_reserved = i; | |
1406 | } | |
73aa8e1a | 1407 | out: |
c030f2e4 | 1408 | mutex_unlock(&con->recovery_lock); |
1409 | return 0; | |
1410 | } | |
1411 | ||
1412 | static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) | |
1413 | { | |
1414 | /* TODO | |
1415 | * write the array to eeprom when SMU disabled. | |
1416 | */ | |
1417 | return 0; | |
1418 | } | |
1419 | ||
1420 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1421 | { | |
1422 | /* TODO | |
1423 | * read the array to eeprom when SMU disabled. | |
1424 | */ | |
1425 | return 0; | |
1426 | } | |
1427 | ||
1428 | static int amdgpu_ras_recovery_init(struct amdgpu_device *adev) | |
1429 | { | |
1430 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1431 | struct ras_err_handler_data **data = &con->eh_data; | |
1432 | ||
1433 | *data = kmalloc(sizeof(**data), | |
1434 | GFP_KERNEL|__GFP_ZERO); | |
1435 | if (!*data) | |
1436 | return -ENOMEM; | |
1437 | ||
1438 | mutex_init(&con->recovery_lock); | |
1439 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1440 | atomic_set(&con->in_recovery, 0); | |
1441 | con->adev = adev; | |
1442 | ||
1443 | amdgpu_ras_load_bad_pages(adev); | |
1444 | amdgpu_ras_reserve_bad_pages(adev); | |
1445 | ||
1446 | return 0; | |
1447 | } | |
1448 | ||
1449 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
1450 | { | |
1451 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1452 | struct ras_err_handler_data *data = con->eh_data; | |
1453 | ||
1454 | cancel_work_sync(&con->recovery_work); | |
1455 | amdgpu_ras_save_bad_pages(adev); | |
1456 | amdgpu_ras_release_bad_pages(adev); | |
1457 | ||
1458 | mutex_lock(&con->recovery_lock); | |
1459 | con->eh_data = NULL; | |
1460 | kfree(data->bps); | |
1461 | kfree(data); | |
1462 | mutex_unlock(&con->recovery_lock); | |
1463 | ||
1464 | return 0; | |
1465 | } | |
1466 | /* recovery end */ | |
1467 | ||
a564808e | 1468 | /* return 0 if ras will reset gpu and repost.*/ |
1469 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
1470 | unsigned int block) | |
1471 | { | |
1472 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1473 | ||
1474 | if (!ras) | |
1475 | return -EINVAL; | |
1476 | ||
1477 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1478 | return 0; | |
1479 | } | |
1480 | ||
5caf466a | 1481 | /* |
1482 | * check hardware's ras ability which will be saved in hw_supported. | |
1483 | * if hardware does not support ras, we can skip some ras initializtion and | |
1484 | * forbid some ras operations from IP. | |
1485 | * if software itself, say boot parameter, limit the ras ability. We still | |
1486 | * need allow IP do some limited operations, like disable. In such case, | |
1487 | * we have to initialize ras as normal. but need check if operation is | |
1488 | * allowed or not in each function. | |
1489 | */ | |
1490 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | |
1491 | uint32_t *hw_supported, uint32_t *supported) | |
c030f2e4 | 1492 | { |
5caf466a | 1493 | *hw_supported = 0; |
1494 | *supported = 0; | |
c030f2e4 | 1495 | |
5caf466a | 1496 | if (amdgpu_sriov_vf(adev) || |
b404ae82 | 1497 | adev->asic_type != CHIP_VEGA20) |
5caf466a | 1498 | return; |
b404ae82 | 1499 | |
5d0f903f | 1500 | if (adev->is_atom_fw && |
1501 | (amdgpu_atomfirmware_mem_ecc_supported(adev) || | |
1502 | amdgpu_atomfirmware_sram_ecc_supported(adev))) | |
5caf466a | 1503 | *hw_supported = AMDGPU_RAS_BLOCK_MASK; |
b404ae82 | 1504 | |
5caf466a | 1505 | *supported = amdgpu_ras_enable == 0 ? |
1506 | 0 : *hw_supported & amdgpu_ras_mask; | |
c030f2e4 | 1507 | } |
1508 | ||
1509 | int amdgpu_ras_init(struct amdgpu_device *adev) | |
1510 | { | |
1511 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
c030f2e4 | 1512 | |
b404ae82 | 1513 | if (con) |
c030f2e4 | 1514 | return 0; |
1515 | ||
1516 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
1517 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
1518 | GFP_KERNEL|__GFP_ZERO); | |
1519 | if (!con) | |
1520 | return -ENOMEM; | |
1521 | ||
1522 | con->objs = (struct ras_manager *)(con + 1); | |
1523 | ||
1524 | amdgpu_ras_set_context(adev, con); | |
1525 | ||
5caf466a | 1526 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
1527 | &con->supported); | |
fb2a3607 HZ |
1528 | if (!con->hw_supported) { |
1529 | amdgpu_ras_set_context(adev, NULL); | |
1530 | kfree(con); | |
1531 | return 0; | |
1532 | } | |
1533 | ||
c030f2e4 | 1534 | con->features = 0; |
1535 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 1536 | /* Might need get this flag from vbios. */ |
1537 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 1538 | |
1539 | if (amdgpu_ras_recovery_init(adev)) | |
1540 | goto recovery_out; | |
1541 | ||
1542 | amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK; | |
1543 | ||
c030f2e4 | 1544 | if (amdgpu_ras_fs_init(adev)) |
1545 | goto fs_out; | |
1546 | ||
51437623 TZ |
1547 | /* ras init for each ras block */ |
1548 | if (adev->umc.funcs->ras_init) | |
1549 | adev->umc.funcs->ras_init(adev); | |
1550 | ||
5d0f903f | 1551 | DRM_INFO("RAS INFO: ras initialized successfully, " |
1552 | "hardware ability[%x] ras_mask[%x]\n", | |
1553 | con->hw_supported, con->supported); | |
c030f2e4 | 1554 | return 0; |
1555 | fs_out: | |
1556 | amdgpu_ras_recovery_fini(adev); | |
1557 | recovery_out: | |
1558 | amdgpu_ras_set_context(adev, NULL); | |
1559 | kfree(con); | |
1560 | ||
1561 | return -EINVAL; | |
1562 | } | |
1563 | ||
a564808e | 1564 | /* do some init work after IP late init as dependence. |
511fdbc3 | 1565 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 1566 | */ |
511fdbc3 | 1567 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 1568 | { |
1569 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1570 | struct ras_manager *obj, *tmp; | |
1571 | ||
1572 | if (!con) | |
1573 | return; | |
1574 | ||
108c6a63 | 1575 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 1576 | /* Set up all other IPs which are not implemented. There is a |
1577 | * tricky thing that IP's actual ras error type should be | |
1578 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
1579 | * ERROR_NONE make sense anyway. | |
1580 | */ | |
1581 | amdgpu_ras_enable_all_features(adev, 1); | |
1582 | ||
1583 | /* We enable ras on all hw_supported block, but as boot | |
1584 | * parameter might disable some of them and one or more IP has | |
1585 | * not implemented yet. So we disable them on behalf. | |
1586 | */ | |
108c6a63 | 1587 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
1588 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
1589 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
1590 | /* there should be no any reference. */ | |
1591 | WARN_ON(alive_obj(obj)); | |
1592 | } | |
191051a1 | 1593 | } |
108c6a63 | 1594 | } |
a564808e | 1595 | |
1596 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
1597 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1598 | /* setup ras obj state as disabled. | |
1599 | * for init_by_vbios case. | |
1600 | * if we want to enable ras, just enable it in a normal way. | |
1601 | * If we want do disable it, need setup ras obj as enabled, | |
1602 | * then issue another TA disable cmd. | |
1603 | * See feature_enable_on_boot | |
1604 | */ | |
1605 | amdgpu_ras_disable_all_features(adev, 1); | |
1606 | amdgpu_ras_reset_gpu(adev, 0); | |
1607 | } | |
108c6a63 | 1608 | } |
1609 | ||
511fdbc3 | 1610 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
1611 | { | |
1612 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1613 | ||
1614 | if (!con) | |
1615 | return; | |
1616 | ||
1617 | amdgpu_ras_disable_all_features(adev, 0); | |
1618 | /* Make sure all ras objects are disabled. */ | |
1619 | if (con->features) | |
1620 | amdgpu_ras_disable_all_features(adev, 1); | |
1621 | } | |
1622 | ||
c030f2e4 | 1623 | /* do some fini work before IP fini as dependence */ |
1624 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
1625 | { | |
1626 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1627 | ||
1628 | if (!con) | |
1629 | return 0; | |
1630 | ||
1631 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ | |
1632 | amdgpu_ras_disable_all_features(adev, 0); | |
1633 | amdgpu_ras_recovery_fini(adev); | |
1634 | return 0; | |
1635 | } | |
1636 | ||
1637 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
1638 | { | |
1639 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1640 | ||
1641 | if (!con) | |
1642 | return 0; | |
1643 | ||
1644 | amdgpu_ras_fs_fini(adev); | |
1645 | amdgpu_ras_interrupt_remove_all(adev); | |
1646 | ||
1647 | WARN(con->features, "Feature mask is not cleared"); | |
1648 | ||
1649 | if (con->features) | |
1650 | amdgpu_ras_disable_all_features(adev, 1); | |
1651 | ||
1652 | amdgpu_ras_set_context(adev, NULL); | |
1653 | kfree(con); | |
1654 | ||
1655 | return 0; | |
1656 | } |