[mirror_ubuntu-kernels.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ras.h

/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 *
 */
#ifndef _AMDGPU_RAS_H
#define _AMDGPU_RAS_H

#include <linux/debugfs.h>
#include <linux/list.h>
#include "amdgpu.h"
#include "amdgpu_psp.h"
#include "ta_ras_if.h"

enum amdgpu_ras_block {
	AMDGPU_RAS_BLOCK__UMC = 0,
	AMDGPU_RAS_BLOCK__SDMA,
	AMDGPU_RAS_BLOCK__GFX,
	AMDGPU_RAS_BLOCK__MMHUB,
	AMDGPU_RAS_BLOCK__ATHUB,
	AMDGPU_RAS_BLOCK__PCIE_BIF,
	AMDGPU_RAS_BLOCK__HDP,
	AMDGPU_RAS_BLOCK__XGMI_WAFL,
	AMDGPU_RAS_BLOCK__DF,
	AMDGPU_RAS_BLOCK__SMN,
	AMDGPU_RAS_BLOCK__SEM,
	AMDGPU_RAS_BLOCK__MP0,
	AMDGPU_RAS_BLOCK__MP1,
	AMDGPU_RAS_BLOCK__FUSE,

	AMDGPU_RAS_BLOCK__LAST
};

#define AMDGPU_RAS_BLOCK_COUNT	AMDGPU_RAS_BLOCK__LAST
#define AMDGPU_RAS_BLOCK_MASK	((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)

enum amdgpu_ras_gfx_subblock {
	/* CPC */
	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
	AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
		AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
		AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
	/* CPF */
	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
		AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
	AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
	/* CPG */
	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
		AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
	AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
	/* GDS */
	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
		AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
	/* SPI */
	AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
	/* SQ */
	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
	AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
	/* SQC (3 ranges) */
	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
	/* SQC range 0 */
	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
	/* SQC range 1 */
	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
	/* SQC range 2 */
	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
	/* TA */
	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
		AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
	AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
	AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
	AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
	/* TCA */
	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
		AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
		AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
	/* TCC (5 sub-ranges) */
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
	/* TCC range 0 */
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
	AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
	AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
		AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
	/* TCC range 1 */
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
		AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
	/* TCC range 2 */
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
	AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
		AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
	/* TCC range 3 */
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
		AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
	/* TCC range 4 */
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
	AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
	AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
		AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
	/* TCI */
	AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
	/* TCP */
	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
		AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
	AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
	AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
	AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
		AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
	/* TD */
	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
		AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
	AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
	/* EA (3 sub-ranges) */
	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
	/* EA range 0 */
	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
		AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
		AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
	/* EA range 1 */
	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
		AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
	/* EA range 2 */
	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
		AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
	/* UTC VM L2 bank */
	AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
	/* UTC VM walker */
	AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
	/* UTC ATC L2 2MB cache */
	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
	/* UTC ATC L2 4KB cache */
	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
	AMDGPU_RAS_BLOCK__GFX_MAX
};

enum amdgpu_ras_error_type {
	AMDGPU_RAS_ERROR__NONE							= 0,
	AMDGPU_RAS_ERROR__PARITY						= 1,
	AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE					= 2,
	AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE					= 4,
	AMDGPU_RAS_ERROR__POISON						= 8,
};

enum amdgpu_ras_ret {
	AMDGPU_RAS_SUCCESS = 0,
	AMDGPU_RAS_FAIL,
	AMDGPU_RAS_UE,
	AMDGPU_RAS_CE,
	AMDGPU_RAS_PT,
};

struct ras_common_if {
	enum amdgpu_ras_block block;
	enum amdgpu_ras_error_type type;
	uint32_t sub_block_index;
	/* block name */
	char name[32];
};

struct amdgpu_ras {
	/* ras infrastructure */
	/* for ras itself. */
	uint32_t hw_supported;
	/* for IP to check its ras ability. */
	uint32_t supported;
	uint32_t features;
	struct list_head head;
	/* debugfs */
	struct dentry *dir;
	/* debugfs ctrl */
	struct dentry *ent;
	/* sysfs */
	struct device_attribute features_attr;
	struct bin_attribute badpages_attr;
	/* block array */
	struct ras_manager *objs;

	/* gpu recovery */
	struct work_struct recovery_work;
	atomic_t in_recovery;
	struct amdgpu_device *adev;
	/* error handler data */
	struct ras_err_handler_data *eh_data;
	struct mutex recovery_lock;

	uint32_t flags;
};

struct ras_fs_data {
	char sysfs_name[32];
	char debugfs_name[32];
};

struct ras_err_data {
	unsigned long ue_count;
	unsigned long ce_count;
	unsigned long err_addr_cnt;
	uint64_t *err_addr;
};

struct ras_err_handler_data {
	/* point to bad pages array */
	struct {
		unsigned long bp;
		struct amdgpu_bo *bo;
	} *bps;
	/* the count of entries */
	int count;
	/* the space can place new entries */
	int space_left;
	/* last reserved entry's index + 1 */
	int last_reserved;
};

typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
		struct ras_err_data *err_data,
		struct amdgpu_iv_entry *entry);

struct ras_ih_data {
	/* interrupt bottom half */
	struct work_struct ih_work;
	int inuse;
	/* IP callback */
	ras_ih_cb cb;
	/* full of entries */
	unsigned char *ring;
	unsigned int ring_size;
	unsigned int element_size;
	unsigned int aligned_element_size;
	unsigned int rptr;
	unsigned int wptr;
};

struct ras_manager {
	struct ras_common_if head;
	/* reference count */
	int use;
	/* ras block link */
	struct list_head node;
	/* the device */
	struct amdgpu_device *adev;
	/* debugfs */
	struct dentry *ent;
	/* sysfs */
	struct device_attribute sysfs_attr;
	int attr_inuse;

	/* fs node name */
	struct ras_fs_data fs_data;

	/* IH data */
	struct ras_ih_data ih_data;

	struct ras_err_data err_data;
};

struct ras_badpage {
	unsigned int bp;
	unsigned int size;
	unsigned int flags;
};

/* interfaces for IP */
struct ras_fs_if {
	struct ras_common_if head;
	char sysfs_name[32];
	char debugfs_name[32];
};

struct ras_query_if {
	struct ras_common_if head;
	unsigned long ue_count;
	unsigned long ce_count;
};

struct ras_inject_if {
	struct ras_common_if head;
	uint64_t address;
	uint64_t value;
};

struct ras_cure_if {
	struct ras_common_if head;
	uint64_t address;
};

struct ras_ih_if {
	struct ras_common_if head;
	ras_ih_cb cb;
};

struct ras_dispatch_if {
	struct ras_common_if head;
	struct amdgpu_iv_entry *entry;
};

struct ras_debug_if {
	union {
		struct ras_common_if head;
		struct ras_inject_if inject;
	};
	int op;
};
/* work flow
 * vbios
 * 1: ras feature enable (enabled by default)
 * psp
 * 2: ras framework init (in ip_init)
 * IP
 * 3: IH add
 * 4: debugfs/sysfs create
 * 5: query/inject
 * 6: debugfs/sysfs remove
 * 7: IH remove
 * 8: feature disable
 */

#define amdgpu_ras_get_context(adev)		((adev)->psp.ras.ras)
#define amdgpu_ras_set_context(adev, ras_con)	((adev)->psp.ras.ras = (ras_con))

/* check if ras is supported on block, say, sdma, gfx */
static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
		unsigned int block)
{
	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);

	if (block >= AMDGPU_RAS_BLOCK_COUNT)
		return 0;
	return ras && (ras->supported & (1 << block));
}

int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
		unsigned int block);

void amdgpu_ras_resume(struct amdgpu_device *adev);
void amdgpu_ras_suspend(struct amdgpu_device *adev);

int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
		bool is_ce);

/* error handling functions */
int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
		unsigned long *bps, int pages);

int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev);

static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev,
		bool is_baco)
{
	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);

	if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
		schedule_work(&ras->recovery_work);
	return 0;
}

static inline enum ta_ras_block
amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
	switch (block) {
	case AMDGPU_RAS_BLOCK__UMC:
		return TA_RAS_BLOCK__UMC;
	case AMDGPU_RAS_BLOCK__SDMA:
		return TA_RAS_BLOCK__SDMA;
	case AMDGPU_RAS_BLOCK__GFX:
		return TA_RAS_BLOCK__GFX;
	case AMDGPU_RAS_BLOCK__MMHUB:
		return TA_RAS_BLOCK__MMHUB;
	case AMDGPU_RAS_BLOCK__ATHUB:
		return TA_RAS_BLOCK__ATHUB;
	case AMDGPU_RAS_BLOCK__PCIE_BIF:
		return TA_RAS_BLOCK__PCIE_BIF;
	case AMDGPU_RAS_BLOCK__HDP:
		return TA_RAS_BLOCK__HDP;
	case AMDGPU_RAS_BLOCK__XGMI_WAFL:
		return TA_RAS_BLOCK__XGMI_WAFL;
	case AMDGPU_RAS_BLOCK__DF:
		return TA_RAS_BLOCK__DF;
	case AMDGPU_RAS_BLOCK__SMN:
		return TA_RAS_BLOCK__SMN;
	case AMDGPU_RAS_BLOCK__SEM:
		return TA_RAS_BLOCK__SEM;
	case AMDGPU_RAS_BLOCK__MP0:
		return TA_RAS_BLOCK__MP0;
	case AMDGPU_RAS_BLOCK__MP1:
		return TA_RAS_BLOCK__MP1;
	case AMDGPU_RAS_BLOCK__FUSE:
		return TA_RAS_BLOCK__FUSE;
	default:
		WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
		return TA_RAS_BLOCK__UMC;
	}
}

static inline enum ta_ras_error_type
amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
	switch (error) {
	case AMDGPU_RAS_ERROR__NONE:
		return TA_RAS_ERROR__NONE;
	case AMDGPU_RAS_ERROR__PARITY:
		return TA_RAS_ERROR__PARITY;
	case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
		return TA_RAS_ERROR__SINGLE_CORRECTABLE;
	case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
		return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
	case AMDGPU_RAS_ERROR__POISON:
		return TA_RAS_ERROR__POISON;
	default:
		WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
		return TA_RAS_ERROR__NONE;
	}
}

/* called in ip_init and ip_fini */
int amdgpu_ras_init(struct amdgpu_device *adev);
int amdgpu_ras_fini(struct amdgpu_device *adev);
int amdgpu_ras_pre_fini(struct amdgpu_device *adev);

int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
		struct ras_common_if *head, bool enable);

int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
		struct ras_common_if *head, bool enable);

int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
		struct ras_fs_if *head);

int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
		struct ras_common_if *head);

void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
		struct ras_fs_if *head);

void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
		struct ras_common_if *head);

int amdgpu_ras_error_query(struct amdgpu_device *adev,
		struct ras_query_if *info);

int amdgpu_ras_error_inject(struct amdgpu_device *adev,
		struct ras_inject_if *info);

int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
		struct ras_ih_if *info);

int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
		struct ras_ih_if *info);

int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
		struct ras_dispatch_if *info);
#endif
Commit	Line	Data
c030f2e4	1	/*
	2	* Copyright 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*
	23	*/
	24	#ifndef _AMDGPU_RAS_H
	25	#define _AMDGPU_RAS_H
	26
	27	#include <linux/debugfs.h>
	28	#include <linux/list.h>
	29	#include "amdgpu.h"
	30	#include "amdgpu_psp.h"
	31	#include "ta_ras_if.h"
	32
	33	enum amdgpu_ras_block {
	34	AMDGPU_RAS_BLOCK__UMC = 0,
	35	AMDGPU_RAS_BLOCK__SDMA,
	36	AMDGPU_RAS_BLOCK__GFX,
	37	AMDGPU_RAS_BLOCK__MMHUB,
	38	AMDGPU_RAS_BLOCK__ATHUB,
	39	AMDGPU_RAS_BLOCK__PCIE_BIF,
	40	AMDGPU_RAS_BLOCK__HDP,
	41	AMDGPU_RAS_BLOCK__XGMI_WAFL,
	42	AMDGPU_RAS_BLOCK__DF,
	43	AMDGPU_RAS_BLOCK__SMN,
	44	AMDGPU_RAS_BLOCK__SEM,
	45	AMDGPU_RAS_BLOCK__MP0,
	46	AMDGPU_RAS_BLOCK__MP1,
	47	AMDGPU_RAS_BLOCK__FUSE,
	48
	49	AMDGPU_RAS_BLOCK__LAST
	50	};
	51
	52	#define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST
	53	#define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
	54
dc23a08f DL	55	enum amdgpu_ras_gfx_subblock {
	56	/* CPC */
	57	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
	58	AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
	59	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
	60	AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
	61	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
	62	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
	63	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
	64	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
	65	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
	66	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
	67	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
	68	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
	69	/* CPF */
	70	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
	71	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
	72	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
	73	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
	74	AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
	75	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
	76	/* CPG */
	77	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
	78	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
	79	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
	80	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
	81	AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
	82	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
	83	/* GDS */
	84	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
	85	AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
	86	AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
	87	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
	88	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
	89	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
	90	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
	91	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
	92	/* SPI */
	93	AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
	94	/* SQ */
	95	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
	96	AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
	97	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
	98	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
	99	AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
	100	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
	101	/* SQC (3 ranges) */
	102	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
	103	/* SQC range 0 */
	104	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
	105	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
	106	AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
	107	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
	108	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
	109	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
	110	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
	111	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
	112	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
	113	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
	114	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
	115	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
	116	/* SQC range 1 */
	117	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
	118	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
119	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
120	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
121	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
122	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
123	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
124	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
125	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
126	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
127	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
128	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
129	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
130	/* SQC range 2 */
131	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
132	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
133	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
134	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
135	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
136	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
137	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
138	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
139	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
140	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
141	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
142	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
143	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
144	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
145	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
146	/* TA */
147	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
148	AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
149	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
150	AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
151	AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
152	AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
153	AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
154	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
155	/* TCA */
156	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
157	AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
158	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
159	AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
160	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
161	AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
162	/* TCC (5 sub-ranges) */
163	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
164	/* TCC range 0 */
165	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
166	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
167	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
168	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
169	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
170	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
171	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
172	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
173	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
174	AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
175	AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
176	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
177	AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
178	/* TCC range 1 */
179	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
180	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
181	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
182	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
183	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
184	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
185	/* TCC range 2 */
186	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
187	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
188	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
189	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
190	AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
191	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
192	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
193	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
194	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
195	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
196	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
197	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
198	/* TCC range 3 */
199	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
200	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
201	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
202	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
203	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
204	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
205	/* TCC range 4 */
206	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
207	AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
208	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
209	AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
210	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
211	AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
212	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
213	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
214	/* TCI */
215	AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
216	/* TCP */
217	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
218	AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
219	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
220	AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
221	AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
222	AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
223	AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
224	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
225	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
226	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
227	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
228	/* TD */
229	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
230	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
231	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
232	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
233	AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
234	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
235	/* EA (3 sub-ranges) */
236	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
237	/* EA range 0 */
238	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
239	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
240	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
241	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
242	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
243	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
244	AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
245	AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
246	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
247	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
248	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
249	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
250	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
251	/* EA range 1 */
252	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
253	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
254	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
255	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
256	AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
257	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
258	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
259	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
260	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
261	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
262	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
263	/* EA range 2 */
264	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
265	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
266	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
267	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
268	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
269	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
270	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
271	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
272	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
273	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
274	/* UTC VM L2 bank */
275	AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
276	/* UTC VM walker */
277	AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
278	/* UTC ATC L2 2MB cache */
279	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
280	/* UTC ATC L2 4KB cache */
281	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
282	AMDGPU_RAS_BLOCK__GFX_MAX
283	};
284
c030f2e4	285	enum amdgpu_ras_error_type {
	286	AMDGPU_RAS_ERROR__NONE = 0,
	287	AMDGPU_RAS_ERROR__PARITY = 1,
	288	AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2,
	289	AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
	290	AMDGPU_RAS_ERROR__POISON = 8,
	291	};
	292
	293	enum amdgpu_ras_ret {
	294	AMDGPU_RAS_SUCCESS = 0,
	295	AMDGPU_RAS_FAIL,
	296	AMDGPU_RAS_UE,
	297	AMDGPU_RAS_CE,
	298	AMDGPU_RAS_PT,
	299	};
	300
	301	struct ras_common_if {
	302	enum amdgpu_ras_block block;
	303	enum amdgpu_ras_error_type type;
	304	uint32_t sub_block_index;
	305	/* block name */
	306	char name[32];
	307	};
	308
c030f2e4	309	struct amdgpu_ras {
c030f2e4	310	/* ras infrastructure */
5caf466a	311	/* for ras itself. */
	312	uint32_t hw_supported;
	313	/* for IP to check its ras ability. */
c030f2e4	314	uint32_t supported;
	315	uint32_t features;
	316	struct list_head head;
	317	/* debugfs */
	318	struct dentry *dir;
36ea1bd2	319	/* debugfs ctrl */
36ea1bd2	320	struct dentry *ent;
c030f2e4	321	/* sysfs */
c030f2e4	322	struct device_attribute features_attr;
466b1793	323	struct bin_attribute badpages_attr;
c030f2e4	324	/* block array */
	325	struct ras_manager *objs;
	326
	327	/* gpu recovery */
	328	struct work_struct recovery_work;
	329	atomic_t in_recovery;
	330	struct amdgpu_device *adev;
	331	/* error handler data */
	332	struct ras_err_handler_data *eh_data;
	333	struct mutex recovery_lock;
108c6a63	334
108c6a63	335	uint32_t flags;
c030f2e4	336	};
c030f2e4	337
7af25d5b HZ	338	struct ras_fs_data {
	339	char sysfs_name[32];
	340	char debugfs_name[32];
	341	};
	342
	343	struct ras_err_data {
	344	unsigned long ue_count;
	345	unsigned long ce_count;
6f102dba TZ	346	unsigned long err_addr_cnt;
6f102dba TZ	347	uint64_t *err_addr;
7af25d5b HZ	348	};
	349
	350	struct ras_err_handler_data {
	351	/* point to bad pages array */
	352	struct {
	353	unsigned long bp;
	354	struct amdgpu_bo *bo;
	355	} *bps;
	356	/* the count of entries */
	357	int count;
	358	/* the space can place new entries */
	359	int space_left;
	360	/* last reserved entry's index + 1 */
	361	int last_reserved;
	362	};
c030f2e4	363
cf04dfd0 TZ	364	typedef int (ras_ih_cb)(struct amdgpu_device adev,
	365	struct ras_err_data *err_data,
	366	struct amdgpu_iv_entry *entry);
	367
	368	struct ras_ih_data {
	369	/* interrupt bottom half */
	370	struct work_struct ih_work;
	371	int inuse;
	372	/* IP callback */
	373	ras_ih_cb cb;
	374	/* full of entries */
	375	unsigned char *ring;
	376	unsigned int ring_size;
	377	unsigned int element_size;
	378	unsigned int aligned_element_size;
	379	unsigned int rptr;
	380	unsigned int wptr;
	381	};
	382
7af25d5b HZ	383	struct ras_manager {
	384	struct ras_common_if head;
	385	/* reference count */
	386	int use;
	387	/* ras block link */
	388	struct list_head node;
	389	/* the device */
	390	struct amdgpu_device *adev;
	391	/* debugfs */
	392	struct dentry *ent;
	393	/* sysfs */
	394	struct device_attribute sysfs_attr;
	395	int attr_inuse;
	396
	397	/* fs node name */
	398	struct ras_fs_data fs_data;
	399
	400	/* IH data */
	401	struct ras_ih_data ih_data;
	402
	403	struct ras_err_data err_data;
	404	};
	405
	406	struct ras_badpage {
	407	unsigned int bp;
	408	unsigned int size;
	409	unsigned int flags;
	410	};
	411
	412	/* interfaces for IP */
c030f2e4	413	struct ras_fs_if {
	414	struct ras_common_if head;
	415	char sysfs_name[32];
	416	char debugfs_name[32];
	417	};
	418
	419	struct ras_query_if {
	420	struct ras_common_if head;
	421	unsigned long ue_count;
	422	unsigned long ce_count;
	423	};
	424
	425	struct ras_inject_if {
	426	struct ras_common_if head;
	427	uint64_t address;
	428	uint64_t value;
	429	};
	430
	431	struct ras_cure_if {
	432	struct ras_common_if head;
	433	uint64_t address;
	434	};
	435
	436	struct ras_ih_if {
	437	struct ras_common_if head;
	438	ras_ih_cb cb;
	439	};
	440
	441	struct ras_dispatch_if {
	442	struct ras_common_if head;
	443	struct amdgpu_iv_entry *entry;
	444	};
	445
36ea1bd2	446	struct ras_debug_if {
	447	union {
	448	struct ras_common_if head;
	449	struct ras_inject_if inject;
	450	};
	451	int op;
	452	};
c030f2e4	453	/* work flow
	454	* vbios
	455	* 1: ras feature enable (enabled by default)
	456	* psp
	457	* 2: ras framework init (in ip_init)
	458	* IP
	459	* 3: IH add
	460	* 4: debugfs/sysfs create
	461	* 5: query/inject
	462	* 6: debugfs/sysfs remove
	463	* 7: IH remove
	464	* 8: feature disable
	465	*/
	466
	467	#define amdgpu_ras_get_context(adev) ((adev)->psp.ras.ras)
	468	#define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras.ras = (ras_con))
	469
	470	/* check if ras is supported on block, say, sdma, gfx */
	471	static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
	472	unsigned int block)
	473	{
	474	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
	475
8252562d DC	476	if (block >= AMDGPU_RAS_BLOCK_COUNT)
8252562d DC	477	return 0;
c030f2e4	478	return ras && (ras->supported & (1 << block));
	479	}
	480
a564808e	481	int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
	482	unsigned int block);
	483
511fdbc3	484	void amdgpu_ras_resume(struct amdgpu_device *adev);
	485	void amdgpu_ras_suspend(struct amdgpu_device *adev);
	486
c030f2e4	487	int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
	488	bool is_ce);
	489
	490	/* error handling functions */
	491	int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
	492	unsigned long *bps, int pages);
	493
	494	int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev);
	495
	496	static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev,
	497	bool is_baco)
	498	{
	499	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
	500
	501	if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
	502	schedule_work(&ras->recovery_work);
	503	return 0;
	504	}
	505
828cfa29	506	static inline enum ta_ras_block
	507	amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
	508	switch (block) {
	509	case AMDGPU_RAS_BLOCK__UMC:
	510	return TA_RAS_BLOCK__UMC;
	511	case AMDGPU_RAS_BLOCK__SDMA:
	512	return TA_RAS_BLOCK__SDMA;
	513	case AMDGPU_RAS_BLOCK__GFX:
	514	return TA_RAS_BLOCK__GFX;
	515	case AMDGPU_RAS_BLOCK__MMHUB:
	516	return TA_RAS_BLOCK__MMHUB;
	517	case AMDGPU_RAS_BLOCK__ATHUB:
	518	return TA_RAS_BLOCK__ATHUB;
	519	case AMDGPU_RAS_BLOCK__PCIE_BIF:
	520	return TA_RAS_BLOCK__PCIE_BIF;
	521	case AMDGPU_RAS_BLOCK__HDP:
	522	return TA_RAS_BLOCK__HDP;
	523	case AMDGPU_RAS_BLOCK__XGMI_WAFL:
	524	return TA_RAS_BLOCK__XGMI_WAFL;
	525	case AMDGPU_RAS_BLOCK__DF:
	526	return TA_RAS_BLOCK__DF;
	527	case AMDGPU_RAS_BLOCK__SMN:
	528	return TA_RAS_BLOCK__SMN;
	529	case AMDGPU_RAS_BLOCK__SEM:
	530	return TA_RAS_BLOCK__SEM;
	531	case AMDGPU_RAS_BLOCK__MP0:
	532	return TA_RAS_BLOCK__MP0;
	533	case AMDGPU_RAS_BLOCK__MP1:
	534	return TA_RAS_BLOCK__MP1;
	535	case AMDGPU_RAS_BLOCK__FUSE:
	536	return TA_RAS_BLOCK__FUSE;
	537	default:
	538	WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
	539	return TA_RAS_BLOCK__UMC;
	540	}
	541	}
	542
	543	static inline enum ta_ras_error_type
	544	amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
	545	switch (error) {
	546	case AMDGPU_RAS_ERROR__NONE:
	547	return TA_RAS_ERROR__NONE;
	548	case AMDGPU_RAS_ERROR__PARITY:
	549	return TA_RAS_ERROR__PARITY;
	550	case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
	551	return TA_RAS_ERROR__SINGLE_CORRECTABLE;
	552	case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
	553	return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
	554	case AMDGPU_RAS_ERROR__POISON:
	555	return TA_RAS_ERROR__POISON;
	556	default:
	557	WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
	558	return TA_RAS_ERROR__NONE;
	559	}
	560	}
	561
c030f2e4	562	/* called in ip_init and ip_fini */
	563	int amdgpu_ras_init(struct amdgpu_device *adev);
	564	int amdgpu_ras_fini(struct amdgpu_device *adev);
	565	int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
	566
	567	int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
	568	struct ras_common_if *head, bool enable);
	569
77de502b	570	int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
	571	struct ras_common_if *head, bool enable);
	572
c030f2e4	573	int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
	574	struct ras_fs_if *head);
	575
	576	int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
	577	struct ras_common_if *head);
	578
450f30ea	579	void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
c030f2e4	580	struct ras_fs_if *head);
c030f2e4	581
450f30ea	582	void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
c030f2e4	583	struct ras_common_if *head);
	584
	585	int amdgpu_ras_error_query(struct amdgpu_device *adev,
	586	struct ras_query_if *info);
	587
	588	int amdgpu_ras_error_inject(struct amdgpu_device *adev,
	589	struct ras_inject_if *info);
	590
	591	int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
	592	struct ras_ih_if *info);
	593
	594	int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
	595	struct ras_ih_if *info);
	596
	597	int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
	598	struct ras_dispatch_if *info);
	599	#endif