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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | * Christian König | |
28 | */ | |
29 | #include <linux/seq_file.h> | |
30 | #include <linux/slab.h> | |
fdf2f6c5 | 31 | #include <linux/uaccess.h> |
4f4824b5 | 32 | #include <linux/debugfs.h> |
fdf2f6c5 | 33 | |
d38ceaf9 AD |
34 | #include <drm/amdgpu_drm.h> |
35 | #include "amdgpu.h" | |
36 | #include "atom.h" | |
37 | ||
38 | /* | |
39 | * Rings | |
40 | * Most engines on the GPU are fed via ring buffers. Ring | |
41 | * buffers are areas of GPU accessible memory that the host | |
42 | * writes commands into and the GPU reads commands out of. | |
43 | * There is a rptr (read pointer) that determines where the | |
44 | * GPU is currently reading, and a wptr (write pointer) | |
45 | * which determines where the host has written. When the | |
46 | * pointers are equal, the ring is idle. When the host | |
47 | * writes commands to the ring buffer, it increments the | |
48 | * wptr. The GPU then starts fetching commands and executes | |
49 | * them until the pointers are equal again. | |
50 | */ | |
d38ceaf9 | 51 | |
d38ceaf9 AD |
52 | /** |
53 | * amdgpu_ring_alloc - allocate space on the ring buffer | |
54 | * | |
55 | * @adev: amdgpu_device pointer | |
56 | * @ring: amdgpu_ring structure holding ring information | |
57 | * @ndw: number of dwords to allocate in the ring buffer | |
58 | * | |
59 | * Allocate @ndw dwords in the ring buffer (all asics). | |
60 | * Returns 0 on success, error on failure. | |
61 | */ | |
62 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw) | |
63 | { | |
d38ceaf9 AD |
64 | /* Align requested size with padding so unlock_commit can |
65 | * pad safely */ | |
79887142 | 66 | ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; |
c7e6be23 CK |
67 | |
68 | /* Make sure we aren't trying to allocate more space | |
69 | * than the maximum for one submission | |
70 | */ | |
71 | if (WARN_ON_ONCE(ndw > ring->max_dw)) | |
72 | return -ENOMEM; | |
73 | ||
d38ceaf9 AD |
74 | ring->count_dw = ndw; |
75 | ring->wptr_old = ring->wptr; | |
f06505b8 CK |
76 | |
77 | if (ring->funcs->begin_use) | |
78 | ring->funcs->begin_use(ring); | |
79 | ||
d38ceaf9 AD |
80 | return 0; |
81 | } | |
82 | ||
edff0e28 JZ |
83 | /** amdgpu_ring_insert_nop - insert NOP packets |
84 | * | |
85 | * @ring: amdgpu_ring structure holding ring information | |
86 | * @count: the number of NOP packets to insert | |
87 | * | |
88 | * This is the generic insert_nop function for rings except SDMA | |
89 | */ | |
90 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) | |
91 | { | |
92 | int i; | |
93 | ||
94 | for (i = 0; i < count; i++) | |
79887142 | 95 | amdgpu_ring_write(ring, ring->funcs->nop); |
edff0e28 JZ |
96 | } |
97 | ||
9e5d5309 CK |
98 | /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets |
99 | * | |
100 | * @ring: amdgpu_ring structure holding ring information | |
101 | * @ib: IB to add NOP packets to | |
102 | * | |
103 | * This is the generic pad_ib function for rings except SDMA | |
104 | */ | |
105 | void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) | |
106 | { | |
79887142 CK |
107 | while (ib->length_dw & ring->funcs->align_mask) |
108 | ib->ptr[ib->length_dw++] = ring->funcs->nop; | |
9e5d5309 CK |
109 | } |
110 | ||
d38ceaf9 AD |
111 | /** |
112 | * amdgpu_ring_commit - tell the GPU to execute the new | |
113 | * commands on the ring buffer | |
114 | * | |
115 | * @adev: amdgpu_device pointer | |
116 | * @ring: amdgpu_ring structure holding ring information | |
117 | * | |
118 | * Update the wptr (write pointer) to tell the GPU to | |
119 | * execute new commands on the ring buffer (all asics). | |
120 | */ | |
121 | void amdgpu_ring_commit(struct amdgpu_ring *ring) | |
122 | { | |
edff0e28 JZ |
123 | uint32_t count; |
124 | ||
d38ceaf9 | 125 | /* We pad to match fetch size */ |
79887142 CK |
126 | count = ring->funcs->align_mask + 1 - |
127 | (ring->wptr & ring->funcs->align_mask); | |
128 | count %= ring->funcs->align_mask + 1; | |
edff0e28 JZ |
129 | ring->funcs->insert_nop(ring, count); |
130 | ||
d38ceaf9 AD |
131 | mb(); |
132 | amdgpu_ring_set_wptr(ring); | |
f06505b8 CK |
133 | |
134 | if (ring->funcs->end_use) | |
135 | ring->funcs->end_use(ring); | |
d38ceaf9 AD |
136 | } |
137 | ||
d38ceaf9 AD |
138 | /** |
139 | * amdgpu_ring_undo - reset the wptr | |
140 | * | |
141 | * @ring: amdgpu_ring structure holding ring information | |
142 | * | |
143 | * Reset the driver's copy of the wptr (all asics). | |
144 | */ | |
145 | void amdgpu_ring_undo(struct amdgpu_ring *ring) | |
146 | { | |
147 | ring->wptr = ring->wptr_old; | |
f06505b8 CK |
148 | |
149 | if (ring->funcs->end_use) | |
150 | ring->funcs->end_use(ring); | |
d38ceaf9 AD |
151 | } |
152 | ||
d38ceaf9 AD |
153 | /** |
154 | * amdgpu_ring_init - init driver ring struct. | |
155 | * | |
156 | * @adev: amdgpu_device pointer | |
157 | * @ring: amdgpu_ring structure holding ring information | |
a3f1cf35 | 158 | * @max_ndw: maximum number of dw for ring alloc |
d38ceaf9 AD |
159 | * @nop: nop packet for this ring |
160 | * | |
161 | * Initialize the driver information for the selected ring (all asics). | |
162 | * Returns 0 on success, error on failure. | |
163 | */ | |
164 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, | |
1c6d567b ND |
165 | unsigned int max_dw, struct amdgpu_irq_src *irq_src, |
166 | unsigned int irq_type, unsigned int hw_prio) | |
d38ceaf9 | 167 | { |
b2ff0e8a | 168 | int r, i; |
b249e18d | 169 | int sched_hw_submission = amdgpu_sched_hw_submission; |
1c6d567b ND |
170 | u32 *num_sched; |
171 | u32 hw_ip; | |
b249e18d AD |
172 | |
173 | /* Set the hw submission limit higher for KIQ because | |
174 | * it's used for a number of gfx/compute tasks by both | |
175 | * KFD and KGD which may have outstanding fences and | |
176 | * it doesn't really use the gpu scheduler anyway; | |
177 | * KIQ tasks get submitted directly to the ring. | |
178 | */ | |
179 | if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) | |
180 | sched_hw_submission = max(sched_hw_submission, 256); | |
1d31408a CK |
181 | else if (ring == &adev->sdma.instance[0].page) |
182 | sched_hw_submission = 256; | |
d38ceaf9 AD |
183 | |
184 | if (ring->adev == NULL) { | |
185 | if (adev->num_rings >= AMDGPU_MAX_RINGS) | |
186 | return -EINVAL; | |
187 | ||
188 | ring->adev = adev; | |
189 | ring->idx = adev->num_rings++; | |
190 | adev->rings[ring->idx] = ring; | |
b249e18d | 191 | r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission); |
4f839a24 CK |
192 | if (r) |
193 | return r; | |
d38ceaf9 AD |
194 | } |
195 | ||
131b4b36 | 196 | r = amdgpu_device_wb_get(adev, &ring->rptr_offs); |
97407b63 AD |
197 | if (r) { |
198 | dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); | |
199 | return r; | |
d38ceaf9 AD |
200 | } |
201 | ||
131b4b36 | 202 | r = amdgpu_device_wb_get(adev, &ring->wptr_offs); |
97407b63 AD |
203 | if (r) { |
204 | dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); | |
205 | return r; | |
206 | } | |
0915fdbc | 207 | |
131b4b36 | 208 | r = amdgpu_device_wb_get(adev, &ring->fence_offs); |
97407b63 AD |
209 | if (r) { |
210 | dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); | |
211 | return r; | |
d38ceaf9 AD |
212 | } |
213 | ||
ef3e1323 JX |
214 | r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs); |
215 | if (r) { | |
216 | dev_err(adev->dev, | |
217 | "(%d) ring trail_fence_offs wb alloc failed\n", r); | |
218 | return r; | |
219 | } | |
220 | ring->trail_fence_gpu_addr = | |
221 | adev->wb.gpu_addr + (ring->trail_fence_offs * 4); | |
222 | ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs]; | |
223 | ||
131b4b36 | 224 | r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs); |
128cff1a ML |
225 | if (r) { |
226 | dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); | |
227 | return r; | |
228 | } | |
229 | ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4); | |
230 | ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs]; | |
714fbf80 ML |
231 | /* always set cond_exec_polling to CONTINUE */ |
232 | *ring->cond_exe_cpu_addr = 1; | |
128cff1a | 233 | |
d38ceaf9 AD |
234 | r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type); |
235 | if (r) { | |
236 | dev_err(adev->dev, "failed initializing fences (%d).\n", r); | |
237 | return r; | |
238 | } | |
239 | ||
b249e18d | 240 | ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission); |
d38ceaf9 | 241 | |
e09706f4 ML |
242 | ring->buf_mask = (ring->ring_size / 4) - 1; |
243 | ring->ptr_mask = ring->funcs->support_64bit_ptrs ? | |
244 | 0xffffffffffffffff : ring->buf_mask; | |
d38ceaf9 AD |
245 | /* Allocate ring buffer */ |
246 | if (ring->ring_obj == NULL) { | |
c8c1a1d2 | 247 | r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE, |
37ac235b CK |
248 | AMDGPU_GEM_DOMAIN_GTT, |
249 | &ring->ring_obj, | |
250 | &ring->gpu_addr, | |
251 | (void **)&ring->ring); | |
d38ceaf9 AD |
252 | if (r) { |
253 | dev_err(adev->dev, "(%d) ring create failed\n", r); | |
254 | return r; | |
255 | } | |
f6bd7942 | 256 | amdgpu_ring_clear_ring(ring); |
d38ceaf9 | 257 | } |
536fbf94 | 258 | |
a3f1cf35 | 259 | ring->max_dw = max_dw; |
1b1f42d8 | 260 | ring->priority = DRM_SCHED_PRIORITY_NORMAL; |
b2ff0e8a | 261 | mutex_init(&ring->priority_mutex); |
d38ceaf9 | 262 | |
a4c24680 | 263 | if (!ring->no_scheduler) { |
1c6d567b ND |
264 | hw_ip = ring->funcs->type; |
265 | num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds; | |
266 | adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] = | |
267 | &ring->sched; | |
268 | } | |
269 | ||
1b1f42d8 | 270 | for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i) |
b2ff0e8a AR |
271 | atomic_set(&ring->num_jobs[i], 0); |
272 | ||
d38ceaf9 AD |
273 | return 0; |
274 | } | |
275 | ||
276 | /** | |
277 | * amdgpu_ring_fini - tear down the driver ring struct. | |
278 | * | |
279 | * @adev: amdgpu_device pointer | |
280 | * @ring: amdgpu_ring structure holding ring information | |
281 | * | |
282 | * Tear down the driver information for the selected ring (all asics). | |
283 | */ | |
284 | void amdgpu_ring_fini(struct amdgpu_ring *ring) | |
285 | { | |
d38ceaf9 | 286 | |
41cc07cf TH |
287 | /* Not to finish a ring which is not initialized */ |
288 | if (!(ring->adev) || !(ring->adev->rings[ring->idx])) | |
289 | return; | |
290 | ||
6f9f9604 ND |
291 | ring->sched.ready = false; |
292 | ||
131b4b36 AD |
293 | amdgpu_device_wb_free(ring->adev, ring->rptr_offs); |
294 | amdgpu_device_wb_free(ring->adev, ring->wptr_offs); | |
7014285a | 295 | |
131b4b36 AD |
296 | amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs); |
297 | amdgpu_device_wb_free(ring->adev, ring->fence_offs); | |
d38ceaf9 | 298 | |
8640faed JZ |
299 | amdgpu_bo_free_kernel(&ring->ring_obj, |
300 | &ring->gpu_addr, | |
301 | (void **)&ring->ring); | |
302 | ||
3af81440 CK |
303 | dma_fence_put(ring->vmid_wait); |
304 | ring->vmid_wait = NULL; | |
10dd74ea | 305 | ring->me = 0; |
3af81440 | 306 | |
d8907643 | 307 | ring->adev->rings[ring->idx] = NULL; |
d38ceaf9 AD |
308 | } |
309 | ||
82853638 AD |
310 | /** |
311 | * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper | |
312 | * | |
313 | * @adev: amdgpu_device pointer | |
314 | * @reg0: register to write | |
315 | * @reg1: register to wait on | |
316 | * @ref: reference value to write/wait on | |
317 | * @mask: mask to wait on | |
318 | * | |
319 | * Helper for rings that don't support write and wait in a | |
320 | * single oneshot packet. | |
321 | */ | |
322 | void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, | |
323 | uint32_t reg0, uint32_t reg1, | |
324 | uint32_t ref, uint32_t mask) | |
325 | { | |
326 | amdgpu_ring_emit_wreg(ring, reg0, ref); | |
327 | amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); | |
328 | } | |
329 | ||
7876fa4f CK |
330 | /** |
331 | * amdgpu_ring_soft_recovery - try to soft recover a ring lockup | |
332 | * | |
333 | * @ring: ring to try the recovery on | |
334 | * @vmid: VMID we try to get going again | |
335 | * @fence: timedout fence | |
336 | * | |
337 | * Tries to get a ring proceeding again when it is stuck. | |
338 | */ | |
339 | bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, | |
340 | struct dma_fence *fence) | |
341 | { | |
342 | ktime_t deadline = ktime_add_us(ktime_get(), 10000); | |
343 | ||
ae1589f6 | 344 | if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence) |
7876fa4f CK |
345 | return false; |
346 | ||
347 | atomic_inc(&ring->adev->gpu_reset_counter); | |
348 | while (!dma_fence_is_signaled(fence) && | |
349 | ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0) | |
350 | ring->funcs->soft_recovery(ring, vmid); | |
351 | ||
352 | return dma_fence_is_signaled(fence); | |
353 | } | |
354 | ||
d38ceaf9 AD |
355 | /* |
356 | * Debugfs info | |
357 | */ | |
358 | #if defined(CONFIG_DEBUG_FS) | |
359 | ||
4f4824b5 TSD |
360 | /* Layout of file is 12 bytes consisting of |
361 | * - rptr | |
362 | * - wptr | |
363 | * - driver's copy of wptr | |
364 | * | |
365 | * followed by n-words of ring data | |
366 | */ | |
367 | static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, | |
368 | size_t size, loff_t *pos) | |
d38ceaf9 | 369 | { |
45063097 | 370 | struct amdgpu_ring *ring = file_inode(f)->i_private; |
4f4824b5 TSD |
371 | int r, i; |
372 | uint32_t value, result, early[3]; | |
373 | ||
c71dbd93 | 374 | if (*pos & 3 || size & 3) |
4f4824b5 TSD |
375 | return -EINVAL; |
376 | ||
377 | result = 0; | |
378 | ||
379 | if (*pos < 12) { | |
9c5c71bb | 380 | early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; |
ec63982e TSD |
381 | early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; |
382 | early[2] = ring->wptr & ring->buf_mask; | |
4f4824b5 TSD |
383 | for (i = *pos / 4; i < 3 && size; i++) { |
384 | r = put_user(early[i], (uint32_t *)buf); | |
385 | if (r) | |
386 | return r; | |
387 | buf += 4; | |
388 | result += 4; | |
389 | size -= 4; | |
390 | *pos += 4; | |
391 | } | |
c7e6be23 | 392 | } |
4f4824b5 TSD |
393 | |
394 | while (size) { | |
395 | if (*pos >= (ring->ring_size + 12)) | |
396 | return result; | |
714fbf80 | 397 | |
4f4824b5 TSD |
398 | value = ring->ring[(*pos - 12)/4]; |
399 | r = put_user(value, (uint32_t*)buf); | |
400 | if (r) | |
401 | return r; | |
402 | buf += 4; | |
403 | result += 4; | |
404 | size -= 4; | |
405 | *pos += 4; | |
d38ceaf9 | 406 | } |
4f4824b5 TSD |
407 | |
408 | return result; | |
d38ceaf9 AD |
409 | } |
410 | ||
4f4824b5 TSD |
411 | static const struct file_operations amdgpu_debugfs_ring_fops = { |
412 | .owner = THIS_MODULE, | |
413 | .read = amdgpu_debugfs_ring_read, | |
414 | .llseek = default_llseek | |
415 | }; | |
d38ceaf9 AD |
416 | |
417 | #endif | |
418 | ||
fd23cfcc AD |
419 | int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, |
420 | struct amdgpu_ring *ring) | |
d38ceaf9 AD |
421 | { |
422 | #if defined(CONFIG_DEBUG_FS) | |
4f4824b5 TSD |
423 | struct drm_minor *minor = adev->ddev->primary; |
424 | struct dentry *ent, *root = minor->debugfs_root; | |
425 | char name[32]; | |
d38ceaf9 | 426 | |
771c8ec1 | 427 | sprintf(name, "amdgpu_ring_%s", ring->name); |
771c8ec1 | 428 | |
4f4824b5 TSD |
429 | ent = debugfs_create_file(name, |
430 | S_IFREG | S_IRUGO, root, | |
431 | ring, &amdgpu_debugfs_ring_fops); | |
eeb2fa0c DC |
432 | if (!ent) |
433 | return -ENOMEM; | |
4f4824b5 TSD |
434 | |
435 | i_size_write(ent->d_inode, ring->ring_size + 12); | |
a909c6bd | 436 | ring->ent = ent; |
d38ceaf9 AD |
437 | #endif |
438 | return 0; | |
439 | } | |
a909c6bd | 440 | |
c66ed765 AG |
441 | /** |
442 | * amdgpu_ring_test_helper - tests ring and set sched readiness status | |
443 | * | |
444 | * @ring: ring to try the recovery on | |
445 | * | |
446 | * Tests ring and set sched readiness status | |
447 | * | |
448 | * Returns 0 on success, error on failure. | |
449 | */ | |
450 | int amdgpu_ring_test_helper(struct amdgpu_ring *ring) | |
451 | { | |
dc9eeff8 | 452 | struct amdgpu_device *adev = ring->adev; |
c66ed765 AG |
453 | int r; |
454 | ||
455 | r = amdgpu_ring_test_ring(ring); | |
dc9eeff8 CK |
456 | if (r) |
457 | DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n", | |
458 | ring->name, r); | |
459 | else | |
460 | DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n", | |
461 | ring->name); | |
c66ed765 AG |
462 | |
463 | ring->sched.ready = !r; | |
c66ed765 AG |
464 | return r; |
465 | } |