[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ring.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 *          Christian König
 */
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/debugfs.h>

#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "atom.h"

/*
 * Rings
 * Most engines on the GPU are fed via ring buffers.  Ring
 * buffers are areas of GPU accessible memory that the host
 * writes commands into and the GPU reads commands out of.
 * There is a rptr (read pointer) that determines where the
 * GPU is currently reading, and a wptr (write pointer)
 * which determines where the host has written.  When the
 * pointers are equal, the ring is idle.  When the host
 * writes commands to the ring buffer, it increments the
 * wptr.  The GPU then starts fetching commands and executes
 * them until the pointers are equal again.
 */

/**
 * amdgpu_ring_alloc - allocate space on the ring buffer
 *
 * @adev: amdgpu_device pointer
 * @ring: amdgpu_ring structure holding ring information
 * @ndw: number of dwords to allocate in the ring buffer
 *
 * Allocate @ndw dwords in the ring buffer (all asics).
 * Returns 0 on success, error on failure.
 */
int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
{
	/* Align requested size with padding so unlock_commit can
	 * pad safely */
	ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;

	/* Make sure we aren't trying to allocate more space
	 * than the maximum for one submission
	 */
	if (WARN_ON_ONCE(ndw > ring->max_dw))
		return -ENOMEM;

	ring->count_dw = ndw;
	ring->wptr_old = ring->wptr;

	if (ring->funcs->begin_use)
		ring->funcs->begin_use(ring);

	return 0;
}

/** amdgpu_ring_insert_nop - insert NOP packets
 *
 * @ring: amdgpu_ring structure holding ring information
 * @count: the number of NOP packets to insert
 *
 * This is the generic insert_nop function for rings except SDMA
 */
void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
{
	int i;

	for (i = 0; i < count; i++)
		amdgpu_ring_write(ring, ring->funcs->nop);
}

/** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
 *
 * @ring: amdgpu_ring structure holding ring information
 * @ib: IB to add NOP packets to
 *
 * This is the generic pad_ib function for rings except SDMA
 */
void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
{
	while (ib->length_dw & ring->funcs->align_mask)
		ib->ptr[ib->length_dw++] = ring->funcs->nop;
}

/**
 * amdgpu_ring_commit - tell the GPU to execute the new
 * commands on the ring buffer
 *
 * @adev: amdgpu_device pointer
 * @ring: amdgpu_ring structure holding ring information
 *
 * Update the wptr (write pointer) to tell the GPU to
 * execute new commands on the ring buffer (all asics).
 */
void amdgpu_ring_commit(struct amdgpu_ring *ring)
{
	uint32_t count;

	/* We pad to match fetch size */
	count = ring->funcs->align_mask + 1 -
		(ring->wptr & ring->funcs->align_mask);
	count %= ring->funcs->align_mask + 1;
	ring->funcs->insert_nop(ring, count);

	mb();
	amdgpu_ring_set_wptr(ring);

	if (ring->funcs->end_use)
		ring->funcs->end_use(ring);
}

/**
 * amdgpu_ring_undo - reset the wptr
 *
 * @ring: amdgpu_ring structure holding ring information
 *
 * Reset the driver's copy of the wptr (all asics).
 */
void amdgpu_ring_undo(struct amdgpu_ring *ring)
{
	ring->wptr = ring->wptr_old;

	if (ring->funcs->end_use)
		ring->funcs->end_use(ring);
}

/**
 * amdgpu_ring_init - init driver ring struct.
 *
 * @adev: amdgpu_device pointer
 * @ring: amdgpu_ring structure holding ring information
 * @max_ndw: maximum number of dw for ring alloc
 * @nop: nop packet for this ring
 *
 * Initialize the driver information for the selected ring (all asics).
 * Returns 0 on success, error on failure.
 */
int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
		     unsigned max_dw, struct amdgpu_irq_src *irq_src,
		     unsigned irq_type)
{
	int r, i;
	int sched_hw_submission = amdgpu_sched_hw_submission;

	/* Set the hw submission limit higher for KIQ because
	 * it's used for a number of gfx/compute tasks by both
	 * KFD and KGD which may have outstanding fences and
	 * it doesn't really use the gpu scheduler anyway;
	 * KIQ tasks get submitted directly to the ring.
	 */
	if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
		sched_hw_submission = max(sched_hw_submission, 256);
	else if (ring == &adev->sdma.instance[0].page)
		sched_hw_submission = 256;

	if (ring->adev == NULL) {
		if (adev->num_rings >= AMDGPU_MAX_RINGS)
			return -EINVAL;

		ring->adev = adev;
		ring->idx = adev->num_rings++;
		adev->rings[ring->idx] = ring;
		r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
		if (r)
			return r;
	}

	r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
	if (r) {
		dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
		return r;
	}

	r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
	if (r) {
		dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
		return r;
	}

	r = amdgpu_device_wb_get(adev, &ring->fence_offs);
	if (r) {
		dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
		return r;
	}

	r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
	if (r) {
		dev_err(adev->dev,
			"(%d) ring trail_fence_offs wb alloc failed\n", r);
		return r;
	}
	ring->trail_fence_gpu_addr =
		adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
	ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];

	r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
	if (r) {
		dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
		return r;
	}
	ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
	ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
	/* always set cond_exec_polling to CONTINUE */
	*ring->cond_exe_cpu_addr = 1;

	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
	if (r) {
		dev_err(adev->dev, "failed initializing fences (%d).\n", r);
		return r;
	}

	ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);

	ring->buf_mask = (ring->ring_size / 4) - 1;
	ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
		0xffffffffffffffff : ring->buf_mask;
	/* Allocate ring buffer */
	if (ring->ring_obj == NULL) {
		r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
					    AMDGPU_GEM_DOMAIN_GTT,
					    &ring->ring_obj,
					    &ring->gpu_addr,
					    (void **)&ring->ring);
		if (r) {
			dev_err(adev->dev, "(%d) ring create failed\n", r);
			return r;
		}
		amdgpu_ring_clear_ring(ring);
	}

	ring->max_dw = max_dw;
	ring->priority = DRM_SCHED_PRIORITY_NORMAL;
	mutex_init(&ring->priority_mutex);

	for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
		atomic_set(&ring->num_jobs[i], 0);

	return 0;
}

/**
 * amdgpu_ring_fini - tear down the driver ring struct.
 *
 * @adev: amdgpu_device pointer
 * @ring: amdgpu_ring structure holding ring information
 *
 * Tear down the driver information for the selected ring (all asics).
 */
void amdgpu_ring_fini(struct amdgpu_ring *ring)
{

	/* Not to finish a ring which is not initialized */
	if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
		return;

	ring->sched.ready = false;

	amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
	amdgpu_device_wb_free(ring->adev, ring->wptr_offs);

	amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
	amdgpu_device_wb_free(ring->adev, ring->fence_offs);

	amdgpu_bo_free_kernel(&ring->ring_obj,
			      &ring->gpu_addr,
			      (void **)&ring->ring);

	dma_fence_put(ring->vmid_wait);
	ring->vmid_wait = NULL;
	ring->me = 0;

	ring->adev->rings[ring->idx] = NULL;
}

/**
 * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
 *
 * @adev: amdgpu_device pointer
 * @reg0: register to write
 * @reg1: register to wait on
 * @ref: reference value to write/wait on
 * @mask: mask to wait on
 *
 * Helper for rings that don't support write and wait in a
 * single oneshot packet.
 */
void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
						uint32_t reg0, uint32_t reg1,
						uint32_t ref, uint32_t mask)
{
	amdgpu_ring_emit_wreg(ring, reg0, ref);
	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
}

/**
 * amdgpu_ring_soft_recovery - try to soft recover a ring lockup
 *
 * @ring: ring to try the recovery on
 * @vmid: VMID we try to get going again
 * @fence: timedout fence
 *
 * Tries to get a ring proceeding again when it is stuck.
 */
bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
			       struct dma_fence *fence)
{
	ktime_t deadline = ktime_add_us(ktime_get(), 10000);

	if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
		return false;

	atomic_inc(&ring->adev->gpu_reset_counter);
	while (!dma_fence_is_signaled(fence) &&
	       ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
		ring->funcs->soft_recovery(ring, vmid);

	return dma_fence_is_signaled(fence);
}

/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)

/* Layout of file is 12 bytes consisting of
 * - rptr
 * - wptr
 * - driver's copy of wptr
 *
 * followed by n-words of ring data
 */
static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
					size_t size, loff_t *pos)
{
	struct amdgpu_ring *ring = file_inode(f)->i_private;
	int r, i;
	uint32_t value, result, early[3];

	if (*pos & 3 || size & 3)
		return -EINVAL;

	result = 0;

	if (*pos < 12) {
		early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
		early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
		early[2] = ring->wptr & ring->buf_mask;
		for (i = *pos / 4; i < 3 && size; i++) {
			r = put_user(early[i], (uint32_t *)buf);
			if (r)
				return r;
			buf += 4;
			result += 4;
			size -= 4;
			*pos += 4;
		}
	}

	while (size) {
		if (*pos >= (ring->ring_size + 12))
			return result;

		value = ring->ring[(*pos - 12)/4];
		r = put_user(value, (uint32_t*)buf);
		if (r)
			return r;
		buf += 4;
		result += 4;
		size -= 4;
		*pos += 4;
	}

	return result;
}

static const struct file_operations amdgpu_debugfs_ring_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_debugfs_ring_read,
	.llseek = default_llseek
};

#endif

int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
			     struct amdgpu_ring *ring)
{
#if defined(CONFIG_DEBUG_FS)
	struct drm_minor *minor = adev->ddev->primary;
	struct dentry *ent, *root = minor->debugfs_root;
	char name[32];

	sprintf(name, "amdgpu_ring_%s", ring->name);

	ent = debugfs_create_file(name,
				  S_IFREG | S_IRUGO, root,
				  ring, &amdgpu_debugfs_ring_fops);
	if (!ent)
		return -ENOMEM;

	i_size_write(ent->d_inode, ring->ring_size + 12);
	ring->ent = ent;
#endif
	return 0;
}

/**
 * amdgpu_ring_test_helper - tests ring and set sched readiness status
 *
 * @ring: ring to try the recovery on
 *
 * Tests ring and set sched readiness status
 *
 * Returns 0 on success, error on failure.
 */
int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;
	int r;

	r = amdgpu_ring_test_ring(ring);
	if (r)
		DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
			      ring->name, r);
	else
		DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
			      ring->name);

	ring->sched.ready = !r;
	return r;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	* Christian König
	28	*/
	29	#include <linux/seq_file.h>
	30	#include <linux/slab.h>
fdf2f6c5	31	#include <linux/uaccess.h>
4f4824b5	32	#include <linux/debugfs.h>
fdf2f6c5	33
d38ceaf9 AD	34	#include <drm/amdgpu_drm.h>
	35	#include "amdgpu.h"
	36	#include "atom.h"
	37
	38	/*
	39	* Rings
	40	* Most engines on the GPU are fed via ring buffers. Ring
	41	* buffers are areas of GPU accessible memory that the host
	42	* writes commands into and the GPU reads commands out of.
	43	* There is a rptr (read pointer) that determines where the
	44	* GPU is currently reading, and a wptr (write pointer)
	45	* which determines where the host has written. When the
	46	* pointers are equal, the ring is idle. When the host
	47	* writes commands to the ring buffer, it increments the
	48	* wptr. The GPU then starts fetching commands and executes
	49	* them until the pointers are equal again.
	50	*/
d38ceaf9	51
d38ceaf9 AD	52	/**
	53	* amdgpu_ring_alloc - allocate space on the ring buffer
	54	*
	55	* @adev: amdgpu_device pointer
	56	* @ring: amdgpu_ring structure holding ring information
	57	* @ndw: number of dwords to allocate in the ring buffer
	58	*
	59	* Allocate @ndw dwords in the ring buffer (all asics).
	60	* Returns 0 on success, error on failure.
	61	*/
	62	int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
	63	{
d38ceaf9 AD	64	/* Align requested size with padding so unlock_commit can
d38ceaf9 AD	65	* pad safely */
79887142	66	ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
c7e6be23 CK	67
	68	/* Make sure we aren't trying to allocate more space
	69	* than the maximum for one submission
	70	*/
	71	if (WARN_ON_ONCE(ndw > ring->max_dw))
	72	return -ENOMEM;
	73
d38ceaf9 AD	74	ring->count_dw = ndw;
d38ceaf9 AD	75	ring->wptr_old = ring->wptr;
f06505b8 CK	76
	77	if (ring->funcs->begin_use)
	78	ring->funcs->begin_use(ring);
	79
d38ceaf9 AD	80	return 0;
	81	}
	82
edff0e28 JZ	83	/** amdgpu_ring_insert_nop - insert NOP packets
	84	*
	85	* @ring: amdgpu_ring structure holding ring information
	86	* @count: the number of NOP packets to insert
	87	*
	88	* This is the generic insert_nop function for rings except SDMA
	89	*/
	90	void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
	91	{
	92	int i;
	93
	94	for (i = 0; i < count; i++)
79887142	95	amdgpu_ring_write(ring, ring->funcs->nop);
edff0e28 JZ	96	}
edff0e28 JZ	97
9e5d5309 CK	98	/** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
	99	*
	100	* @ring: amdgpu_ring structure holding ring information
	101	* @ib: IB to add NOP packets to
	102	*
	103	* This is the generic pad_ib function for rings except SDMA
	104	*/
	105	void amdgpu_ring_generic_pad_ib(struct amdgpu_ring ring, struct amdgpu_ib ib)
	106	{
79887142 CK	107	while (ib->length_dw & ring->funcs->align_mask)
79887142 CK	108	ib->ptr[ib->length_dw++] = ring->funcs->nop;
9e5d5309 CK	109	}
9e5d5309 CK	110
d38ceaf9 AD	111	/**
	112	* amdgpu_ring_commit - tell the GPU to execute the new
	113	* commands on the ring buffer
	114	*
	115	* @adev: amdgpu_device pointer
	116	* @ring: amdgpu_ring structure holding ring information
	117	*
	118	* Update the wptr (write pointer) to tell the GPU to
	119	* execute new commands on the ring buffer (all asics).
	120	*/
	121	void amdgpu_ring_commit(struct amdgpu_ring *ring)
	122	{
edff0e28 JZ	123	uint32_t count;
edff0e28 JZ	124
d38ceaf9	125	/* We pad to match fetch size */
79887142 CK	126	count = ring->funcs->align_mask + 1 -
	127	(ring->wptr & ring->funcs->align_mask);
	128	count %= ring->funcs->align_mask + 1;
edff0e28 JZ	129	ring->funcs->insert_nop(ring, count);
edff0e28 JZ	130
d38ceaf9 AD	131	mb();
d38ceaf9 AD	132	amdgpu_ring_set_wptr(ring);
f06505b8 CK	133
	134	if (ring->funcs->end_use)
	135	ring->funcs->end_use(ring);
d38ceaf9 AD	136	}
d38ceaf9 AD	137
d38ceaf9 AD	138	/**
	139	* amdgpu_ring_undo - reset the wptr
	140	*
	141	* @ring: amdgpu_ring structure holding ring information
	142	*
	143	* Reset the driver's copy of the wptr (all asics).
	144	*/
	145	void amdgpu_ring_undo(struct amdgpu_ring *ring)
	146	{
	147	ring->wptr = ring->wptr_old;
f06505b8 CK	148
	149	if (ring->funcs->end_use)
	150	ring->funcs->end_use(ring);
d38ceaf9 AD	151	}
d38ceaf9 AD	152
d38ceaf9 AD	153	/**
	154	* amdgpu_ring_init - init driver ring struct.
	155	*
	156	* @adev: amdgpu_device pointer
	157	* @ring: amdgpu_ring structure holding ring information
a3f1cf35	158	* @max_ndw: maximum number of dw for ring alloc
d38ceaf9 AD	159	* @nop: nop packet for this ring
	160	*
	161	* Initialize the driver information for the selected ring (all asics).
	162	* Returns 0 on success, error on failure.
	163	*/
	164	int amdgpu_ring_init(struct amdgpu_device adev, struct amdgpu_ring ring,
79887142 CK	165	unsigned max_dw, struct amdgpu_irq_src *irq_src,
79887142 CK	166	unsigned irq_type)
d38ceaf9	167	{
b2ff0e8a	168	int r, i;
b249e18d AD	169	int sched_hw_submission = amdgpu_sched_hw_submission;
	170
	171	/* Set the hw submission limit higher for KIQ because
	172	* it's used for a number of gfx/compute tasks by both
	173	* KFD and KGD which may have outstanding fences and
	174	* it doesn't really use the gpu scheduler anyway;
	175	* KIQ tasks get submitted directly to the ring.
	176	*/
	177	if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
	178	sched_hw_submission = max(sched_hw_submission, 256);
1d31408a CK	179	else if (ring == &adev->sdma.instance[0].page)
1d31408a CK	180	sched_hw_submission = 256;
d38ceaf9 AD	181
	182	if (ring->adev == NULL) {
	183	if (adev->num_rings >= AMDGPU_MAX_RINGS)
	184	return -EINVAL;
	185
	186	ring->adev = adev;
	187	ring->idx = adev->num_rings++;
	188	adev->rings[ring->idx] = ring;
b249e18d	189	r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
4f839a24 CK	190	if (r)
4f839a24 CK	191	return r;
d38ceaf9 AD	192	}
d38ceaf9 AD	193
131b4b36	194	r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
97407b63 AD	195	if (r) {
	196	dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
	197	return r;
d38ceaf9 AD	198	}
d38ceaf9 AD	199
131b4b36	200	r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
97407b63 AD	201	if (r) {
	202	dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
	203	return r;
	204	}
0915fdbc	205
131b4b36	206	r = amdgpu_device_wb_get(adev, &ring->fence_offs);
97407b63 AD	207	if (r) {
	208	dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
	209	return r;
d38ceaf9 AD	210	}
d38ceaf9 AD	211
ef3e1323 JX	212	r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
	213	if (r) {
	214	dev_err(adev->dev,
	215	"(%d) ring trail_fence_offs wb alloc failed\n", r);
	216	return r;
	217	}
	218	ring->trail_fence_gpu_addr =
	219	adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
	220	ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];
	221
131b4b36	222	r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
128cff1a ML	223	if (r) {
	224	dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
	225	return r;
	226	}
	227	ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
	228	ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
714fbf80 ML	229	/* always set cond_exec_polling to CONTINUE */
714fbf80 ML	230	*ring->cond_exe_cpu_addr = 1;
128cff1a	231
d38ceaf9 AD	232	r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
	233	if (r) {
	234	dev_err(adev->dev, "failed initializing fences (%d).\n", r);
	235	return r;
	236	}
	237
b249e18d	238	ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
d38ceaf9	239
e09706f4 ML	240	ring->buf_mask = (ring->ring_size / 4) - 1;
	241	ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
	242	0xffffffffffffffff : ring->buf_mask;
d38ceaf9 AD	243	/* Allocate ring buffer */
d38ceaf9 AD	244	if (ring->ring_obj == NULL) {
c8c1a1d2	245	r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
37ac235b CK	246	AMDGPU_GEM_DOMAIN_GTT,
	247	&ring->ring_obj,
	248	&ring->gpu_addr,
	249	(void **)&ring->ring);
d38ceaf9 AD	250	if (r) {
	251	dev_err(adev->dev, "(%d) ring create failed\n", r);
	252	return r;
	253	}
f6bd7942	254	amdgpu_ring_clear_ring(ring);
d38ceaf9	255	}
536fbf94	256
a3f1cf35	257	ring->max_dw = max_dw;
1b1f42d8	258	ring->priority = DRM_SCHED_PRIORITY_NORMAL;
b2ff0e8a	259	mutex_init(&ring->priority_mutex);
d38ceaf9	260
1b1f42d8	261	for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
b2ff0e8a AR	262	atomic_set(&ring->num_jobs[i], 0);
b2ff0e8a AR	263
d38ceaf9 AD	264	return 0;
	265	}
	266
	267	/**
	268	* amdgpu_ring_fini - tear down the driver ring struct.
	269	*
	270	* @adev: amdgpu_device pointer
	271	* @ring: amdgpu_ring structure holding ring information
	272	*
	273	* Tear down the driver information for the selected ring (all asics).
	274	*/
	275	void amdgpu_ring_fini(struct amdgpu_ring *ring)
	276	{
d38ceaf9	277
41cc07cf TH	278	/* Not to finish a ring which is not initialized */
	279	if (!(ring->adev) \|\| !(ring->adev->rings[ring->idx]))
	280	return;
	281
6f9f9604 ND	282	ring->sched.ready = false;
6f9f9604 ND	283
131b4b36 AD	284	amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
131b4b36 AD	285	amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
7014285a	286
131b4b36 AD	287	amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
131b4b36 AD	288	amdgpu_device_wb_free(ring->adev, ring->fence_offs);
d38ceaf9	289
8640faed JZ	290	amdgpu_bo_free_kernel(&ring->ring_obj,
	291	&ring->gpu_addr,
	292	(void **)&ring->ring);
	293
3af81440 CK	294	dma_fence_put(ring->vmid_wait);
3af81440 CK	295	ring->vmid_wait = NULL;
10dd74ea	296	ring->me = 0;
3af81440	297
d8907643	298	ring->adev->rings[ring->idx] = NULL;
d38ceaf9 AD	299	}
d38ceaf9 AD	300
82853638 AD	301	/**
	302	* amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
	303	*
	304	* @adev: amdgpu_device pointer
	305	* @reg0: register to write
	306	* @reg1: register to wait on
	307	* @ref: reference value to write/wait on
	308	* @mask: mask to wait on
	309	*
	310	* Helper for rings that don't support write and wait in a
	311	* single oneshot packet.
	312	*/
	313	void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
	314	uint32_t reg0, uint32_t reg1,
	315	uint32_t ref, uint32_t mask)
	316	{
	317	amdgpu_ring_emit_wreg(ring, reg0, ref);
	318	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
	319	}
	320
7876fa4f CK	321	/**
	322	* amdgpu_ring_soft_recovery - try to soft recover a ring lockup
	323	*
	324	* @ring: ring to try the recovery on
	325	* @vmid: VMID we try to get going again
	326	* @fence: timedout fence
	327	*
	328	* Tries to get a ring proceeding again when it is stuck.
	329	*/
	330	bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
	331	struct dma_fence *fence)
	332	{
	333	ktime_t deadline = ktime_add_us(ktime_get(), 10000);
	334
ae1589f6	335	if (amdgpu_sriov_vf(ring->adev) \|\| !ring->funcs->soft_recovery \|\| !fence)
7876fa4f CK	336	return false;
	337
	338	atomic_inc(&ring->adev->gpu_reset_counter);
	339	while (!dma_fence_is_signaled(fence) &&
	340	ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
	341	ring->funcs->soft_recovery(ring, vmid);
	342
	343	return dma_fence_is_signaled(fence);
	344	}
	345
d38ceaf9 AD	346	/*
	347	* Debugfs info
	348	*/
	349	#if defined(CONFIG_DEBUG_FS)
	350
4f4824b5 TSD	351	/* Layout of file is 12 bytes consisting of
	352	* - rptr
	353	* - wptr
	354	* - driver's copy of wptr
	355	*
	356	* followed by n-words of ring data
	357	*/
	358	static ssize_t amdgpu_debugfs_ring_read(struct file f, char __user buf,
	359	size_t size, loff_t *pos)
d38ceaf9	360	{
45063097	361	struct amdgpu_ring *ring = file_inode(f)->i_private;
4f4824b5 TSD	362	int r, i;
	363	uint32_t value, result, early[3];
	364
c71dbd93	365	if (*pos & 3 \|\| size & 3)
4f4824b5 TSD	366	return -EINVAL;
	367
	368	result = 0;
	369
	370	if (*pos < 12) {
9c5c71bb	371	early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
ec63982e TSD	372	early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
ec63982e TSD	373	early[2] = ring->wptr & ring->buf_mask;
4f4824b5 TSD	374	for (i = *pos / 4; i < 3 && size; i++) {
	375	r = put_user(early[i], (uint32_t *)buf);
	376	if (r)
	377	return r;
	378	buf += 4;
	379	result += 4;
	380	size -= 4;
	381	*pos += 4;
	382	}
c7e6be23	383	}
4f4824b5 TSD	384
	385	while (size) {
	386	if (*pos >= (ring->ring_size + 12))
	387	return result;
714fbf80	388
4f4824b5 TSD	389	value = ring->ring[(*pos - 12)/4];
	390	r = put_user(value, (uint32_t*)buf);
	391	if (r)
	392	return r;
	393	buf += 4;
	394	result += 4;
	395	size -= 4;
	396	*pos += 4;
d38ceaf9	397	}
4f4824b5 TSD	398
4f4824b5 TSD	399	return result;
d38ceaf9 AD	400	}
d38ceaf9 AD	401
4f4824b5 TSD	402	static const struct file_operations amdgpu_debugfs_ring_fops = {
	403	.owner = THIS_MODULE,
	404	.read = amdgpu_debugfs_ring_read,
	405	.llseek = default_llseek
	406	};
d38ceaf9 AD	407
	408	#endif
	409
fd23cfcc AD	410	int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
fd23cfcc AD	411	struct amdgpu_ring *ring)
d38ceaf9 AD	412	{
d38ceaf9 AD	413	#if defined(CONFIG_DEBUG_FS)
4f4824b5 TSD	414	struct drm_minor *minor = adev->ddev->primary;
	415	struct dentry ent, root = minor->debugfs_root;
	416	char name[32];
d38ceaf9	417
771c8ec1	418	sprintf(name, "amdgpu_ring_%s", ring->name);
771c8ec1	419
4f4824b5 TSD	420	ent = debugfs_create_file(name,
	421	S_IFREG \| S_IRUGO, root,
	422	ring, &amdgpu_debugfs_ring_fops);
eeb2fa0c DC	423	if (!ent)
eeb2fa0c DC	424	return -ENOMEM;
4f4824b5 TSD	425
4f4824b5 TSD	426	i_size_write(ent->d_inode, ring->ring_size + 12);
a909c6bd	427	ring->ent = ent;
d38ceaf9 AD	428	#endif
	429	return 0;
	430	}
a909c6bd	431
c66ed765 AG	432	/**
	433	* amdgpu_ring_test_helper - tests ring and set sched readiness status
	434	*
	435	* @ring: ring to try the recovery on
	436	*
	437	* Tests ring and set sched readiness status
	438	*
	439	* Returns 0 on success, error on failure.
	440	*/
	441	int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
	442	{
dc9eeff8	443	struct amdgpu_device *adev = ring->adev;
c66ed765 AG	444	int r;
	445
	446	r = amdgpu_ring_test_ring(ring);
dc9eeff8 CK	447	if (r)
	448	DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
	449	ring->name, r);
	450	else
	451	DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
	452	ring->name);
c66ed765 AG	453
c66ed765 AG	454	ring->sched.ready = !r;
c66ed765 AG	455	return r;
c66ed765 AG	456	}