[mirror_ubuntu-kernels.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_sdma.h

/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __AMDGPU_SDMA_H__
#define __AMDGPU_SDMA_H__

/* max number of IP instances */
#define AMDGPU_MAX_SDMA_INSTANCES		8

enum amdgpu_sdma_irq {
	AMDGPU_SDMA_IRQ_INSTANCE0  = 0,
	AMDGPU_SDMA_IRQ_INSTANCE1,
	AMDGPU_SDMA_IRQ_INSTANCE2,
	AMDGPU_SDMA_IRQ_INSTANCE3,
	AMDGPU_SDMA_IRQ_INSTANCE4,
	AMDGPU_SDMA_IRQ_INSTANCE5,
	AMDGPU_SDMA_IRQ_INSTANCE6,
	AMDGPU_SDMA_IRQ_INSTANCE7,
	AMDGPU_SDMA_IRQ_LAST
};

struct amdgpu_sdma_instance {
	/* SDMA firmware */
	const struct firmware	*fw;
	uint32_t		fw_version;
	uint32_t		feature_version;

	struct amdgpu_ring	ring;
	struct amdgpu_ring	page;
	bool			burst_nop;
};

struct amdgpu_sdma {
	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
	struct amdgpu_irq_src	trap_irq;
	struct amdgpu_irq_src	illegal_inst_irq;
	struct amdgpu_irq_src	ecc_irq;
	int			num_instances;
	uint32_t                    srbm_soft_reset;
	bool			has_page_queue;
	struct ras_common_if	*ras_if;
};

/*
 * Provided by hw blocks that can move/clear data.  e.g., gfx or sdma
 * But currently, we use sdma to move data.
 */
struct amdgpu_buffer_funcs {
	/* maximum bytes in a single operation */
	uint32_t	copy_max_bytes;

	/* number of dw to reserve per operation */
	unsigned	copy_num_dw;

	/* used for buffer migration */
	void (*emit_copy_buffer)(struct amdgpu_ib *ib,
				 /* src addr in bytes */
				 uint64_t src_offset,
				 /* dst addr in bytes */
				 uint64_t dst_offset,
				 /* number of byte to transfer */
				 uint32_t byte_count);

	/* maximum bytes in a single operation */
	uint32_t	fill_max_bytes;

	/* number of dw to reserve per operation */
	unsigned	fill_num_dw;

	/* used for buffer clearing */
	void (*emit_fill_buffer)(struct amdgpu_ib *ib,
				 /* value to write to memory */
				 uint32_t src_data,
				 /* dst addr in bytes */
				 uint64_t dst_offset,
				 /* number of byte to fill */
				 uint32_t byte_count);
};

#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b))
#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))

struct amdgpu_sdma_instance *
amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
#endif
Commit	Line	Data
bb7743bc HR	1	/*
	2	* Copyright 2018 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __AMDGPU_SDMA_H__
	25	#define __AMDGPU_SDMA_H__
	26
	27	/* max number of IP instances */
667a4822	28	#define AMDGPU_MAX_SDMA_INSTANCES 8
bb7743bc HR	29
bb7743bc HR	30	enum amdgpu_sdma_irq {
af67772d ED	31	AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
af67772d ED	32	AMDGPU_SDMA_IRQ_INSTANCE1,
667a4822 LM	33	AMDGPU_SDMA_IRQ_INSTANCE2,
	34	AMDGPU_SDMA_IRQ_INSTANCE3,
	35	AMDGPU_SDMA_IRQ_INSTANCE4,
	36	AMDGPU_SDMA_IRQ_INSTANCE5,
	37	AMDGPU_SDMA_IRQ_INSTANCE6,
	38	AMDGPU_SDMA_IRQ_INSTANCE7,
bb7743bc HR	39	AMDGPU_SDMA_IRQ_LAST
	40	};
	41
	42	struct amdgpu_sdma_instance {
	43	/* SDMA firmware */
	44	const struct firmware *fw;
	45	uint32_t fw_version;
	46	uint32_t feature_version;
	47
	48	struct amdgpu_ring ring;
9194a339	49	struct amdgpu_ring page;
bb7743bc HR	50	bool burst_nop;
	51	};
	52
	53	struct amdgpu_sdma {
	54	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
bb7743bc HR	55	struct amdgpu_irq_src trap_irq;
bb7743bc HR	56	struct amdgpu_irq_src illegal_inst_irq;
8cf12507	57	struct amdgpu_irq_src ecc_irq;
bb7743bc HR	58	int num_instances;
bb7743bc HR	59	uint32_t srbm_soft_reset;
2a85e816	60	bool has_page_queue;
8cf12507	61	struct ras_common_if *ras_if;
bb7743bc HR	62	};
	63
	64	/*
	65	* Provided by hw blocks that can move/clear data. e.g., gfx or sdma
	66	* But currently, we use sdma to move data.
	67	*/
	68	struct amdgpu_buffer_funcs {
	69	/* maximum bytes in a single operation */
	70	uint32_t copy_max_bytes;
	71
	72	/* number of dw to reserve per operation */
	73	unsigned copy_num_dw;
	74
	75	/* used for buffer migration */
	76	void (emit_copy_buffer)(struct amdgpu_ib ib,
	77	/* src addr in bytes */
	78	uint64_t src_offset,
	79	/* dst addr in bytes */
	80	uint64_t dst_offset,
	81	/* number of byte to transfer */
	82	uint32_t byte_count);
	83
	84	/* maximum bytes in a single operation */
	85	uint32_t fill_max_bytes;
	86
	87	/* number of dw to reserve per operation */
	88	unsigned fill_num_dw;
	89
	90	/* used for buffer clearing */
	91	void (emit_fill_buffer)(struct amdgpu_ib ib,
	92	/* value to write to memory */
	93	uint32_t src_data,
	94	/* dst addr in bytes */
	95	uint64_t dst_offset,
	96	/* number of byte to fill */
	97	uint32_t byte_count);
	98	};
	99
	100	#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
	101	#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
	102
	103	struct amdgpu_sdma_instance *
ccf191f8	104	amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
f6cffc0d	105	int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring ring, uint32_t index);
ca1eb732	106	uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
bb7743bc	107	#endif