[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_sync.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Christian König <christian.koenig@amd.com>
 */

#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"

struct amdgpu_sync_entry {
	struct hlist_node	node;
	struct fence		*fence;
};

/**
 * amdgpu_sync_create - zero init sync object
 *
 * @sync: sync object to initialize
 *
 * Just clear the sync object for now.
 */
void amdgpu_sync_create(struct amdgpu_sync *sync)
{
	unsigned i;

	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
		sync->semaphores[i] = NULL;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		sync->sync_to[i] = NULL;

	hash_init(sync->fences);
	sync->last_vm_update = NULL;
}

static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
{
	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);

	if (a_fence)
		return a_fence->ring->adev == adev;
	if (s_fence)
		return (struct amdgpu_device *)s_fence->sched->priv == adev;
	return false;
}

static bool amdgpu_sync_test_owner(struct fence *f, void *owner)
{
	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	if (s_fence)
		return s_fence->owner == owner;
	if (a_fence)
		return a_fence->owner == owner;
	return false;
}

/**
 * amdgpu_sync_fence - remember to sync to this fence
 *
 * @sync: sync object to add fence to
 * @fence: fence to sync to
 *
 */
int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
		      struct fence *f)
{
	struct amdgpu_sync_entry *e;
	struct amdgpu_fence *fence;
	struct amdgpu_fence *other;
	struct fence *tmp, *later;

	if (!f)
		return 0;

	if (amdgpu_sync_same_dev(adev, f) &&
	    amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM)) {
		if (sync->last_vm_update) {
			tmp = sync->last_vm_update;
			BUG_ON(f->context != tmp->context);
			later = (f->seqno - tmp->seqno <= INT_MAX) ? f : tmp;
			sync->last_vm_update = fence_get(later);
			fence_put(tmp);
		} else
			sync->last_vm_update = fence_get(f);
	}

	fence = to_amdgpu_fence(f);
	if (!fence || fence->ring->adev != adev) {
		hash_for_each_possible(sync->fences, e, node, f->context) {
			struct fence *new;
			if (unlikely(e->fence->context != f->context))
				continue;
			new = fence_get(fence_later(e->fence, f));
			if (new) {
				fence_put(e->fence);
				e->fence = new;
			}
			return 0;
		}

		e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
		if (!e)
			return -ENOMEM;

		hash_add(sync->fences, &e->node, f->context);
		e->fence = fence_get(f);
		return 0;
	}

	other = sync->sync_to[fence->ring->idx];
	sync->sync_to[fence->ring->idx] = amdgpu_fence_ref(
		amdgpu_fence_later(fence, other));
	amdgpu_fence_unref(&other);

	return 0;
}

static void *amdgpu_sync_get_owner(struct fence *f)
{
	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);

	if (s_fence)
		return s_fence->owner;
	else if (a_fence)
		return a_fence->owner;
	return AMDGPU_FENCE_OWNER_UNDEFINED;
}

/**
 * amdgpu_sync_resv - use the semaphores to sync to a reservation object
 *
 * @sync: sync object to add fences from reservation object to
 * @resv: reservation object with embedded fence
 * @shared: true if we should only sync to the exclusive fence
 *
 * Sync to the fence using the semaphore objects
 */
int amdgpu_sync_resv(struct amdgpu_device *adev,
		     struct amdgpu_sync *sync,
		     struct reservation_object *resv,
		     void *owner)
{
	struct reservation_object_list *flist;
	struct fence *f;
	void *fence_owner;
	unsigned i;
	int r = 0;

	if (resv == NULL)
		return -EINVAL;

	/* always sync to the exclusive fence */
	f = reservation_object_get_excl(resv);
	r = amdgpu_sync_fence(adev, sync, f);

	flist = reservation_object_get_list(resv);
	if (!flist || r)
		return r;

	for (i = 0; i < flist->shared_count; ++i) {
		f = rcu_dereference_protected(flist->shared[i],
					      reservation_object_held(resv));
		if (amdgpu_sync_same_dev(adev, f)) {
			/* VM updates are only interesting
			 * for other VM updates and moves.
			 */
			fence_owner = amdgpu_sync_get_owner(f);
			if ((owner != AMDGPU_FENCE_OWNER_MOVE) &&
			    (fence_owner != AMDGPU_FENCE_OWNER_MOVE) &&
			    ((owner == AMDGPU_FENCE_OWNER_VM) !=
			     (fence_owner == AMDGPU_FENCE_OWNER_VM)))
				continue;

			/* Ignore fence from the same owner as
			 * long as it isn't undefined.
			 */
			if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
			    fence_owner == owner)
				continue;
		}

		r = amdgpu_sync_fence(adev, sync, f);
		if (r)
			break;
	}
	return r;
}

struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync)
{
	struct amdgpu_sync_entry *e;
	struct hlist_node *tmp;
	struct fence *f;
	int i;

	hash_for_each_safe(sync->fences, i, tmp, e, node) {

		f = e->fence;

		hash_del(&e->node);
		kfree(e);

		if (!fence_is_signaled(f))
			return f;

		fence_put(f);
	}
	return NULL;
}

int amdgpu_sync_wait(struct amdgpu_sync *sync)
{
	struct amdgpu_sync_entry *e;
	struct hlist_node *tmp;
	int i, r;

	hash_for_each_safe(sync->fences, i, tmp, e, node) {
		r = fence_wait(e->fence, false);
		if (r)
			return r;

		hash_del(&e->node);
		fence_put(e->fence);
		kfree(e);
	}

	if (amdgpu_enable_semaphores)
		return 0;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		struct amdgpu_fence *fence = sync->sync_to[i];
		if (!fence)
			continue;

		r = fence_wait(&fence->base, false);
		if (r)
			return r;
	}

	return 0;
}

/**
 * amdgpu_sync_rings - sync ring to all registered fences
 *
 * @sync: sync object to use
 * @ring: ring that needs sync
 *
 * Ensure that all registered fences are signaled before letting
 * the ring continue. The caller must hold the ring lock.
 */
int amdgpu_sync_rings(struct amdgpu_sync *sync,
		      struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;
	unsigned count = 0;
	int i, r;

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
		struct amdgpu_fence *fence = sync->sync_to[i];
		struct amdgpu_semaphore *semaphore;
		struct amdgpu_ring *other = adev->rings[i];

		/* check if we really need to sync */
		if (!amdgpu_fence_need_sync(fence, ring))
			continue;

		/* prevent GPU deadlocks */
		if (!other->ready) {
			dev_err(adev->dev, "Syncing to a disabled ring!");
			return -EINVAL;
		}

		if (amdgpu_enable_scheduler || !amdgpu_enable_semaphores ||
		    (count >= AMDGPU_NUM_SYNCS)) {
			/* not enough room, wait manually */
			r = fence_wait(&fence->base, false);
			if (r)
				return r;
			continue;
		}
		r = amdgpu_semaphore_create(adev, &semaphore);
		if (r)
			return r;

		sync->semaphores[count++] = semaphore;

		/* allocate enough space for sync command */
		r = amdgpu_ring_alloc(other, 16);
		if (r)
			return r;

		/* emit the signal semaphore */
		if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
			/* signaling wasn't successful wait manually */
			amdgpu_ring_undo(other);
			r = fence_wait(&fence->base, false);
			if (r)
				return r;
			continue;
		}

		/* we assume caller has already allocated space on waiters ring */
		if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
			/* waiting wasn't successful wait manually */
			amdgpu_ring_undo(other);
			r = fence_wait(&fence->base, false);
			if (r)
				return r;
			continue;
		}

		amdgpu_ring_commit(other);
		amdgpu_fence_note_sync(fence, ring);
	}

	return 0;
}

/**
 * amdgpu_sync_free - free the sync object
 *
 * @adev: amdgpu_device pointer
 * @sync: sync object to use
 * @fence: fence to use for the free
 *
 * Free the sync object by freeing all semaphores in it.
 */
void amdgpu_sync_free(struct amdgpu_device *adev,
		      struct amdgpu_sync *sync,
		      struct fence *fence)
{
	struct amdgpu_sync_entry *e;
	struct hlist_node *tmp;
	unsigned i;

	hash_for_each_safe(sync->fences, i, tmp, e, node) {
		hash_del(&e->node);
		fence_put(e->fence);
		kfree(e);
	}

	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
		amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);

	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
		amdgpu_fence_unref(&sync->sync_to[i]);

	fence_put(sync->last_vm_update);
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Christian König <christian.koenig@amd.com>
	29	*/
	30
	31	#include <drm/drmP.h>
	32	#include "amdgpu.h"
	33	#include "amdgpu_trace.h"
	34
f91b3a69 CK	35	struct amdgpu_sync_entry {
	36	struct hlist_node node;
	37	struct fence *fence;
	38	};
	39
d38ceaf9 AD	40	/**
	41	* amdgpu_sync_create - zero init sync object
	42	*
	43	* @sync: sync object to initialize
	44	*
	45	* Just clear the sync object for now.
	46	*/
	47	void amdgpu_sync_create(struct amdgpu_sync *sync)
	48	{
	49	unsigned i;
	50
	51	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
	52	sync->semaphores[i] = NULL;
	53
	54	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	55	sync->sync_to[i] = NULL;
	56
f91b3a69	57	hash_init(sync->fences);
d38ceaf9 AD	58	sync->last_vm_update = NULL;
	59	}
	60
3c62338c CZ	61	static bool amdgpu_sync_same_dev(struct amdgpu_device adev, struct fence f)
	62	{
	63	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	64	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	65
	66	if (a_fence)
	67	return a_fence->ring->adev == adev;
	68	if (s_fence)
9b398fa5	69	return (struct amdgpu_device *)s_fence->sched->priv == adev;
3c62338c CZ	70	return false;
	71	}
	72
	73	static bool amdgpu_sync_test_owner(struct fence f, void owner)
	74	{
	75	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	76	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	77	if (s_fence)
	78	return s_fence->owner == owner;
	79	if (a_fence)
	80	return a_fence->owner == owner;
	81	return false;
	82	}
	83
d38ceaf9	84	/**
91e1a520	85	* amdgpu_sync_fence - remember to sync to this fence
d38ceaf9 AD	86	*
	87	* @sync: sync object to add fence to
	88	* @fence: fence to sync to
	89	*
d38ceaf9	90	*/
91e1a520 CK	91	int amdgpu_sync_fence(struct amdgpu_device adev, struct amdgpu_sync sync,
91e1a520 CK	92	struct fence *f)
d38ceaf9	93	{
f91b3a69	94	struct amdgpu_sync_entry *e;
91e1a520	95	struct amdgpu_fence *fence;
d38ceaf9	96	struct amdgpu_fence *other;
3c62338c	97	struct fence tmp, later;
d38ceaf9	98
91e1a520 CK	99	if (!f)
	100	return 0;
	101
3c62338c CZ	102	if (amdgpu_sync_same_dev(adev, f) &&
	103	amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM)) {
	104	if (sync->last_vm_update) {
	105	tmp = sync->last_vm_update;
	106	BUG_ON(f->context != tmp->context);
	107	later = (f->seqno - tmp->seqno <= INT_MAX) ? f : tmp;
	108	sync->last_vm_update = fence_get(later);
	109	fence_put(tmp);
	110	} else
	111	sync->last_vm_update = fence_get(f);
	112	}
	113
91e1a520	114	fence = to_amdgpu_fence(f);
f91b3a69 CK	115	if (!fence \|\| fence->ring->adev != adev) {
	116	hash_for_each_possible(sync->fences, e, node, f->context) {
	117	struct fence *new;
	118	if (unlikely(e->fence->context != f->context))
	119	continue;
	120	new = fence_get(fence_later(e->fence, f));
	121	if (new) {
	122	fence_put(e->fence);
	123	e->fence = new;
	124	}
	125	return 0;
	126	}
	127
	128	e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
	129	if (!e)
	130	return -ENOMEM;
	131
	132	hash_add(sync->fences, &e->node, f->context);
	133	e->fence = fence_get(f);
	134	return 0;
	135	}
d38ceaf9 AD	136
	137	other = sync->sync_to[fence->ring->idx];
	138	sync->sync_to[fence->ring->idx] = amdgpu_fence_ref(
	139	amdgpu_fence_later(fence, other));
	140	amdgpu_fence_unref(&other);
	141
91e1a520	142	return 0;
d38ceaf9 AD	143	}
d38ceaf9 AD	144
423a9480 CZ	145	static void amdgpu_sync_get_owner(struct fence f)
	146	{
	147	struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
	148	struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
	149
	150	if (s_fence)
	151	return s_fence->owner;
	152	else if (a_fence)
	153	return a_fence->owner;
	154	return AMDGPU_FENCE_OWNER_UNDEFINED;
	155	}
	156
d38ceaf9 AD	157	/**
	158	* amdgpu_sync_resv - use the semaphores to sync to a reservation object
	159	*
	160	* @sync: sync object to add fences from reservation object to
	161	* @resv: reservation object with embedded fence
	162	* @shared: true if we should only sync to the exclusive fence
	163	*
	164	* Sync to the fence using the semaphore objects
	165	*/
	166	int amdgpu_sync_resv(struct amdgpu_device *adev,
	167	struct amdgpu_sync *sync,
	168	struct reservation_object *resv,
	169	void *owner)
	170	{
	171	struct reservation_object_list *flist;
	172	struct fence *f;
423a9480	173	void *fence_owner;
d38ceaf9 AD	174	unsigned i;
	175	int r = 0;
	176
4b095304 JZ	177	if (resv == NULL)
	178	return -EINVAL;
	179
d38ceaf9 AD	180	/* always sync to the exclusive fence */
d38ceaf9 AD	181	f = reservation_object_get_excl(resv);
91e1a520	182	r = amdgpu_sync_fence(adev, sync, f);
d38ceaf9 AD	183
	184	flist = reservation_object_get_list(resv);
	185	if (!flist \|\| r)
	186	return r;
	187
	188	for (i = 0; i < flist->shared_count; ++i) {
	189	f = rcu_dereference_protected(flist->shared[i],
	190	reservation_object_held(resv));
423a9480	191	if (amdgpu_sync_same_dev(adev, f)) {
1d3897e0 CK	192	/* VM updates are only interesting
	193	* for other VM updates and moves.
	194	*/
423a9480	195	fence_owner = amdgpu_sync_get_owner(f);
1d3897e0	196	if ((owner != AMDGPU_FENCE_OWNER_MOVE) &&
423a9480	197	(fence_owner != AMDGPU_FENCE_OWNER_MOVE) &&
1d3897e0	198	((owner == AMDGPU_FENCE_OWNER_VM) !=
423a9480	199	(fence_owner == AMDGPU_FENCE_OWNER_VM)))
91e1a520 CK	200	continue;
91e1a520 CK	201
1d3897e0 CK	202	/* Ignore fence from the same owner as
	203	* long as it isn't undefined.
	204	*/
	205	if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
423a9480	206	fence_owner == owner)
1d3897e0 CK	207	continue;
	208	}
	209
91e1a520 CK	210	r = amdgpu_sync_fence(adev, sync, f);
	211	if (r)
	212	break;
d38ceaf9 AD	213	}
	214	return r;
	215	}
	216
e61235db CK	217	struct fence amdgpu_sync_get_fence(struct amdgpu_sync sync)
	218	{
	219	struct amdgpu_sync_entry *e;
	220	struct hlist_node *tmp;
	221	struct fence *f;
	222	int i;
	223
	224	hash_for_each_safe(sync->fences, i, tmp, e, node) {
	225
	226	f = e->fence;
	227
	228	hash_del(&e->node);
	229	kfree(e);
	230
	231	if (!fence_is_signaled(f))
	232	return f;
	233
	234	fence_put(f);
	235	}
	236	return NULL;
	237	}
	238
f91b3a69 CK	239	int amdgpu_sync_wait(struct amdgpu_sync *sync)
	240	{
	241	struct amdgpu_sync_entry *e;
	242	struct hlist_node *tmp;
	243	int i, r;
	244
	245	hash_for_each_safe(sync->fences, i, tmp, e, node) {
	246	r = fence_wait(e->fence, false);
	247	if (r)
	248	return r;
	249
	250	hash_del(&e->node);
	251	fence_put(e->fence);
	252	kfree(e);
	253	}
3daea9e3 CK	254
	255	if (amdgpu_enable_semaphores)
	256	return 0;
	257
	258	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
	259	struct amdgpu_fence *fence = sync->sync_to[i];
	260	if (!fence)
	261	continue;
	262
	263	r = fence_wait(&fence->base, false);
	264	if (r)
	265	return r;
	266	}
	267
f91b3a69 CK	268	return 0;
	269	}
	270
d38ceaf9 AD	271	/**
	272	* amdgpu_sync_rings - sync ring to all registered fences
	273	*
	274	* @sync: sync object to use
	275	* @ring: ring that needs sync
	276	*
	277	* Ensure that all registered fences are signaled before letting
	278	* the ring continue. The caller must hold the ring lock.
	279	*/
	280	int amdgpu_sync_rings(struct amdgpu_sync *sync,
	281	struct amdgpu_ring *ring)
	282	{
	283	struct amdgpu_device *adev = ring->adev;
	284	unsigned count = 0;
	285	int i, r;
	286
	287	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
	288	struct amdgpu_fence *fence = sync->sync_to[i];
	289	struct amdgpu_semaphore *semaphore;
	290	struct amdgpu_ring *other = adev->rings[i];
	291
	292	/* check if we really need to sync */
	293	if (!amdgpu_fence_need_sync(fence, ring))
	294	continue;
	295
	296	/* prevent GPU deadlocks */
	297	if (!other->ready) {
	298	dev_err(adev->dev, "Syncing to a disabled ring!");
	299	return -EINVAL;
	300	}
	301
3daea9e3 CK	302	if (amdgpu_enable_scheduler \|\| !amdgpu_enable_semaphores \|\|
3daea9e3 CK	303	(count >= AMDGPU_NUM_SYNCS)) {
d38ceaf9	304	/* not enough room, wait manually */
02bc0650	305	r = fence_wait(&fence->base, false);
d38ceaf9 AD	306	if (r)
	307	return r;
	308	continue;
	309	}
	310	r = amdgpu_semaphore_create(adev, &semaphore);
	311	if (r)
	312	return r;
	313
	314	sync->semaphores[count++] = semaphore;
	315
	316	/* allocate enough space for sync command */
	317	r = amdgpu_ring_alloc(other, 16);
	318	if (r)
	319	return r;
	320
	321	/* emit the signal semaphore */
	322	if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
	323	/* signaling wasn't successful wait manually */
	324	amdgpu_ring_undo(other);
02bc0650	325	r = fence_wait(&fence->base, false);
d38ceaf9 AD	326	if (r)
	327	return r;
	328	continue;
	329	}
	330
	331	/* we assume caller has already allocated space on waiters ring */
	332	if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
	333	/* waiting wasn't successful wait manually */
	334	amdgpu_ring_undo(other);
02bc0650	335	r = fence_wait(&fence->base, false);
d38ceaf9 AD	336	if (r)
	337	return r;
	338	continue;
	339	}
	340
	341	amdgpu_ring_commit(other);
	342	amdgpu_fence_note_sync(fence, ring);
	343	}
	344
	345	return 0;
	346	}
	347
	348	/**
	349	* amdgpu_sync_free - free the sync object
	350	*
	351	* @adev: amdgpu_device pointer
	352	* @sync: sync object to use
	353	* @fence: fence to use for the free
	354	*
	355	* Free the sync object by freeing all semaphores in it.
	356	*/
	357	void amdgpu_sync_free(struct amdgpu_device *adev,
	358	struct amdgpu_sync *sync,
4ce9891e	359	struct fence *fence)
d38ceaf9	360	{
f91b3a69 CK	361	struct amdgpu_sync_entry *e;
f91b3a69 CK	362	struct hlist_node *tmp;
d38ceaf9 AD	363	unsigned i;
d38ceaf9 AD	364
f91b3a69 CK	365	hash_for_each_safe(sync->fences, i, tmp, e, node) {
	366	hash_del(&e->node);
	367	fence_put(e->fence);
	368	kfree(e);
	369	}
	370
d38ceaf9 AD	371	for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
	372	amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);
	373
	374	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
	375	amdgpu_fence_unref(&sync->sync_to[i]);
	376
3c62338c	377	fence_put(sync->last_vm_update);
d38ceaf9	378	}