]>
Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Christian König <christian.koenig@amd.com> | |
29 | */ | |
30 | ||
31 | #include <drm/drmP.h> | |
32 | #include "amdgpu.h" | |
33 | #include "amdgpu_trace.h" | |
34 | ||
f91b3a69 CK |
35 | struct amdgpu_sync_entry { |
36 | struct hlist_node node; | |
37 | struct fence *fence; | |
38 | }; | |
39 | ||
d38ceaf9 AD |
40 | /** |
41 | * amdgpu_sync_create - zero init sync object | |
42 | * | |
43 | * @sync: sync object to initialize | |
44 | * | |
45 | * Just clear the sync object for now. | |
46 | */ | |
47 | void amdgpu_sync_create(struct amdgpu_sync *sync) | |
48 | { | |
f91b3a69 | 49 | hash_init(sync->fences); |
d38ceaf9 AD |
50 | sync->last_vm_update = NULL; |
51 | } | |
52 | ||
bcc634f4 CK |
53 | /** |
54 | * amdgpu_sync_same_dev - test if fence belong to us | |
55 | * | |
56 | * @adev: amdgpu device to use for the test | |
57 | * @f: fence to test | |
58 | * | |
59 | * Test if the fence was issued by us. | |
60 | */ | |
3c62338c CZ |
61 | static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f) |
62 | { | |
63 | struct amdgpu_fence *a_fence = to_amdgpu_fence(f); | |
64 | struct amd_sched_fence *s_fence = to_amd_sched_fence(f); | |
65 | ||
66 | if (a_fence) | |
67 | return a_fence->ring->adev == adev; | |
4f839a24 CK |
68 | |
69 | if (s_fence) { | |
70 | struct amdgpu_ring *ring; | |
71 | ||
72 | ring = container_of(s_fence->sched, struct amdgpu_ring, sched); | |
73 | return ring->adev == adev; | |
74 | } | |
75 | ||
3c62338c CZ |
76 | return false; |
77 | } | |
78 | ||
bcc634f4 CK |
79 | /** |
80 | * amdgpu_sync_get_owner - extract the owner of a fence | |
81 | * | |
82 | * @fence: fence get the owner from | |
83 | * | |
84 | * Extract who originally created the fence. | |
85 | */ | |
86 | static void *amdgpu_sync_get_owner(struct fence *f) | |
3c62338c CZ |
87 | { |
88 | struct amdgpu_fence *a_fence = to_amdgpu_fence(f); | |
89 | struct amd_sched_fence *s_fence = to_amd_sched_fence(f); | |
bcc634f4 | 90 | |
3c62338c | 91 | if (s_fence) |
bcc634f4 CK |
92 | return s_fence->owner; |
93 | else if (a_fence) | |
94 | return a_fence->owner; | |
95 | return AMDGPU_FENCE_OWNER_UNDEFINED; | |
3c62338c CZ |
96 | } |
97 | ||
bcc634f4 CK |
98 | /** |
99 | * amdgpu_sync_keep_later - Keep the later fence | |
100 | * | |
101 | * @keep: existing fence to test | |
102 | * @fence: new fence | |
103 | * | |
104 | * Either keep the existing fence or the new one, depending which one is later. | |
105 | */ | |
24233860 CK |
106 | static void amdgpu_sync_keep_later(struct fence **keep, struct fence *fence) |
107 | { | |
108 | if (*keep && fence_is_later(*keep, fence)) | |
109 | return; | |
110 | ||
111 | fence_put(*keep); | |
112 | *keep = fence_get(fence); | |
113 | } | |
114 | ||
d38ceaf9 | 115 | /** |
91e1a520 | 116 | * amdgpu_sync_fence - remember to sync to this fence |
d38ceaf9 AD |
117 | * |
118 | * @sync: sync object to add fence to | |
119 | * @fence: fence to sync to | |
120 | * | |
d38ceaf9 | 121 | */ |
91e1a520 CK |
122 | int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, |
123 | struct fence *f) | |
d38ceaf9 | 124 | { |
f91b3a69 | 125 | struct amdgpu_sync_entry *e; |
d38ceaf9 | 126 | |
91e1a520 CK |
127 | if (!f) |
128 | return 0; | |
129 | ||
3c62338c | 130 | if (amdgpu_sync_same_dev(adev, f) && |
bcc634f4 | 131 | amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM) |
24233860 | 132 | amdgpu_sync_keep_later(&sync->last_vm_update, f); |
3c62338c | 133 | |
046c12c6 CK |
134 | hash_for_each_possible(sync->fences, e, node, f->context) { |
135 | if (unlikely(e->fence->context != f->context)) | |
136 | continue; | |
f91b3a69 | 137 | |
046c12c6 | 138 | amdgpu_sync_keep_later(&e->fence, f); |
f91b3a69 CK |
139 | return 0; |
140 | } | |
d38ceaf9 | 141 | |
046c12c6 CK |
142 | e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL); |
143 | if (!e) | |
144 | return -ENOMEM; | |
d38ceaf9 | 145 | |
046c12c6 CK |
146 | hash_add(sync->fences, &e->node, f->context); |
147 | e->fence = fence_get(f); | |
91e1a520 | 148 | return 0; |
d38ceaf9 AD |
149 | } |
150 | ||
151 | /** | |
2f4b9400 | 152 | * amdgpu_sync_resv - sync to a reservation object |
d38ceaf9 AD |
153 | * |
154 | * @sync: sync object to add fences from reservation object to | |
155 | * @resv: reservation object with embedded fence | |
156 | * @shared: true if we should only sync to the exclusive fence | |
157 | * | |
2f4b9400 | 158 | * Sync to the fence |
d38ceaf9 AD |
159 | */ |
160 | int amdgpu_sync_resv(struct amdgpu_device *adev, | |
161 | struct amdgpu_sync *sync, | |
162 | struct reservation_object *resv, | |
163 | void *owner) | |
164 | { | |
165 | struct reservation_object_list *flist; | |
166 | struct fence *f; | |
423a9480 | 167 | void *fence_owner; |
d38ceaf9 AD |
168 | unsigned i; |
169 | int r = 0; | |
170 | ||
4b095304 JZ |
171 | if (resv == NULL) |
172 | return -EINVAL; | |
173 | ||
d38ceaf9 AD |
174 | /* always sync to the exclusive fence */ |
175 | f = reservation_object_get_excl(resv); | |
91e1a520 | 176 | r = amdgpu_sync_fence(adev, sync, f); |
d38ceaf9 AD |
177 | |
178 | flist = reservation_object_get_list(resv); | |
179 | if (!flist || r) | |
180 | return r; | |
181 | ||
182 | for (i = 0; i < flist->shared_count; ++i) { | |
183 | f = rcu_dereference_protected(flist->shared[i], | |
184 | reservation_object_held(resv)); | |
423a9480 | 185 | if (amdgpu_sync_same_dev(adev, f)) { |
1d3897e0 CK |
186 | /* VM updates are only interesting |
187 | * for other VM updates and moves. | |
188 | */ | |
423a9480 | 189 | fence_owner = amdgpu_sync_get_owner(f); |
7a91d6cb CK |
190 | if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) && |
191 | (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) && | |
1d3897e0 | 192 | ((owner == AMDGPU_FENCE_OWNER_VM) != |
423a9480 | 193 | (fence_owner == AMDGPU_FENCE_OWNER_VM))) |
91e1a520 CK |
194 | continue; |
195 | ||
1d3897e0 CK |
196 | /* Ignore fence from the same owner as |
197 | * long as it isn't undefined. | |
198 | */ | |
199 | if (owner != AMDGPU_FENCE_OWNER_UNDEFINED && | |
423a9480 | 200 | fence_owner == owner) |
1d3897e0 CK |
201 | continue; |
202 | } | |
203 | ||
91e1a520 CK |
204 | r = amdgpu_sync_fence(adev, sync, f); |
205 | if (r) | |
206 | break; | |
d38ceaf9 AD |
207 | } |
208 | return r; | |
209 | } | |
210 | ||
e61235db CK |
211 | struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync) |
212 | { | |
213 | struct amdgpu_sync_entry *e; | |
214 | struct hlist_node *tmp; | |
215 | struct fence *f; | |
216 | int i; | |
217 | ||
218 | hash_for_each_safe(sync->fences, i, tmp, e, node) { | |
219 | ||
220 | f = e->fence; | |
221 | ||
222 | hash_del(&e->node); | |
223 | kfree(e); | |
224 | ||
225 | if (!fence_is_signaled(f)) | |
226 | return f; | |
227 | ||
228 | fence_put(f); | |
229 | } | |
230 | return NULL; | |
231 | } | |
232 | ||
f91b3a69 CK |
233 | int amdgpu_sync_wait(struct amdgpu_sync *sync) |
234 | { | |
235 | struct amdgpu_sync_entry *e; | |
236 | struct hlist_node *tmp; | |
237 | int i, r; | |
238 | ||
239 | hash_for_each_safe(sync->fences, i, tmp, e, node) { | |
240 | r = fence_wait(e->fence, false); | |
241 | if (r) | |
242 | return r; | |
243 | ||
244 | hash_del(&e->node); | |
245 | fence_put(e->fence); | |
246 | kfree(e); | |
247 | } | |
3daea9e3 | 248 | |
f91b3a69 CK |
249 | return 0; |
250 | } | |
251 | ||
d38ceaf9 AD |
252 | /** |
253 | * amdgpu_sync_free - free the sync object | |
254 | * | |
d38ceaf9 | 255 | * @sync: sync object to use |
d38ceaf9 | 256 | * |
2f4b9400 | 257 | * Free the sync object. |
d38ceaf9 | 258 | */ |
8a8f0b48 | 259 | void amdgpu_sync_free(struct amdgpu_sync *sync) |
d38ceaf9 | 260 | { |
f91b3a69 CK |
261 | struct amdgpu_sync_entry *e; |
262 | struct hlist_node *tmp; | |
d38ceaf9 AD |
263 | unsigned i; |
264 | ||
f91b3a69 CK |
265 | hash_for_each_safe(sync->fences, i, tmp, e, node) { |
266 | hash_del(&e->node); | |
267 | fence_put(e->fence); | |
268 | kfree(e); | |
269 | } | |
270 | ||
3c62338c | 271 | fence_put(sync->last_vm_update); |
d38ceaf9 | 272 | } |