[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ttm.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __AMDGPU_TTM_H__
#define __AMDGPU_TTM_H__

#include <linux/dma-direction.h>
#include <drm/gpu_scheduler.h>
#include "amdgpu.h"

#define AMDGPU_PL_GDS		(TTM_PL_PRIV + 0)
#define AMDGPU_PL_GWS		(TTM_PL_PRIV + 1)
#define AMDGPU_PL_OA		(TTM_PL_PRIV + 2)

#define AMDGPU_PL_FLAG_GDS		(TTM_PL_FLAG_PRIV << 0)
#define AMDGPU_PL_FLAG_GWS		(TTM_PL_FLAG_PRIV << 1)
#define AMDGPU_PL_FLAG_OA		(TTM_PL_FLAG_PRIV << 2)

#define AMDGPU_GTT_MAX_TRANSFER_SIZE	512
#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2

#define AMDGPU_POISON	0xd0bed0be

struct amdgpu_mman {
	struct ttm_bo_device		bdev;
	bool				mem_global_referenced;
	bool				initialized;
	void __iomem			*aper_base_kaddr;

#if defined(CONFIG_DEBUG_FS)
	struct dentry			*debugfs_entries[8];
#endif

	/* buffer handling */
	const struct amdgpu_buffer_funcs	*buffer_funcs;
	struct amdgpu_ring			*buffer_funcs_ring;
	bool					buffer_funcs_enabled;

	struct mutex				gtt_window_lock;
	/* Scheduler entity for buffer moves */
	struct drm_sched_entity			entity;
};

struct amdgpu_copy_mem {
	struct ttm_buffer_object	*bo;
	struct ttm_mem_reg		*mem;
	unsigned long			offset;
};

extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;

bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);

u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
			      struct ttm_mem_reg *mem,
			      struct device *dev,
			      enum dma_data_direction dir,
			      struct sg_table **sgt);
void amdgpu_vram_mgr_free_sgt(struct amdgpu_device *adev,
			      struct device *dev,
			      enum dma_data_direction dir,
			      struct sg_table *sgt);
uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);

int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_late_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
					bool enable);

int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
		       uint64_t dst_offset, uint32_t byte_count,
		       struct dma_resv *resv,
		       struct dma_fence **fence, bool direct_submit,
		       bool vm_needs_flush, bool tmz);
int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
			       const struct amdgpu_copy_mem *src,
			       const struct amdgpu_copy_mem *dst,
			       uint64_t size, bool tmz,
			       struct dma_resv *resv,
			       struct dma_fence **f);
int amdgpu_fill_buffer(struct amdgpu_bo *bo,
			uint32_t src_data,
			struct dma_resv *resv,
			struct dma_fence **fence);

int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);

#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages);
bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
#else
static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
					       struct page **pages)
{
	return -EPERM;
}
static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
{
	return false;
}
#endif

void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
				     uint32_t flags);
bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
				  unsigned long end);
bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
				       int *last_invalidated);
bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
				 struct ttm_mem_reg *mem);

int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);

#endif
Commit	Line	Data
c632d799 FC	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __AMDGPU_TTM_H__
	25	#define __AMDGPU_TTM_H__
	26
f44ffd67	27	#include <linux/dma-direction.h>
1b1f42d8	28	#include <drm/gpu_scheduler.h>
f44ffd67	29	#include "amdgpu.h"
c632d799	30
283cde69 CK	31	#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
	32	#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
	33	#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
c632d799	34
283cde69 CK	35	#define AMDGPU_PL_FLAG_GDS (TTM_PL_FLAG_PRIV << 0)
	36	#define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
	37	#define AMDGPU_PL_FLAG_OA (TTM_PL_FLAG_PRIV << 2)
c632d799	38
cc25188a CK	39	#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
	40	#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
	41
ab2f7a5c FK	42	#define AMDGPU_POISON 0xd0bed0be
ab2f7a5c FK	43
c632d799	44	struct amdgpu_mman {
c632d799 FC	45	struct ttm_bo_device bdev;
	46	bool mem_global_referenced;
	47	bool initialized;
f8f4b9a6	48	void __iomem *aper_base_kaddr;
c632d799 FC	49
c632d799 FC	50	#if defined(CONFIG_DEBUG_FS)
a40cfa0b	51	struct dentry *debugfs_entries[8];
c632d799 FC	52	#endif
	53
	54	/* buffer handling */
	55	const struct amdgpu_buffer_funcs *buffer_funcs;
	56	struct amdgpu_ring *buffer_funcs_ring;
81988f9c	57	bool buffer_funcs_enabled;
abca90f1 CK	58
abca90f1 CK	59	struct mutex gtt_window_lock;
c632d799	60	/* Scheduler entity for buffer moves */
1b1f42d8	61	struct drm_sched_entity entity;
c632d799 FC	62	};
c632d799 FC	63
1eca5a53 HK	64	struct amdgpu_copy_mem {
	65	struct ttm_buffer_object *bo;
	66	struct ttm_mem_reg *mem;
	67	unsigned long offset;
	68	};
	69
bb990bb0	70	extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
6a7f76e7	71	extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
bb990bb0	72
3da917b6	73	bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
9255d77d	74	uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
c1c7ce8f	75	int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
bb990bb0	76
ddc21af4	77	u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
f44ffd67 CK	78	int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
	79	struct ttm_mem_reg *mem,
	80	struct device *dev,
	81	enum dma_data_direction dir,
	82	struct sg_table **sgt);
	83	void amdgpu_vram_mgr_free_sgt(struct amdgpu_device *adev,
	84	struct device *dev,
	85	enum dma_data_direction dir,
	86	struct sg_table *sgt);
3c848bb3 CK	87	uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
	88	uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
	89
c396ef9b	90	int amdgpu_ttm_init(struct amdgpu_device *adev);
6f752ec2	91	void amdgpu_ttm_late_init(struct amdgpu_device *adev);
c396ef9b	92	void amdgpu_ttm_fini(struct amdgpu_device *adev);
57adc4ce CK	93	void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
57adc4ce CK	94	bool enable);
c396ef9b	95
fc9c8f54 CK	96	int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
fc9c8f54 CK	97	uint64_t dst_offset, uint32_t byte_count,
52791eee	98	struct dma_resv *resv,
fc9c8f54	99	struct dma_fence **fence, bool direct_submit,
c9dc9cfe	100	bool vm_needs_flush, bool tmz);
1eca5a53	101	int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
f0ee63cb CK	102	const struct amdgpu_copy_mem *src,
f0ee63cb CK	103	const struct amdgpu_copy_mem *dst,
effb97cc	104	uint64_t size, bool tmz,
52791eee	105	struct dma_resv *resv,
1eca5a53	106	struct dma_fence **f);
c632d799	107	int amdgpu_fill_buffer(struct amdgpu_bo *bo,
44e1baeb	108	uint32_t src_data,
52791eee	109	struct dma_resv *resv,
f54d1867	110	struct dma_fence **fence);
c632d799 FC	111
c632d799 FC	112	int amdgpu_mmap(struct file filp, struct vm_area_struct vma);
c5835bbb	113	int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
c1c7ce8f	114	int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
b1a8ef95	115	uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
c855e250	116
ad595b86	117	#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
e5eaa7cc	118	int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo bo, struct page *pages);
899fbde1	119	bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
ad595b86	120	#else
e5eaa7cc PY	121	static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
e5eaa7cc PY	122	struct page **pages)
ad595b86 PY	123	{
	124	return -EPERM;
	125	}
	126	static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
	127	{
	128	return false;
	129	}
	130	#endif
	131
711becf0	132	void amdgpu_ttm_tt_set_user_pages(struct ttm_tt ttm, struct page *pages);
711becf0 CK	133	int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
	134	uint32_t flags);
	135	bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
	136	struct mm_struct amdgpu_ttm_tt_get_usermm(struct ttm_tt ttm);
	137	bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
	138	unsigned long end);
	139	bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
	140	int *last_invalidated);
899fbde1	141	bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
711becf0	142	bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
24a8d289	143	uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt ttm, struct ttm_mem_reg mem);
711becf0 CK	144	uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device adev, struct ttm_tt ttm,
	145	struct ttm_mem_reg *mem);
	146
c5820361	147	int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
c5820361	148
c632d799	149	#endif