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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Christian König <deathsimple@vodafone.de> | |
29 | */ | |
30 | ||
31 | #include <linux/firmware.h> | |
32 | #include <linux/module.h> | |
33 | #include <drm/drmP.h> | |
34 | #include <drm/drm.h> | |
35 | ||
36 | #include "amdgpu.h" | |
37 | #include "amdgpu_pm.h" | |
38 | #include "amdgpu_uvd.h" | |
39 | #include "cikd.h" | |
40 | #include "uvd/uvd_4_2_d.h" | |
41 | ||
42 | /* 1 second timeout */ | |
08086635 | 43 | #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) |
4cb5877c CK |
44 | |
45 | /* Firmware versions for VI */ | |
46 | #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) | |
47 | #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) | |
48 | #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) | |
49 | #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) | |
50 | ||
8e008dd7 | 51 | /* Polaris10/11 firmware version */ |
4cb5877c | 52 | #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) |
d38ceaf9 AD |
53 | |
54 | /* Firmware Names */ | |
55 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
56 | #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" | |
edf600da CK |
57 | #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" |
58 | #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" | |
59 | #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" | |
d38ceaf9 AD |
60 | #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" |
61 | #endif | |
c65444fe JZ |
62 | #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" |
63 | #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" | |
974ee3db | 64 | #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" |
a39c8cea | 65 | #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" |
2cc0c0b5 | 66 | #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" |
925a51c4 | 67 | #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" |
c4642a47 | 68 | #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" |
d38ceaf9 | 69 | |
09bfb891 LL |
70 | #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" |
71 | ||
72 | #define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00) | |
73 | #define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00) | |
74 | #define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00) | |
75 | #define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00) | |
76 | #define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00) | |
77 | ||
d38ceaf9 AD |
78 | /** |
79 | * amdgpu_uvd_cs_ctx - Command submission parser context | |
80 | * | |
81 | * Used for emulating virtual memory support on UVD 4.2. | |
82 | */ | |
83 | struct amdgpu_uvd_cs_ctx { | |
84 | struct amdgpu_cs_parser *parser; | |
85 | unsigned reg, count; | |
86 | unsigned data0, data1; | |
87 | unsigned idx; | |
88 | unsigned ib_idx; | |
89 | ||
90 | /* does the IB has a msg command */ | |
91 | bool has_msg_cmd; | |
92 | ||
93 | /* minimum buffer sizes */ | |
94 | unsigned *buf_sizes; | |
95 | }; | |
96 | ||
97 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
98 | MODULE_FIRMWARE(FIRMWARE_BONAIRE); | |
99 | MODULE_FIRMWARE(FIRMWARE_KABINI); | |
100 | MODULE_FIRMWARE(FIRMWARE_KAVERI); | |
101 | MODULE_FIRMWARE(FIRMWARE_HAWAII); | |
102 | MODULE_FIRMWARE(FIRMWARE_MULLINS); | |
103 | #endif | |
104 | MODULE_FIRMWARE(FIRMWARE_TONGA); | |
105 | MODULE_FIRMWARE(FIRMWARE_CARRIZO); | |
974ee3db | 106 | MODULE_FIRMWARE(FIRMWARE_FIJI); |
a39c8cea | 107 | MODULE_FIRMWARE(FIRMWARE_STONEY); |
2cc0c0b5 FC |
108 | MODULE_FIRMWARE(FIRMWARE_POLARIS10); |
109 | MODULE_FIRMWARE(FIRMWARE_POLARIS11); | |
c4642a47 | 110 | MODULE_FIRMWARE(FIRMWARE_POLARIS12); |
d38ceaf9 | 111 | |
09bfb891 LL |
112 | MODULE_FIRMWARE(FIRMWARE_VEGA10); |
113 | ||
d38ceaf9 AD |
114 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work); |
115 | ||
116 | int amdgpu_uvd_sw_init(struct amdgpu_device *adev) | |
117 | { | |
ead833ec CK |
118 | struct amdgpu_ring *ring; |
119 | struct amd_sched_rq *rq; | |
d38ceaf9 AD |
120 | unsigned long bo_size; |
121 | const char *fw_name; | |
122 | const struct common_firmware_header *hdr; | |
123 | unsigned version_major, version_minor, family_id; | |
124 | int i, r; | |
125 | ||
126 | INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); | |
127 | ||
128 | switch (adev->asic_type) { | |
129 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
130 | case CHIP_BONAIRE: | |
131 | fw_name = FIRMWARE_BONAIRE; | |
132 | break; | |
133 | case CHIP_KABINI: | |
134 | fw_name = FIRMWARE_KABINI; | |
135 | break; | |
136 | case CHIP_KAVERI: | |
137 | fw_name = FIRMWARE_KAVERI; | |
138 | break; | |
139 | case CHIP_HAWAII: | |
140 | fw_name = FIRMWARE_HAWAII; | |
141 | break; | |
142 | case CHIP_MULLINS: | |
143 | fw_name = FIRMWARE_MULLINS; | |
144 | break; | |
145 | #endif | |
146 | case CHIP_TONGA: | |
147 | fw_name = FIRMWARE_TONGA; | |
148 | break; | |
974ee3db DZ |
149 | case CHIP_FIJI: |
150 | fw_name = FIRMWARE_FIJI; | |
151 | break; | |
d38ceaf9 AD |
152 | case CHIP_CARRIZO: |
153 | fw_name = FIRMWARE_CARRIZO; | |
154 | break; | |
a39c8cea SL |
155 | case CHIP_STONEY: |
156 | fw_name = FIRMWARE_STONEY; | |
157 | break; | |
2cc0c0b5 FC |
158 | case CHIP_POLARIS10: |
159 | fw_name = FIRMWARE_POLARIS10; | |
38d75817 | 160 | break; |
2cc0c0b5 FC |
161 | case CHIP_POLARIS11: |
162 | fw_name = FIRMWARE_POLARIS11; | |
c4642a47 | 163 | break; |
09bfb891 LL |
164 | case CHIP_VEGA10: |
165 | fw_name = FIRMWARE_VEGA10; | |
166 | break; | |
c4642a47 JZ |
167 | case CHIP_POLARIS12: |
168 | fw_name = FIRMWARE_POLARIS12; | |
38d75817 | 169 | break; |
d38ceaf9 AD |
170 | default: |
171 | return -EINVAL; | |
172 | } | |
173 | ||
174 | r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); | |
175 | if (r) { | |
176 | dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", | |
177 | fw_name); | |
178 | return r; | |
179 | } | |
180 | ||
181 | r = amdgpu_ucode_validate(adev->uvd.fw); | |
182 | if (r) { | |
183 | dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", | |
184 | fw_name); | |
185 | release_firmware(adev->uvd.fw); | |
186 | adev->uvd.fw = NULL; | |
187 | return r; | |
188 | } | |
189 | ||
c0365541 AN |
190 | /* Set the default UVD handles that the firmware can handle */ |
191 | adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; | |
192 | ||
d38ceaf9 AD |
193 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; |
194 | family_id = le32_to_cpu(hdr->ucode_version) & 0xff; | |
195 | version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; | |
196 | version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; | |
197 | DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", | |
198 | version_major, version_minor, family_id); | |
199 | ||
c0365541 AN |
200 | /* |
201 | * Limit the number of UVD handles depending on microcode major | |
202 | * and minor versions. The firmware version which has 40 UVD | |
203 | * instances support is 1.80. So all subsequent versions should | |
204 | * also have the same support. | |
205 | */ | |
206 | if ((version_major > 0x01) || | |
207 | ((version_major == 0x01) && (version_minor >= 0x50))) | |
208 | adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; | |
209 | ||
562e2689 SJ |
210 | adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | |
211 | (family_id << 8)); | |
212 | ||
8e008dd7 SJ |
213 | if ((adev->asic_type == CHIP_POLARIS10 || |
214 | adev->asic_type == CHIP_POLARIS11) && | |
215 | (adev->uvd.fw_version < FW_1_66_16)) | |
216 | DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", | |
217 | version_major, version_minor); | |
218 | ||
09bfb891 | 219 | bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE |
c0365541 | 220 | + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; |
09bfb891 LL |
221 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) |
222 | bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); | |
223 | ||
4b62e697 CK |
224 | r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, |
225 | AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo, | |
226 | &adev->uvd.gpu_addr, &adev->uvd.cpu_addr); | |
d38ceaf9 AD |
227 | if (r) { |
228 | dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); | |
229 | return r; | |
230 | } | |
231 | ||
ead833ec CK |
232 | ring = &adev->uvd.ring; |
233 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; | |
234 | r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, | |
b3eebe3d | 235 | rq, amdgpu_sched_jobs, NULL); |
ead833ec CK |
236 | if (r != 0) { |
237 | DRM_ERROR("Failed setting up UVD run queue.\n"); | |
238 | return r; | |
239 | } | |
240 | ||
c0365541 | 241 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
d38ceaf9 AD |
242 | atomic_set(&adev->uvd.handles[i], 0); |
243 | adev->uvd.filp[i] = NULL; | |
244 | } | |
245 | ||
246 | /* from uvd v5.0 HW addressing capacity increased to 64 bits */ | |
5fc3aeeb | 247 | if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) |
d38ceaf9 AD |
248 | adev->uvd.address_64_bit = true; |
249 | ||
4cb5877c CK |
250 | switch (adev->asic_type) { |
251 | case CHIP_TONGA: | |
252 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; | |
253 | break; | |
254 | case CHIP_CARRIZO: | |
255 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; | |
256 | break; | |
257 | case CHIP_FIJI: | |
258 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; | |
259 | break; | |
260 | case CHIP_STONEY: | |
261 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; | |
262 | break; | |
263 | default: | |
264 | adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; | |
265 | } | |
266 | ||
d38ceaf9 AD |
267 | return 0; |
268 | } | |
269 | ||
270 | int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) | |
271 | { | |
4ff184d7 | 272 | int i; |
05f19eb5 | 273 | kfree(adev->uvd.saved_bo); |
d38ceaf9 | 274 | |
ead833ec CK |
275 | amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); |
276 | ||
8640faed JZ |
277 | amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo, |
278 | &adev->uvd.gpu_addr, | |
279 | (void **)&adev->uvd.cpu_addr); | |
d38ceaf9 AD |
280 | |
281 | amdgpu_ring_fini(&adev->uvd.ring); | |
282 | ||
4ff184d7 ML |
283 | for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) |
284 | amdgpu_ring_fini(&adev->uvd.ring_enc[i]); | |
285 | ||
d38ceaf9 AD |
286 | release_firmware(adev->uvd.fw); |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | int amdgpu_uvd_suspend(struct amdgpu_device *adev) | |
292 | { | |
3f99dd81 LL |
293 | unsigned size; |
294 | void *ptr; | |
3f99dd81 | 295 | int i; |
d38ceaf9 AD |
296 | |
297 | if (adev->uvd.vcpu_bo == NULL) | |
298 | return 0; | |
299 | ||
c0365541 | 300 | for (i = 0; i < adev->uvd.max_handles; ++i) |
3f99dd81 LL |
301 | if (atomic_read(&adev->uvd.handles[i])) |
302 | break; | |
303 | ||
304 | if (i == AMDGPU_MAX_UVD_HANDLES) | |
305 | return 0; | |
306 | ||
85cc88f0 RZ |
307 | cancel_delayed_work_sync(&adev->uvd.idle_work); |
308 | ||
3f99dd81 | 309 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
3f99dd81 | 310 | ptr = adev->uvd.cpu_addr; |
d38ceaf9 | 311 | |
3f99dd81 LL |
312 | adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); |
313 | if (!adev->uvd.saved_bo) | |
314 | return -ENOMEM; | |
d38ceaf9 | 315 | |
ba0b2275 | 316 | memcpy_fromio(adev->uvd.saved_bo, ptr, size); |
d38ceaf9 AD |
317 | |
318 | return 0; | |
319 | } | |
320 | ||
321 | int amdgpu_uvd_resume(struct amdgpu_device *adev) | |
322 | { | |
323 | unsigned size; | |
324 | void *ptr; | |
d38ceaf9 AD |
325 | |
326 | if (adev->uvd.vcpu_bo == NULL) | |
327 | return -EINVAL; | |
328 | ||
d38ceaf9 | 329 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
d38ceaf9 | 330 | ptr = adev->uvd.cpu_addr; |
d38ceaf9 | 331 | |
3f99dd81 | 332 | if (adev->uvd.saved_bo != NULL) { |
ba0b2275 | 333 | memcpy_toio(ptr, adev->uvd.saved_bo, size); |
3f99dd81 LL |
334 | kfree(adev->uvd.saved_bo); |
335 | adev->uvd.saved_bo = NULL; | |
d23be4e3 LL |
336 | } else { |
337 | const struct common_firmware_header *hdr; | |
338 | unsigned offset; | |
339 | ||
340 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; | |
09bfb891 LL |
341 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
342 | offset = le32_to_cpu(hdr->ucode_array_offset_bytes); | |
343 | memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset, | |
344 | le32_to_cpu(hdr->ucode_size_bytes)); | |
345 | size -= le32_to_cpu(hdr->ucode_size_bytes); | |
346 | ptr += le32_to_cpu(hdr->ucode_size_bytes); | |
347 | } | |
ba0b2275 | 348 | memset_io(ptr, 0, size); |
d23be4e3 | 349 | } |
d38ceaf9 AD |
350 | |
351 | return 0; | |
352 | } | |
353 | ||
354 | void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) | |
355 | { | |
356 | struct amdgpu_ring *ring = &adev->uvd.ring; | |
357 | int i, r; | |
358 | ||
c0365541 | 359 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
d38ceaf9 AD |
360 | uint32_t handle = atomic_read(&adev->uvd.handles[i]); |
361 | if (handle != 0 && adev->uvd.filp[i] == filp) { | |
f54d1867 | 362 | struct dma_fence *fence; |
d38ceaf9 | 363 | |
d7af97db CK |
364 | r = amdgpu_uvd_get_destroy_msg(ring, handle, |
365 | false, &fence); | |
d38ceaf9 AD |
366 | if (r) { |
367 | DRM_ERROR("Error destroying UVD (%d)!\n", r); | |
368 | continue; | |
369 | } | |
370 | ||
f54d1867 CW |
371 | dma_fence_wait(fence, false); |
372 | dma_fence_put(fence); | |
d38ceaf9 AD |
373 | |
374 | adev->uvd.filp[i] = NULL; | |
375 | atomic_set(&adev->uvd.handles[i], 0); | |
376 | } | |
377 | } | |
378 | } | |
379 | ||
765e7fbf | 380 | static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) |
d38ceaf9 AD |
381 | { |
382 | int i; | |
765e7fbf CK |
383 | for (i = 0; i < abo->placement.num_placement; ++i) { |
384 | abo->placements[i].fpfn = 0 >> PAGE_SHIFT; | |
385 | abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; | |
d38ceaf9 AD |
386 | } |
387 | } | |
388 | ||
80983e4d AD |
389 | static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) |
390 | { | |
391 | uint32_t lo, hi; | |
392 | uint64_t addr; | |
393 | ||
394 | lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); | |
395 | hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); | |
396 | addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); | |
397 | ||
398 | return addr; | |
399 | } | |
400 | ||
d38ceaf9 AD |
401 | /** |
402 | * amdgpu_uvd_cs_pass1 - first parsing round | |
403 | * | |
404 | * @ctx: UVD parser context | |
405 | * | |
406 | * Make sure UVD message and feedback buffers are in VRAM and | |
407 | * nobody is violating an 256MB boundary. | |
408 | */ | |
409 | static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) | |
410 | { | |
411 | struct amdgpu_bo_va_mapping *mapping; | |
412 | struct amdgpu_bo *bo; | |
80983e4d AD |
413 | uint32_t cmd; |
414 | uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); | |
d38ceaf9 AD |
415 | int r = 0; |
416 | ||
9cca0b8e CK |
417 | r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); |
418 | if (r) { | |
d38ceaf9 | 419 | DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); |
9cca0b8e | 420 | return r; |
d38ceaf9 AD |
421 | } |
422 | ||
423 | if (!ctx->parser->adev->uvd.address_64_bit) { | |
424 | /* check if it's a message or feedback command */ | |
425 | cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; | |
426 | if (cmd == 0x0 || cmd == 0x3) { | |
427 | /* yes, force it into VRAM */ | |
428 | uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; | |
429 | amdgpu_ttm_placement_from_domain(bo, domain); | |
430 | } | |
431 | amdgpu_uvd_force_into_uvd_segment(bo); | |
432 | ||
433 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); | |
434 | } | |
435 | ||
436 | return r; | |
437 | } | |
438 | ||
439 | /** | |
440 | * amdgpu_uvd_cs_msg_decode - handle UVD decode message | |
441 | * | |
442 | * @msg: pointer to message structure | |
443 | * @buf_sizes: returned buffer sizes | |
444 | * | |
445 | * Peek into the decode message and calculate the necessary buffer sizes. | |
446 | */ | |
8e008dd7 SJ |
447 | static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, |
448 | unsigned buf_sizes[]) | |
d38ceaf9 AD |
449 | { |
450 | unsigned stream_type = msg[4]; | |
451 | unsigned width = msg[6]; | |
452 | unsigned height = msg[7]; | |
453 | unsigned dpb_size = msg[9]; | |
454 | unsigned pitch = msg[28]; | |
455 | unsigned level = msg[57]; | |
456 | ||
457 | unsigned width_in_mb = width / 16; | |
458 | unsigned height_in_mb = ALIGN(height / 16, 2); | |
459 | unsigned fs_in_mb = width_in_mb * height_in_mb; | |
460 | ||
21df89a5 | 461 | unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; |
e5a6858d | 462 | unsigned min_ctx_size = ~0; |
d38ceaf9 AD |
463 | |
464 | image_size = width * height; | |
465 | image_size += image_size / 2; | |
466 | image_size = ALIGN(image_size, 1024); | |
467 | ||
468 | switch (stream_type) { | |
469 | case 0: /* H264 */ | |
d38ceaf9 AD |
470 | switch(level) { |
471 | case 30: | |
472 | num_dpb_buffer = 8100 / fs_in_mb; | |
473 | break; | |
474 | case 31: | |
475 | num_dpb_buffer = 18000 / fs_in_mb; | |
476 | break; | |
477 | case 32: | |
478 | num_dpb_buffer = 20480 / fs_in_mb; | |
479 | break; | |
480 | case 41: | |
481 | num_dpb_buffer = 32768 / fs_in_mb; | |
482 | break; | |
483 | case 42: | |
484 | num_dpb_buffer = 34816 / fs_in_mb; | |
485 | break; | |
486 | case 50: | |
487 | num_dpb_buffer = 110400 / fs_in_mb; | |
488 | break; | |
489 | case 51: | |
490 | num_dpb_buffer = 184320 / fs_in_mb; | |
491 | break; | |
492 | default: | |
493 | num_dpb_buffer = 184320 / fs_in_mb; | |
494 | break; | |
495 | } | |
496 | num_dpb_buffer++; | |
497 | if (num_dpb_buffer > 17) | |
498 | num_dpb_buffer = 17; | |
499 | ||
500 | /* reference picture buffer */ | |
501 | min_dpb_size = image_size * num_dpb_buffer; | |
502 | ||
503 | /* macroblock context buffer */ | |
504 | min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
505 | ||
506 | /* IT surface buffer */ | |
507 | min_dpb_size += width_in_mb * height_in_mb * 32; | |
508 | break; | |
509 | ||
510 | case 1: /* VC1 */ | |
511 | ||
512 | /* reference picture buffer */ | |
513 | min_dpb_size = image_size * 3; | |
514 | ||
515 | /* CONTEXT_BUFFER */ | |
516 | min_dpb_size += width_in_mb * height_in_mb * 128; | |
517 | ||
518 | /* IT surface buffer */ | |
519 | min_dpb_size += width_in_mb * 64; | |
520 | ||
521 | /* DB surface buffer */ | |
522 | min_dpb_size += width_in_mb * 128; | |
523 | ||
524 | /* BP */ | |
525 | tmp = max(width_in_mb, height_in_mb); | |
526 | min_dpb_size += ALIGN(tmp * 7 * 16, 64); | |
527 | break; | |
528 | ||
529 | case 3: /* MPEG2 */ | |
530 | ||
531 | /* reference picture buffer */ | |
532 | min_dpb_size = image_size * 3; | |
533 | break; | |
534 | ||
535 | case 4: /* MPEG4 */ | |
536 | ||
537 | /* reference picture buffer */ | |
538 | min_dpb_size = image_size * 3; | |
539 | ||
540 | /* CM */ | |
541 | min_dpb_size += width_in_mb * height_in_mb * 64; | |
542 | ||
543 | /* IT surface buffer */ | |
544 | min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); | |
545 | break; | |
546 | ||
8e008dd7 SJ |
547 | case 7: /* H264 Perf */ |
548 | switch(level) { | |
549 | case 30: | |
550 | num_dpb_buffer = 8100 / fs_in_mb; | |
551 | break; | |
552 | case 31: | |
553 | num_dpb_buffer = 18000 / fs_in_mb; | |
554 | break; | |
555 | case 32: | |
556 | num_dpb_buffer = 20480 / fs_in_mb; | |
557 | break; | |
558 | case 41: | |
559 | num_dpb_buffer = 32768 / fs_in_mb; | |
560 | break; | |
561 | case 42: | |
562 | num_dpb_buffer = 34816 / fs_in_mb; | |
563 | break; | |
564 | case 50: | |
565 | num_dpb_buffer = 110400 / fs_in_mb; | |
566 | break; | |
567 | case 51: | |
568 | num_dpb_buffer = 184320 / fs_in_mb; | |
569 | break; | |
570 | default: | |
571 | num_dpb_buffer = 184320 / fs_in_mb; | |
572 | break; | |
573 | } | |
574 | num_dpb_buffer++; | |
575 | if (num_dpb_buffer > 17) | |
576 | num_dpb_buffer = 17; | |
577 | ||
578 | /* reference picture buffer */ | |
579 | min_dpb_size = image_size * num_dpb_buffer; | |
580 | ||
4cb5877c | 581 | if (!adev->uvd.use_ctx_buf){ |
8e008dd7 SJ |
582 | /* macroblock context buffer */ |
583 | min_dpb_size += | |
584 | width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
585 | ||
586 | /* IT surface buffer */ | |
587 | min_dpb_size += width_in_mb * height_in_mb * 32; | |
588 | } else { | |
589 | /* macroblock context buffer */ | |
590 | min_ctx_size = | |
591 | width_in_mb * height_in_mb * num_dpb_buffer * 192; | |
592 | } | |
593 | break; | |
594 | ||
d0b83d41 LL |
595 | case 8: /* MJPEG */ |
596 | min_dpb_size = 0; | |
597 | break; | |
598 | ||
86fa0bdc CK |
599 | case 16: /* H265 */ |
600 | image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; | |
601 | image_size = ALIGN(image_size, 256); | |
602 | ||
603 | num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; | |
604 | min_dpb_size = image_size * num_dpb_buffer; | |
8c8bac59 BZ |
605 | min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) |
606 | * 16 * num_dpb_buffer + 52 * 1024; | |
86fa0bdc CK |
607 | break; |
608 | ||
d38ceaf9 AD |
609 | default: |
610 | DRM_ERROR("UVD codec not handled %d!\n", stream_type); | |
611 | return -EINVAL; | |
612 | } | |
613 | ||
614 | if (width > pitch) { | |
615 | DRM_ERROR("Invalid UVD decoding target pitch!\n"); | |
616 | return -EINVAL; | |
617 | } | |
618 | ||
619 | if (dpb_size < min_dpb_size) { | |
620 | DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", | |
621 | dpb_size, min_dpb_size); | |
622 | return -EINVAL; | |
623 | } | |
624 | ||
625 | buf_sizes[0x1] = dpb_size; | |
626 | buf_sizes[0x2] = image_size; | |
8c8bac59 | 627 | buf_sizes[0x4] = min_ctx_size; |
d38ceaf9 AD |
628 | return 0; |
629 | } | |
630 | ||
631 | /** | |
632 | * amdgpu_uvd_cs_msg - handle UVD message | |
633 | * | |
634 | * @ctx: UVD parser context | |
635 | * @bo: buffer object containing the message | |
636 | * @offset: offset into the buffer object | |
637 | * | |
638 | * Peek into the UVD message and extract the session id. | |
639 | * Make sure that we don't open up to many sessions. | |
640 | */ | |
641 | static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, | |
642 | struct amdgpu_bo *bo, unsigned offset) | |
643 | { | |
644 | struct amdgpu_device *adev = ctx->parser->adev; | |
645 | int32_t *msg, msg_type, handle; | |
d38ceaf9 | 646 | void *ptr; |
4127a59e CK |
647 | long r; |
648 | int i; | |
d38ceaf9 AD |
649 | |
650 | if (offset & 0x3F) { | |
651 | DRM_ERROR("UVD messages must be 64 byte aligned!\n"); | |
652 | return -EINVAL; | |
653 | } | |
654 | ||
d38ceaf9 AD |
655 | r = amdgpu_bo_kmap(bo, &ptr); |
656 | if (r) { | |
4127a59e | 657 | DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); |
d38ceaf9 AD |
658 | return r; |
659 | } | |
660 | ||
661 | msg = ptr + offset; | |
662 | ||
663 | msg_type = msg[1]; | |
664 | handle = msg[2]; | |
665 | ||
666 | if (handle == 0) { | |
667 | DRM_ERROR("Invalid UVD handle!\n"); | |
668 | return -EINVAL; | |
669 | } | |
670 | ||
5146419e LL |
671 | switch (msg_type) { |
672 | case 0: | |
673 | /* it's a create msg, calc image size (width * height) */ | |
674 | amdgpu_bo_kunmap(bo); | |
675 | ||
676 | /* try to alloc a new handle */ | |
c0365541 | 677 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
5146419e LL |
678 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
679 | DRM_ERROR("Handle 0x%x already in use!\n", handle); | |
680 | return -EINVAL; | |
681 | } | |
682 | ||
683 | if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { | |
684 | adev->uvd.filp[i] = ctx->parser->filp; | |
685 | return 0; | |
686 | } | |
687 | } | |
688 | ||
689 | DRM_ERROR("No more free UVD handles!\n"); | |
7129d3ae | 690 | return -ENOSPC; |
5146419e LL |
691 | |
692 | case 1: | |
d38ceaf9 | 693 | /* it's a decode msg, calc buffer sizes */ |
8e008dd7 | 694 | r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); |
d38ceaf9 AD |
695 | amdgpu_bo_kunmap(bo); |
696 | if (r) | |
697 | return r; | |
698 | ||
5146419e | 699 | /* validate the handle */ |
c0365541 | 700 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
5146419e LL |
701 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
702 | if (adev->uvd.filp[i] != ctx->parser->filp) { | |
703 | DRM_ERROR("UVD handle collision detected!\n"); | |
704 | return -EINVAL; | |
705 | } | |
706 | return 0; | |
707 | } | |
708 | } | |
709 | ||
710 | DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); | |
711 | return -ENOENT; | |
712 | ||
713 | case 2: | |
d38ceaf9 | 714 | /* it's a destroy msg, free the handle */ |
c0365541 | 715 | for (i = 0; i < adev->uvd.max_handles; ++i) |
d38ceaf9 AD |
716 | atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); |
717 | amdgpu_bo_kunmap(bo); | |
718 | return 0; | |
d38ceaf9 | 719 | |
5146419e LL |
720 | default: |
721 | DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); | |
722 | return -EINVAL; | |
d38ceaf9 | 723 | } |
5146419e | 724 | BUG(); |
d38ceaf9 AD |
725 | return -EINVAL; |
726 | } | |
727 | ||
728 | /** | |
729 | * amdgpu_uvd_cs_pass2 - second parsing round | |
730 | * | |
731 | * @ctx: UVD parser context | |
732 | * | |
733 | * Patch buffer addresses, make sure buffer sizes are correct. | |
734 | */ | |
735 | static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) | |
736 | { | |
737 | struct amdgpu_bo_va_mapping *mapping; | |
738 | struct amdgpu_bo *bo; | |
80983e4d | 739 | uint32_t cmd; |
d38ceaf9 | 740 | uint64_t start, end; |
80983e4d | 741 | uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); |
d38ceaf9 AD |
742 | int r; |
743 | ||
9cca0b8e CK |
744 | r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); |
745 | if (r) { | |
042eb910 | 746 | DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); |
9cca0b8e | 747 | return r; |
042eb910 | 748 | } |
d38ceaf9 AD |
749 | |
750 | start = amdgpu_bo_gpu_offset(bo); | |
751 | ||
a9f87f64 | 752 | end = (mapping->last + 1 - mapping->start); |
d38ceaf9 AD |
753 | end = end * AMDGPU_GPU_PAGE_SIZE + start; |
754 | ||
a9f87f64 | 755 | addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; |
d38ceaf9 AD |
756 | start += addr; |
757 | ||
7270f839 CK |
758 | amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, |
759 | lower_32_bits(start)); | |
760 | amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, | |
761 | upper_32_bits(start)); | |
d38ceaf9 AD |
762 | |
763 | cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; | |
764 | if (cmd < 0x4) { | |
765 | if ((end - start) < ctx->buf_sizes[cmd]) { | |
766 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | |
767 | (unsigned)(end - start), | |
768 | ctx->buf_sizes[cmd]); | |
769 | return -EINVAL; | |
770 | } | |
771 | ||
8c8bac59 BZ |
772 | } else if (cmd == 0x206) { |
773 | if ((end - start) < ctx->buf_sizes[4]) { | |
774 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, | |
775 | (unsigned)(end - start), | |
776 | ctx->buf_sizes[4]); | |
777 | return -EINVAL; | |
778 | } | |
d38ceaf9 AD |
779 | } else if ((cmd != 0x100) && (cmd != 0x204)) { |
780 | DRM_ERROR("invalid UVD command %X!\n", cmd); | |
781 | return -EINVAL; | |
782 | } | |
783 | ||
784 | if (!ctx->parser->adev->uvd.address_64_bit) { | |
785 | if ((start >> 28) != ((end - 1) >> 28)) { | |
786 | DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", | |
787 | start, end); | |
788 | return -EINVAL; | |
789 | } | |
790 | ||
791 | if ((cmd == 0 || cmd == 0x3) && | |
792 | (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { | |
793 | DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", | |
794 | start, end); | |
795 | return -EINVAL; | |
796 | } | |
797 | } | |
798 | ||
799 | if (cmd == 0) { | |
800 | ctx->has_msg_cmd = true; | |
801 | r = amdgpu_uvd_cs_msg(ctx, bo, addr); | |
802 | if (r) | |
803 | return r; | |
804 | } else if (!ctx->has_msg_cmd) { | |
805 | DRM_ERROR("Message needed before other commands are send!\n"); | |
806 | return -EINVAL; | |
807 | } | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
812 | /** | |
813 | * amdgpu_uvd_cs_reg - parse register writes | |
814 | * | |
815 | * @ctx: UVD parser context | |
816 | * @cb: callback function | |
817 | * | |
818 | * Parse the register writes, call cb on each complete command. | |
819 | */ | |
820 | static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, | |
821 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) | |
822 | { | |
50838c8c | 823 | struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; |
d38ceaf9 AD |
824 | int i, r; |
825 | ||
826 | ctx->idx++; | |
827 | for (i = 0; i <= ctx->count; ++i) { | |
828 | unsigned reg = ctx->reg + i; | |
829 | ||
830 | if (ctx->idx >= ib->length_dw) { | |
831 | DRM_ERROR("Register command after end of CS!\n"); | |
832 | return -EINVAL; | |
833 | } | |
834 | ||
835 | switch (reg) { | |
836 | case mmUVD_GPCOM_VCPU_DATA0: | |
837 | ctx->data0 = ctx->idx; | |
838 | break; | |
839 | case mmUVD_GPCOM_VCPU_DATA1: | |
840 | ctx->data1 = ctx->idx; | |
841 | break; | |
842 | case mmUVD_GPCOM_VCPU_CMD: | |
843 | r = cb(ctx); | |
844 | if (r) | |
845 | return r; | |
846 | break; | |
847 | case mmUVD_ENGINE_CNTL: | |
8dd31d74 | 848 | case mmUVD_NO_OP: |
d38ceaf9 AD |
849 | break; |
850 | default: | |
851 | DRM_ERROR("Invalid reg 0x%X!\n", reg); | |
852 | return -EINVAL; | |
853 | } | |
854 | ctx->idx++; | |
855 | } | |
856 | return 0; | |
857 | } | |
858 | ||
859 | /** | |
860 | * amdgpu_uvd_cs_packets - parse UVD packets | |
861 | * | |
862 | * @ctx: UVD parser context | |
863 | * @cb: callback function | |
864 | * | |
865 | * Parse the command stream packets. | |
866 | */ | |
867 | static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, | |
868 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) | |
869 | { | |
50838c8c | 870 | struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; |
d38ceaf9 AD |
871 | int r; |
872 | ||
873 | for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { | |
874 | uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); | |
875 | unsigned type = CP_PACKET_GET_TYPE(cmd); | |
876 | switch (type) { | |
877 | case PACKET_TYPE0: | |
878 | ctx->reg = CP_PACKET0_GET_REG(cmd); | |
879 | ctx->count = CP_PACKET_GET_COUNT(cmd); | |
880 | r = amdgpu_uvd_cs_reg(ctx, cb); | |
881 | if (r) | |
882 | return r; | |
883 | break; | |
884 | case PACKET_TYPE2: | |
885 | ++ctx->idx; | |
886 | break; | |
887 | default: | |
888 | DRM_ERROR("Unknown packet type %d !\n", type); | |
889 | return -EINVAL; | |
890 | } | |
891 | } | |
892 | return 0; | |
893 | } | |
894 | ||
895 | /** | |
896 | * amdgpu_uvd_ring_parse_cs - UVD command submission parser | |
897 | * | |
898 | * @parser: Command submission parser context | |
899 | * | |
900 | * Parse the command stream, patch in addresses as necessary. | |
901 | */ | |
902 | int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) | |
903 | { | |
904 | struct amdgpu_uvd_cs_ctx ctx = {}; | |
905 | unsigned buf_sizes[] = { | |
906 | [0x00000000] = 2048, | |
8c8bac59 BZ |
907 | [0x00000001] = 0xFFFFFFFF, |
908 | [0x00000002] = 0xFFFFFFFF, | |
d38ceaf9 | 909 | [0x00000003] = 2048, |
8c8bac59 | 910 | [0x00000004] = 0xFFFFFFFF, |
d38ceaf9 | 911 | }; |
50838c8c | 912 | struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; |
d38ceaf9 AD |
913 | int r; |
914 | ||
45088efc CK |
915 | parser->job->vm = NULL; |
916 | ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); | |
917 | ||
d38ceaf9 AD |
918 | if (ib->length_dw % 16) { |
919 | DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", | |
920 | ib->length_dw); | |
921 | return -EINVAL; | |
922 | } | |
923 | ||
924 | ctx.parser = parser; | |
925 | ctx.buf_sizes = buf_sizes; | |
926 | ctx.ib_idx = ib_idx; | |
927 | ||
042eb910 AD |
928 | /* first round only required on chips without UVD 64 bit address support */ |
929 | if (!parser->adev->uvd.address_64_bit) { | |
930 | /* first round, make sure the buffers are actually in the UVD segment */ | |
931 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); | |
932 | if (r) | |
933 | return r; | |
934 | } | |
d38ceaf9 AD |
935 | |
936 | /* second round, patch buffer addresses into the command stream */ | |
937 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); | |
938 | if (r) | |
939 | return r; | |
940 | ||
941 | if (!ctx.has_msg_cmd) { | |
942 | DRM_ERROR("UVD-IBs need a msg command!\n"); | |
943 | return -EINVAL; | |
944 | } | |
945 | ||
d38ceaf9 AD |
946 | return 0; |
947 | } | |
948 | ||
d7af97db | 949 | static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, |
f54d1867 | 950 | bool direct, struct dma_fence **fence) |
d38ceaf9 AD |
951 | { |
952 | struct ttm_validate_buffer tv; | |
953 | struct ww_acquire_ctx ticket; | |
954 | struct list_head head; | |
d71518b5 CK |
955 | struct amdgpu_job *job; |
956 | struct amdgpu_ib *ib; | |
f54d1867 | 957 | struct dma_fence *f = NULL; |
7b5ec431 | 958 | struct amdgpu_device *adev = ring->adev; |
d38ceaf9 | 959 | uint64_t addr; |
09bfb891 | 960 | uint32_t data[4]; |
d38ceaf9 AD |
961 | int i, r; |
962 | ||
963 | memset(&tv, 0, sizeof(tv)); | |
964 | tv.bo = &bo->tbo; | |
965 | ||
966 | INIT_LIST_HEAD(&head); | |
967 | list_add(&tv.head, &head); | |
968 | ||
969 | r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL); | |
970 | if (r) | |
971 | return r; | |
972 | ||
a7d64de6 | 973 | if (!ring->adev->uvd.address_64_bit) { |
d38ceaf9 AD |
974 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); |
975 | amdgpu_uvd_force_into_uvd_segment(bo); | |
976 | } | |
977 | ||
978 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); | |
979 | if (r) | |
980 | goto err; | |
d71518b5 CK |
981 | |
982 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); | |
7b5ec431 | 983 | if (r) |
d71518b5 | 984 | goto err; |
d38ceaf9 | 985 | |
09bfb891 LL |
986 | if (adev->asic_type >= CHIP_VEGA10) { |
987 | data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0); | |
988 | data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0); | |
989 | data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0); | |
990 | data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0); | |
991 | } else { | |
992 | data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); | |
993 | data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); | |
994 | data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); | |
995 | data[3] = PACKET0(mmUVD_NO_OP, 0); | |
996 | } | |
997 | ||
d71518b5 | 998 | ib = &job->ibs[0]; |
d38ceaf9 | 999 | addr = amdgpu_bo_gpu_offset(bo); |
09bfb891 | 1000 | ib->ptr[0] = data[0]; |
7b5ec431 | 1001 | ib->ptr[1] = addr; |
09bfb891 | 1002 | ib->ptr[2] = data[1]; |
7b5ec431 | 1003 | ib->ptr[3] = addr >> 32; |
09bfb891 | 1004 | ib->ptr[4] = data[2]; |
7b5ec431 | 1005 | ib->ptr[5] = 0; |
c8b4f288 | 1006 | for (i = 6; i < 16; i += 2) { |
09bfb891 | 1007 | ib->ptr[i] = data[3]; |
c8b4f288 AD |
1008 | ib->ptr[i+1] = 0; |
1009 | } | |
7b5ec431 | 1010 | ib->length_dw = 16; |
d38ceaf9 | 1011 | |
d7af97db | 1012 | if (direct) { |
50ddc75e | 1013 | r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); |
f54d1867 | 1014 | job->fence = dma_fence_get(f); |
d7af97db CK |
1015 | if (r) |
1016 | goto err_free; | |
1017 | ||
1018 | amdgpu_job_free(job); | |
1019 | } else { | |
ead833ec | 1020 | r = amdgpu_job_submit(job, ring, &adev->uvd.entity, |
d7af97db CK |
1021 | AMDGPU_FENCE_OWNER_UNDEFINED, &f); |
1022 | if (r) | |
1023 | goto err_free; | |
1024 | } | |
d38ceaf9 | 1025 | |
1763552e | 1026 | ttm_eu_fence_buffer_objects(&ticket, &head, f); |
d38ceaf9 | 1027 | |
7b5ec431 | 1028 | if (fence) |
f54d1867 | 1029 | *fence = dma_fence_get(f); |
d38ceaf9 | 1030 | amdgpu_bo_unref(&bo); |
f54d1867 | 1031 | dma_fence_put(f); |
7b5ec431 | 1032 | |
7b5ec431 | 1033 | return 0; |
d71518b5 CK |
1034 | |
1035 | err_free: | |
1036 | amdgpu_job_free(job); | |
1037 | ||
d38ceaf9 AD |
1038 | err: |
1039 | ttm_eu_backoff_reservation(&ticket, &head); | |
1040 | return r; | |
1041 | } | |
1042 | ||
1043 | /* multiple fence commands without any stream commands in between can | |
1044 | crash the vcpu so just try to emmit a dummy create/destroy msg to | |
1045 | avoid this */ | |
1046 | int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, | |
f54d1867 | 1047 | struct dma_fence **fence) |
d38ceaf9 AD |
1048 | { |
1049 | struct amdgpu_device *adev = ring->adev; | |
1050 | struct amdgpu_bo *bo; | |
1051 | uint32_t *msg; | |
1052 | int r, i; | |
1053 | ||
1054 | r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, | |
857d913d | 1055 | AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
1056 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
1057 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
2046d46d | 1058 | NULL, NULL, 0, &bo); |
d38ceaf9 AD |
1059 | if (r) |
1060 | return r; | |
1061 | ||
1062 | r = amdgpu_bo_reserve(bo, false); | |
1063 | if (r) { | |
1064 | amdgpu_bo_unref(&bo); | |
1065 | return r; | |
1066 | } | |
1067 | ||
1068 | r = amdgpu_bo_kmap(bo, (void **)&msg); | |
1069 | if (r) { | |
1070 | amdgpu_bo_unreserve(bo); | |
1071 | amdgpu_bo_unref(&bo); | |
1072 | return r; | |
1073 | } | |
1074 | ||
1075 | /* stitch together an UVD create msg */ | |
1076 | msg[0] = cpu_to_le32(0x00000de4); | |
1077 | msg[1] = cpu_to_le32(0x00000000); | |
1078 | msg[2] = cpu_to_le32(handle); | |
1079 | msg[3] = cpu_to_le32(0x00000000); | |
1080 | msg[4] = cpu_to_le32(0x00000000); | |
1081 | msg[5] = cpu_to_le32(0x00000000); | |
1082 | msg[6] = cpu_to_le32(0x00000000); | |
1083 | msg[7] = cpu_to_le32(0x00000780); | |
1084 | msg[8] = cpu_to_le32(0x00000440); | |
1085 | msg[9] = cpu_to_le32(0x00000000); | |
1086 | msg[10] = cpu_to_le32(0x01b37000); | |
1087 | for (i = 11; i < 1024; ++i) | |
1088 | msg[i] = cpu_to_le32(0x0); | |
1089 | ||
1090 | amdgpu_bo_kunmap(bo); | |
1091 | amdgpu_bo_unreserve(bo); | |
1092 | ||
d7af97db | 1093 | return amdgpu_uvd_send_msg(ring, bo, true, fence); |
d38ceaf9 AD |
1094 | } |
1095 | ||
1096 | int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, | |
f54d1867 | 1097 | bool direct, struct dma_fence **fence) |
d38ceaf9 AD |
1098 | { |
1099 | struct amdgpu_device *adev = ring->adev; | |
1100 | struct amdgpu_bo *bo; | |
1101 | uint32_t *msg; | |
1102 | int r, i; | |
1103 | ||
1104 | r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true, | |
857d913d | 1105 | AMDGPU_GEM_DOMAIN_VRAM, |
03f48dd5 CK |
1106 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
1107 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, | |
2046d46d | 1108 | NULL, NULL, 0, &bo); |
d38ceaf9 AD |
1109 | if (r) |
1110 | return r; | |
1111 | ||
1112 | r = amdgpu_bo_reserve(bo, false); | |
1113 | if (r) { | |
1114 | amdgpu_bo_unref(&bo); | |
1115 | return r; | |
1116 | } | |
1117 | ||
1118 | r = amdgpu_bo_kmap(bo, (void **)&msg); | |
1119 | if (r) { | |
1120 | amdgpu_bo_unreserve(bo); | |
1121 | amdgpu_bo_unref(&bo); | |
1122 | return r; | |
1123 | } | |
1124 | ||
1125 | /* stitch together an UVD destroy msg */ | |
1126 | msg[0] = cpu_to_le32(0x00000de4); | |
1127 | msg[1] = cpu_to_le32(0x00000002); | |
1128 | msg[2] = cpu_to_le32(handle); | |
1129 | msg[3] = cpu_to_le32(0x00000000); | |
1130 | for (i = 4; i < 1024; ++i) | |
1131 | msg[i] = cpu_to_le32(0x0); | |
1132 | ||
1133 | amdgpu_bo_kunmap(bo); | |
1134 | amdgpu_bo_unreserve(bo); | |
1135 | ||
d7af97db | 1136 | return amdgpu_uvd_send_msg(ring, bo, direct, fence); |
d38ceaf9 AD |
1137 | } |
1138 | ||
1139 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work) | |
1140 | { | |
1141 | struct amdgpu_device *adev = | |
1142 | container_of(work, struct amdgpu_device, uvd.idle_work.work); | |
713c0021 | 1143 | unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring); |
d38ceaf9 | 1144 | |
d9af2259 XY |
1145 | if (amdgpu_sriov_vf(adev)) |
1146 | return; | |
1147 | ||
713c0021 | 1148 | if (fences == 0) { |
d38ceaf9 AD |
1149 | if (adev->pm.dpm_enabled) { |
1150 | amdgpu_dpm_enable_uvd(adev, false); | |
1151 | } else { | |
1152 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); | |
e38ca2b3 RZ |
1153 | /* shutdown the UVD block */ |
1154 | amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, | |
1155 | AMD_PG_STATE_GATE); | |
1156 | amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, | |
1157 | AMD_CG_STATE_GATE); | |
d38ceaf9 AD |
1158 | } |
1159 | } else { | |
08086635 | 1160 | schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); |
d38ceaf9 AD |
1161 | } |
1162 | } | |
1163 | ||
c4120d55 | 1164 | void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) |
d38ceaf9 | 1165 | { |
c4120d55 | 1166 | struct amdgpu_device *adev = ring->adev; |
d38ceaf9 | 1167 | bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); |
d38ceaf9 | 1168 | |
d9af2259 XY |
1169 | if (amdgpu_sriov_vf(adev)) |
1170 | return; | |
1171 | ||
d38ceaf9 AD |
1172 | if (set_clocks) { |
1173 | if (adev->pm.dpm_enabled) { | |
1174 | amdgpu_dpm_enable_uvd(adev, true); | |
1175 | } else { | |
1176 | amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); | |
e38ca2b3 RZ |
1177 | amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, |
1178 | AMD_CG_STATE_UNGATE); | |
1179 | amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, | |
1180 | AMD_PG_STATE_UNGATE); | |
d38ceaf9 AD |
1181 | } |
1182 | } | |
1183 | } | |
c4120d55 CK |
1184 | |
1185 | void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) | |
1186 | { | |
1187 | schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); | |
1188 | } | |
8de190c9 CK |
1189 | |
1190 | /** | |
1191 | * amdgpu_uvd_ring_test_ib - test ib execution | |
1192 | * | |
1193 | * @ring: amdgpu_ring pointer | |
1194 | * | |
1195 | * Test if we can successfully execute an IB | |
1196 | */ | |
bbec97aa | 1197 | int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
8de190c9 | 1198 | { |
f54d1867 | 1199 | struct dma_fence *fence; |
bbec97aa | 1200 | long r; |
8de190c9 CK |
1201 | |
1202 | r = amdgpu_uvd_get_create_msg(ring, 1, NULL); | |
1203 | if (r) { | |
bbec97aa | 1204 | DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); |
8de190c9 CK |
1205 | goto error; |
1206 | } | |
1207 | ||
1208 | r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); | |
1209 | if (r) { | |
bbec97aa | 1210 | DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); |
8de190c9 CK |
1211 | goto error; |
1212 | } | |
1213 | ||
f54d1867 | 1214 | r = dma_fence_wait_timeout(fence, false, timeout); |
bbec97aa CK |
1215 | if (r == 0) { |
1216 | DRM_ERROR("amdgpu: IB test timed out.\n"); | |
1217 | r = -ETIMEDOUT; | |
1218 | } else if (r < 0) { | |
1219 | DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); | |
1220 | } else { | |
1221 | DRM_INFO("ib test on ring %d succeeded\n", ring->idx); | |
1222 | r = 0; | |
8de190c9 | 1223 | } |
bbec97aa | 1224 | |
f54d1867 | 1225 | dma_fence_put(fence); |
c2a4c5b7 JC |
1226 | |
1227 | error: | |
8de190c9 CK |
1228 | return r; |
1229 | } | |
44879b62 AN |
1230 | |
1231 | /** | |
1232 | * amdgpu_uvd_used_handles - returns used UVD handles | |
1233 | * | |
1234 | * @adev: amdgpu_device pointer | |
1235 | * | |
1236 | * Returns the number of UVD handles in use | |
1237 | */ | |
1238 | uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) | |
1239 | { | |
1240 | unsigned i; | |
1241 | uint32_t used_handles = 0; | |
1242 | ||
1243 | for (i = 0; i < adev->uvd.max_handles; ++i) { | |
1244 | /* | |
1245 | * Handles can be freed in any order, and not | |
1246 | * necessarily linear. So we need to count | |
1247 | * all non-zero handles. | |
1248 | */ | |
1249 | if (atomic_read(&adev->uvd.handles[i])) | |
1250 | used_handles++; | |
1251 | } | |
1252 | ||
1253 | return used_handles; | |
1254 | } |