[mirror_ubuntu-kernels.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vcn.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __AMDGPU_VCN_H__
#define __AMDGPU_VCN_H__

#define AMDGPU_VCN_STACK_SIZE		(128*1024)
#define AMDGPU_VCN_CONTEXT_SIZE 	(512*1024)

#define AMDGPU_VCN_FIRMWARE_OFFSET	256
#define AMDGPU_VCN_MAX_ENC_RINGS	3

#define AMDGPU_MAX_VCN_INSTANCES	2

#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)

#define VCN_DEC_KMD_CMD 		0x80000000
#define VCN_DEC_CMD_FENCE		0x00000000
#define VCN_DEC_CMD_TRAP		0x00000001
#define VCN_DEC_CMD_WRITE_REG		0x00000004
#define VCN_DEC_CMD_REG_READ_COND_WAIT	0x00000006
#define VCN_DEC_CMD_PACKET_START	0x0000000a
#define VCN_DEC_CMD_PACKET_END		0x0000000b

#define VCN_ENC_CMD_NO_OP		0x00000000
#define VCN_ENC_CMD_END 		0x00000001
#define VCN_ENC_CMD_IB			0x00000002
#define VCN_ENC_CMD_FENCE		0x00000003
#define VCN_ENC_CMD_TRAP		0x00000004
#define VCN_ENC_CMD_REG_WRITE		0x0000000b
#define VCN_ENC_CMD_REG_WAIT		0x0000000c

#define VCN_VID_SOC_ADDRESS_2_0 	0x1fa00
#define VCN_AON_SOC_ADDRESS_2_0 	0x1f800
#define VCN_VID_IP_ADDRESS_2_0		0x0
#define VCN_AON_IP_ADDRESS_2_0		0x30000

#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) 				\
	({	WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); 			\
		WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, 				\
			UVD_DPG_LMA_CTL__MASK_EN_MASK | 				\
			((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 	\
			<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | 			\
			(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); 		\
		RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); 				\
	})

#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) 			\
	do { 										\
		WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); 			\
		WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); 			\
		WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, 				\
			UVD_DPG_LMA_CTL__READ_WRITE_MASK | 				\
			((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 	\
			<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | 			\
			(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); 		\
	} while (0)

#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst, reg) 						\
	({											\
		uint32_t internal_reg_offset, addr;						\
		bool video_range, aon_range;							\
												\
		addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg);		\
		addr <<= 2; 									\
		video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && 		\
				((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600)))));	\
		aon_range   = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && 		\
				((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600)))));	\
		if (video_range) 								\
			internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + 	\
				(VCN_VID_IP_ADDRESS_2_0));					\
		else if (aon_range)								\
			internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + 	\
				(VCN_AON_IP_ADDRESS_2_0));					\
		else										\
			internal_reg_offset = (0xFFFFF & addr);					\
												\
		internal_reg_offset >>= 2;							\
	})

#define RREG32_SOC15_DPG_MODE_2_0(offset, mask_en) 						\
	({ 											\
		WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, 					\
			(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | 				\
			mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | 				\
			offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); 			\
		RREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA); 					\
	})

#define WREG32_SOC15_DPG_MODE_2_0(offset, value, mask_en, indirect)				\
	do { 											\
		if (!indirect) { 								\
			WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA, value); 			\
			WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, 				\
				(0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | 			\
				 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | 			\
				 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); 		\
		} else { 									\
			*adev->vcn.dpg_sram_curr_addr++ = offset; 				\
			*adev->vcn.dpg_sram_curr_addr++ = value; 				\
		} 										\
	} while (0)

enum engine_status_constants {
	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
	UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
	UVD_STATUS__UVD_BUSY = 0x00000004,
	GB_ADDR_CONFIG_DEFAULT = 0x26010011,
	UVD_STATUS__IDLE = 0x2,
	UVD_STATUS__BUSY = 0x5,
	UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
	UVD_STATUS__RBC_BUSY = 0x1,
	UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
};

enum internal_dpg_state {
	VCN_DPG_STATE__UNPAUSE = 0,
	VCN_DPG_STATE__PAUSE,
};

struct dpg_pause_state {
	enum internal_dpg_state fw_based;
	enum internal_dpg_state jpeg;
};

struct amdgpu_vcn_reg{
	unsigned	data0;
	unsigned	data1;
	unsigned	cmd;
	unsigned	nop;
	unsigned	context_id;
	unsigned	ib_vmid;
	unsigned	ib_bar_low;
	unsigned	ib_bar_high;
	unsigned	ib_size;
	unsigned	gp_scratch8;
	unsigned	scratch9;
	unsigned	jpeg_pitch;
};

struct amdgpu_vcn_inst {
	struct amdgpu_bo	*vcpu_bo;
	void			*cpu_addr;
	uint64_t		gpu_addr;
	void			*saved_bo;
	struct amdgpu_ring	ring_dec;
	struct amdgpu_ring	ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
	struct amdgpu_ring	ring_jpeg;
	struct amdgpu_irq_src	irq;
	struct amdgpu_vcn_reg	external;
};

struct amdgpu_vcn {
	unsigned		fw_version;
	struct delayed_work	idle_work;
	const struct firmware	*fw;	/* VCN firmware */
	unsigned		num_enc_rings;
	enum amd_powergating_state cur_state;
	struct dpg_pause_state pause_state;

	bool			indirect_sram;
	struct amdgpu_bo	*dpg_sram_bo;
	void			*dpg_sram_cpu_addr;
	uint64_t		dpg_sram_gpu_addr;
	uint32_t		*dpg_sram_curr_addr;

	uint8_t	num_vcn_inst;
	struct amdgpu_vcn_inst	inst[AMDGPU_MAX_VCN_INSTANCES];
	struct amdgpu_vcn_reg	internal;

	unsigned	harvest_config;
	int (*pause_dpg_mode)(struct amdgpu_device *adev,
		struct dpg_pause_state *new_state);
};

int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
int amdgpu_vcn_resume(struct amdgpu_device *adev);
void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);

int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);

int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);

int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout);

#endif
Commit	Line	Data
95d0906f LL	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __AMDGPU_VCN_H__
	25	#define __AMDGPU_VCN_H__
	26
825da4d9	27	#define AMDGPU_VCN_STACK_SIZE (128*1024)
60a2309e	28	#define AMDGPU_VCN_CONTEXT_SIZE (512*1024)
825da4d9	29
95aa13f6 LL	30	#define AMDGPU_VCN_FIRMWARE_OFFSET 256
	31	#define AMDGPU_VCN_MAX_ENC_RINGS 3
	32
c01b6a1d JZ	33	#define AMDGPU_MAX_VCN_INSTANCES 2
c01b6a1d JZ	34
cd1fd7b3 JZ	35	#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
	36	#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
	37
333fe325	38	#define VCN_DEC_KMD_CMD 0x80000000
3639f7d8 LL	39	#define VCN_DEC_CMD_FENCE 0x00000000
	40	#define VCN_DEC_CMD_TRAP 0x00000001
	41	#define VCN_DEC_CMD_WRITE_REG 0x00000004
	42	#define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
	43	#define VCN_DEC_CMD_PACKET_START 0x0000000a
	44	#define VCN_DEC_CMD_PACKET_END 0x0000000b
7741cced	45
8ace845f LL	46	#define VCN_ENC_CMD_NO_OP 0x00000000
	47	#define VCN_ENC_CMD_END 0x00000001
	48	#define VCN_ENC_CMD_IB 0x00000002
	49	#define VCN_ENC_CMD_FENCE 0x00000003
	50	#define VCN_ENC_CMD_TRAP 0x00000004
	51	#define VCN_ENC_CMD_REG_WRITE 0x0000000b
	52	#define VCN_ENC_CMD_REG_WAIT 0x0000000c
	53
19c663fc LL	54	#define VCN_VID_SOC_ADDRESS_2_0 0x1fa00
	55	#define VCN_AON_SOC_ADDRESS_2_0 0x1f800
	56	#define VCN_VID_IP_ADDRESS_2_0 0x0
	57	#define VCN_AON_IP_ADDRESS_2_0 0x30000
	58
05eee12d LL	59	#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
	60	({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
	61	WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
	62	UVD_DPG_LMA_CTL__MASK_EN_MASK \| \
	63	((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
	64	<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) \| \
	65	(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
	66	RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
	67	})
	68
	69	#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
	70	do { \
	71	WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
	72	WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
	73	WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
	74	UVD_DPG_LMA_CTL__READ_WRITE_MASK \| \
	75	((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
	76	<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) \| \
	77	(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
	78	} while (0)
	79
19c663fc LL	80	#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst, reg) \
	81	({ \
	82	uint32_t internal_reg_offset, addr; \
	83	bool video_range, aon_range; \
	84	\
	85	addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
	86	addr <<= 2; \
	87	video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \
	88	((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \
	89	aon_range = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && \
	90	((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600))))); \
	91	if (video_range) \
	92	internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + \
	93	(VCN_VID_IP_ADDRESS_2_0)); \
	94	else if (aon_range) \
	95	internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + \
	96	(VCN_AON_IP_ADDRESS_2_0)); \
	97	else \
	98	internal_reg_offset = (0xFFFFF & addr); \
	99	\
	100	internal_reg_offset >>= 2; \
	101	})
	102
	103	#define RREG32_SOC15_DPG_MODE_2_0(offset, mask_en) \
	104	({ \
	105	WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, \
	106	(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT \| \
	107	mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT \| \
	108	offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
	109	RREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA); \
	110	})
	111
	112	#define WREG32_SOC15_DPG_MODE_2_0(offset, value, mask_en, indirect) \
	113	do { \
	114	if (!indirect) { \
	115	WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA, value); \
	116	WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, \
	117	(0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT \| \
	118	mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT \| \
	119	offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
dc8ae677 LL	120	} else { \
	121	*adev->vcn.dpg_sram_curr_addr++ = offset; \
	122	*adev->vcn.dpg_sram_curr_addr++ = value; \
19c663fc LL	123	} \
	124	} while (0)
	125
d58c5d9a RZ	126	enum engine_status_constants {
d58c5d9a RZ	127	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
863dd269	128	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
d58c5d9a RZ	129	UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
	130	UVD_STATUS__UVD_BUSY = 0x00000004,
	131	GB_ADDR_CONFIG_DEFAULT = 0x26010011,
	132	UVD_STATUS__IDLE = 0x2,
	133	UVD_STATUS__BUSY = 0x5,
	134	UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
	135	UVD_STATUS__RBC_BUSY = 0x1,
1b61de45	136	UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
d58c5d9a RZ	137	};
d58c5d9a RZ	138
0b8690b7 JZ	139	enum internal_dpg_state {
	140	VCN_DPG_STATE__UNPAUSE = 0,
	141	VCN_DPG_STATE__PAUSE,
	142	};
	143
	144	struct dpg_pause_state {
	145	enum internal_dpg_state fw_based;
	146	enum internal_dpg_state jpeg;
	147	};
	148
45a1a48b	149	struct amdgpu_vcn_reg{
60a2309e LL	150	unsigned data0;
	151	unsigned data1;
	152	unsigned cmd;
	153	unsigned nop;
22a8f442 LL	154	unsigned context_id;
	155	unsigned ib_vmid;
	156	unsigned ib_bar_low;
	157	unsigned ib_bar_high;
	158	unsigned ib_size;
	159	unsigned gp_scratch8;
45a1a48b	160	unsigned scratch9;
9085914a	161	unsigned jpeg_pitch;
45a1a48b LL	162	};
45a1a48b LL	163
c01b6a1d	164	struct amdgpu_vcn_inst {
95aa13f6 LL	165	struct amdgpu_bo *vcpu_bo;
	166	void *cpu_addr;
	167	uint64_t gpu_addr;
95aa13f6	168	void *saved_bo;
95aa13f6 LL	169	struct amdgpu_ring ring_dec;
95aa13f6 LL	170	struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
fa3087f7	171	struct amdgpu_ring ring_jpeg;
95aa13f6	172	struct amdgpu_irq_src irq;
c01b6a1d JZ	173	struct amdgpu_vcn_reg external;
	174	};
	175
	176	struct amdgpu_vcn {
	177	unsigned fw_version;
	178	struct delayed_work idle_work;
	179	const struct firmware fw; / VCN firmware */
101c6fee	180	unsigned num_enc_rings;
c95f75f4	181	enum amd_powergating_state cur_state;
0b8690b7	182	struct dpg_pause_state pause_state;
a77b9fdf LL	183
	184	bool indirect_sram;
	185	struct amdgpu_bo *dpg_sram_bo;
	186	void *dpg_sram_cpu_addr;
	187	uint64_t dpg_sram_gpu_addr;
	188	uint32_t *dpg_sram_curr_addr;
c01b6a1d JZ	189
	190	uint8_t num_vcn_inst;
	191	struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES];
	192	struct amdgpu_vcn_reg internal;
	193
cd1fd7b3	194	unsigned harvest_config;
c01b6a1d JZ	195	int (pause_dpg_mode)(struct amdgpu_device adev,
c01b6a1d JZ	196	struct dpg_pause_state *new_state);
95aa13f6 LL	197	};
95aa13f6 LL	198
95d0906f LL	199	int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
	200	int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
	201	int amdgpu_vcn_suspend(struct amdgpu_device *adev);
	202	int amdgpu_vcn_resume(struct amdgpu_device *adev);
	203	void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
	204	void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
8c303c01 LL	205
8c303c01 LL	206	int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
95d0906f LL	207	int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
95d0906f LL	208
2d531d81 LL	209	int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
	210	int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
	211
b1d37606	212	int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
6173040f	213	int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout);
b1d37606	214
95d0906f	215	#endif