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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
02208441 | 30 | #include <linux/idr.h> |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "amdgpu_trace.h" | |
ede0dd86 | 35 | #include "amdgpu_amdkfd.h" |
c8c5e569 | 36 | #include "amdgpu_gmc.h" |
d38ceaf9 | 37 | |
7fc48e59 AG |
38 | /** |
39 | * DOC: GPUVM | |
40 | * | |
d38ceaf9 AD |
41 | * GPUVM is similar to the legacy gart on older asics, however |
42 | * rather than there being a single global gart table | |
43 | * for the entire GPU, there are multiple VM page tables active | |
44 | * at any given time. The VM page tables can contain a mix | |
45 | * vram pages and system memory pages and system memory pages | |
46 | * can be mapped as snooped (cached system pages) or unsnooped | |
47 | * (uncached system pages). | |
48 | * Each VM has an ID associated with it and there is a page table | |
49 | * associated with each VMID. When execting a command buffer, | |
50 | * the kernel tells the the ring what VMID to use for that command | |
51 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
52 | * The userspace drivers maintain their own address space and the kernel | |
53 | * sets up their pages tables accordingly when they submit their | |
54 | * command buffers and a VMID is assigned. | |
55 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
56 | * SI supports 16. | |
57 | */ | |
58 | ||
a9f87f64 CK |
59 | #define START(node) ((node)->start) |
60 | #define LAST(node) ((node)->last) | |
61 | ||
62 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
63 | START, LAST, static, amdgpu_vm_it) | |
64 | ||
65 | #undef START | |
66 | #undef LAST | |
67 | ||
7fc48e59 AG |
68 | /** |
69 | * struct amdgpu_pte_update_params - Local structure | |
70 | * | |
71 | * Encapsulate some VM table update parameters to reduce | |
f4833c4f | 72 | * the number of function parameters |
7fc48e59 | 73 | * |
f4833c4f | 74 | */ |
29efc4f5 | 75 | struct amdgpu_pte_update_params { |
7fc48e59 AG |
76 | |
77 | /** | |
78 | * @adev: amdgpu device we do this update for | |
79 | */ | |
27c5f36f | 80 | struct amdgpu_device *adev; |
7fc48e59 AG |
81 | |
82 | /** | |
83 | * @vm: optional amdgpu_vm we do this update for | |
84 | */ | |
49ac8a24 | 85 | struct amdgpu_vm *vm; |
7fc48e59 AG |
86 | |
87 | /** | |
88 | * @src: address where to copy page table entries from | |
89 | */ | |
f4833c4f | 90 | uint64_t src; |
7fc48e59 AG |
91 | |
92 | /** | |
93 | * @ib: indirect buffer to fill with commands | |
94 | */ | |
f4833c4f | 95 | struct amdgpu_ib *ib; |
7fc48e59 AG |
96 | |
97 | /** | |
98 | * @func: Function which actually does the update | |
99 | */ | |
373ac645 CK |
100 | void (*func)(struct amdgpu_pte_update_params *params, |
101 | struct amdgpu_bo *bo, uint64_t pe, | |
afef8b8f | 102 | uint64_t addr, unsigned count, uint32_t incr, |
6b777607 | 103 | uint64_t flags); |
7fc48e59 AG |
104 | /** |
105 | * @pages_addr: | |
106 | * | |
107 | * DMA addresses to use for mapping, used during VM update by CPU | |
b4d42511 HK |
108 | */ |
109 | dma_addr_t *pages_addr; | |
7fc48e59 AG |
110 | |
111 | /** | |
112 | * @kptr: | |
113 | * | |
114 | * Kernel pointer of PD/PT BO that needs to be updated, | |
115 | * used during VM update by CPU | |
116 | */ | |
b4d42511 | 117 | void *kptr; |
f4833c4f HK |
118 | }; |
119 | ||
7fc48e59 AG |
120 | /** |
121 | * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback | |
122 | */ | |
284710fa | 123 | struct amdgpu_prt_cb { |
7fc48e59 AG |
124 | |
125 | /** | |
126 | * @adev: amdgpu device | |
127 | */ | |
284710fa | 128 | struct amdgpu_device *adev; |
7fc48e59 AG |
129 | |
130 | /** | |
131 | * @cb: callback | |
132 | */ | |
284710fa CK |
133 | struct dma_fence_cb cb; |
134 | }; | |
135 | ||
50783147 CK |
136 | /** |
137 | * amdgpu_vm_level_shift - return the addr shift for each level | |
138 | * | |
139 | * @adev: amdgpu_device pointer | |
7fc48e59 | 140 | * @level: VMPT level |
50783147 | 141 | * |
7fc48e59 AG |
142 | * Returns: |
143 | * The number of bits the pfn needs to be right shifted for a level. | |
50783147 CK |
144 | */ |
145 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
146 | unsigned level) | |
147 | { | |
196f7489 CZ |
148 | unsigned shift = 0xff; |
149 | ||
150 | switch (level) { | |
151 | case AMDGPU_VM_PDB2: | |
152 | case AMDGPU_VM_PDB1: | |
153 | case AMDGPU_VM_PDB0: | |
154 | shift = 9 * (AMDGPU_VM_PDB0 - level) + | |
50783147 | 155 | adev->vm_manager.block_size; |
196f7489 CZ |
156 | break; |
157 | case AMDGPU_VM_PTB: | |
158 | shift = 0; | |
159 | break; | |
160 | default: | |
161 | dev_err(adev->dev, "the level%d isn't supported.\n", level); | |
162 | } | |
163 | ||
164 | return shift; | |
50783147 CK |
165 | } |
166 | ||
d38ceaf9 | 167 | /** |
72a7ec5c | 168 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
169 | * |
170 | * @adev: amdgpu_device pointer | |
7fc48e59 | 171 | * @level: VMPT level |
d38ceaf9 | 172 | * |
7fc48e59 AG |
173 | * Returns: |
174 | * The number of entries in a page directory or page table. | |
d38ceaf9 | 175 | */ |
72a7ec5c CK |
176 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
177 | unsigned level) | |
d38ceaf9 | 178 | { |
196f7489 CZ |
179 | unsigned shift = amdgpu_vm_level_shift(adev, |
180 | adev->vm_manager.root_level); | |
0410c5e5 | 181 | |
196f7489 | 182 | if (level == adev->vm_manager.root_level) |
72a7ec5c | 183 | /* For the root directory */ |
0410c5e5 | 184 | return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; |
196f7489 | 185 | else if (level != AMDGPU_VM_PTB) |
0410c5e5 CK |
186 | /* Everything in between */ |
187 | return 512; | |
188 | else | |
72a7ec5c | 189 | /* For the page tables on the leaves */ |
36b32a68 | 190 | return AMDGPU_VM_PTE_COUNT(adev); |
d38ceaf9 AD |
191 | } |
192 | ||
cb90b97b CK |
193 | /** |
194 | * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT | |
195 | * | |
196 | * @adev: amdgpu_device pointer | |
197 | * @level: VMPT level | |
198 | * | |
199 | * Returns: | |
200 | * The mask to extract the entry number of a PD/PT from an address. | |
201 | */ | |
202 | static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev, | |
203 | unsigned int level) | |
204 | { | |
205 | if (level <= adev->vm_manager.root_level) | |
206 | return 0xffffffff; | |
207 | else if (level != AMDGPU_VM_PTB) | |
208 | return 0x1ff; | |
209 | else | |
210 | return AMDGPU_VM_PTE_COUNT(adev) - 1; | |
211 | } | |
212 | ||
d38ceaf9 | 213 | /** |
72a7ec5c | 214 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
215 | * |
216 | * @adev: amdgpu_device pointer | |
7fc48e59 | 217 | * @level: VMPT level |
d38ceaf9 | 218 | * |
7fc48e59 AG |
219 | * Returns: |
220 | * The size of the BO for a page directory or page table in bytes. | |
d38ceaf9 | 221 | */ |
72a7ec5c | 222 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 223 | { |
72a7ec5c | 224 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
225 | } |
226 | ||
bcdc9fd6 CK |
227 | /** |
228 | * amdgpu_vm_bo_evicted - vm_bo is evicted | |
229 | * | |
230 | * @vm_bo: vm_bo which is evicted | |
231 | * | |
232 | * State for PDs/PTs and per VM BOs which are not at the location they should | |
233 | * be. | |
234 | */ | |
235 | static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) | |
236 | { | |
237 | struct amdgpu_vm *vm = vm_bo->vm; | |
238 | struct amdgpu_bo *bo = vm_bo->bo; | |
239 | ||
240 | vm_bo->moved = true; | |
241 | if (bo->tbo.type == ttm_bo_type_kernel) | |
242 | list_move(&vm_bo->vm_status, &vm->evicted); | |
243 | else | |
244 | list_move_tail(&vm_bo->vm_status, &vm->evicted); | |
245 | } | |
246 | ||
247 | /** | |
248 | * amdgpu_vm_bo_relocated - vm_bo is reloacted | |
249 | * | |
250 | * @vm_bo: vm_bo which is relocated | |
251 | * | |
252 | * State for PDs/PTs which needs to update their parent PD. | |
253 | */ | |
254 | static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) | |
255 | { | |
256 | list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); | |
257 | } | |
258 | ||
259 | /** | |
260 | * amdgpu_vm_bo_moved - vm_bo is moved | |
261 | * | |
262 | * @vm_bo: vm_bo which is moved | |
263 | * | |
264 | * State for per VM BOs which are moved, but that change is not yet reflected | |
265 | * in the page tables. | |
266 | */ | |
267 | static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) | |
268 | { | |
269 | list_move(&vm_bo->vm_status, &vm_bo->vm->moved); | |
270 | } | |
271 | ||
272 | /** | |
273 | * amdgpu_vm_bo_idle - vm_bo is idle | |
274 | * | |
275 | * @vm_bo: vm_bo which is now idle | |
276 | * | |
277 | * State for PDs/PTs and per VM BOs which have gone through the state machine | |
278 | * and are now idle. | |
279 | */ | |
280 | static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) | |
281 | { | |
282 | list_move(&vm_bo->vm_status, &vm_bo->vm->idle); | |
283 | vm_bo->moved = false; | |
284 | } | |
285 | ||
286 | /** | |
287 | * amdgpu_vm_bo_invalidated - vm_bo is invalidated | |
288 | * | |
289 | * @vm_bo: vm_bo which is now invalidated | |
290 | * | |
291 | * State for normal BOs which are invalidated and that change not yet reflected | |
292 | * in the PTs. | |
293 | */ | |
294 | static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) | |
295 | { | |
296 | spin_lock(&vm_bo->vm->invalidated_lock); | |
297 | list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated); | |
298 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
299 | } | |
300 | ||
301 | /** | |
302 | * amdgpu_vm_bo_done - vm_bo is done | |
303 | * | |
304 | * @vm_bo: vm_bo which is now done | |
305 | * | |
306 | * State for normal BOs which are invalidated and that change has been updated | |
307 | * in the PTs. | |
308 | */ | |
309 | static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) | |
310 | { | |
311 | spin_lock(&vm_bo->vm->invalidated_lock); | |
312 | list_del_init(&vm_bo->vm_status); | |
313 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
314 | } | |
315 | ||
c460f8a6 CK |
316 | /** |
317 | * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm | |
318 | * | |
319 | * @base: base structure for tracking BO usage in a VM | |
320 | * @vm: vm to which bo is to be added | |
321 | * @bo: amdgpu buffer object | |
322 | * | |
323 | * Initialize a bo_va_base structure and add it to the appropriate lists | |
324 | * | |
325 | */ | |
326 | static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, | |
327 | struct amdgpu_vm *vm, | |
328 | struct amdgpu_bo *bo) | |
329 | { | |
330 | base->vm = vm; | |
331 | base->bo = bo; | |
646b9025 | 332 | base->next = NULL; |
c460f8a6 CK |
333 | INIT_LIST_HEAD(&base->vm_status); |
334 | ||
335 | if (!bo) | |
336 | return; | |
646b9025 CK |
337 | base->next = bo->vm_bo; |
338 | bo->vm_bo = base; | |
c460f8a6 CK |
339 | |
340 | if (bo->tbo.resv != vm->root.base.bo->tbo.resv) | |
341 | return; | |
342 | ||
343 | vm->bulk_moveable = false; | |
344 | if (bo->tbo.type == ttm_bo_type_kernel) | |
bcdc9fd6 | 345 | amdgpu_vm_bo_relocated(base); |
c460f8a6 | 346 | else |
bcdc9fd6 | 347 | amdgpu_vm_bo_idle(base); |
c460f8a6 CK |
348 | |
349 | if (bo->preferred_domains & | |
350 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)) | |
351 | return; | |
352 | ||
353 | /* | |
354 | * we checked all the prerequisites, but it looks like this per vm bo | |
355 | * is currently evicted. add the bo to the evicted list to make sure it | |
356 | * is validated on next vm use to avoid fault. | |
357 | * */ | |
bcdc9fd6 | 358 | amdgpu_vm_bo_evicted(base); |
c460f8a6 CK |
359 | } |
360 | ||
ba79fde4 CK |
361 | /** |
362 | * amdgpu_vm_pt_parent - get the parent page directory | |
363 | * | |
364 | * @pt: child page table | |
365 | * | |
366 | * Helper to get the parent entry for the child page table. NULL if we are at | |
367 | * the root page directory. | |
368 | */ | |
369 | static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt) | |
370 | { | |
371 | struct amdgpu_bo *parent = pt->base.bo->parent; | |
372 | ||
373 | if (!parent) | |
374 | return NULL; | |
375 | ||
646b9025 | 376 | return container_of(parent->vm_bo, struct amdgpu_vm_pt, base); |
ba79fde4 CK |
377 | } |
378 | ||
73633e32 CK |
379 | /** |
380 | * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt | |
381 | */ | |
382 | struct amdgpu_vm_pt_cursor { | |
383 | uint64_t pfn; | |
384 | struct amdgpu_vm_pt *parent; | |
385 | struct amdgpu_vm_pt *entry; | |
386 | unsigned level; | |
387 | }; | |
388 | ||
389 | /** | |
390 | * amdgpu_vm_pt_start - start PD/PT walk | |
391 | * | |
392 | * @adev: amdgpu_device pointer | |
393 | * @vm: amdgpu_vm structure | |
394 | * @start: start address of the walk | |
395 | * @cursor: state to initialize | |
396 | * | |
397 | * Initialize a amdgpu_vm_pt_cursor to start a walk. | |
398 | */ | |
399 | static void amdgpu_vm_pt_start(struct amdgpu_device *adev, | |
400 | struct amdgpu_vm *vm, uint64_t start, | |
401 | struct amdgpu_vm_pt_cursor *cursor) | |
402 | { | |
403 | cursor->pfn = start; | |
404 | cursor->parent = NULL; | |
405 | cursor->entry = &vm->root; | |
406 | cursor->level = adev->vm_manager.root_level; | |
407 | } | |
408 | ||
409 | /** | |
410 | * amdgpu_vm_pt_descendant - go to child node | |
411 | * | |
412 | * @adev: amdgpu_device pointer | |
413 | * @cursor: current state | |
414 | * | |
415 | * Walk to the child node of the current node. | |
416 | * Returns: | |
417 | * True if the walk was possible, false otherwise. | |
418 | */ | |
419 | static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev, | |
420 | struct amdgpu_vm_pt_cursor *cursor) | |
421 | { | |
cb90b97b | 422 | unsigned mask, shift, idx; |
73633e32 CK |
423 | |
424 | if (!cursor->entry->entries) | |
425 | return false; | |
426 | ||
427 | BUG_ON(!cursor->entry->base.bo); | |
cb90b97b | 428 | mask = amdgpu_vm_entries_mask(adev, cursor->level); |
73633e32 CK |
429 | shift = amdgpu_vm_level_shift(adev, cursor->level); |
430 | ||
431 | ++cursor->level; | |
cb90b97b | 432 | idx = (cursor->pfn >> shift) & mask; |
73633e32 CK |
433 | cursor->parent = cursor->entry; |
434 | cursor->entry = &cursor->entry->entries[idx]; | |
435 | return true; | |
436 | } | |
437 | ||
438 | /** | |
439 | * amdgpu_vm_pt_sibling - go to sibling node | |
440 | * | |
441 | * @adev: amdgpu_device pointer | |
442 | * @cursor: current state | |
443 | * | |
444 | * Walk to the sibling node of the current node. | |
445 | * Returns: | |
446 | * True if the walk was possible, false otherwise. | |
447 | */ | |
448 | static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev, | |
449 | struct amdgpu_vm_pt_cursor *cursor) | |
450 | { | |
451 | unsigned shift, num_entries; | |
452 | ||
453 | /* Root doesn't have a sibling */ | |
454 | if (!cursor->parent) | |
455 | return false; | |
456 | ||
457 | /* Go to our parents and see if we got a sibling */ | |
458 | shift = amdgpu_vm_level_shift(adev, cursor->level - 1); | |
459 | num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1); | |
460 | ||
461 | if (cursor->entry == &cursor->parent->entries[num_entries - 1]) | |
462 | return false; | |
463 | ||
464 | cursor->pfn += 1ULL << shift; | |
465 | cursor->pfn &= ~((1ULL << shift) - 1); | |
466 | ++cursor->entry; | |
467 | return true; | |
468 | } | |
469 | ||
470 | /** | |
471 | * amdgpu_vm_pt_ancestor - go to parent node | |
472 | * | |
473 | * @cursor: current state | |
474 | * | |
475 | * Walk to the parent node of the current node. | |
476 | * Returns: | |
477 | * True if the walk was possible, false otherwise. | |
478 | */ | |
479 | static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor) | |
480 | { | |
481 | if (!cursor->parent) | |
482 | return false; | |
483 | ||
484 | --cursor->level; | |
485 | cursor->entry = cursor->parent; | |
486 | cursor->parent = amdgpu_vm_pt_parent(cursor->parent); | |
487 | return true; | |
488 | } | |
489 | ||
490 | /** | |
491 | * amdgpu_vm_pt_next - get next PD/PT in hieratchy | |
492 | * | |
493 | * @adev: amdgpu_device pointer | |
494 | * @cursor: current state | |
495 | * | |
496 | * Walk the PD/PT tree to the next node. | |
497 | */ | |
498 | static void amdgpu_vm_pt_next(struct amdgpu_device *adev, | |
499 | struct amdgpu_vm_pt_cursor *cursor) | |
500 | { | |
501 | /* First try a newborn child */ | |
502 | if (amdgpu_vm_pt_descendant(adev, cursor)) | |
503 | return; | |
504 | ||
505 | /* If that didn't worked try to find a sibling */ | |
506 | while (!amdgpu_vm_pt_sibling(adev, cursor)) { | |
507 | /* No sibling, go to our parents and grandparents */ | |
508 | if (!amdgpu_vm_pt_ancestor(cursor)) { | |
509 | cursor->pfn = ~0ll; | |
510 | return; | |
511 | } | |
512 | } | |
513 | } | |
514 | ||
515 | /** | |
516 | * amdgpu_vm_pt_first_leaf - get first leaf PD/PT | |
517 | * | |
518 | * @adev: amdgpu_device pointer | |
519 | * @vm: amdgpu_vm structure | |
520 | * @start: start addr of the walk | |
521 | * @cursor: state to initialize | |
522 | * | |
523 | * Start a walk and go directly to the leaf node. | |
524 | */ | |
525 | static void amdgpu_vm_pt_first_leaf(struct amdgpu_device *adev, | |
526 | struct amdgpu_vm *vm, uint64_t start, | |
527 | struct amdgpu_vm_pt_cursor *cursor) | |
528 | { | |
529 | amdgpu_vm_pt_start(adev, vm, start, cursor); | |
530 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
531 | } | |
532 | ||
533 | /** | |
534 | * amdgpu_vm_pt_next_leaf - get next leaf PD/PT | |
535 | * | |
536 | * @adev: amdgpu_device pointer | |
537 | * @cursor: current state | |
538 | * | |
539 | * Walk the PD/PT tree to the next leaf node. | |
540 | */ | |
541 | static void amdgpu_vm_pt_next_leaf(struct amdgpu_device *adev, | |
542 | struct amdgpu_vm_pt_cursor *cursor) | |
543 | { | |
544 | amdgpu_vm_pt_next(adev, cursor); | |
545 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
546 | } | |
547 | ||
548 | /** | |
549 | * for_each_amdgpu_vm_pt_leaf - walk over all leaf PDs/PTs in the hierarchy | |
550 | */ | |
551 | #define for_each_amdgpu_vm_pt_leaf(adev, vm, start, end, cursor) \ | |
552 | for (amdgpu_vm_pt_first_leaf((adev), (vm), (start), &(cursor)); \ | |
553 | (cursor).pfn <= end; amdgpu_vm_pt_next_leaf((adev), &(cursor))) | |
554 | ||
555 | /** | |
556 | * amdgpu_vm_pt_first_dfs - start a deep first search | |
557 | * | |
558 | * @adev: amdgpu_device structure | |
559 | * @vm: amdgpu_vm structure | |
560 | * @cursor: state to initialize | |
561 | * | |
562 | * Starts a deep first traversal of the PD/PT tree. | |
563 | */ | |
564 | static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev, | |
565 | struct amdgpu_vm *vm, | |
566 | struct amdgpu_vm_pt_cursor *cursor) | |
567 | { | |
568 | amdgpu_vm_pt_start(adev, vm, 0, cursor); | |
569 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
570 | } | |
571 | ||
572 | /** | |
573 | * amdgpu_vm_pt_next_dfs - get the next node for a deep first search | |
574 | * | |
575 | * @adev: amdgpu_device structure | |
576 | * @cursor: current state | |
577 | * | |
578 | * Move the cursor to the next node in a deep first search. | |
579 | */ | |
580 | static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev, | |
581 | struct amdgpu_vm_pt_cursor *cursor) | |
582 | { | |
583 | if (!cursor->entry) | |
584 | return; | |
585 | ||
586 | if (!cursor->parent) | |
587 | cursor->entry = NULL; | |
588 | else if (amdgpu_vm_pt_sibling(adev, cursor)) | |
589 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
590 | else | |
591 | amdgpu_vm_pt_ancestor(cursor); | |
592 | } | |
593 | ||
594 | /** | |
595 | * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs | |
596 | */ | |
597 | #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) \ | |
598 | for (amdgpu_vm_pt_first_dfs((adev), (vm), &(cursor)), \ | |
599 | (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\ | |
600 | (entry); (entry) = (cursor).entry, \ | |
601 | amdgpu_vm_pt_next_dfs((adev), &(cursor))) | |
602 | ||
d38ceaf9 | 603 | /** |
56467ebf | 604 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
605 | * |
606 | * @vm: vm providing the BOs | |
3c0eea6c | 607 | * @validated: head of validation list |
56467ebf | 608 | * @entry: entry to add |
d38ceaf9 AD |
609 | * |
610 | * Add the page directory to the list of BOs to | |
56467ebf | 611 | * validate for command submission. |
d38ceaf9 | 612 | */ |
56467ebf CK |
613 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
614 | struct list_head *validated, | |
615 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 616 | { |
56467ebf | 617 | entry->priority = 0; |
e83dfe4d | 618 | entry->tv.bo = &vm->root.base.bo->tbo; |
56467ebf | 619 | entry->tv.shared = true; |
2f568dbd | 620 | entry->user_pages = NULL; |
56467ebf CK |
621 | list_add(&entry->tv.head, validated); |
622 | } | |
d38ceaf9 | 623 | |
f921661b HR |
624 | /** |
625 | * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU | |
626 | * | |
627 | * @adev: amdgpu device pointer | |
628 | * @vm: vm providing the BOs | |
629 | * | |
630 | * Move all BOs to the end of LRU and remember their positions to put them | |
631 | * together. | |
632 | */ | |
633 | void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, | |
634 | struct amdgpu_vm *vm) | |
635 | { | |
636 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
637 | struct amdgpu_vm_bo_base *bo_base; | |
638 | ||
639 | if (vm->bulk_moveable) { | |
640 | spin_lock(&glob->lru_lock); | |
641 | ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move); | |
642 | spin_unlock(&glob->lru_lock); | |
643 | return; | |
644 | } | |
645 | ||
646 | memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move)); | |
647 | ||
648 | spin_lock(&glob->lru_lock); | |
649 | list_for_each_entry(bo_base, &vm->idle, vm_status) { | |
650 | struct amdgpu_bo *bo = bo_base->bo; | |
651 | ||
652 | if (!bo->parent) | |
653 | continue; | |
654 | ||
655 | ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move); | |
656 | if (bo->shadow) | |
657 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo, | |
658 | &vm->lru_bulk_move); | |
659 | } | |
660 | spin_unlock(&glob->lru_lock); | |
661 | ||
662 | vm->bulk_moveable = true; | |
663 | } | |
664 | ||
670fecc8 | 665 | /** |
f7da30d9 | 666 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
670fecc8 | 667 | * |
5a712a87 | 668 | * @adev: amdgpu device pointer |
56467ebf | 669 | * @vm: vm providing the BOs |
670fecc8 CK |
670 | * @validate: callback to do the validation |
671 | * @param: parameter for the validation callback | |
672 | * | |
673 | * Validate the page table BOs on command submission if neccessary. | |
7fc48e59 AG |
674 | * |
675 | * Returns: | |
676 | * Validation result. | |
670fecc8 | 677 | */ |
f7da30d9 CK |
678 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
679 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
680 | void *param) | |
670fecc8 | 681 | { |
91ccdd24 CK |
682 | struct amdgpu_vm_bo_base *bo_base, *tmp; |
683 | int r = 0; | |
670fecc8 | 684 | |
f921661b HR |
685 | vm->bulk_moveable &= list_empty(&vm->evicted); |
686 | ||
91ccdd24 CK |
687 | list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { |
688 | struct amdgpu_bo *bo = bo_base->bo; | |
670fecc8 | 689 | |
262b9c39 CK |
690 | r = validate(param, bo); |
691 | if (r) | |
692 | break; | |
670fecc8 | 693 | |
af4c0f65 | 694 | if (bo->tbo.type != ttm_bo_type_kernel) { |
bcdc9fd6 | 695 | amdgpu_vm_bo_moved(bo_base); |
af4c0f65 | 696 | } else { |
17cc5252 CK |
697 | if (vm->use_cpu_for_update) |
698 | r = amdgpu_bo_kmap(bo, NULL); | |
699 | else | |
700 | r = amdgpu_ttm_alloc_gart(&bo->tbo); | |
284dec43 CK |
701 | if (r) |
702 | break; | |
3d5fe658 CK |
703 | if (bo->shadow) { |
704 | r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo); | |
705 | if (r) | |
706 | break; | |
707 | } | |
bcdc9fd6 | 708 | amdgpu_vm_bo_relocated(bo_base); |
af4c0f65 | 709 | } |
670fecc8 CK |
710 | } |
711 | ||
91ccdd24 | 712 | return r; |
670fecc8 CK |
713 | } |
714 | ||
56467ebf | 715 | /** |
34d7be5d | 716 | * amdgpu_vm_ready - check VM is ready for updates |
56467ebf | 717 | * |
34d7be5d | 718 | * @vm: VM to check |
d38ceaf9 | 719 | * |
34d7be5d | 720 | * Check if all VM PDs/PTs are ready for updates |
7fc48e59 AG |
721 | * |
722 | * Returns: | |
723 | * True if eviction list is empty. | |
d38ceaf9 | 724 | */ |
3f3333f8 | 725 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
d38ceaf9 | 726 | { |
af4c0f65 | 727 | return list_empty(&vm->evicted); |
d711e139 CK |
728 | } |
729 | ||
13307f7e CK |
730 | /** |
731 | * amdgpu_vm_clear_bo - initially clear the PDs/PTs | |
732 | * | |
733 | * @adev: amdgpu_device pointer | |
7fc48e59 | 734 | * @vm: VM to clear BO from |
13307f7e CK |
735 | * @bo: BO to clear |
736 | * @level: level this BO is at | |
00553cf8 | 737 | * @pte_support_ats: indicate ATS support from PTE |
13307f7e CK |
738 | * |
739 | * Root PD needs to be reserved when calling this. | |
7fc48e59 AG |
740 | * |
741 | * Returns: | |
742 | * 0 on success, errno otherwise. | |
13307f7e CK |
743 | */ |
744 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
4584312d CK |
745 | struct amdgpu_vm *vm, struct amdgpu_bo *bo, |
746 | unsigned level, bool pte_support_ats) | |
13307f7e CK |
747 | { |
748 | struct ttm_operation_ctx ctx = { true, false }; | |
749 | struct dma_fence *fence = NULL; | |
4584312d | 750 | unsigned entries, ats_entries; |
13307f7e CK |
751 | struct amdgpu_ring *ring; |
752 | struct amdgpu_job *job; | |
4584312d | 753 | uint64_t addr; |
13307f7e CK |
754 | int r; |
755 | ||
4584312d CK |
756 | entries = amdgpu_bo_size(bo) / 8; |
757 | ||
758 | if (pte_support_ats) { | |
759 | if (level == adev->vm_manager.root_level) { | |
760 | ats_entries = amdgpu_vm_level_shift(adev, level); | |
761 | ats_entries += AMDGPU_GPU_PAGE_SHIFT; | |
ad9a5b78 | 762 | ats_entries = AMDGPU_GMC_HOLE_START >> ats_entries; |
4584312d CK |
763 | ats_entries = min(ats_entries, entries); |
764 | entries -= ats_entries; | |
765 | } else { | |
766 | ats_entries = entries; | |
767 | entries = 0; | |
768 | } | |
13307f7e | 769 | } else { |
4584312d | 770 | ats_entries = 0; |
13307f7e CK |
771 | } |
772 | ||
068c3304 | 773 | ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched); |
13307f7e CK |
774 | |
775 | r = reservation_object_reserve_shared(bo->tbo.resv); | |
776 | if (r) | |
777 | return r; | |
778 | ||
779 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); | |
780 | if (r) | |
781 | goto error; | |
782 | ||
284dec43 CK |
783 | r = amdgpu_ttm_alloc_gart(&bo->tbo); |
784 | if (r) | |
785 | return r; | |
786 | ||
13307f7e CK |
787 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
788 | if (r) | |
789 | goto error; | |
790 | ||
1cadf2b3 | 791 | addr = amdgpu_bo_gpu_offset(bo); |
4584312d CK |
792 | if (ats_entries) { |
793 | uint64_t ats_value; | |
794 | ||
795 | ats_value = AMDGPU_PTE_DEFAULT_ATC; | |
796 | if (level != AMDGPU_VM_PTB) | |
797 | ats_value |= AMDGPU_PDE_PTE; | |
798 | ||
799 | amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, | |
800 | ats_entries, 0, ats_value); | |
801 | addr += ats_entries * 8; | |
802 | } | |
803 | ||
804 | if (entries) | |
805 | amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, | |
806 | entries, 0, 0); | |
807 | ||
13307f7e CK |
808 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); |
809 | ||
810 | WARN_ON(job->ibs[0].length_dw > 64); | |
29e8357b CK |
811 | r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv, |
812 | AMDGPU_FENCE_OWNER_UNDEFINED, false); | |
813 | if (r) | |
814 | goto error_free; | |
815 | ||
0e28b10f CK |
816 | r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_UNDEFINED, |
817 | &fence); | |
13307f7e CK |
818 | if (r) |
819 | goto error_free; | |
820 | ||
821 | amdgpu_bo_fence(bo, fence, true); | |
822 | dma_fence_put(fence); | |
e61736da CK |
823 | |
824 | if (bo->shadow) | |
825 | return amdgpu_vm_clear_bo(adev, vm, bo->shadow, | |
826 | level, pte_support_ats); | |
827 | ||
13307f7e CK |
828 | return 0; |
829 | ||
830 | error_free: | |
831 | amdgpu_job_free(job); | |
832 | ||
833 | error: | |
834 | return r; | |
835 | } | |
836 | ||
e21eb261 CK |
837 | /** |
838 | * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation | |
839 | * | |
840 | * @adev: amdgpu_device pointer | |
841 | * @vm: requesting vm | |
842 | * @bp: resulting BO allocation parameters | |
843 | */ | |
844 | static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
845 | int level, struct amdgpu_bo_param *bp) | |
846 | { | |
847 | memset(bp, 0, sizeof(*bp)); | |
848 | ||
849 | bp->size = amdgpu_vm_bo_size(adev, level); | |
850 | bp->byte_align = AMDGPU_GPU_PAGE_SIZE; | |
851 | bp->domain = AMDGPU_GEM_DOMAIN_VRAM; | |
284dec43 CK |
852 | if (bp->size <= PAGE_SIZE && adev->asic_type >= CHIP_VEGA10 && |
853 | adev->flags & AMD_IS_APU) | |
854 | bp->domain |= AMDGPU_GEM_DOMAIN_GTT; | |
855 | bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain); | |
856 | bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
857 | AMDGPU_GEM_CREATE_CPU_GTT_USWC; | |
e21eb261 CK |
858 | if (vm->use_cpu_for_update) |
859 | bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
03e9dee1 FK |
860 | else if (!vm->root.base.bo || vm->root.base.bo->shadow) |
861 | bp->flags |= AMDGPU_GEM_CREATE_SHADOW; | |
e21eb261 CK |
862 | bp->type = ttm_bo_type_kernel; |
863 | if (vm->root.base.bo) | |
864 | bp->resv = vm->root.base.bo->tbo.resv; | |
865 | } | |
866 | ||
663e4577 CK |
867 | /** |
868 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
869 | * | |
870 | * @adev: amdgpu_device pointer | |
871 | * @vm: VM to allocate page tables for | |
872 | * @saddr: Start address which needs to be allocated | |
873 | * @size: Size from start address we need. | |
874 | * | |
d72a6887 | 875 | * Make sure the page directories and page tables are allocated |
7fc48e59 AG |
876 | * |
877 | * Returns: | |
878 | * 0 on success, errno otherwise. | |
663e4577 CK |
879 | */ |
880 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
881 | struct amdgpu_vm *vm, | |
882 | uint64_t saddr, uint64_t size) | |
883 | { | |
d72a6887 CK |
884 | struct amdgpu_vm_pt_cursor cursor; |
885 | struct amdgpu_bo *pt; | |
4584312d | 886 | bool ats = false; |
d72a6887 CK |
887 | uint64_t eaddr; |
888 | int r; | |
663e4577 CK |
889 | |
890 | /* validate the parameters */ | |
891 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
892 | return -EINVAL; | |
893 | ||
894 | eaddr = saddr + size - 1; | |
4584312d CK |
895 | |
896 | if (vm->pte_support_ats) | |
ad9a5b78 | 897 | ats = saddr < AMDGPU_GMC_HOLE_START; |
663e4577 CK |
898 | |
899 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
900 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
901 | ||
4584312d CK |
902 | if (eaddr >= adev->vm_manager.max_pfn) { |
903 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", | |
904 | eaddr, adev->vm_manager.max_pfn); | |
905 | return -EINVAL; | |
906 | } | |
907 | ||
d72a6887 CK |
908 | for_each_amdgpu_vm_pt_leaf(adev, vm, saddr, eaddr, cursor) { |
909 | struct amdgpu_vm_pt *entry = cursor.entry; | |
910 | struct amdgpu_bo_param bp; | |
911 | ||
912 | if (cursor.level < AMDGPU_VM_PTB) { | |
913 | unsigned num_entries; | |
914 | ||
915 | num_entries = amdgpu_vm_num_entries(adev, cursor.level); | |
916 | entry->entries = kvmalloc_array(num_entries, | |
917 | sizeof(*entry->entries), | |
918 | GFP_KERNEL | | |
919 | __GFP_ZERO); | |
920 | if (!entry->entries) | |
921 | return -ENOMEM; | |
922 | } | |
923 | ||
924 | ||
925 | if (entry->base.bo) | |
926 | continue; | |
927 | ||
928 | amdgpu_vm_bo_param(adev, vm, cursor.level, &bp); | |
929 | ||
930 | r = amdgpu_bo_create(adev, &bp, &pt); | |
931 | if (r) | |
932 | return r; | |
933 | ||
934 | r = amdgpu_vm_clear_bo(adev, vm, pt, cursor.level, ats); | |
935 | if (r) | |
936 | goto error_free_pt; | |
937 | ||
938 | if (vm->use_cpu_for_update) { | |
939 | r = amdgpu_bo_kmap(pt, NULL); | |
940 | if (r) | |
941 | goto error_free_pt; | |
942 | } | |
943 | ||
944 | /* Keep a reference to the root directory to avoid | |
945 | * freeing them up in the wrong order. | |
946 | */ | |
947 | pt->parent = amdgpu_bo_ref(cursor.parent->base.bo); | |
948 | ||
949 | amdgpu_vm_bo_base_init(&entry->base, vm, pt); | |
950 | } | |
951 | ||
952 | return 0; | |
953 | ||
954 | error_free_pt: | |
955 | amdgpu_bo_unref(&pt->shadow); | |
956 | amdgpu_bo_unref(&pt); | |
957 | return r; | |
663e4577 CK |
958 | } |
959 | ||
229a37f8 CK |
960 | /** |
961 | * amdgpu_vm_free_pts - free PD/PT levels | |
962 | * | |
963 | * @adev: amdgpu device structure | |
964 | * @parent: PD/PT starting level to free | |
965 | * @level: level of parent structure | |
966 | * | |
967 | * Free the page directory or page table level and all sub levels. | |
968 | */ | |
969 | static void amdgpu_vm_free_pts(struct amdgpu_device *adev, | |
970 | struct amdgpu_vm *vm) | |
971 | { | |
972 | struct amdgpu_vm_pt_cursor cursor; | |
973 | struct amdgpu_vm_pt *entry; | |
974 | ||
975 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) { | |
976 | ||
977 | if (entry->base.bo) { | |
646b9025 | 978 | entry->base.bo->vm_bo = NULL; |
229a37f8 CK |
979 | list_del(&entry->base.vm_status); |
980 | amdgpu_bo_unref(&entry->base.bo->shadow); | |
981 | amdgpu_bo_unref(&entry->base.bo); | |
982 | } | |
983 | kvfree(entry->entries); | |
984 | } | |
985 | ||
986 | BUG_ON(vm->root.base.bo); | |
987 | } | |
988 | ||
e59c0205 AX |
989 | /** |
990 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
991 | * | |
992 | * @adev: amdgpu_device pointer | |
993 | */ | |
994 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 995 | { |
a1255107 | 996 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
997 | bool has_compute_vm_bug; |
998 | struct amdgpu_ring *ring; | |
999 | int i; | |
93dcc37d | 1000 | |
e59c0205 | 1001 | has_compute_vm_bug = false; |
93dcc37d | 1002 | |
2990a1fc | 1003 | ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); |
e59c0205 AX |
1004 | if (ip_block) { |
1005 | /* Compute has a VM bug for GFX version < 7. | |
1006 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
1007 | if (ip_block->version->major <= 7) | |
1008 | has_compute_vm_bug = true; | |
1009 | else if (ip_block->version->major == 8) | |
1010 | if (adev->gfx.mec_fw_version < 673) | |
1011 | has_compute_vm_bug = true; | |
1012 | } | |
93dcc37d | 1013 | |
e59c0205 AX |
1014 | for (i = 0; i < adev->num_rings; i++) { |
1015 | ring = adev->rings[i]; | |
1016 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
1017 | /* only compute rings */ | |
1018 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 1019 | else |
e59c0205 | 1020 | ring->has_compute_vm_bug = false; |
93dcc37d | 1021 | } |
93dcc37d AD |
1022 | } |
1023 | ||
7fc48e59 AG |
1024 | /** |
1025 | * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job. | |
1026 | * | |
1027 | * @ring: ring on which the job will be submitted | |
1028 | * @job: job to submit | |
1029 | * | |
1030 | * Returns: | |
1031 | * True if sync is needed. | |
1032 | */ | |
b9bf33d5 CZ |
1033 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
1034 | struct amdgpu_job *job) | |
e60f8db5 | 1035 | { |
b9bf33d5 CZ |
1036 | struct amdgpu_device *adev = ring->adev; |
1037 | unsigned vmhub = ring->funcs->vmhub; | |
620f774f CK |
1038 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
1039 | struct amdgpu_vmid *id; | |
b9bf33d5 | 1040 | bool gds_switch_needed; |
e59c0205 | 1041 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 | 1042 | |
c4f46f22 | 1043 | if (job->vmid == 0) |
b9bf33d5 | 1044 | return false; |
c4f46f22 | 1045 | id = &id_mgr->ids[job->vmid]; |
b9bf33d5 CZ |
1046 | gds_switch_needed = ring->funcs->emit_gds_switch && ( |
1047 | id->gds_base != job->gds_base || | |
1048 | id->gds_size != job->gds_size || | |
1049 | id->gws_base != job->gws_base || | |
1050 | id->gws_size != job->gws_size || | |
1051 | id->oa_base != job->oa_base || | |
1052 | id->oa_size != job->oa_size); | |
e60f8db5 | 1053 | |
620f774f | 1054 | if (amdgpu_vmid_had_gpu_reset(adev, id)) |
b9bf33d5 | 1055 | return true; |
e60f8db5 | 1056 | |
bb37b67d | 1057 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
1058 | } |
1059 | ||
d38ceaf9 AD |
1060 | /** |
1061 | * amdgpu_vm_flush - hardware flush the vm | |
1062 | * | |
1063 | * @ring: ring to use for flush | |
00553cf8 | 1064 | * @job: related job |
7fc48e59 | 1065 | * @need_pipe_sync: is pipe sync needed |
d38ceaf9 | 1066 | * |
4ff37a83 | 1067 | * Emit a VM flush when it is necessary. |
7fc48e59 AG |
1068 | * |
1069 | * Returns: | |
1070 | * 0 on success, errno otherwise. | |
d38ceaf9 | 1071 | */ |
8fdf074f | 1072 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 1073 | { |
971fe9a9 | 1074 | struct amdgpu_device *adev = ring->adev; |
7645670d | 1075 | unsigned vmhub = ring->funcs->vmhub; |
620f774f | 1076 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
c4f46f22 | 1077 | struct amdgpu_vmid *id = &id_mgr->ids[job->vmid]; |
d564a06e | 1078 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
1079 | id->gds_base != job->gds_base || |
1080 | id->gds_size != job->gds_size || | |
1081 | id->gws_base != job->gws_base || | |
1082 | id->gws_size != job->gws_size || | |
1083 | id->oa_base != job->oa_base || | |
1084 | id->oa_size != job->oa_size); | |
de37e68a | 1085 | bool vm_flush_needed = job->vm_needs_flush; |
b3cd285f CK |
1086 | bool pasid_mapping_needed = id->pasid != job->pasid || |
1087 | !id->pasid_mapping || | |
1088 | !dma_fence_is_signaled(id->pasid_mapping); | |
1089 | struct dma_fence *fence = NULL; | |
c0e51931 | 1090 | unsigned patch_offset = 0; |
41d9eb2c | 1091 | int r; |
d564a06e | 1092 | |
620f774f | 1093 | if (amdgpu_vmid_had_gpu_reset(adev, id)) { |
f7d015b9 CK |
1094 | gds_switch_needed = true; |
1095 | vm_flush_needed = true; | |
b3cd285f | 1096 | pasid_mapping_needed = true; |
f7d015b9 | 1097 | } |
971fe9a9 | 1098 | |
b3cd285f | 1099 | gds_switch_needed &= !!ring->funcs->emit_gds_switch; |
d8de8260 AG |
1100 | vm_flush_needed &= !!ring->funcs->emit_vm_flush && |
1101 | job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET; | |
b3cd285f CK |
1102 | pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping && |
1103 | ring->funcs->emit_wreg; | |
1104 | ||
8fdf074f | 1105 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 1106 | return 0; |
41d9eb2c | 1107 | |
c0e51931 CK |
1108 | if (ring->funcs->init_cond_exec) |
1109 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 1110 | |
8fdf074f ML |
1111 | if (need_pipe_sync) |
1112 | amdgpu_ring_emit_pipeline_sync(ring); | |
1113 | ||
b3cd285f | 1114 | if (vm_flush_needed) { |
c4f46f22 | 1115 | trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr); |
c633c00b | 1116 | amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr); |
b3cd285f CK |
1117 | } |
1118 | ||
1119 | if (pasid_mapping_needed) | |
1120 | amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); | |
e9d672b2 | 1121 | |
b3cd285f | 1122 | if (vm_flush_needed || pasid_mapping_needed) { |
d240cd9e | 1123 | r = amdgpu_fence_emit(ring, &fence, 0); |
c0e51931 CK |
1124 | if (r) |
1125 | return r; | |
b3cd285f | 1126 | } |
e9d672b2 | 1127 | |
b3cd285f | 1128 | if (vm_flush_needed) { |
7645670d | 1129 | mutex_lock(&id_mgr->lock); |
c0e51931 | 1130 | dma_fence_put(id->last_flush); |
b3cd285f CK |
1131 | id->last_flush = dma_fence_get(fence); |
1132 | id->current_gpu_reset_count = | |
1133 | atomic_read(&adev->gpu_reset_counter); | |
7645670d | 1134 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 1135 | } |
e9d672b2 | 1136 | |
b3cd285f CK |
1137 | if (pasid_mapping_needed) { |
1138 | id->pasid = job->pasid; | |
1139 | dma_fence_put(id->pasid_mapping); | |
1140 | id->pasid_mapping = dma_fence_get(fence); | |
1141 | } | |
1142 | dma_fence_put(fence); | |
1143 | ||
7c4378f4 | 1144 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
1145 | id->gds_base = job->gds_base; |
1146 | id->gds_size = job->gds_size; | |
1147 | id->gws_base = job->gws_base; | |
1148 | id->gws_size = job->gws_size; | |
1149 | id->oa_base = job->oa_base; | |
1150 | id->oa_size = job->oa_size; | |
c4f46f22 | 1151 | amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base, |
c0e51931 CK |
1152 | job->gds_size, job->gws_base, |
1153 | job->gws_size, job->oa_base, | |
1154 | job->oa_size); | |
1155 | } | |
1156 | ||
1157 | if (ring->funcs->patch_cond_exec) | |
1158 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
1159 | ||
1160 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
1161 | if (ring->funcs->emit_switch_buffer) { | |
1162 | amdgpu_ring_emit_switch_buffer(ring); | |
1163 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 1164 | } |
41d9eb2c | 1165 | return 0; |
971fe9a9 CK |
1166 | } |
1167 | ||
d38ceaf9 AD |
1168 | /** |
1169 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
1170 | * | |
1171 | * @vm: requested vm | |
1172 | * @bo: requested buffer object | |
1173 | * | |
8843dbbb | 1174 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
1175 | * Search inside the @bos vm list for the requested vm |
1176 | * Returns the found bo_va or NULL if none is found | |
1177 | * | |
1178 | * Object has to be reserved! | |
7fc48e59 AG |
1179 | * |
1180 | * Returns: | |
1181 | * Found bo_va or NULL. | |
d38ceaf9 AD |
1182 | */ |
1183 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
1184 | struct amdgpu_bo *bo) | |
1185 | { | |
646b9025 | 1186 | struct amdgpu_vm_bo_base *base; |
d38ceaf9 | 1187 | |
646b9025 CK |
1188 | for (base = bo->vm_bo; base; base = base->next) { |
1189 | if (base->vm != vm) | |
1190 | continue; | |
1191 | ||
1192 | return container_of(base, struct amdgpu_bo_va, base); | |
d38ceaf9 AD |
1193 | } |
1194 | return NULL; | |
1195 | } | |
1196 | ||
1197 | /** | |
afef8b8f | 1198 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 1199 | * |
29efc4f5 | 1200 | * @params: see amdgpu_pte_update_params definition |
373ac645 | 1201 | * @bo: PD/PT to update |
d38ceaf9 AD |
1202 | * @pe: addr of the page entry |
1203 | * @addr: dst addr to write into pe | |
1204 | * @count: number of page entries to update | |
1205 | * @incr: increase next addr by incr bytes | |
1206 | * @flags: hw access flags | |
d38ceaf9 AD |
1207 | * |
1208 | * Traces the parameters and calls the right asic functions | |
1209 | * to setup the page table using the DMA. | |
1210 | */ | |
afef8b8f | 1211 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
373ac645 | 1212 | struct amdgpu_bo *bo, |
afef8b8f CK |
1213 | uint64_t pe, uint64_t addr, |
1214 | unsigned count, uint32_t incr, | |
6b777607 | 1215 | uint64_t flags) |
d38ceaf9 | 1216 | { |
373ac645 | 1217 | pe += amdgpu_bo_gpu_offset(bo); |
ec2f05f0 | 1218 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 1219 | |
afef8b8f | 1220 | if (count < 3) { |
de9ea7bd CK |
1221 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
1222 | addr | flags, count, incr); | |
d38ceaf9 AD |
1223 | |
1224 | } else { | |
27c5f36f | 1225 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
1226 | count, incr, flags); |
1227 | } | |
1228 | } | |
1229 | ||
afef8b8f CK |
1230 | /** |
1231 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
1232 | * | |
1233 | * @params: see amdgpu_pte_update_params definition | |
373ac645 | 1234 | * @bo: PD/PT to update |
afef8b8f CK |
1235 | * @pe: addr of the page entry |
1236 | * @addr: dst addr to write into pe | |
1237 | * @count: number of page entries to update | |
1238 | * @incr: increase next addr by incr bytes | |
1239 | * @flags: hw access flags | |
1240 | * | |
1241 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
1242 | */ | |
1243 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
373ac645 | 1244 | struct amdgpu_bo *bo, |
afef8b8f CK |
1245 | uint64_t pe, uint64_t addr, |
1246 | unsigned count, uint32_t incr, | |
6b777607 | 1247 | uint64_t flags) |
afef8b8f | 1248 | { |
ec2f05f0 | 1249 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 1250 | |
373ac645 | 1251 | pe += amdgpu_bo_gpu_offset(bo); |
ec2f05f0 CK |
1252 | trace_amdgpu_vm_copy_ptes(pe, src, count); |
1253 | ||
1254 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
1255 | } |
1256 | ||
d38ceaf9 | 1257 | /** |
b07c9d2a | 1258 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 1259 | * |
b07c9d2a | 1260 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
1261 | * @addr: the unmapped addr |
1262 | * | |
1263 | * Look up the physical address of the page that the pte resolves | |
7fc48e59 AG |
1264 | * to. |
1265 | * | |
1266 | * Returns: | |
1267 | * The pointer for the page table entry. | |
d38ceaf9 | 1268 | */ |
de9ea7bd | 1269 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
1270 | { |
1271 | uint64_t result; | |
1272 | ||
de9ea7bd CK |
1273 | /* page table offset */ |
1274 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 1275 | |
de9ea7bd CK |
1276 | /* in case cpu page size != gpu page size*/ |
1277 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 1278 | |
b07c9d2a | 1279 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
1280 | |
1281 | return result; | |
1282 | } | |
1283 | ||
3c824172 HK |
1284 | /** |
1285 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU | |
1286 | * | |
1287 | * @params: see amdgpu_pte_update_params definition | |
373ac645 | 1288 | * @bo: PD/PT to update |
3c824172 HK |
1289 | * @pe: kmap addr of the page entry |
1290 | * @addr: dst addr to write into pe | |
1291 | * @count: number of page entries to update | |
1292 | * @incr: increase next addr by incr bytes | |
1293 | * @flags: hw access flags | |
1294 | * | |
1295 | * Write count number of PT/PD entries directly. | |
1296 | */ | |
1297 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, | |
373ac645 | 1298 | struct amdgpu_bo *bo, |
3c824172 HK |
1299 | uint64_t pe, uint64_t addr, |
1300 | unsigned count, uint32_t incr, | |
1301 | uint64_t flags) | |
1302 | { | |
1303 | unsigned int i; | |
b4d42511 | 1304 | uint64_t value; |
3c824172 | 1305 | |
373ac645 CK |
1306 | pe += (unsigned long)amdgpu_bo_kptr(bo); |
1307 | ||
03918b36 CK |
1308 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
1309 | ||
3c824172 | 1310 | for (i = 0; i < count; i++) { |
b4d42511 HK |
1311 | value = params->pages_addr ? |
1312 | amdgpu_vm_map_gart(params->pages_addr, addr) : | |
1313 | addr; | |
132f34e4 CK |
1314 | amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe, |
1315 | i, value, flags); | |
3c824172 HK |
1316 | addr += incr; |
1317 | } | |
3c824172 HK |
1318 | } |
1319 | ||
7fc48e59 AG |
1320 | |
1321 | /** | |
1322 | * amdgpu_vm_wait_pd - Wait for PT BOs to be free. | |
1323 | * | |
1324 | * @adev: amdgpu_device pointer | |
1325 | * @vm: related vm | |
1326 | * @owner: fence owner | |
1327 | * | |
1328 | * Returns: | |
1329 | * 0 on success, errno otherwise. | |
1330 | */ | |
a33cab7a CK |
1331 | static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
1332 | void *owner) | |
3c824172 HK |
1333 | { |
1334 | struct amdgpu_sync sync; | |
1335 | int r; | |
1336 | ||
1337 | amdgpu_sync_create(&sync); | |
177ae09b | 1338 | amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false); |
3c824172 HK |
1339 | r = amdgpu_sync_wait(&sync, true); |
1340 | amdgpu_sync_free(&sync); | |
1341 | ||
1342 | return r; | |
1343 | } | |
1344 | ||
1c860a02 CK |
1345 | /** |
1346 | * amdgpu_vm_update_func - helper to call update function | |
1347 | * | |
1348 | * Calls the update function for both the given BO as well as its shadow. | |
1349 | */ | |
1350 | static void amdgpu_vm_update_func(struct amdgpu_pte_update_params *params, | |
1351 | struct amdgpu_bo *bo, | |
1352 | uint64_t pe, uint64_t addr, | |
1353 | unsigned count, uint32_t incr, | |
1354 | uint64_t flags) | |
1355 | { | |
1356 | if (bo->shadow) | |
1357 | params->func(params, bo->shadow, pe, addr, count, incr, flags); | |
1358 | params->func(params, bo, pe, addr, count, incr, flags); | |
1359 | } | |
1360 | ||
f8991bab | 1361 | /* |
6989f246 | 1362 | * amdgpu_vm_update_pde - update a single level in the hierarchy |
f8991bab | 1363 | * |
6989f246 | 1364 | * @param: parameters for the update |
f8991bab | 1365 | * @vm: requested vm |
194d2161 | 1366 | * @parent: parent directory |
6989f246 | 1367 | * @entry: entry to update |
f8991bab | 1368 | * |
6989f246 | 1369 | * Makes sure the requested entry in parent is up to date. |
f8991bab | 1370 | */ |
6989f246 CK |
1371 | static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, |
1372 | struct amdgpu_vm *vm, | |
1373 | struct amdgpu_vm_pt *parent, | |
1374 | struct amdgpu_vm_pt *entry) | |
d38ceaf9 | 1375 | { |
373ac645 | 1376 | struct amdgpu_bo *bo = parent->base.bo, *pbo; |
3de676d8 CK |
1377 | uint64_t pde, pt, flags; |
1378 | unsigned level; | |
d5fc5e82 | 1379 | |
6989f246 CK |
1380 | /* Don't update huge pages here */ |
1381 | if (entry->huge) | |
1382 | return; | |
d38ceaf9 | 1383 | |
373ac645 | 1384 | for (level = 0, pbo = bo->parent; pbo; ++level) |
3de676d8 CK |
1385 | pbo = pbo->parent; |
1386 | ||
196f7489 | 1387 | level += params->adev->vm_manager.root_level; |
24a8d289 | 1388 | amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags); |
373ac645 | 1389 | pde = (entry - parent->entries) * 8; |
1c860a02 | 1390 | amdgpu_vm_update_func(params, bo, pde, pt, 1, 0, flags); |
d38ceaf9 AD |
1391 | } |
1392 | ||
92456b93 | 1393 | /* |
d4085ea9 | 1394 | * amdgpu_vm_invalidate_pds - mark all PDs as invalid |
92456b93 | 1395 | * |
7fc48e59 AG |
1396 | * @adev: amdgpu_device pointer |
1397 | * @vm: related vm | |
92456b93 CK |
1398 | * |
1399 | * Mark all PD level as invalid after an error. | |
1400 | */ | |
d4085ea9 CK |
1401 | static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev, |
1402 | struct amdgpu_vm *vm) | |
92456b93 | 1403 | { |
d4085ea9 CK |
1404 | struct amdgpu_vm_pt_cursor cursor; |
1405 | struct amdgpu_vm_pt *entry; | |
92456b93 | 1406 | |
d4085ea9 CK |
1407 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, cursor, entry) |
1408 | if (entry->base.bo && !entry->base.moved) | |
bcdc9fd6 | 1409 | amdgpu_vm_bo_relocated(&entry->base); |
92456b93 CK |
1410 | } |
1411 | ||
194d2161 CK |
1412 | /* |
1413 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1414 | * | |
1415 | * @adev: amdgpu_device pointer | |
1416 | * @vm: requested vm | |
1417 | * | |
1418 | * Makes sure all directories are up to date. | |
7fc48e59 AG |
1419 | * |
1420 | * Returns: | |
1421 | * 0 for success, error for failure. | |
194d2161 CK |
1422 | */ |
1423 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1424 | struct amdgpu_vm *vm) | |
1425 | { | |
6989f246 CK |
1426 | struct amdgpu_pte_update_params params; |
1427 | struct amdgpu_job *job; | |
1428 | unsigned ndw = 0; | |
78aa02c7 | 1429 | int r = 0; |
92456b93 | 1430 | |
6989f246 CK |
1431 | if (list_empty(&vm->relocated)) |
1432 | return 0; | |
1433 | ||
1434 | restart: | |
1435 | memset(¶ms, 0, sizeof(params)); | |
1436 | params.adev = adev; | |
1437 | ||
1438 | if (vm->use_cpu_for_update) { | |
1439 | r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); | |
1440 | if (unlikely(r)) | |
1441 | return r; | |
1442 | ||
1443 | params.func = amdgpu_vm_cpu_set_ptes; | |
1444 | } else { | |
1445 | ndw = 512 * 8; | |
1446 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
1447 | if (r) | |
1448 | return r; | |
1449 | ||
1450 | params.ib = &job->ibs[0]; | |
1451 | params.func = amdgpu_vm_do_set_ptes; | |
1452 | } | |
1453 | ||
ea09729c | 1454 | while (!list_empty(&vm->relocated)) { |
6989f246 | 1455 | struct amdgpu_vm_pt *pt, *entry; |
ea09729c | 1456 | |
ba79fde4 CK |
1457 | entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt, |
1458 | base.vm_status); | |
1459 | amdgpu_vm_bo_idle(&entry->base); | |
ea09729c | 1460 | |
ba79fde4 CK |
1461 | pt = amdgpu_vm_pt_parent(entry); |
1462 | if (!pt) | |
6989f246 | 1463 | continue; |
6989f246 | 1464 | |
6989f246 CK |
1465 | amdgpu_vm_update_pde(¶ms, vm, pt, entry); |
1466 | ||
6989f246 CK |
1467 | if (!vm->use_cpu_for_update && |
1468 | (ndw - params.ib->length_dw) < 32) | |
1469 | break; | |
ea09729c | 1470 | } |
92456b93 | 1471 | |
68c62306 CK |
1472 | if (vm->use_cpu_for_update) { |
1473 | /* Flush HDP */ | |
1474 | mb(); | |
69882565 | 1475 | amdgpu_asic_flush_hdp(adev, NULL); |
6989f246 CK |
1476 | } else if (params.ib->length_dw == 0) { |
1477 | amdgpu_job_free(job); | |
1478 | } else { | |
1479 | struct amdgpu_bo *root = vm->root.base.bo; | |
1480 | struct amdgpu_ring *ring; | |
1481 | struct dma_fence *fence; | |
1482 | ||
068c3304 | 1483 | ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, |
6989f246 CK |
1484 | sched); |
1485 | ||
1486 | amdgpu_ring_pad_ib(ring, params.ib); | |
1487 | amdgpu_sync_resv(adev, &job->sync, root->tbo.resv, | |
1488 | AMDGPU_FENCE_OWNER_VM, false); | |
6989f246 | 1489 | WARN_ON(params.ib->length_dw > ndw); |
0e28b10f CK |
1490 | r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, |
1491 | &fence); | |
6989f246 CK |
1492 | if (r) |
1493 | goto error; | |
1494 | ||
1495 | amdgpu_bo_fence(root, fence, true); | |
1496 | dma_fence_put(vm->last_update); | |
1497 | vm->last_update = fence; | |
68c62306 CK |
1498 | } |
1499 | ||
6989f246 CK |
1500 | if (!list_empty(&vm->relocated)) |
1501 | goto restart; | |
1502 | ||
1503 | return 0; | |
1504 | ||
1505 | error: | |
d4085ea9 | 1506 | amdgpu_vm_invalidate_pds(adev, vm); |
6989f246 | 1507 | amdgpu_job_free(job); |
92456b93 | 1508 | return r; |
194d2161 CK |
1509 | } |
1510 | ||
cf2f0a37 | 1511 | /** |
dfcd99f6 | 1512 | * amdgpu_vm_update_huge - figure out parameters for PTE updates |
cf2f0a37 | 1513 | * |
dfcd99f6 | 1514 | * Make sure to set the right flags for the PTEs at the desired level. |
cf2f0a37 | 1515 | */ |
dfcd99f6 CK |
1516 | static void amdgpu_vm_update_huge(struct amdgpu_pte_update_params *params, |
1517 | struct amdgpu_bo *bo, unsigned level, | |
1518 | uint64_t pe, uint64_t addr, | |
1519 | unsigned count, uint32_t incr, | |
1520 | uint64_t flags) | |
cf2f0a37 | 1521 | |
dfcd99f6 CK |
1522 | { |
1523 | if (level != AMDGPU_VM_PTB) { | |
cf2f0a37 | 1524 | flags |= AMDGPU_PDE_PTE; |
dfcd99f6 | 1525 | amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags); |
cf2f0a37 AD |
1526 | } |
1527 | ||
dfcd99f6 CK |
1528 | amdgpu_vm_update_func(params, bo, pe, addr, count, incr, flags); |
1529 | } | |
1530 | ||
1531 | /** | |
1532 | * amdgpu_vm_fragment - get fragment for PTEs | |
1533 | * | |
1534 | * @params: see amdgpu_pte_update_params definition | |
1535 | * @start: first PTE to handle | |
1536 | * @end: last PTE to handle | |
1537 | * @flags: hw mapping flags | |
1538 | * @frag: resulting fragment size | |
1539 | * @frag_end: end of this fragment | |
1540 | * | |
1541 | * Returns the first possible fragment for the start and end address. | |
1542 | */ | |
1543 | static void amdgpu_vm_fragment(struct amdgpu_pte_update_params *params, | |
1544 | uint64_t start, uint64_t end, uint64_t flags, | |
1545 | unsigned int *frag, uint64_t *frag_end) | |
1546 | { | |
1547 | /** | |
1548 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1549 | * field in the PTE. When this field is set to a non-zero value, page | |
1550 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1551 | * flags are considered valid for all PTEs within the fragment range | |
1552 | * and corresponding mappings are assumed to be physically contiguous. | |
1553 | * | |
1554 | * The L1 TLB can store a single PTE for the whole fragment, | |
1555 | * significantly increasing the space available for translation | |
1556 | * caching. This leads to large improvements in throughput when the | |
1557 | * TLB is under pressure. | |
1558 | * | |
1559 | * The L2 TLB distributes small and large fragments into two | |
1560 | * asymmetric partitions. The large fragment cache is significantly | |
1561 | * larger. Thus, we try to use large fragments wherever possible. | |
1562 | * Userspace can support this by aligning virtual base address and | |
1563 | * allocation size to the fragment size. | |
1b1d5c43 CK |
1564 | * |
1565 | * Starting with Vega10 the fragment size only controls the L1. The L2 | |
1566 | * is now directly feed with small/huge/giant pages from the walker. | |
dfcd99f6 | 1567 | */ |
1b1d5c43 CK |
1568 | unsigned max_frag; |
1569 | ||
1570 | if (params->adev->asic_type < CHIP_VEGA10) | |
1571 | max_frag = params->adev->vm_manager.fragment_size; | |
1572 | else | |
1573 | max_frag = 31; | |
dfcd99f6 CK |
1574 | |
1575 | /* system pages are non continuously */ | |
0c70dd49 | 1576 | if (params->src) { |
dfcd99f6 CK |
1577 | *frag = 0; |
1578 | *frag_end = end; | |
ec5207c9 | 1579 | return; |
3cc1d3ea | 1580 | } |
cf2f0a37 | 1581 | |
dfcd99f6 CK |
1582 | /* This intentionally wraps around if no bit is set */ |
1583 | *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1); | |
1584 | if (*frag >= max_frag) { | |
1585 | *frag = max_frag; | |
1586 | *frag_end = end & ~((1ULL << max_frag) - 1); | |
1587 | } else { | |
1588 | *frag_end = start + (1 << *frag); | |
1589 | } | |
4e2cb640 CK |
1590 | } |
1591 | ||
d38ceaf9 AD |
1592 | /** |
1593 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1594 | * | |
29efc4f5 | 1595 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1596 | * @start: start of GPU address range |
1597 | * @end: end of GPU address range | |
677131a1 | 1598 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1599 | * @flags: mapping flags |
1600 | * | |
8843dbbb | 1601 | * Update the page tables in the range @start - @end. |
7fc48e59 AG |
1602 | * |
1603 | * Returns: | |
1604 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 | 1605 | */ |
cc28c4ed | 1606 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
dfcd99f6 CK |
1607 | uint64_t start, uint64_t end, |
1608 | uint64_t dst, uint64_t flags) | |
d38ceaf9 | 1609 | { |
36b32a68 | 1610 | struct amdgpu_device *adev = params->adev; |
dfa70550 | 1611 | struct amdgpu_vm_pt_cursor cursor; |
dfcd99f6 CK |
1612 | uint64_t frag_start = start, frag_end; |
1613 | unsigned int frag; | |
1614 | ||
1615 | /* figure out the initial fragment */ | |
1616 | amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end); | |
d38ceaf9 | 1617 | |
dfcd99f6 CK |
1618 | /* walk over the address space and update the PTs */ |
1619 | amdgpu_vm_pt_start(adev, params->vm, start, &cursor); | |
1620 | while (cursor.pfn < end) { | |
dfa70550 | 1621 | struct amdgpu_bo *pt = cursor.entry->base.bo; |
cb90b97b | 1622 | unsigned shift, parent_shift, mask; |
dfcd99f6 | 1623 | uint64_t incr, entry_end, pe_start; |
cf2f0a37 | 1624 | |
dfcd99f6 | 1625 | if (!pt) |
cf2f0a37 | 1626 | return -ENOENT; |
4e2cb640 | 1627 | |
dfcd99f6 CK |
1628 | /* The root level can't be a huge page */ |
1629 | if (cursor.level == adev->vm_manager.root_level) { | |
1630 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1631 | return -ENOENT; | |
cf2f0a37 | 1632 | continue; |
dfa70550 | 1633 | } |
cf2f0a37 | 1634 | |
dfcd99f6 CK |
1635 | /* First check if the entry is already handled */ |
1636 | if (cursor.pfn < frag_start) { | |
1637 | cursor.entry->huge = true; | |
1638 | amdgpu_vm_pt_next(adev, &cursor); | |
1639 | continue; | |
1640 | } | |
92696dd5 | 1641 | |
dfcd99f6 CK |
1642 | /* If it isn't already handled it can't be a huge page */ |
1643 | if (cursor.entry->huge) { | |
1644 | /* Add the entry to the relocated list to update it. */ | |
1645 | cursor.entry->huge = false; | |
1646 | amdgpu_vm_bo_relocated(&cursor.entry->base); | |
1647 | } | |
92696dd5 | 1648 | |
dfcd99f6 CK |
1649 | shift = amdgpu_vm_level_shift(adev, cursor.level); |
1650 | parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1); | |
1651 | if (adev->asic_type < CHIP_VEGA10) { | |
1652 | /* No huge page support before GMC v9 */ | |
1653 | if (cursor.level != AMDGPU_VM_PTB) { | |
1654 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1655 | return -ENOENT; | |
1656 | continue; | |
1657 | } | |
1658 | } else if (frag < shift) { | |
1659 | /* We can't use this level when the fragment size is | |
1660 | * smaller than the address shift. Go to the next | |
1661 | * child entry and try again. | |
1662 | */ | |
1663 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1664 | return -ENOENT; | |
1665 | continue; | |
1666 | } else if (frag >= parent_shift) { | |
1667 | /* If the fragment size is even larger than the parent | |
1668 | * shift we should go up one level and check it again. | |
1669 | */ | |
1670 | if (!amdgpu_vm_pt_ancestor(&cursor)) | |
1671 | return -ENOENT; | |
1672 | continue; | |
6849d47c RH |
1673 | } |
1674 | ||
dfcd99f6 CK |
1675 | /* Looks good so far, calculate parameters for the update */ |
1676 | incr = AMDGPU_GPU_PAGE_SIZE << shift; | |
cb90b97b CK |
1677 | mask = amdgpu_vm_entries_mask(adev, cursor.level); |
1678 | pe_start = ((cursor.pfn >> shift) & mask) * 8; | |
1679 | entry_end = (mask + 1) << shift; | |
dfcd99f6 CK |
1680 | entry_end += cursor.pfn & ~(entry_end - 1); |
1681 | entry_end = min(entry_end, end); | |
1682 | ||
1683 | do { | |
1684 | uint64_t upd_end = min(entry_end, frag_end); | |
1685 | unsigned nptes = (upd_end - frag_start) >> shift; | |
1686 | ||
1687 | amdgpu_vm_update_huge(params, pt, cursor.level, | |
1688 | pe_start, dst, nptes, incr, | |
1689 | flags | AMDGPU_PTE_FRAG(frag)); | |
1690 | ||
1691 | pe_start += nptes * 8; | |
1692 | dst += nptes * AMDGPU_GPU_PAGE_SIZE << shift; | |
1693 | ||
1694 | frag_start = upd_end; | |
1695 | if (frag_start >= frag_end) { | |
1696 | /* figure out the next fragment */ | |
1697 | amdgpu_vm_fragment(params, frag_start, end, | |
1698 | flags, &frag, &frag_end); | |
1699 | if (frag < shift) | |
1700 | break; | |
1701 | } | |
1702 | } while (frag_start < entry_end); | |
92696dd5 | 1703 | |
dfcd99f6 CK |
1704 | if (frag >= shift) |
1705 | amdgpu_vm_pt_next(adev, &cursor); | |
92696dd5 | 1706 | } |
6849d47c RH |
1707 | |
1708 | return 0; | |
d38ceaf9 AD |
1709 | } |
1710 | ||
d38ceaf9 AD |
1711 | /** |
1712 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1713 | * | |
1714 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1715 | * @exclusive: fence we need to sync to |
fa3ab3c7 | 1716 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 | 1717 | * @vm: requested vm |
a14faa65 CK |
1718 | * @start: start of mapped range |
1719 | * @last: last mapped entry | |
1720 | * @flags: flags for the entries | |
d38ceaf9 | 1721 | * @addr: addr to set the area to |
d38ceaf9 AD |
1722 | * @fence: optional resulting fence |
1723 | * | |
a14faa65 | 1724 | * Fill in the page table entries between @start and @last. |
7fc48e59 AG |
1725 | * |
1726 | * Returns: | |
1727 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1728 | */ |
1729 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1730 | struct dma_fence *exclusive, |
fa3ab3c7 | 1731 | dma_addr_t *pages_addr, |
d38ceaf9 | 1732 | struct amdgpu_vm *vm, |
a14faa65 | 1733 | uint64_t start, uint64_t last, |
6b777607 | 1734 | uint64_t flags, uint64_t addr, |
f54d1867 | 1735 | struct dma_fence **fence) |
d38ceaf9 | 1736 | { |
2d55e45a | 1737 | struct amdgpu_ring *ring; |
a1e08d3b | 1738 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1739 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1740 | struct amdgpu_job *job; |
29efc4f5 | 1741 | struct amdgpu_pte_update_params params; |
f54d1867 | 1742 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1743 | int r; |
1744 | ||
afef8b8f CK |
1745 | memset(¶ms, 0, sizeof(params)); |
1746 | params.adev = adev; | |
49ac8a24 | 1747 | params.vm = vm; |
afef8b8f | 1748 | |
a33cab7a CK |
1749 | /* sync to everything on unmapping */ |
1750 | if (!(flags & AMDGPU_PTE_VALID)) | |
1751 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1752 | ||
b4d42511 HK |
1753 | if (vm->use_cpu_for_update) { |
1754 | /* params.src is used as flag to indicate system Memory */ | |
1755 | if (pages_addr) | |
1756 | params.src = ~0; | |
1757 | ||
1758 | /* Wait for PT BOs to be free. PTs share the same resv. object | |
1759 | * as the root PD BO | |
1760 | */ | |
a33cab7a | 1761 | r = amdgpu_vm_wait_pd(adev, vm, owner); |
b4d42511 HK |
1762 | if (unlikely(r)) |
1763 | return r; | |
1764 | ||
1765 | params.func = amdgpu_vm_cpu_set_ptes; | |
1766 | params.pages_addr = pages_addr; | |
dfcd99f6 CK |
1767 | return amdgpu_vm_update_ptes(¶ms, start, last + 1, |
1768 | addr, flags); | |
b4d42511 HK |
1769 | } |
1770 | ||
068c3304 | 1771 | ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched); |
27c5f36f | 1772 | |
a14faa65 | 1773 | nptes = last - start + 1; |
d38ceaf9 AD |
1774 | |
1775 | /* | |
86209523 | 1776 | * reserve space for two commands every (1 << BLOCK_SIZE) |
d38ceaf9 | 1777 | * entries or 2k dwords (whatever is smaller) |
86209523 BN |
1778 | * |
1779 | * The second command is for the shadow pagetables. | |
d38ceaf9 | 1780 | */ |
104bd2ca ED |
1781 | if (vm->root.base.bo->shadow) |
1782 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2; | |
1783 | else | |
1784 | ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1); | |
d38ceaf9 AD |
1785 | |
1786 | /* padding, etc. */ | |
1787 | ndw = 64; | |
1788 | ||
570144c6 | 1789 | if (pages_addr) { |
b0456f93 | 1790 | /* copy commands needed */ |
e6d92197 | 1791 | ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; |
d38ceaf9 | 1792 | |
b0456f93 | 1793 | /* and also PTEs */ |
d38ceaf9 AD |
1794 | ndw += nptes * 2; |
1795 | ||
afef8b8f CK |
1796 | params.func = amdgpu_vm_do_copy_ptes; |
1797 | ||
d38ceaf9 AD |
1798 | } else { |
1799 | /* set page commands needed */ | |
44e1baeb | 1800 | ndw += ncmds * 10; |
d38ceaf9 | 1801 | |
6849d47c | 1802 | /* extra commands for begin/end fragments */ |
11528640 ED |
1803 | if (vm->root.base.bo->shadow) |
1804 | ndw += 2 * 10 * adev->vm_manager.fragment_size * 2; | |
1805 | else | |
1806 | ndw += 2 * 10 * adev->vm_manager.fragment_size; | |
afef8b8f CK |
1807 | |
1808 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1809 | } |
1810 | ||
d71518b5 CK |
1811 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1812 | if (r) | |
d38ceaf9 | 1813 | return r; |
d71518b5 | 1814 | |
29efc4f5 | 1815 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1816 | |
570144c6 | 1817 | if (pages_addr) { |
b0456f93 CK |
1818 | uint64_t *pte; |
1819 | unsigned i; | |
1820 | ||
1821 | /* Put the PTEs at the end of the IB. */ | |
1822 | i = ndw - nptes * 2; | |
1823 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1824 | params.src = job->ibs->gpu_addr + i * 4; | |
1825 | ||
1826 | for (i = 0; i < nptes; ++i) { | |
1827 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1828 | AMDGPU_GPU_PAGE_SIZE); | |
1829 | pte[i] |= flags; | |
1830 | } | |
d7a4ac66 | 1831 | addr = 0; |
b0456f93 CK |
1832 | } |
1833 | ||
cebb52b7 | 1834 | r = amdgpu_sync_fence(adev, &job->sync, exclusive, false); |
3cabaa54 CK |
1835 | if (r) |
1836 | goto error_free; | |
1837 | ||
3f3333f8 | 1838 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, |
177ae09b | 1839 | owner, false); |
a1e08d3b CK |
1840 | if (r) |
1841 | goto error_free; | |
d38ceaf9 | 1842 | |
3f3333f8 | 1843 | r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv); |
a1e08d3b CK |
1844 | if (r) |
1845 | goto error_free; | |
1846 | ||
dfcd99f6 | 1847 | r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags); |
cc28c4ed HK |
1848 | if (r) |
1849 | goto error_free; | |
d38ceaf9 | 1850 | |
29efc4f5 CK |
1851 | amdgpu_ring_pad_ib(ring, params.ib); |
1852 | WARN_ON(params.ib->length_dw > ndw); | |
0e28b10f | 1853 | r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, &f); |
4af9f07c CZ |
1854 | if (r) |
1855 | goto error_free; | |
d38ceaf9 | 1856 | |
3f3333f8 | 1857 | amdgpu_bo_fence(vm->root.base.bo, f, true); |
284710fa CK |
1858 | dma_fence_put(*fence); |
1859 | *fence = f; | |
d38ceaf9 | 1860 | return 0; |
d5fc5e82 CZ |
1861 | |
1862 | error_free: | |
d71518b5 | 1863 | amdgpu_job_free(job); |
4af9f07c | 1864 | return r; |
d38ceaf9 AD |
1865 | } |
1866 | ||
a14faa65 CK |
1867 | /** |
1868 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1869 | * | |
1870 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1871 | * @exclusive: fence we need to sync to |
8358dcee | 1872 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1873 | * @vm: requested vm |
1874 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1875 | * @flags: HW flags for the mapping |
63e0ba40 | 1876 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1877 | * @fence: optional resulting fence |
1878 | * | |
1879 | * Split the mapping into smaller chunks so that each update fits | |
1880 | * into a SDMA IB. | |
7fc48e59 AG |
1881 | * |
1882 | * Returns: | |
1883 | * 0 for success, -EINVAL for failure. | |
a14faa65 CK |
1884 | */ |
1885 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1886 | struct dma_fence *exclusive, |
8358dcee | 1887 | dma_addr_t *pages_addr, |
a14faa65 CK |
1888 | struct amdgpu_vm *vm, |
1889 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1890 | uint64_t flags, |
63e0ba40 | 1891 | struct drm_mm_node *nodes, |
f54d1867 | 1892 | struct dma_fence **fence) |
a14faa65 | 1893 | { |
9fc8fc70 | 1894 | unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; |
570144c6 | 1895 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1896 | int r; |
1897 | ||
1898 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1899 | * but in case of something, we filter the flags in first place | |
1900 | */ | |
1901 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1902 | flags &= ~AMDGPU_PTE_READABLE; | |
1903 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1904 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1905 | ||
15b31c59 AX |
1906 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1907 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1908 | ||
b0fd18b0 AX |
1909 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1910 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1911 | ||
d0766e98 ZJ |
1912 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1913 | (adev->asic_type >= CHIP_VEGA10)) { | |
1914 | flags |= AMDGPU_PTE_PRT; | |
1915 | flags &= ~AMDGPU_PTE_VALID; | |
1916 | } | |
1917 | ||
a14faa65 CK |
1918 | trace_amdgpu_vm_bo_update(mapping); |
1919 | ||
63e0ba40 CK |
1920 | pfn = mapping->offset >> PAGE_SHIFT; |
1921 | if (nodes) { | |
1922 | while (pfn >= nodes->size) { | |
1923 | pfn -= nodes->size; | |
1924 | ++nodes; | |
1925 | } | |
fa3ab3c7 | 1926 | } |
a14faa65 | 1927 | |
63e0ba40 | 1928 | do { |
9fc8fc70 | 1929 | dma_addr_t *dma_addr = NULL; |
63e0ba40 CK |
1930 | uint64_t max_entries; |
1931 | uint64_t addr, last; | |
a14faa65 | 1932 | |
63e0ba40 CK |
1933 | if (nodes) { |
1934 | addr = nodes->start << PAGE_SHIFT; | |
1935 | max_entries = (nodes->size - pfn) * | |
463d2fe8 | 1936 | AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1937 | } else { |
1938 | addr = 0; | |
1939 | max_entries = S64_MAX; | |
1940 | } | |
a14faa65 | 1941 | |
63e0ba40 | 1942 | if (pages_addr) { |
9fc8fc70 CK |
1943 | uint64_t count; |
1944 | ||
457e0fee | 1945 | max_entries = min(max_entries, 16ull * 1024ull); |
38e624a1 | 1946 | for (count = 1; |
463d2fe8 | 1947 | count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
38e624a1 | 1948 | ++count) { |
9fc8fc70 CK |
1949 | uint64_t idx = pfn + count; |
1950 | ||
1951 | if (pages_addr[idx] != | |
1952 | (pages_addr[idx - 1] + PAGE_SIZE)) | |
1953 | break; | |
1954 | } | |
1955 | ||
1956 | if (count < min_linear_pages) { | |
1957 | addr = pfn << PAGE_SHIFT; | |
1958 | dma_addr = pages_addr; | |
1959 | } else { | |
1960 | addr = pages_addr[pfn]; | |
463d2fe8 | 1961 | max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
9fc8fc70 CK |
1962 | } |
1963 | ||
63e0ba40 CK |
1964 | } else if (flags & AMDGPU_PTE_VALID) { |
1965 | addr += adev->vm_manager.vram_base_offset; | |
9fc8fc70 | 1966 | addr += pfn << PAGE_SHIFT; |
63e0ba40 | 1967 | } |
63e0ba40 | 1968 | |
a9f87f64 | 1969 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
9fc8fc70 | 1970 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, |
a14faa65 CK |
1971 | start, last, flags, addr, |
1972 | fence); | |
1973 | if (r) | |
1974 | return r; | |
1975 | ||
463d2fe8 | 1976 | pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1977 | if (nodes && nodes->size == pfn) { |
1978 | pfn = 0; | |
1979 | ++nodes; | |
1980 | } | |
a14faa65 | 1981 | start = last + 1; |
63e0ba40 | 1982 | |
a9f87f64 | 1983 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1984 | |
1985 | return 0; | |
1986 | } | |
1987 | ||
d38ceaf9 AD |
1988 | /** |
1989 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1990 | * | |
1991 | * @adev: amdgpu_device pointer | |
1992 | * @bo_va: requested BO and VM object | |
99e124f4 | 1993 | * @clear: if true clear the entries |
d38ceaf9 AD |
1994 | * |
1995 | * Fill in the page table entries for @bo_va. | |
7fc48e59 AG |
1996 | * |
1997 | * Returns: | |
1998 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1999 | */ |
2000 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
2001 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 2002 | bool clear) |
d38ceaf9 | 2003 | { |
ec681545 CK |
2004 | struct amdgpu_bo *bo = bo_va->base.bo; |
2005 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2006 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 2007 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 2008 | struct ttm_mem_reg *mem; |
63e0ba40 | 2009 | struct drm_mm_node *nodes; |
4e55eb38 | 2010 | struct dma_fence *exclusive, **last_update; |
457e0fee | 2011 | uint64_t flags; |
d38ceaf9 AD |
2012 | int r; |
2013 | ||
7eb80427 | 2014 | if (clear || !bo) { |
99e124f4 | 2015 | mem = NULL; |
63e0ba40 | 2016 | nodes = NULL; |
99e124f4 CK |
2017 | exclusive = NULL; |
2018 | } else { | |
8358dcee CK |
2019 | struct ttm_dma_tt *ttm; |
2020 | ||
7eb80427 | 2021 | mem = &bo->tbo.mem; |
63e0ba40 CK |
2022 | nodes = mem->mm_node; |
2023 | if (mem->mem_type == TTM_PL_TT) { | |
7eb80427 | 2024 | ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm); |
8358dcee | 2025 | pages_addr = ttm->dma_address; |
9ab21462 | 2026 | } |
ec681545 | 2027 | exclusive = reservation_object_get_excl(bo->tbo.resv); |
d38ceaf9 AD |
2028 | } |
2029 | ||
457e0fee | 2030 | if (bo) |
ec681545 | 2031 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
457e0fee | 2032 | else |
a5f6b5b1 | 2033 | flags = 0x0; |
d38ceaf9 | 2034 | |
4e55eb38 CK |
2035 | if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) |
2036 | last_update = &vm->last_update; | |
2037 | else | |
2038 | last_update = &bo_va->last_pt_update; | |
2039 | ||
3d7d4d3a CK |
2040 | if (!clear && bo_va->base.moved) { |
2041 | bo_va->base.moved = false; | |
7fc11959 | 2042 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 2043 | |
cb7b6ec2 CK |
2044 | } else if (bo_va->cleared != clear) { |
2045 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 2046 | } |
7fc11959 CK |
2047 | |
2048 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
457e0fee | 2049 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
63e0ba40 | 2050 | mapping, flags, nodes, |
4e55eb38 | 2051 | last_update); |
d38ceaf9 AD |
2052 | if (r) |
2053 | return r; | |
2054 | } | |
2055 | ||
cb7b6ec2 CK |
2056 | if (vm->use_cpu_for_update) { |
2057 | /* Flush HDP */ | |
2058 | mb(); | |
69882565 | 2059 | amdgpu_asic_flush_hdp(adev, NULL); |
d6c10f6b CK |
2060 | } |
2061 | ||
bb475839 JZ |
2062 | /* If the BO is not in its preferred location add it back to |
2063 | * the evicted list so that it gets validated again on the | |
2064 | * next command submission. | |
2065 | */ | |
806f043f CK |
2066 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
2067 | uint32_t mem_type = bo->tbo.mem.mem_type; | |
2068 | ||
2069 | if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type))) | |
bcdc9fd6 | 2070 | amdgpu_vm_bo_evicted(&bo_va->base); |
806f043f | 2071 | else |
bcdc9fd6 | 2072 | amdgpu_vm_bo_idle(&bo_va->base); |
c12a2ee5 | 2073 | } else { |
bcdc9fd6 | 2074 | amdgpu_vm_bo_done(&bo_va->base); |
806f043f | 2075 | } |
d38ceaf9 | 2076 | |
cb7b6ec2 CK |
2077 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
2078 | bo_va->cleared = clear; | |
2079 | ||
2080 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
2081 | list_for_each_entry(mapping, &bo_va->valids, list) | |
2082 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
2083 | } |
2084 | ||
d38ceaf9 AD |
2085 | return 0; |
2086 | } | |
2087 | ||
284710fa CK |
2088 | /** |
2089 | * amdgpu_vm_update_prt_state - update the global PRT state | |
7fc48e59 AG |
2090 | * |
2091 | * @adev: amdgpu_device pointer | |
284710fa CK |
2092 | */ |
2093 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
2094 | { | |
2095 | unsigned long flags; | |
2096 | bool enable; | |
2097 | ||
2098 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 2099 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
132f34e4 | 2100 | adev->gmc.gmc_funcs->set_prt(adev, enable); |
284710fa CK |
2101 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); |
2102 | } | |
2103 | ||
451bc8eb | 2104 | /** |
4388fc2a | 2105 | * amdgpu_vm_prt_get - add a PRT user |
7fc48e59 AG |
2106 | * |
2107 | * @adev: amdgpu_device pointer | |
451bc8eb CK |
2108 | */ |
2109 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
2110 | { | |
132f34e4 | 2111 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
2112 | return; |
2113 | ||
451bc8eb CK |
2114 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
2115 | amdgpu_vm_update_prt_state(adev); | |
2116 | } | |
2117 | ||
0b15f2fc CK |
2118 | /** |
2119 | * amdgpu_vm_prt_put - drop a PRT user | |
7fc48e59 AG |
2120 | * |
2121 | * @adev: amdgpu_device pointer | |
0b15f2fc CK |
2122 | */ |
2123 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
2124 | { | |
451bc8eb | 2125 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
2126 | amdgpu_vm_update_prt_state(adev); |
2127 | } | |
2128 | ||
284710fa | 2129 | /** |
451bc8eb | 2130 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
7fc48e59 AG |
2131 | * |
2132 | * @fence: fence for the callback | |
00553cf8 | 2133 | * @_cb: the callback function |
284710fa CK |
2134 | */ |
2135 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
2136 | { | |
2137 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
2138 | ||
0b15f2fc | 2139 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
2140 | kfree(cb); |
2141 | } | |
2142 | ||
451bc8eb CK |
2143 | /** |
2144 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
7fc48e59 AG |
2145 | * |
2146 | * @adev: amdgpu_device pointer | |
2147 | * @fence: fence for the callback | |
451bc8eb CK |
2148 | */ |
2149 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
2150 | struct dma_fence *fence) | |
2151 | { | |
4388fc2a | 2152 | struct amdgpu_prt_cb *cb; |
451bc8eb | 2153 | |
132f34e4 | 2154 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
2155 | return; |
2156 | ||
2157 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
2158 | if (!cb) { |
2159 | /* Last resort when we are OOM */ | |
2160 | if (fence) | |
2161 | dma_fence_wait(fence, false); | |
2162 | ||
486a68f5 | 2163 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
2164 | } else { |
2165 | cb->adev = adev; | |
2166 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
2167 | amdgpu_vm_prt_cb)) | |
2168 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
2169 | } | |
2170 | } | |
2171 | ||
284710fa CK |
2172 | /** |
2173 | * amdgpu_vm_free_mapping - free a mapping | |
2174 | * | |
2175 | * @adev: amdgpu_device pointer | |
2176 | * @vm: requested vm | |
2177 | * @mapping: mapping to be freed | |
2178 | * @fence: fence of the unmap operation | |
2179 | * | |
2180 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
2181 | */ | |
2182 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
2183 | struct amdgpu_vm *vm, | |
2184 | struct amdgpu_bo_va_mapping *mapping, | |
2185 | struct dma_fence *fence) | |
2186 | { | |
451bc8eb CK |
2187 | if (mapping->flags & AMDGPU_PTE_PRT) |
2188 | amdgpu_vm_add_prt_cb(adev, fence); | |
2189 | kfree(mapping); | |
2190 | } | |
284710fa | 2191 | |
451bc8eb CK |
2192 | /** |
2193 | * amdgpu_vm_prt_fini - finish all prt mappings | |
2194 | * | |
2195 | * @adev: amdgpu_device pointer | |
2196 | * @vm: requested vm | |
2197 | * | |
2198 | * Register a cleanup callback to disable PRT support after VM dies. | |
2199 | */ | |
2200 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2201 | { | |
3f3333f8 | 2202 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
451bc8eb CK |
2203 | struct dma_fence *excl, **shared; |
2204 | unsigned i, shared_count; | |
2205 | int r; | |
0b15f2fc | 2206 | |
451bc8eb CK |
2207 | r = reservation_object_get_fences_rcu(resv, &excl, |
2208 | &shared_count, &shared); | |
2209 | if (r) { | |
2210 | /* Not enough memory to grab the fence list, as last resort | |
2211 | * block for all the fences to complete. | |
2212 | */ | |
2213 | reservation_object_wait_timeout_rcu(resv, true, false, | |
2214 | MAX_SCHEDULE_TIMEOUT); | |
2215 | return; | |
284710fa | 2216 | } |
451bc8eb CK |
2217 | |
2218 | /* Add a callback for each fence in the reservation object */ | |
2219 | amdgpu_vm_prt_get(adev); | |
2220 | amdgpu_vm_add_prt_cb(adev, excl); | |
2221 | ||
2222 | for (i = 0; i < shared_count; ++i) { | |
2223 | amdgpu_vm_prt_get(adev); | |
2224 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
2225 | } | |
2226 | ||
2227 | kfree(shared); | |
284710fa CK |
2228 | } |
2229 | ||
d38ceaf9 AD |
2230 | /** |
2231 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
2232 | * | |
2233 | * @adev: amdgpu_device pointer | |
2234 | * @vm: requested vm | |
f3467818 NH |
2235 | * @fence: optional resulting fence (unchanged if no work needed to be done |
2236 | * or if an error occurred) | |
d38ceaf9 AD |
2237 | * |
2238 | * Make sure all freed BOs are cleared in the PT. | |
d38ceaf9 | 2239 | * PTs have to be reserved and mutex must be locked! |
7fc48e59 AG |
2240 | * |
2241 | * Returns: | |
2242 | * 0 for success. | |
2243 | * | |
d38ceaf9 AD |
2244 | */ |
2245 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
2246 | struct amdgpu_vm *vm, |
2247 | struct dma_fence **fence) | |
d38ceaf9 AD |
2248 | { |
2249 | struct amdgpu_bo_va_mapping *mapping; | |
4584312d | 2250 | uint64_t init_pte_value = 0; |
f3467818 | 2251 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
2252 | int r; |
2253 | ||
2254 | while (!list_empty(&vm->freed)) { | |
2255 | mapping = list_first_entry(&vm->freed, | |
2256 | struct amdgpu_bo_va_mapping, list); | |
2257 | list_del(&mapping->list); | |
e17841b9 | 2258 | |
ad9a5b78 CK |
2259 | if (vm->pte_support_ats && |
2260 | mapping->start < AMDGPU_GMC_HOLE_START) | |
6d16dac8 | 2261 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec | 2262 | |
570144c6 | 2263 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, |
fc6aa33d | 2264 | mapping->start, mapping->last, |
51ac7eec | 2265 | init_pte_value, 0, &f); |
f3467818 | 2266 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 2267 | if (r) { |
f3467818 | 2268 | dma_fence_put(f); |
d38ceaf9 | 2269 | return r; |
284710fa | 2270 | } |
f3467818 | 2271 | } |
d38ceaf9 | 2272 | |
f3467818 NH |
2273 | if (fence && f) { |
2274 | dma_fence_put(*fence); | |
2275 | *fence = f; | |
2276 | } else { | |
2277 | dma_fence_put(f); | |
d38ceaf9 | 2278 | } |
f3467818 | 2279 | |
d38ceaf9 AD |
2280 | return 0; |
2281 | ||
2282 | } | |
2283 | ||
2284 | /** | |
73fb16e7 | 2285 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
2286 | * |
2287 | * @adev: amdgpu_device pointer | |
2288 | * @vm: requested vm | |
2289 | * | |
73fb16e7 | 2290 | * Make sure all BOs which are moved are updated in the PTs. |
7fc48e59 AG |
2291 | * |
2292 | * Returns: | |
2293 | * 0 for success. | |
d38ceaf9 | 2294 | * |
73fb16e7 | 2295 | * PTs have to be reserved! |
d38ceaf9 | 2296 | */ |
73fb16e7 | 2297 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 2298 | struct amdgpu_vm *vm) |
d38ceaf9 | 2299 | { |
789f3317 | 2300 | struct amdgpu_bo_va *bo_va, *tmp; |
c12a2ee5 | 2301 | struct reservation_object *resv; |
73fb16e7 | 2302 | bool clear; |
789f3317 | 2303 | int r; |
d38ceaf9 | 2304 | |
c12a2ee5 CK |
2305 | list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { |
2306 | /* Per VM BOs never need to bo cleared in the page tables */ | |
2307 | r = amdgpu_vm_bo_update(adev, bo_va, false); | |
2308 | if (r) | |
2309 | return r; | |
2310 | } | |
32b41ac2 | 2311 | |
c12a2ee5 CK |
2312 | spin_lock(&vm->invalidated_lock); |
2313 | while (!list_empty(&vm->invalidated)) { | |
2314 | bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, | |
2315 | base.vm_status); | |
2316 | resv = bo_va->base.bo->tbo.resv; | |
2317 | spin_unlock(&vm->invalidated_lock); | |
ec363e0d | 2318 | |
ec363e0d | 2319 | /* Try to reserve the BO to avoid clearing its ptes */ |
c12a2ee5 | 2320 | if (!amdgpu_vm_debug && reservation_object_trylock(resv)) |
ec363e0d CK |
2321 | clear = false; |
2322 | /* Somebody else is using the BO right now */ | |
2323 | else | |
2324 | clear = true; | |
73fb16e7 CK |
2325 | |
2326 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
c12a2ee5 | 2327 | if (r) |
d38ceaf9 AD |
2328 | return r; |
2329 | ||
c12a2ee5 | 2330 | if (!clear) |
ec363e0d | 2331 | reservation_object_unlock(resv); |
c12a2ee5 | 2332 | spin_lock(&vm->invalidated_lock); |
d38ceaf9 | 2333 | } |
c12a2ee5 | 2334 | spin_unlock(&vm->invalidated_lock); |
d38ceaf9 | 2335 | |
789f3317 | 2336 | return 0; |
d38ceaf9 AD |
2337 | } |
2338 | ||
2339 | /** | |
2340 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
2341 | * | |
2342 | * @adev: amdgpu_device pointer | |
2343 | * @vm: requested vm | |
2344 | * @bo: amdgpu buffer object | |
2345 | * | |
8843dbbb | 2346 | * Add @bo into the requested vm. |
d38ceaf9 | 2347 | * Add @bo to the list of bos associated with the vm |
7fc48e59 AG |
2348 | * |
2349 | * Returns: | |
2350 | * Newly added bo_va or NULL for failure | |
d38ceaf9 AD |
2351 | * |
2352 | * Object has to be reserved! | |
2353 | */ | |
2354 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
2355 | struct amdgpu_vm *vm, | |
2356 | struct amdgpu_bo *bo) | |
2357 | { | |
2358 | struct amdgpu_bo_va *bo_va; | |
2359 | ||
2360 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2361 | if (bo_va == NULL) { | |
2362 | return NULL; | |
2363 | } | |
3f4299be | 2364 | amdgpu_vm_bo_base_init(&bo_va->base, vm, bo); |
ec681545 | 2365 | |
d38ceaf9 | 2366 | bo_va->ref_count = 1; |
7fc11959 CK |
2367 | INIT_LIST_HEAD(&bo_va->valids); |
2368 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2369 | |
d38ceaf9 AD |
2370 | return bo_va; |
2371 | } | |
2372 | ||
73fb16e7 CK |
2373 | |
2374 | /** | |
2375 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
2376 | * | |
2377 | * @adev: amdgpu_device pointer | |
2378 | * @bo_va: bo_va to store the address | |
2379 | * @mapping: the mapping to insert | |
2380 | * | |
2381 | * Insert a new mapping into all structures. | |
2382 | */ | |
2383 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2384 | struct amdgpu_bo_va *bo_va, | |
2385 | struct amdgpu_bo_va_mapping *mapping) | |
2386 | { | |
2387 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2388 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2389 | ||
aebc5e6f | 2390 | mapping->bo_va = bo_va; |
73fb16e7 CK |
2391 | list_add(&mapping->list, &bo_va->invalids); |
2392 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2393 | ||
2394 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2395 | amdgpu_vm_prt_get(adev); | |
2396 | ||
862b8c57 CK |
2397 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv && |
2398 | !bo_va->base.moved) { | |
862b8c57 | 2399 | list_move(&bo_va->base.vm_status, &vm->moved); |
73fb16e7 CK |
2400 | } |
2401 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2402 | } | |
2403 | ||
d38ceaf9 AD |
2404 | /** |
2405 | * amdgpu_vm_bo_map - map bo inside a vm | |
2406 | * | |
2407 | * @adev: amdgpu_device pointer | |
2408 | * @bo_va: bo_va to store the address | |
2409 | * @saddr: where to map the BO | |
2410 | * @offset: requested offset in the BO | |
00553cf8 | 2411 | * @size: BO size in bytes |
d38ceaf9 AD |
2412 | * @flags: attributes of pages (read/write/valid/etc.) |
2413 | * | |
2414 | * Add a mapping of the BO at the specefied addr into the VM. | |
7fc48e59 AG |
2415 | * |
2416 | * Returns: | |
2417 | * 0 for success, error for failure. | |
d38ceaf9 | 2418 | * |
49b02b18 | 2419 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2420 | */ |
2421 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2422 | struct amdgpu_bo_va *bo_va, | |
2423 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2424 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2425 | { |
a9f87f64 | 2426 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2427 | struct amdgpu_bo *bo = bo_va->base.bo; |
2428 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2429 | uint64_t eaddr; |
d38ceaf9 | 2430 | |
0be52de9 CK |
2431 | /* validate the parameters */ |
2432 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2433 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2434 | return -EINVAL; |
0be52de9 | 2435 | |
d38ceaf9 | 2436 | /* make sure object fit at this offset */ |
005ae95e | 2437 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2438 | if (saddr >= eaddr || |
ec681545 | 2439 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 2440 | return -EINVAL; |
d38ceaf9 | 2441 | |
d38ceaf9 AD |
2442 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2443 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2444 | ||
a9f87f64 CK |
2445 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2446 | if (tmp) { | |
d38ceaf9 AD |
2447 | /* bo and tmp overlap, invalid addr */ |
2448 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2449 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2450 | tmp->start, tmp->last + 1); |
663e4577 | 2451 | return -EINVAL; |
d38ceaf9 AD |
2452 | } |
2453 | ||
2454 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2455 | if (!mapping) |
2456 | return -ENOMEM; | |
d38ceaf9 | 2457 | |
a9f87f64 CK |
2458 | mapping->start = saddr; |
2459 | mapping->last = eaddr; | |
d38ceaf9 AD |
2460 | mapping->offset = offset; |
2461 | mapping->flags = flags; | |
2462 | ||
73fb16e7 | 2463 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
2464 | |
2465 | return 0; | |
2466 | } | |
2467 | ||
2468 | /** | |
2469 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2470 | * | |
2471 | * @adev: amdgpu_device pointer | |
2472 | * @bo_va: bo_va to store the address | |
2473 | * @saddr: where to map the BO | |
2474 | * @offset: requested offset in the BO | |
00553cf8 | 2475 | * @size: BO size in bytes |
80f95c57 CK |
2476 | * @flags: attributes of pages (read/write/valid/etc.) |
2477 | * | |
2478 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2479 | * mappings as we do so. | |
7fc48e59 AG |
2480 | * |
2481 | * Returns: | |
2482 | * 0 for success, error for failure. | |
80f95c57 CK |
2483 | * |
2484 | * Object has to be reserved and unreserved outside! | |
2485 | */ | |
2486 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2487 | struct amdgpu_bo_va *bo_va, | |
2488 | uint64_t saddr, uint64_t offset, | |
2489 | uint64_t size, uint64_t flags) | |
2490 | { | |
2491 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2492 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
2493 | uint64_t eaddr; |
2494 | int r; | |
2495 | ||
2496 | /* validate the parameters */ | |
2497 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2498 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2499 | return -EINVAL; | |
2500 | ||
2501 | /* make sure object fit at this offset */ | |
2502 | eaddr = saddr + size - 1; | |
2503 | if (saddr >= eaddr || | |
ec681545 | 2504 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
2505 | return -EINVAL; |
2506 | ||
2507 | /* Allocate all the needed memory */ | |
2508 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2509 | if (!mapping) | |
2510 | return -ENOMEM; | |
2511 | ||
ec681545 | 2512 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2513 | if (r) { |
2514 | kfree(mapping); | |
2515 | return r; | |
2516 | } | |
2517 | ||
2518 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2519 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2520 | ||
a9f87f64 CK |
2521 | mapping->start = saddr; |
2522 | mapping->last = eaddr; | |
80f95c57 CK |
2523 | mapping->offset = offset; |
2524 | mapping->flags = flags; | |
2525 | ||
73fb16e7 | 2526 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 2527 | |
d38ceaf9 | 2528 | return 0; |
d38ceaf9 AD |
2529 | } |
2530 | ||
2531 | /** | |
2532 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2533 | * | |
2534 | * @adev: amdgpu_device pointer | |
2535 | * @bo_va: bo_va to remove the address from | |
2536 | * @saddr: where to the BO is mapped | |
2537 | * | |
2538 | * Remove a mapping of the BO at the specefied addr from the VM. | |
7fc48e59 AG |
2539 | * |
2540 | * Returns: | |
2541 | * 0 for success, error for failure. | |
d38ceaf9 | 2542 | * |
49b02b18 | 2543 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2544 | */ |
2545 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2546 | struct amdgpu_bo_va *bo_va, | |
2547 | uint64_t saddr) | |
2548 | { | |
2549 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2550 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2551 | bool valid = true; |
d38ceaf9 | 2552 | |
6c7fc503 | 2553 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2554 | |
7fc11959 | 2555 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2556 | if (mapping->start == saddr) |
d38ceaf9 AD |
2557 | break; |
2558 | } | |
2559 | ||
7fc11959 CK |
2560 | if (&mapping->list == &bo_va->valids) { |
2561 | valid = false; | |
2562 | ||
2563 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2564 | if (mapping->start == saddr) |
7fc11959 CK |
2565 | break; |
2566 | } | |
2567 | ||
32b41ac2 | 2568 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2569 | return -ENOENT; |
d38ceaf9 | 2570 | } |
32b41ac2 | 2571 | |
d38ceaf9 | 2572 | list_del(&mapping->list); |
a9f87f64 | 2573 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2574 | mapping->bo_va = NULL; |
93e3e438 | 2575 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2576 | |
e17841b9 | 2577 | if (valid) |
d38ceaf9 | 2578 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2579 | else |
284710fa CK |
2580 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2581 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2582 | |
2583 | return 0; | |
2584 | } | |
2585 | ||
dc54d3d1 CK |
2586 | /** |
2587 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2588 | * | |
2589 | * @adev: amdgpu_device pointer | |
2590 | * @vm: VM structure to use | |
2591 | * @saddr: start of the range | |
2592 | * @size: size of the range | |
2593 | * | |
2594 | * Remove all mappings in a range, split them as appropriate. | |
7fc48e59 AG |
2595 | * |
2596 | * Returns: | |
2597 | * 0 for success, error for failure. | |
dc54d3d1 CK |
2598 | */ |
2599 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2600 | struct amdgpu_vm *vm, | |
2601 | uint64_t saddr, uint64_t size) | |
2602 | { | |
2603 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2604 | LIST_HEAD(removed); |
2605 | uint64_t eaddr; | |
2606 | ||
2607 | eaddr = saddr + size - 1; | |
2608 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2609 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2610 | ||
2611 | /* Allocate all the needed memory */ | |
2612 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2613 | if (!before) | |
2614 | return -ENOMEM; | |
27f6d610 | 2615 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2616 | |
2617 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2618 | if (!after) { | |
2619 | kfree(before); | |
2620 | return -ENOMEM; | |
2621 | } | |
27f6d610 | 2622 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2623 | |
2624 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2625 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2626 | while (tmp) { | |
dc54d3d1 | 2627 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2628 | if (tmp->start < saddr) { |
2629 | before->start = tmp->start; | |
2630 | before->last = saddr - 1; | |
dc54d3d1 CK |
2631 | before->offset = tmp->offset; |
2632 | before->flags = tmp->flags; | |
387f49e5 JZ |
2633 | before->bo_va = tmp->bo_va; |
2634 | list_add(&before->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2635 | } |
2636 | ||
2637 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2638 | if (tmp->last > eaddr) { |
2639 | after->start = eaddr + 1; | |
2640 | after->last = tmp->last; | |
dc54d3d1 | 2641 | after->offset = tmp->offset; |
a9f87f64 | 2642 | after->offset += after->start - tmp->start; |
dc54d3d1 | 2643 | after->flags = tmp->flags; |
387f49e5 JZ |
2644 | after->bo_va = tmp->bo_va; |
2645 | list_add(&after->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2646 | } |
2647 | ||
2648 | list_del(&tmp->list); | |
2649 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2650 | |
2651 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2652 | } |
2653 | ||
2654 | /* And free them up */ | |
2655 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2656 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2657 | list_del(&tmp->list); |
2658 | ||
a9f87f64 CK |
2659 | if (tmp->start < saddr) |
2660 | tmp->start = saddr; | |
2661 | if (tmp->last > eaddr) | |
2662 | tmp->last = eaddr; | |
dc54d3d1 | 2663 | |
aebc5e6f | 2664 | tmp->bo_va = NULL; |
dc54d3d1 CK |
2665 | list_add(&tmp->list, &vm->freed); |
2666 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2667 | } | |
2668 | ||
27f6d610 JZ |
2669 | /* Insert partial mapping before the range */ |
2670 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2671 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2672 | if (before->flags & AMDGPU_PTE_PRT) |
2673 | amdgpu_vm_prt_get(adev); | |
2674 | } else { | |
2675 | kfree(before); | |
2676 | } | |
2677 | ||
2678 | /* Insert partial mapping after the range */ | |
27f6d610 | 2679 | if (!list_empty(&after->list)) { |
a9f87f64 | 2680 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2681 | if (after->flags & AMDGPU_PTE_PRT) |
2682 | amdgpu_vm_prt_get(adev); | |
2683 | } else { | |
2684 | kfree(after); | |
2685 | } | |
2686 | ||
2687 | return 0; | |
2688 | } | |
2689 | ||
aebc5e6f CK |
2690 | /** |
2691 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2692 | * | |
2693 | * @vm: the requested VM | |
00553cf8 | 2694 | * @addr: the address |
aebc5e6f CK |
2695 | * |
2696 | * Find a mapping by it's address. | |
7fc48e59 AG |
2697 | * |
2698 | * Returns: | |
2699 | * The amdgpu_bo_va_mapping matching for addr or NULL | |
2700 | * | |
aebc5e6f CK |
2701 | */ |
2702 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2703 | uint64_t addr) | |
2704 | { | |
2705 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2706 | } | |
2707 | ||
8ab19ea6 CK |
2708 | /** |
2709 | * amdgpu_vm_bo_trace_cs - trace all reserved mappings | |
2710 | * | |
2711 | * @vm: the requested vm | |
2712 | * @ticket: CS ticket | |
2713 | * | |
2714 | * Trace all mappings of BOs reserved during a command submission. | |
2715 | */ | |
2716 | void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) | |
2717 | { | |
2718 | struct amdgpu_bo_va_mapping *mapping; | |
2719 | ||
2720 | if (!trace_amdgpu_vm_bo_cs_enabled()) | |
2721 | return; | |
2722 | ||
2723 | for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping; | |
2724 | mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) { | |
2725 | if (mapping->bo_va && mapping->bo_va->base.bo) { | |
2726 | struct amdgpu_bo *bo; | |
2727 | ||
2728 | bo = mapping->bo_va->base.bo; | |
2729 | if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket) | |
2730 | continue; | |
2731 | } | |
2732 | ||
2733 | trace_amdgpu_vm_bo_cs(mapping); | |
2734 | } | |
2735 | } | |
2736 | ||
d38ceaf9 AD |
2737 | /** |
2738 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2739 | * | |
2740 | * @adev: amdgpu_device pointer | |
2741 | * @bo_va: requested bo_va | |
2742 | * | |
8843dbbb | 2743 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2744 | * |
2745 | * Object have to be reserved! | |
2746 | */ | |
2747 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2748 | struct amdgpu_bo_va *bo_va) | |
2749 | { | |
2750 | struct amdgpu_bo_va_mapping *mapping, *next; | |
fbbf794c | 2751 | struct amdgpu_bo *bo = bo_va->base.bo; |
ec681545 | 2752 | struct amdgpu_vm *vm = bo_va->base.vm; |
646b9025 | 2753 | struct amdgpu_vm_bo_base **base; |
d38ceaf9 | 2754 | |
646b9025 CK |
2755 | if (bo) { |
2756 | if (bo->tbo.resv == vm->root.base.bo->tbo.resv) | |
2757 | vm->bulk_moveable = false; | |
fbbf794c | 2758 | |
646b9025 CK |
2759 | for (base = &bo_va->base.bo->vm_bo; *base; |
2760 | base = &(*base)->next) { | |
2761 | if (*base != &bo_va->base) | |
2762 | continue; | |
2763 | ||
2764 | *base = bo_va->base.next; | |
2765 | break; | |
2766 | } | |
2767 | } | |
d38ceaf9 | 2768 | |
c12a2ee5 | 2769 | spin_lock(&vm->invalidated_lock); |
ec681545 | 2770 | list_del(&bo_va->base.vm_status); |
c12a2ee5 | 2771 | spin_unlock(&vm->invalidated_lock); |
d38ceaf9 | 2772 | |
7fc11959 | 2773 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2774 | list_del(&mapping->list); |
a9f87f64 | 2775 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2776 | mapping->bo_va = NULL; |
93e3e438 | 2777 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2778 | list_add(&mapping->list, &vm->freed); |
2779 | } | |
2780 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2781 | list_del(&mapping->list); | |
a9f87f64 | 2782 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2783 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2784 | bo_va->last_pt_update); | |
d38ceaf9 | 2785 | } |
32b41ac2 | 2786 | |
f54d1867 | 2787 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2788 | kfree(bo_va); |
d38ceaf9 AD |
2789 | } |
2790 | ||
2791 | /** | |
2792 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2793 | * | |
2794 | * @adev: amdgpu_device pointer | |
d38ceaf9 | 2795 | * @bo: amdgpu buffer object |
00553cf8 | 2796 | * @evicted: is the BO evicted |
d38ceaf9 | 2797 | * |
8843dbbb | 2798 | * Mark @bo as invalid. |
d38ceaf9 AD |
2799 | */ |
2800 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2801 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2802 | { |
ec681545 CK |
2803 | struct amdgpu_vm_bo_base *bo_base; |
2804 | ||
4bebccee CZ |
2805 | /* shadow bo doesn't have bo base, its validation needs its parent */ |
2806 | if (bo->parent && bo->parent->shadow == bo) | |
2807 | bo = bo->parent; | |
2808 | ||
646b9025 | 2809 | for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { |
3f3333f8 CK |
2810 | struct amdgpu_vm *vm = bo_base->vm; |
2811 | ||
3f3333f8 | 2812 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
bcdc9fd6 | 2813 | amdgpu_vm_bo_evicted(bo_base); |
3f3333f8 CK |
2814 | continue; |
2815 | } | |
2816 | ||
bcdc9fd6 | 2817 | if (bo_base->moved) |
3f3333f8 | 2818 | continue; |
bcdc9fd6 | 2819 | bo_base->moved = true; |
3f3333f8 | 2820 | |
bcdc9fd6 CK |
2821 | if (bo->tbo.type == ttm_bo_type_kernel) |
2822 | amdgpu_vm_bo_relocated(bo_base); | |
2823 | else if (bo->tbo.resv == vm->root.base.bo->tbo.resv) | |
2824 | amdgpu_vm_bo_moved(bo_base); | |
2825 | else | |
2826 | amdgpu_vm_bo_invalidated(bo_base); | |
d38ceaf9 AD |
2827 | } |
2828 | } | |
2829 | ||
7fc48e59 AG |
2830 | /** |
2831 | * amdgpu_vm_get_block_size - calculate VM page table size as power of two | |
2832 | * | |
2833 | * @vm_size: VM size | |
2834 | * | |
2835 | * Returns: | |
2836 | * VM page table as power of two | |
2837 | */ | |
bab4fee7 JZ |
2838 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2839 | { | |
2840 | /* Total bits covered by PD + PTs */ | |
2841 | unsigned bits = ilog2(vm_size) + 18; | |
2842 | ||
2843 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2844 | Above that split equal between PD and PTs */ | |
2845 | if (vm_size <= 8) | |
2846 | return (bits - 9); | |
2847 | else | |
2848 | return ((bits + 3) / 2); | |
2849 | } | |
2850 | ||
d07f14be RH |
2851 | /** |
2852 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2853 | * |
2854 | * @adev: amdgpu_device pointer | |
43370c4c | 2855 | * @min_vm_size: the minimum vm size in GB if it's set auto |
00553cf8 AG |
2856 | * @fragment_size_default: Default PTE fragment size |
2857 | * @max_level: max VMPT level | |
2858 | * @max_bits: max address space size in bits | |
2859 | * | |
bab4fee7 | 2860 | */ |
43370c4c | 2861 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, |
f3368128 CK |
2862 | uint32_t fragment_size_default, unsigned max_level, |
2863 | unsigned max_bits) | |
bab4fee7 | 2864 | { |
43370c4c FK |
2865 | unsigned int max_size = 1 << (max_bits - 30); |
2866 | unsigned int vm_size; | |
36539dce CK |
2867 | uint64_t tmp; |
2868 | ||
2869 | /* adjust vm size first */ | |
f3368128 | 2870 | if (amdgpu_vm_size != -1) { |
fdd5faaa | 2871 | vm_size = amdgpu_vm_size; |
f3368128 CK |
2872 | if (vm_size > max_size) { |
2873 | dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", | |
2874 | amdgpu_vm_size, max_size); | |
2875 | vm_size = max_size; | |
2876 | } | |
43370c4c FK |
2877 | } else { |
2878 | struct sysinfo si; | |
2879 | unsigned int phys_ram_gb; | |
2880 | ||
2881 | /* Optimal VM size depends on the amount of physical | |
2882 | * RAM available. Underlying requirements and | |
2883 | * assumptions: | |
2884 | * | |
2885 | * - Need to map system memory and VRAM from all GPUs | |
2886 | * - VRAM from other GPUs not known here | |
2887 | * - Assume VRAM <= system memory | |
2888 | * - On GFX8 and older, VM space can be segmented for | |
2889 | * different MTYPEs | |
2890 | * - Need to allow room for fragmentation, guard pages etc. | |
2891 | * | |
2892 | * This adds up to a rough guess of system memory x3. | |
2893 | * Round up to power of two to maximize the available | |
2894 | * VM size with the given page table size. | |
2895 | */ | |
2896 | si_meminfo(&si); | |
2897 | phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit + | |
2898 | (1 << 30) - 1) >> 30; | |
2899 | vm_size = roundup_pow_of_two( | |
2900 | min(max(phys_ram_gb * 3, min_vm_size), max_size)); | |
f3368128 | 2901 | } |
fdd5faaa CK |
2902 | |
2903 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
36539dce CK |
2904 | |
2905 | tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); | |
97489129 CK |
2906 | if (amdgpu_vm_block_size != -1) |
2907 | tmp >>= amdgpu_vm_block_size - 9; | |
36539dce CK |
2908 | tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; |
2909 | adev->vm_manager.num_level = min(max_level, (unsigned)tmp); | |
196f7489 CZ |
2910 | switch (adev->vm_manager.num_level) { |
2911 | case 3: | |
2912 | adev->vm_manager.root_level = AMDGPU_VM_PDB2; | |
2913 | break; | |
2914 | case 2: | |
2915 | adev->vm_manager.root_level = AMDGPU_VM_PDB1; | |
2916 | break; | |
2917 | case 1: | |
2918 | adev->vm_manager.root_level = AMDGPU_VM_PDB0; | |
2919 | break; | |
2920 | default: | |
2921 | dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n"); | |
2922 | } | |
b38f41eb | 2923 | /* block size depends on vm size and hw setup*/ |
97489129 | 2924 | if (amdgpu_vm_block_size != -1) |
bab4fee7 | 2925 | adev->vm_manager.block_size = |
97489129 CK |
2926 | min((unsigned)amdgpu_vm_block_size, max_bits |
2927 | - AMDGPU_GPU_PAGE_SHIFT | |
2928 | - 9 * adev->vm_manager.num_level); | |
2929 | else if (adev->vm_manager.num_level > 1) | |
2930 | adev->vm_manager.block_size = 9; | |
bab4fee7 | 2931 | else |
97489129 | 2932 | adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); |
bab4fee7 | 2933 | |
b38f41eb CK |
2934 | if (amdgpu_vm_fragment_size == -1) |
2935 | adev->vm_manager.fragment_size = fragment_size_default; | |
2936 | else | |
2937 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
d07f14be | 2938 | |
36539dce CK |
2939 | DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", |
2940 | vm_size, adev->vm_manager.num_level + 1, | |
2941 | adev->vm_manager.block_size, | |
fdd5faaa | 2942 | adev->vm_manager.fragment_size); |
bab4fee7 JZ |
2943 | } |
2944 | ||
240cd9a6 OZ |
2945 | static struct amdgpu_retryfault_hashtable *init_fault_hash(void) |
2946 | { | |
2947 | struct amdgpu_retryfault_hashtable *fault_hash; | |
2948 | ||
2949 | fault_hash = kmalloc(sizeof(*fault_hash), GFP_KERNEL); | |
2950 | if (!fault_hash) | |
2951 | return fault_hash; | |
2952 | ||
2953 | INIT_CHASH_TABLE(fault_hash->hash, | |
2954 | AMDGPU_PAGEFAULT_HASH_BITS, 8, 0); | |
2955 | spin_lock_init(&fault_hash->lock); | |
2956 | fault_hash->count = 0; | |
2957 | ||
2958 | return fault_hash; | |
2959 | } | |
2960 | ||
d38ceaf9 AD |
2961 | /** |
2962 | * amdgpu_vm_init - initialize a vm instance | |
2963 | * | |
2964 | * @adev: amdgpu_device pointer | |
2965 | * @vm: requested vm | |
9a4b7d4c | 2966 | * @vm_context: Indicates if it GFX or Compute context |
00553cf8 | 2967 | * @pasid: Process address space identifier |
d38ceaf9 | 2968 | * |
8843dbbb | 2969 | * Init @vm fields. |
7fc48e59 AG |
2970 | * |
2971 | * Returns: | |
2972 | * 0 for success, error for failure. | |
d38ceaf9 | 2973 | */ |
9a4b7d4c | 2974 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 2975 | int vm_context, unsigned int pasid) |
d38ceaf9 | 2976 | { |
3216c6b7 | 2977 | struct amdgpu_bo_param bp; |
3f4299be | 2978 | struct amdgpu_bo *root; |
36bbf3bf | 2979 | int r, i; |
d38ceaf9 | 2980 | |
f808c13f | 2981 | vm->va = RB_ROOT_CACHED; |
36bbf3bf CZ |
2982 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2983 | vm->reserved_vmid[i] = NULL; | |
3f3333f8 | 2984 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2985 | INIT_LIST_HEAD(&vm->relocated); |
27c7b9ae | 2986 | INIT_LIST_HEAD(&vm->moved); |
806f043f | 2987 | INIT_LIST_HEAD(&vm->idle); |
c12a2ee5 CK |
2988 | INIT_LIST_HEAD(&vm->invalidated); |
2989 | spin_lock_init(&vm->invalidated_lock); | |
d38ceaf9 | 2990 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2991 | |
2bd9ccfa | 2992 | /* create scheduler entity for page table updates */ |
3798e9a6 CK |
2993 | r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs, |
2994 | adev->vm_manager.vm_pte_num_rqs, NULL); | |
2bd9ccfa | 2995 | if (r) |
f566ceb1 | 2996 | return r; |
2bd9ccfa | 2997 | |
51ac7eec YZ |
2998 | vm->pte_support_ats = false; |
2999 | ||
3000 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
3001 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
3002 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec | 3003 | |
741deade | 3004 | if (adev->asic_type == CHIP_RAVEN) |
51ac7eec | 3005 | vm->pte_support_ats = true; |
13307f7e | 3006 | } else { |
9a4b7d4c HK |
3007 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
3008 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
13307f7e | 3009 | } |
9a4b7d4c HK |
3010 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
3011 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
c8c5e569 | 3012 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)), |
9a4b7d4c | 3013 | "CPU update of VM recommended only for large BAR system\n"); |
d5884513 | 3014 | vm->last_update = NULL; |
05906dec | 3015 | |
e21eb261 | 3016 | amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp); |
03e9dee1 FK |
3017 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) |
3018 | bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW; | |
3f4299be | 3019 | r = amdgpu_bo_create(adev, &bp, &root); |
d38ceaf9 | 3020 | if (r) |
2bd9ccfa CK |
3021 | goto error_free_sched_entity; |
3022 | ||
3f4299be | 3023 | r = amdgpu_bo_reserve(root, true); |
d3aab672 CK |
3024 | if (r) |
3025 | goto error_free_root; | |
3026 | ||
3f4299be | 3027 | r = amdgpu_vm_clear_bo(adev, vm, root, |
4584312d CK |
3028 | adev->vm_manager.root_level, |
3029 | vm->pte_support_ats); | |
13307f7e CK |
3030 | if (r) |
3031 | goto error_unreserve; | |
3032 | ||
3f4299be | 3033 | amdgpu_vm_bo_base_init(&vm->root.base, vm, root); |
d3aab672 | 3034 | amdgpu_bo_unreserve(vm->root.base.bo); |
d38ceaf9 | 3035 | |
02208441 FK |
3036 | if (pasid) { |
3037 | unsigned long flags; | |
3038 | ||
3039 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3040 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
3041 | GFP_ATOMIC); | |
3042 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3043 | if (r < 0) | |
3044 | goto error_free_root; | |
3045 | ||
3046 | vm->pasid = pasid; | |
0a096fb6 CK |
3047 | } |
3048 | ||
240cd9a6 OZ |
3049 | vm->fault_hash = init_fault_hash(); |
3050 | if (!vm->fault_hash) { | |
3051 | r = -ENOMEM; | |
3052 | goto error_free_root; | |
3053 | } | |
3054 | ||
a2f14820 | 3055 | INIT_KFIFO(vm->faults); |
c98171cc | 3056 | vm->fault_credit = 16; |
d38ceaf9 AD |
3057 | |
3058 | return 0; | |
2bd9ccfa | 3059 | |
13307f7e CK |
3060 | error_unreserve: |
3061 | amdgpu_bo_unreserve(vm->root.base.bo); | |
3062 | ||
67003a15 | 3063 | error_free_root: |
3f3333f8 CK |
3064 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
3065 | amdgpu_bo_unref(&vm->root.base.bo); | |
3066 | vm->root.base.bo = NULL; | |
2bd9ccfa CK |
3067 | |
3068 | error_free_sched_entity: | |
cdc50176 | 3069 | drm_sched_entity_destroy(&vm->entity); |
2bd9ccfa CK |
3070 | |
3071 | return r; | |
d38ceaf9 AD |
3072 | } |
3073 | ||
b236fa1d FK |
3074 | /** |
3075 | * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM | |
3076 | * | |
7fc48e59 AG |
3077 | * @adev: amdgpu_device pointer |
3078 | * @vm: requested vm | |
3079 | * | |
b236fa1d FK |
3080 | * This only works on GFX VMs that don't have any BOs added and no |
3081 | * page tables allocated yet. | |
3082 | * | |
3083 | * Changes the following VM parameters: | |
3084 | * - use_cpu_for_update | |
3085 | * - pte_supports_ats | |
3086 | * - pasid (old PASID is released, because compute manages its own PASIDs) | |
3087 | * | |
3088 | * Reinitializes the page directory to reflect the changed ATS | |
b5d21aac | 3089 | * setting. |
b236fa1d | 3090 | * |
7fc48e59 AG |
3091 | * Returns: |
3092 | * 0 for success, -errno for errors. | |
b236fa1d | 3093 | */ |
1685b01a | 3094 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid) |
b236fa1d | 3095 | { |
741deade | 3096 | bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); |
b236fa1d FK |
3097 | int r; |
3098 | ||
3099 | r = amdgpu_bo_reserve(vm->root.base.bo, true); | |
3100 | if (r) | |
3101 | return r; | |
3102 | ||
3103 | /* Sanity checks */ | |
3104 | if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) { | |
3105 | r = -EINVAL; | |
1685b01a OZ |
3106 | goto unreserve_bo; |
3107 | } | |
3108 | ||
3109 | if (pasid) { | |
3110 | unsigned long flags; | |
3111 | ||
3112 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3113 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
3114 | GFP_ATOMIC); | |
3115 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3116 | ||
3117 | if (r == -ENOSPC) | |
3118 | goto unreserve_bo; | |
3119 | r = 0; | |
b236fa1d FK |
3120 | } |
3121 | ||
3122 | /* Check if PD needs to be reinitialized and do it before | |
3123 | * changing any other state, in case it fails. | |
3124 | */ | |
3125 | if (pte_support_ats != vm->pte_support_ats) { | |
3126 | r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, | |
3127 | adev->vm_manager.root_level, | |
3128 | pte_support_ats); | |
3129 | if (r) | |
1685b01a | 3130 | goto free_idr; |
b236fa1d FK |
3131 | } |
3132 | ||
3133 | /* Update VM state */ | |
3134 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
3135 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
3136 | vm->pte_support_ats = pte_support_ats; | |
3137 | DRM_DEBUG_DRIVER("VM update mode is %s\n", | |
3138 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
c8c5e569 | 3139 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)), |
b236fa1d FK |
3140 | "CPU update of VM recommended only for large BAR system\n"); |
3141 | ||
3142 | if (vm->pasid) { | |
3143 | unsigned long flags; | |
3144 | ||
3145 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3146 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3147 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3148 | ||
1685b01a OZ |
3149 | /* Free the original amdgpu allocated pasid |
3150 | * Will be replaced with kfd allocated pasid | |
3151 | */ | |
3152 | amdgpu_pasid_free(vm->pasid); | |
b236fa1d FK |
3153 | vm->pasid = 0; |
3154 | } | |
3155 | ||
b5d21aac SL |
3156 | /* Free the shadow bo for compute VM */ |
3157 | amdgpu_bo_unref(&vm->root.base.bo->shadow); | |
3158 | ||
1685b01a OZ |
3159 | if (pasid) |
3160 | vm->pasid = pasid; | |
3161 | ||
3162 | goto unreserve_bo; | |
3163 | ||
3164 | free_idr: | |
3165 | if (pasid) { | |
3166 | unsigned long flags; | |
3167 | ||
3168 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3169 | idr_remove(&adev->vm_manager.pasid_idr, pasid); | |
3170 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3171 | } | |
3172 | unreserve_bo: | |
b236fa1d FK |
3173 | amdgpu_bo_unreserve(vm->root.base.bo); |
3174 | return r; | |
3175 | } | |
3176 | ||
bf47afba OZ |
3177 | /** |
3178 | * amdgpu_vm_release_compute - release a compute vm | |
3179 | * @adev: amdgpu_device pointer | |
3180 | * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute | |
3181 | * | |
3182 | * This is a correspondant of amdgpu_vm_make_compute. It decouples compute | |
3183 | * pasid from vm. Compute should stop use of vm after this call. | |
3184 | */ | |
3185 | void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
3186 | { | |
3187 | if (vm->pasid) { | |
3188 | unsigned long flags; | |
3189 | ||
3190 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3191 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3192 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3193 | } | |
3194 | vm->pasid = 0; | |
3195 | } | |
3196 | ||
d38ceaf9 AD |
3197 | /** |
3198 | * amdgpu_vm_fini - tear down a vm instance | |
3199 | * | |
3200 | * @adev: amdgpu_device pointer | |
3201 | * @vm: requested vm | |
3202 | * | |
8843dbbb | 3203 | * Tear down @vm. |
d38ceaf9 AD |
3204 | * Unbind the VM and remove all bos from the vm bo list |
3205 | */ | |
3206 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
3207 | { | |
3208 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
132f34e4 | 3209 | bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt; |
2642cf11 | 3210 | struct amdgpu_bo *root; |
a2f14820 | 3211 | u64 fault; |
2642cf11 | 3212 | int i, r; |
d38ceaf9 | 3213 | |
ede0dd86 FK |
3214 | amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm); |
3215 | ||
a2f14820 FK |
3216 | /* Clear pending page faults from IH when the VM is destroyed */ |
3217 | while (kfifo_get(&vm->faults, &fault)) | |
240cd9a6 | 3218 | amdgpu_vm_clear_fault(vm->fault_hash, fault); |
a2f14820 | 3219 | |
02208441 FK |
3220 | if (vm->pasid) { |
3221 | unsigned long flags; | |
3222 | ||
3223 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
3224 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
3225 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
3226 | } | |
3227 | ||
240cd9a6 OZ |
3228 | kfree(vm->fault_hash); |
3229 | vm->fault_hash = NULL; | |
3230 | ||
cdc50176 | 3231 | drm_sched_entity_destroy(&vm->entity); |
2bd9ccfa | 3232 | |
f808c13f | 3233 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
d38ceaf9 AD |
3234 | dev_err(adev->dev, "still active bo inside vm\n"); |
3235 | } | |
f808c13f DB |
3236 | rbtree_postorder_for_each_entry_safe(mapping, tmp, |
3237 | &vm->va.rb_root, rb) { | |
d38ceaf9 | 3238 | list_del(&mapping->list); |
a9f87f64 | 3239 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
3240 | kfree(mapping); |
3241 | } | |
3242 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 3243 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 3244 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 3245 | prt_fini_needed = false; |
451bc8eb | 3246 | } |
284710fa | 3247 | |
d38ceaf9 | 3248 | list_del(&mapping->list); |
451bc8eb | 3249 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
3250 | } |
3251 | ||
2642cf11 CK |
3252 | root = amdgpu_bo_ref(vm->root.base.bo); |
3253 | r = amdgpu_bo_reserve(root, true); | |
3254 | if (r) { | |
3255 | dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); | |
3256 | } else { | |
229a37f8 | 3257 | amdgpu_vm_free_pts(adev, vm); |
2642cf11 CK |
3258 | amdgpu_bo_unreserve(root); |
3259 | } | |
3260 | amdgpu_bo_unref(&root); | |
d5884513 | 3261 | dma_fence_put(vm->last_update); |
1e9ef26f | 3262 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
620f774f | 3263 | amdgpu_vmid_free_reserved(adev, vm, i); |
d38ceaf9 | 3264 | } |
ea89f8c9 | 3265 | |
c98171cc FK |
3266 | /** |
3267 | * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID | |
3268 | * | |
3269 | * @adev: amdgpu_device pointer | |
3270 | * @pasid: PASID do identify the VM | |
3271 | * | |
7fc48e59 AG |
3272 | * This function is expected to be called in interrupt context. |
3273 | * | |
3274 | * Returns: | |
3275 | * True if there was fault credit, false otherwise | |
c98171cc FK |
3276 | */ |
3277 | bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, | |
3278 | unsigned int pasid) | |
3279 | { | |
3280 | struct amdgpu_vm *vm; | |
3281 | ||
3282 | spin_lock(&adev->vm_manager.pasid_lock); | |
3283 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
d958939a | 3284 | if (!vm) { |
c98171cc | 3285 | /* VM not found, can't track fault credit */ |
d958939a | 3286 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc | 3287 | return true; |
d958939a | 3288 | } |
c98171cc FK |
3289 | |
3290 | /* No lock needed. only accessed by IRQ handler */ | |
d958939a | 3291 | if (!vm->fault_credit) { |
c98171cc | 3292 | /* Too many faults in this VM */ |
d958939a | 3293 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc | 3294 | return false; |
d958939a | 3295 | } |
c98171cc FK |
3296 | |
3297 | vm->fault_credit--; | |
d958939a | 3298 | spin_unlock(&adev->vm_manager.pasid_lock); |
c98171cc FK |
3299 | return true; |
3300 | } | |
3301 | ||
a9a78b32 CK |
3302 | /** |
3303 | * amdgpu_vm_manager_init - init the VM manager | |
3304 | * | |
3305 | * @adev: amdgpu_device pointer | |
3306 | * | |
3307 | * Initialize the VM manager structures | |
3308 | */ | |
3309 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
3310 | { | |
620f774f | 3311 | unsigned i; |
a9a78b32 | 3312 | |
620f774f | 3313 | amdgpu_vmid_mgr_init(adev); |
2d55e45a | 3314 | |
f54d1867 CW |
3315 | adev->vm_manager.fence_context = |
3316 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
3317 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
3318 | adev->vm_manager.seqno[i] = 0; | |
3319 | ||
284710fa | 3320 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 3321 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
3322 | |
3323 | /* If not overridden by the user, by default, only in large BAR systems | |
3324 | * Compute VM tables will be updated by CPU | |
3325 | */ | |
3326 | #ifdef CONFIG_X86_64 | |
3327 | if (amdgpu_vm_update_mode == -1) { | |
c8c5e569 | 3328 | if (amdgpu_gmc_vram_full_visible(&adev->gmc)) |
9a4b7d4c HK |
3329 | adev->vm_manager.vm_update_mode = |
3330 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
3331 | else | |
3332 | adev->vm_manager.vm_update_mode = 0; | |
3333 | } else | |
3334 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
3335 | #else | |
3336 | adev->vm_manager.vm_update_mode = 0; | |
3337 | #endif | |
3338 | ||
02208441 FK |
3339 | idr_init(&adev->vm_manager.pasid_idr); |
3340 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
a9a78b32 CK |
3341 | } |
3342 | ||
ea89f8c9 CK |
3343 | /** |
3344 | * amdgpu_vm_manager_fini - cleanup VM manager | |
3345 | * | |
3346 | * @adev: amdgpu_device pointer | |
3347 | * | |
3348 | * Cleanup the VM manager and free resources. | |
3349 | */ | |
3350 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
3351 | { | |
02208441 FK |
3352 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); |
3353 | idr_destroy(&adev->vm_manager.pasid_idr); | |
3354 | ||
620f774f | 3355 | amdgpu_vmid_mgr_fini(adev); |
ea89f8c9 | 3356 | } |
cfbcacf4 | 3357 | |
7fc48e59 AG |
3358 | /** |
3359 | * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs. | |
3360 | * | |
3361 | * @dev: drm device pointer | |
3362 | * @data: drm_amdgpu_vm | |
3363 | * @filp: drm file pointer | |
3364 | * | |
3365 | * Returns: | |
3366 | * 0 for success, -errno for errors. | |
3367 | */ | |
cfbcacf4 CZ |
3368 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
3369 | { | |
3370 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
3371 | struct amdgpu_device *adev = dev->dev_private; |
3372 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
3373 | int r; | |
cfbcacf4 CZ |
3374 | |
3375 | switch (args->in.op) { | |
3376 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f | 3377 | /* current, we only have requirement to reserve vmid from gfxhub */ |
620f774f | 3378 | r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
1e9ef26f CZ |
3379 | if (r) |
3380 | return r; | |
3381 | break; | |
cfbcacf4 | 3382 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
620f774f | 3383 | amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
3384 | break; |
3385 | default: | |
3386 | return -EINVAL; | |
3387 | } | |
3388 | ||
3389 | return 0; | |
3390 | } | |
2aa37bf5 AG |
3391 | |
3392 | /** | |
3393 | * amdgpu_vm_get_task_info - Extracts task info for a PASID. | |
3394 | * | |
989edc69 | 3395 | * @adev: drm device pointer |
2aa37bf5 AG |
3396 | * @pasid: PASID identifier for VM |
3397 | * @task_info: task_info to fill. | |
3398 | */ | |
3399 | void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid, | |
3400 | struct amdgpu_task_info *task_info) | |
3401 | { | |
3402 | struct amdgpu_vm *vm; | |
3403 | ||
3404 | spin_lock(&adev->vm_manager.pasid_lock); | |
3405 | ||
3406 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3407 | if (vm) | |
3408 | *task_info = vm->task_info; | |
3409 | ||
3410 | spin_unlock(&adev->vm_manager.pasid_lock); | |
3411 | } | |
3412 | ||
3413 | /** | |
3414 | * amdgpu_vm_set_task_info - Sets VMs task info. | |
3415 | * | |
3416 | * @vm: vm for which to set the info | |
3417 | */ | |
3418 | void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) | |
3419 | { | |
3420 | if (!vm->task_info.pid) { | |
3421 | vm->task_info.pid = current->pid; | |
3422 | get_task_comm(vm->task_info.task_name, current); | |
3423 | ||
3424 | if (current->group_leader->mm == current->mm) { | |
3425 | vm->task_info.tgid = current->group_leader->pid; | |
3426 | get_task_comm(vm->task_info.process_name, current->group_leader); | |
3427 | } | |
3428 | } | |
3429 | } | |
240cd9a6 OZ |
3430 | |
3431 | /** | |
3432 | * amdgpu_vm_add_fault - Add a page fault record to fault hash table | |
3433 | * | |
3434 | * @fault_hash: fault hash table | |
3435 | * @key: 64-bit encoding of PASID and address | |
3436 | * | |
3437 | * This should be called when a retry page fault interrupt is | |
3438 | * received. If this is a new page fault, it will be added to a hash | |
3439 | * table. The return value indicates whether this is a new fault, or | |
3440 | * a fault that was already known and is already being handled. | |
3441 | * | |
3442 | * If there are too many pending page faults, this will fail. Retry | |
3443 | * interrupts should be ignored in this case until there is enough | |
3444 | * free space. | |
3445 | * | |
3446 | * Returns 0 if the fault was added, 1 if the fault was already known, | |
3447 | * -ENOSPC if there are too many pending faults. | |
3448 | */ | |
3449 | int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key) | |
3450 | { | |
3451 | unsigned long flags; | |
3452 | int r = -ENOSPC; | |
3453 | ||
3454 | if (WARN_ON_ONCE(!fault_hash)) | |
3455 | /* Should be allocated in amdgpu_vm_init | |
3456 | */ | |
3457 | return r; | |
3458 | ||
3459 | spin_lock_irqsave(&fault_hash->lock, flags); | |
3460 | ||
3461 | /* Only let the hash table fill up to 50% for best performance */ | |
3462 | if (fault_hash->count >= (1 << (AMDGPU_PAGEFAULT_HASH_BITS-1))) | |
3463 | goto unlock_out; | |
3464 | ||
3465 | r = chash_table_copy_in(&fault_hash->hash, key, NULL); | |
3466 | if (!r) | |
3467 | fault_hash->count++; | |
3468 | ||
3469 | /* chash_table_copy_in should never fail unless we're losing count */ | |
3470 | WARN_ON_ONCE(r < 0); | |
3471 | ||
3472 | unlock_out: | |
3473 | spin_unlock_irqrestore(&fault_hash->lock, flags); | |
3474 | return r; | |
3475 | } | |
3476 | ||
3477 | /** | |
3478 | * amdgpu_vm_clear_fault - Remove a page fault record | |
3479 | * | |
3480 | * @fault_hash: fault hash table | |
3481 | * @key: 64-bit encoding of PASID and address | |
3482 | * | |
3483 | * This should be called when a page fault has been handled. Any | |
3484 | * future interrupt with this key will be processed as a new | |
3485 | * page fault. | |
3486 | */ | |
3487 | void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key) | |
3488 | { | |
3489 | unsigned long flags; | |
3490 | int r; | |
3491 | ||
3492 | if (!fault_hash) | |
3493 | return; | |
3494 | ||
3495 | spin_lock_irqsave(&fault_hash->lock, flags); | |
3496 | ||
3497 | r = chash_table_remove(&fault_hash->hash, key, NULL); | |
3498 | if (!WARN_ON_ONCE(r < 0)) { | |
3499 | fault_hash->count--; | |
3500 | WARN_ON_ONCE(fault_hash->count < 0); | |
3501 | } | |
3502 | ||
3503 | spin_unlock_irqrestore(&fault_hash->lock, flags); | |
3504 | } |