]>
Commit | Line | Data |
---|---|---|
d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
02208441 | 30 | #include <linux/idr.h> |
d38ceaf9 AD |
31 | #include <drm/drmP.h> |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "amdgpu_trace.h" | |
ede0dd86 | 35 | #include "amdgpu_amdkfd.h" |
c8c5e569 | 36 | #include "amdgpu_gmc.h" |
df399b06 | 37 | #include "amdgpu_xgmi.h" |
d38ceaf9 | 38 | |
7fc48e59 AG |
39 | /** |
40 | * DOC: GPUVM | |
41 | * | |
d38ceaf9 AD |
42 | * GPUVM is similar to the legacy gart on older asics, however |
43 | * rather than there being a single global gart table | |
44 | * for the entire GPU, there are multiple VM page tables active | |
45 | * at any given time. The VM page tables can contain a mix | |
46 | * vram pages and system memory pages and system memory pages | |
47 | * can be mapped as snooped (cached system pages) or unsnooped | |
48 | * (uncached system pages). | |
49 | * Each VM has an ID associated with it and there is a page table | |
50 | * associated with each VMID. When execting a command buffer, | |
51 | * the kernel tells the the ring what VMID to use for that command | |
52 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
53 | * The userspace drivers maintain their own address space and the kernel | |
54 | * sets up their pages tables accordingly when they submit their | |
55 | * command buffers and a VMID is assigned. | |
56 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
57 | * SI supports 16. | |
58 | */ | |
59 | ||
a9f87f64 CK |
60 | #define START(node) ((node)->start) |
61 | #define LAST(node) ((node)->last) | |
62 | ||
63 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
64 | START, LAST, static, amdgpu_vm_it) | |
65 | ||
66 | #undef START | |
67 | #undef LAST | |
68 | ||
7fc48e59 AG |
69 | /** |
70 | * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback | |
71 | */ | |
284710fa | 72 | struct amdgpu_prt_cb { |
7fc48e59 AG |
73 | |
74 | /** | |
75 | * @adev: amdgpu device | |
76 | */ | |
284710fa | 77 | struct amdgpu_device *adev; |
7fc48e59 AG |
78 | |
79 | /** | |
80 | * @cb: callback | |
81 | */ | |
284710fa CK |
82 | struct dma_fence_cb cb; |
83 | }; | |
84 | ||
50783147 CK |
85 | /** |
86 | * amdgpu_vm_level_shift - return the addr shift for each level | |
87 | * | |
88 | * @adev: amdgpu_device pointer | |
7fc48e59 | 89 | * @level: VMPT level |
50783147 | 90 | * |
7fc48e59 AG |
91 | * Returns: |
92 | * The number of bits the pfn needs to be right shifted for a level. | |
50783147 CK |
93 | */ |
94 | static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, | |
95 | unsigned level) | |
96 | { | |
196f7489 CZ |
97 | unsigned shift = 0xff; |
98 | ||
99 | switch (level) { | |
100 | case AMDGPU_VM_PDB2: | |
101 | case AMDGPU_VM_PDB1: | |
102 | case AMDGPU_VM_PDB0: | |
103 | shift = 9 * (AMDGPU_VM_PDB0 - level) + | |
50783147 | 104 | adev->vm_manager.block_size; |
196f7489 CZ |
105 | break; |
106 | case AMDGPU_VM_PTB: | |
107 | shift = 0; | |
108 | break; | |
109 | default: | |
110 | dev_err(adev->dev, "the level%d isn't supported.\n", level); | |
111 | } | |
112 | ||
113 | return shift; | |
50783147 CK |
114 | } |
115 | ||
d38ceaf9 | 116 | /** |
72a7ec5c | 117 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
118 | * |
119 | * @adev: amdgpu_device pointer | |
7fc48e59 | 120 | * @level: VMPT level |
d38ceaf9 | 121 | * |
7fc48e59 AG |
122 | * Returns: |
123 | * The number of entries in a page directory or page table. | |
d38ceaf9 | 124 | */ |
72a7ec5c CK |
125 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
126 | unsigned level) | |
d38ceaf9 | 127 | { |
196f7489 CZ |
128 | unsigned shift = amdgpu_vm_level_shift(adev, |
129 | adev->vm_manager.root_level); | |
0410c5e5 | 130 | |
196f7489 | 131 | if (level == adev->vm_manager.root_level) |
72a7ec5c | 132 | /* For the root directory */ |
9ce2b991 | 133 | return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift; |
196f7489 | 134 | else if (level != AMDGPU_VM_PTB) |
0410c5e5 CK |
135 | /* Everything in between */ |
136 | return 512; | |
137 | else | |
72a7ec5c | 138 | /* For the page tables on the leaves */ |
36b32a68 | 139 | return AMDGPU_VM_PTE_COUNT(adev); |
d38ceaf9 AD |
140 | } |
141 | ||
780637cb CK |
142 | /** |
143 | * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD | |
144 | * | |
145 | * @adev: amdgpu_device pointer | |
146 | * | |
147 | * Returns: | |
148 | * The number of entries in the root page directory which needs the ATS setting. | |
149 | */ | |
150 | static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev) | |
151 | { | |
152 | unsigned shift; | |
153 | ||
154 | shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level); | |
155 | return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT); | |
156 | } | |
157 | ||
cb90b97b CK |
158 | /** |
159 | * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT | |
160 | * | |
161 | * @adev: amdgpu_device pointer | |
162 | * @level: VMPT level | |
163 | * | |
164 | * Returns: | |
165 | * The mask to extract the entry number of a PD/PT from an address. | |
166 | */ | |
167 | static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev, | |
168 | unsigned int level) | |
169 | { | |
170 | if (level <= adev->vm_manager.root_level) | |
171 | return 0xffffffff; | |
172 | else if (level != AMDGPU_VM_PTB) | |
173 | return 0x1ff; | |
174 | else | |
175 | return AMDGPU_VM_PTE_COUNT(adev) - 1; | |
176 | } | |
177 | ||
d38ceaf9 | 178 | /** |
72a7ec5c | 179 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
180 | * |
181 | * @adev: amdgpu_device pointer | |
7fc48e59 | 182 | * @level: VMPT level |
d38ceaf9 | 183 | * |
7fc48e59 AG |
184 | * Returns: |
185 | * The size of the BO for a page directory or page table in bytes. | |
d38ceaf9 | 186 | */ |
72a7ec5c | 187 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 188 | { |
72a7ec5c | 189 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
190 | } |
191 | ||
bcdc9fd6 CK |
192 | /** |
193 | * amdgpu_vm_bo_evicted - vm_bo is evicted | |
194 | * | |
195 | * @vm_bo: vm_bo which is evicted | |
196 | * | |
197 | * State for PDs/PTs and per VM BOs which are not at the location they should | |
198 | * be. | |
199 | */ | |
200 | static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) | |
201 | { | |
202 | struct amdgpu_vm *vm = vm_bo->vm; | |
203 | struct amdgpu_bo *bo = vm_bo->bo; | |
204 | ||
205 | vm_bo->moved = true; | |
206 | if (bo->tbo.type == ttm_bo_type_kernel) | |
207 | list_move(&vm_bo->vm_status, &vm->evicted); | |
208 | else | |
209 | list_move_tail(&vm_bo->vm_status, &vm->evicted); | |
210 | } | |
211 | ||
212 | /** | |
213 | * amdgpu_vm_bo_relocated - vm_bo is reloacted | |
214 | * | |
215 | * @vm_bo: vm_bo which is relocated | |
216 | * | |
217 | * State for PDs/PTs which needs to update their parent PD. | |
218 | */ | |
219 | static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) | |
220 | { | |
221 | list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); | |
222 | } | |
223 | ||
224 | /** | |
225 | * amdgpu_vm_bo_moved - vm_bo is moved | |
226 | * | |
227 | * @vm_bo: vm_bo which is moved | |
228 | * | |
229 | * State for per VM BOs which are moved, but that change is not yet reflected | |
230 | * in the page tables. | |
231 | */ | |
232 | static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) | |
233 | { | |
234 | list_move(&vm_bo->vm_status, &vm_bo->vm->moved); | |
235 | } | |
236 | ||
237 | /** | |
238 | * amdgpu_vm_bo_idle - vm_bo is idle | |
239 | * | |
240 | * @vm_bo: vm_bo which is now idle | |
241 | * | |
242 | * State for PDs/PTs and per VM BOs which have gone through the state machine | |
243 | * and are now idle. | |
244 | */ | |
245 | static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) | |
246 | { | |
247 | list_move(&vm_bo->vm_status, &vm_bo->vm->idle); | |
248 | vm_bo->moved = false; | |
249 | } | |
250 | ||
251 | /** | |
252 | * amdgpu_vm_bo_invalidated - vm_bo is invalidated | |
253 | * | |
254 | * @vm_bo: vm_bo which is now invalidated | |
255 | * | |
256 | * State for normal BOs which are invalidated and that change not yet reflected | |
257 | * in the PTs. | |
258 | */ | |
259 | static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) | |
260 | { | |
261 | spin_lock(&vm_bo->vm->invalidated_lock); | |
262 | list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated); | |
263 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
264 | } | |
265 | ||
266 | /** | |
267 | * amdgpu_vm_bo_done - vm_bo is done | |
268 | * | |
269 | * @vm_bo: vm_bo which is now done | |
270 | * | |
271 | * State for normal BOs which are invalidated and that change has been updated | |
272 | * in the PTs. | |
273 | */ | |
274 | static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) | |
275 | { | |
276 | spin_lock(&vm_bo->vm->invalidated_lock); | |
277 | list_del_init(&vm_bo->vm_status); | |
278 | spin_unlock(&vm_bo->vm->invalidated_lock); | |
279 | } | |
280 | ||
c460f8a6 CK |
281 | /** |
282 | * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm | |
283 | * | |
284 | * @base: base structure for tracking BO usage in a VM | |
285 | * @vm: vm to which bo is to be added | |
286 | * @bo: amdgpu buffer object | |
287 | * | |
288 | * Initialize a bo_va_base structure and add it to the appropriate lists | |
289 | * | |
290 | */ | |
291 | static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, | |
292 | struct amdgpu_vm *vm, | |
293 | struct amdgpu_bo *bo) | |
294 | { | |
295 | base->vm = vm; | |
296 | base->bo = bo; | |
646b9025 | 297 | base->next = NULL; |
c460f8a6 CK |
298 | INIT_LIST_HEAD(&base->vm_status); |
299 | ||
300 | if (!bo) | |
301 | return; | |
646b9025 CK |
302 | base->next = bo->vm_bo; |
303 | bo->vm_bo = base; | |
c460f8a6 CK |
304 | |
305 | if (bo->tbo.resv != vm->root.base.bo->tbo.resv) | |
306 | return; | |
307 | ||
308 | vm->bulk_moveable = false; | |
fda43ab6 | 309 | if (bo->tbo.type == ttm_bo_type_kernel && bo->parent) |
bcdc9fd6 | 310 | amdgpu_vm_bo_relocated(base); |
c460f8a6 | 311 | else |
bcdc9fd6 | 312 | amdgpu_vm_bo_idle(base); |
c460f8a6 CK |
313 | |
314 | if (bo->preferred_domains & | |
315 | amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)) | |
316 | return; | |
317 | ||
318 | /* | |
319 | * we checked all the prerequisites, but it looks like this per vm bo | |
320 | * is currently evicted. add the bo to the evicted list to make sure it | |
321 | * is validated on next vm use to avoid fault. | |
322 | * */ | |
bcdc9fd6 | 323 | amdgpu_vm_bo_evicted(base); |
c460f8a6 CK |
324 | } |
325 | ||
ba79fde4 CK |
326 | /** |
327 | * amdgpu_vm_pt_parent - get the parent page directory | |
328 | * | |
329 | * @pt: child page table | |
330 | * | |
331 | * Helper to get the parent entry for the child page table. NULL if we are at | |
332 | * the root page directory. | |
333 | */ | |
334 | static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt) | |
335 | { | |
336 | struct amdgpu_bo *parent = pt->base.bo->parent; | |
337 | ||
338 | if (!parent) | |
339 | return NULL; | |
340 | ||
646b9025 | 341 | return container_of(parent->vm_bo, struct amdgpu_vm_pt, base); |
ba79fde4 CK |
342 | } |
343 | ||
73633e32 CK |
344 | /** |
345 | * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt | |
346 | */ | |
347 | struct amdgpu_vm_pt_cursor { | |
348 | uint64_t pfn; | |
349 | struct amdgpu_vm_pt *parent; | |
350 | struct amdgpu_vm_pt *entry; | |
351 | unsigned level; | |
352 | }; | |
353 | ||
354 | /** | |
355 | * amdgpu_vm_pt_start - start PD/PT walk | |
356 | * | |
357 | * @adev: amdgpu_device pointer | |
358 | * @vm: amdgpu_vm structure | |
359 | * @start: start address of the walk | |
360 | * @cursor: state to initialize | |
361 | * | |
362 | * Initialize a amdgpu_vm_pt_cursor to start a walk. | |
363 | */ | |
364 | static void amdgpu_vm_pt_start(struct amdgpu_device *adev, | |
365 | struct amdgpu_vm *vm, uint64_t start, | |
366 | struct amdgpu_vm_pt_cursor *cursor) | |
367 | { | |
368 | cursor->pfn = start; | |
369 | cursor->parent = NULL; | |
370 | cursor->entry = &vm->root; | |
371 | cursor->level = adev->vm_manager.root_level; | |
372 | } | |
373 | ||
374 | /** | |
375 | * amdgpu_vm_pt_descendant - go to child node | |
376 | * | |
377 | * @adev: amdgpu_device pointer | |
378 | * @cursor: current state | |
379 | * | |
380 | * Walk to the child node of the current node. | |
381 | * Returns: | |
382 | * True if the walk was possible, false otherwise. | |
383 | */ | |
384 | static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev, | |
385 | struct amdgpu_vm_pt_cursor *cursor) | |
386 | { | |
cb90b97b | 387 | unsigned mask, shift, idx; |
73633e32 CK |
388 | |
389 | if (!cursor->entry->entries) | |
390 | return false; | |
391 | ||
392 | BUG_ON(!cursor->entry->base.bo); | |
cb90b97b | 393 | mask = amdgpu_vm_entries_mask(adev, cursor->level); |
73633e32 CK |
394 | shift = amdgpu_vm_level_shift(adev, cursor->level); |
395 | ||
396 | ++cursor->level; | |
cb90b97b | 397 | idx = (cursor->pfn >> shift) & mask; |
73633e32 CK |
398 | cursor->parent = cursor->entry; |
399 | cursor->entry = &cursor->entry->entries[idx]; | |
400 | return true; | |
401 | } | |
402 | ||
403 | /** | |
404 | * amdgpu_vm_pt_sibling - go to sibling node | |
405 | * | |
406 | * @adev: amdgpu_device pointer | |
407 | * @cursor: current state | |
408 | * | |
409 | * Walk to the sibling node of the current node. | |
410 | * Returns: | |
411 | * True if the walk was possible, false otherwise. | |
412 | */ | |
413 | static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev, | |
414 | struct amdgpu_vm_pt_cursor *cursor) | |
415 | { | |
416 | unsigned shift, num_entries; | |
417 | ||
418 | /* Root doesn't have a sibling */ | |
419 | if (!cursor->parent) | |
420 | return false; | |
421 | ||
422 | /* Go to our parents and see if we got a sibling */ | |
423 | shift = amdgpu_vm_level_shift(adev, cursor->level - 1); | |
424 | num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1); | |
425 | ||
426 | if (cursor->entry == &cursor->parent->entries[num_entries - 1]) | |
427 | return false; | |
428 | ||
429 | cursor->pfn += 1ULL << shift; | |
430 | cursor->pfn &= ~((1ULL << shift) - 1); | |
431 | ++cursor->entry; | |
432 | return true; | |
433 | } | |
434 | ||
435 | /** | |
436 | * amdgpu_vm_pt_ancestor - go to parent node | |
437 | * | |
438 | * @cursor: current state | |
439 | * | |
440 | * Walk to the parent node of the current node. | |
441 | * Returns: | |
442 | * True if the walk was possible, false otherwise. | |
443 | */ | |
444 | static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor) | |
445 | { | |
446 | if (!cursor->parent) | |
447 | return false; | |
448 | ||
449 | --cursor->level; | |
450 | cursor->entry = cursor->parent; | |
451 | cursor->parent = amdgpu_vm_pt_parent(cursor->parent); | |
452 | return true; | |
453 | } | |
454 | ||
455 | /** | |
456 | * amdgpu_vm_pt_next - get next PD/PT in hieratchy | |
457 | * | |
458 | * @adev: amdgpu_device pointer | |
459 | * @cursor: current state | |
460 | * | |
461 | * Walk the PD/PT tree to the next node. | |
462 | */ | |
463 | static void amdgpu_vm_pt_next(struct amdgpu_device *adev, | |
464 | struct amdgpu_vm_pt_cursor *cursor) | |
465 | { | |
466 | /* First try a newborn child */ | |
467 | if (amdgpu_vm_pt_descendant(adev, cursor)) | |
468 | return; | |
469 | ||
470 | /* If that didn't worked try to find a sibling */ | |
471 | while (!amdgpu_vm_pt_sibling(adev, cursor)) { | |
472 | /* No sibling, go to our parents and grandparents */ | |
473 | if (!amdgpu_vm_pt_ancestor(cursor)) { | |
474 | cursor->pfn = ~0ll; | |
475 | return; | |
476 | } | |
477 | } | |
478 | } | |
479 | ||
480 | /** | |
73633e32 | 481 | * amdgpu_vm_pt_first_dfs - start a deep first search |
73633e32 | 482 | * |
73633e32 | 483 | * @adev: amdgpu_device structure |
73633e32 | 484 | * @vm: amdgpu_vm structure |
73633e32 CK |
485 | * @cursor: state to initialize |
486 | * | |
73633e32 | 487 | * Starts a deep first traversal of the PD/PT tree. |
73633e32 | 488 | */ |
73633e32 CK |
489 | static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev, |
490 | struct amdgpu_vm *vm, | |
e35fb064 | 491 | struct amdgpu_vm_pt_cursor *start, |
73633e32 CK |
492 | struct amdgpu_vm_pt_cursor *cursor) |
493 | { | |
e35fb064 CK |
494 | if (start) |
495 | *cursor = *start; | |
496 | else | |
497 | amdgpu_vm_pt_start(adev, vm, 0, cursor); | |
73633e32 | 498 | while (amdgpu_vm_pt_descendant(adev, cursor)); |
73633e32 CK |
499 | } |
500 | ||
501 | /** | |
e35fb064 | 502 | * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue |
73633e32 | 503 | * |
e35fb064 CK |
504 | * @start: starting point for the search |
505 | * @entry: current entry | |
73633e32 | 506 | * |
e35fb064 CK |
507 | * Returns: |
508 | * True when the search should continue, false otherwise. | |
73633e32 | 509 | */ |
e35fb064 CK |
510 | static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start, |
511 | struct amdgpu_vm_pt *entry) | |
73633e32 | 512 | { |
e35fb064 | 513 | return entry && (!start || entry != start->entry); |
73633e32 CK |
514 | } |
515 | ||
516 | /** | |
517 | * amdgpu_vm_pt_next_dfs - get the next node for a deep first search | |
518 | * | |
519 | * @adev: amdgpu_device structure | |
520 | * @cursor: current state | |
521 | * | |
522 | * Move the cursor to the next node in a deep first search. | |
523 | */ | |
524 | static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev, | |
525 | struct amdgpu_vm_pt_cursor *cursor) | |
526 | { | |
527 | if (!cursor->entry) | |
528 | return; | |
529 | ||
530 | if (!cursor->parent) | |
531 | cursor->entry = NULL; | |
532 | else if (amdgpu_vm_pt_sibling(adev, cursor)) | |
533 | while (amdgpu_vm_pt_descendant(adev, cursor)); | |
534 | else | |
535 | amdgpu_vm_pt_ancestor(cursor); | |
536 | } | |
537 | ||
538 | /** | |
539 | * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs | |
540 | */ | |
e35fb064 CK |
541 | #define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \ |
542 | for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \ | |
73633e32 | 543 | (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\ |
e35fb064 CK |
544 | amdgpu_vm_pt_continue_dfs((start), (entry)); \ |
545 | (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor))) | |
73633e32 | 546 | |
d38ceaf9 | 547 | /** |
56467ebf | 548 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
549 | * |
550 | * @vm: vm providing the BOs | |
3c0eea6c | 551 | * @validated: head of validation list |
56467ebf | 552 | * @entry: entry to add |
d38ceaf9 AD |
553 | * |
554 | * Add the page directory to the list of BOs to | |
56467ebf | 555 | * validate for command submission. |
d38ceaf9 | 556 | */ |
56467ebf CK |
557 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
558 | struct list_head *validated, | |
559 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 560 | { |
56467ebf | 561 | entry->priority = 0; |
e83dfe4d | 562 | entry->tv.bo = &vm->root.base.bo->tbo; |
07daa8a0 CK |
563 | /* One for the VM updates, one for TTM and one for the CS job */ |
564 | entry->tv.num_shared = 3; | |
2f568dbd | 565 | entry->user_pages = NULL; |
56467ebf CK |
566 | list_add(&entry->tv.head, validated); |
567 | } | |
d38ceaf9 | 568 | |
b61857b5 CZ |
569 | void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo) |
570 | { | |
571 | struct amdgpu_bo *abo; | |
572 | struct amdgpu_vm_bo_base *bo_base; | |
573 | ||
574 | if (!amdgpu_bo_is_amdgpu_bo(bo)) | |
575 | return; | |
576 | ||
577 | if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT) | |
578 | return; | |
579 | ||
580 | abo = ttm_to_amdgpu_bo(bo); | |
581 | if (!abo->parent) | |
582 | return; | |
583 | for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) { | |
584 | struct amdgpu_vm *vm = bo_base->vm; | |
585 | ||
586 | if (abo->tbo.resv == vm->root.base.bo->tbo.resv) | |
587 | vm->bulk_moveable = false; | |
588 | } | |
589 | ||
590 | } | |
f921661b HR |
591 | /** |
592 | * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU | |
593 | * | |
594 | * @adev: amdgpu device pointer | |
595 | * @vm: vm providing the BOs | |
596 | * | |
597 | * Move all BOs to the end of LRU and remember their positions to put them | |
598 | * together. | |
599 | */ | |
600 | void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, | |
601 | struct amdgpu_vm *vm) | |
602 | { | |
603 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
604 | struct amdgpu_vm_bo_base *bo_base; | |
605 | ||
a213c2c7 | 606 | #if 0 |
f921661b HR |
607 | if (vm->bulk_moveable) { |
608 | spin_lock(&glob->lru_lock); | |
609 | ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move); | |
610 | spin_unlock(&glob->lru_lock); | |
611 | return; | |
612 | } | |
a213c2c7 | 613 | #endif |
f921661b HR |
614 | |
615 | memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move)); | |
616 | ||
617 | spin_lock(&glob->lru_lock); | |
618 | list_for_each_entry(bo_base, &vm->idle, vm_status) { | |
619 | struct amdgpu_bo *bo = bo_base->bo; | |
620 | ||
621 | if (!bo->parent) | |
622 | continue; | |
623 | ||
624 | ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move); | |
625 | if (bo->shadow) | |
626 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo, | |
627 | &vm->lru_bulk_move); | |
628 | } | |
629 | spin_unlock(&glob->lru_lock); | |
630 | ||
631 | vm->bulk_moveable = true; | |
632 | } | |
633 | ||
670fecc8 | 634 | /** |
f7da30d9 | 635 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
670fecc8 | 636 | * |
5a712a87 | 637 | * @adev: amdgpu device pointer |
56467ebf | 638 | * @vm: vm providing the BOs |
670fecc8 CK |
639 | * @validate: callback to do the validation |
640 | * @param: parameter for the validation callback | |
641 | * | |
642 | * Validate the page table BOs on command submission if neccessary. | |
7fc48e59 AG |
643 | * |
644 | * Returns: | |
645 | * Validation result. | |
670fecc8 | 646 | */ |
f7da30d9 CK |
647 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
648 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
649 | void *param) | |
670fecc8 | 650 | { |
91ccdd24 CK |
651 | struct amdgpu_vm_bo_base *bo_base, *tmp; |
652 | int r = 0; | |
670fecc8 | 653 | |
39bbd331 CK |
654 | vm->bulk_moveable &= list_empty(&vm->evicted); |
655 | ||
91ccdd24 CK |
656 | list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { |
657 | struct amdgpu_bo *bo = bo_base->bo; | |
670fecc8 | 658 | |
262b9c39 CK |
659 | r = validate(param, bo); |
660 | if (r) | |
661 | break; | |
670fecc8 | 662 | |
af4c0f65 | 663 | if (bo->tbo.type != ttm_bo_type_kernel) { |
bcdc9fd6 | 664 | amdgpu_vm_bo_moved(bo_base); |
af4c0f65 | 665 | } else { |
ecf96b52 | 666 | vm->update_funcs->map_table(bo); |
fda43ab6 CK |
667 | if (bo->parent) |
668 | amdgpu_vm_bo_relocated(bo_base); | |
17cc5252 | 669 | else |
fda43ab6 | 670 | amdgpu_vm_bo_idle(bo_base); |
af4c0f65 | 671 | } |
670fecc8 CK |
672 | } |
673 | ||
91ccdd24 | 674 | return r; |
670fecc8 CK |
675 | } |
676 | ||
56467ebf | 677 | /** |
34d7be5d | 678 | * amdgpu_vm_ready - check VM is ready for updates |
56467ebf | 679 | * |
34d7be5d | 680 | * @vm: VM to check |
d38ceaf9 | 681 | * |
34d7be5d | 682 | * Check if all VM PDs/PTs are ready for updates |
7fc48e59 AG |
683 | * |
684 | * Returns: | |
685 | * True if eviction list is empty. | |
d38ceaf9 | 686 | */ |
3f3333f8 | 687 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
d38ceaf9 | 688 | { |
af4c0f65 | 689 | return list_empty(&vm->evicted); |
d711e139 CK |
690 | } |
691 | ||
13307f7e CK |
692 | /** |
693 | * amdgpu_vm_clear_bo - initially clear the PDs/PTs | |
694 | * | |
695 | * @adev: amdgpu_device pointer | |
7fc48e59 | 696 | * @vm: VM to clear BO from |
13307f7e | 697 | * @bo: BO to clear |
13307f7e CK |
698 | * |
699 | * Root PD needs to be reserved when calling this. | |
7fc48e59 AG |
700 | * |
701 | * Returns: | |
702 | * 0 on success, errno otherwise. | |
13307f7e CK |
703 | */ |
704 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
780637cb CK |
705 | struct amdgpu_vm *vm, |
706 | struct amdgpu_bo *bo) | |
13307f7e CK |
707 | { |
708 | struct ttm_operation_ctx ctx = { true, false }; | |
780637cb | 709 | unsigned level = adev->vm_manager.root_level; |
adc7e863 | 710 | struct amdgpu_vm_update_params params; |
780637cb | 711 | struct amdgpu_bo *ancestor = bo; |
4584312d | 712 | unsigned entries, ats_entries; |
4584312d | 713 | uint64_t addr; |
13307f7e CK |
714 | int r; |
715 | ||
780637cb CK |
716 | /* Figure out our place in the hierarchy */ |
717 | if (ancestor->parent) { | |
718 | ++level; | |
719 | while (ancestor->parent->parent) { | |
720 | ++level; | |
721 | ancestor = ancestor->parent; | |
722 | } | |
723 | } | |
724 | ||
4584312d | 725 | entries = amdgpu_bo_size(bo) / 8; |
780637cb CK |
726 | if (!vm->pte_support_ats) { |
727 | ats_entries = 0; | |
4584312d | 728 | |
780637cb CK |
729 | } else if (!bo->parent) { |
730 | ats_entries = amdgpu_vm_num_ats_entries(adev); | |
731 | ats_entries = min(ats_entries, entries); | |
732 | entries -= ats_entries; | |
4584312d | 733 | |
780637cb CK |
734 | } else { |
735 | struct amdgpu_vm_pt *pt; | |
736 | ||
737 | pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base); | |
738 | ats_entries = amdgpu_vm_num_ats_entries(adev); | |
739 | if ((pt - vm->root.entries) >= ats_entries) { | |
740 | ats_entries = 0; | |
4584312d CK |
741 | } else { |
742 | ats_entries = entries; | |
743 | entries = 0; | |
744 | } | |
13307f7e CK |
745 | } |
746 | ||
13307f7e CK |
747 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); |
748 | if (r) | |
83cd8397 | 749 | return r; |
13307f7e | 750 | |
83cd8397 CK |
751 | if (bo->shadow) { |
752 | r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement, | |
753 | &ctx); | |
754 | if (r) | |
755 | return r; | |
83cd8397 CK |
756 | } |
757 | ||
ecf96b52 | 758 | r = vm->update_funcs->map_table(bo); |
284dec43 CK |
759 | if (r) |
760 | return r; | |
761 | ||
adc7e863 CK |
762 | memset(¶ms, 0, sizeof(params)); |
763 | params.adev = adev; | |
764 | params.vm = vm; | |
765 | ||
766 | r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_KFD, NULL); | |
13307f7e | 767 | if (r) |
83cd8397 | 768 | return r; |
13307f7e | 769 | |
adc7e863 | 770 | addr = 0; |
4584312d | 771 | if (ats_entries) { |
5fa76a9d | 772 | uint64_t value = 0, flags; |
4584312d | 773 | |
5fa76a9d CK |
774 | flags = AMDGPU_PTE_DEFAULT_ATC; |
775 | if (level != AMDGPU_VM_PTB) { | |
776 | /* Handle leaf PDEs as PTEs */ | |
777 | flags |= AMDGPU_PDE_PTE; | |
778 | amdgpu_gmc_get_vm_pde(adev, level, &value, &flags); | |
779 | } | |
4584312d | 780 | |
adc7e863 | 781 | r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries, |
5fa76a9d | 782 | value, flags); |
adc7e863 CK |
783 | if (r) |
784 | return r; | |
13307f7e | 785 | |
4584312d CK |
786 | addr += ats_entries * 8; |
787 | } | |
788 | ||
e95b93ce | 789 | if (entries) { |
b6f3a51e CK |
790 | uint64_t value = 0, flags = 0; |
791 | ||
792 | if (adev->asic_type >= CHIP_VEGA10) { | |
793 | if (level != AMDGPU_VM_PTB) { | |
794 | /* Handle leaf PDEs as PTEs */ | |
795 | flags |= AMDGPU_PDE_PTE; | |
796 | amdgpu_gmc_get_vm_pde(adev, level, | |
797 | &value, &flags); | |
798 | } else { | |
799 | /* Workaround for fault priority problem on GMC9 */ | |
800 | flags = AMDGPU_PTE_EXECUTABLE; | |
801 | } | |
802 | } | |
e95b93ce | 803 | |
adc7e863 | 804 | r = vm->update_funcs->update(¶ms, bo, addr, 0, entries, |
b6f3a51e | 805 | value, flags); |
adc7e863 CK |
806 | if (r) |
807 | return r; | |
e95b93ce | 808 | } |
4584312d | 809 | |
adc7e863 | 810 | return vm->update_funcs->commit(¶ms, NULL); |
13307f7e CK |
811 | } |
812 | ||
e21eb261 CK |
813 | /** |
814 | * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation | |
815 | * | |
816 | * @adev: amdgpu_device pointer | |
817 | * @vm: requesting vm | |
818 | * @bp: resulting BO allocation parameters | |
819 | */ | |
820 | static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm, | |
821 | int level, struct amdgpu_bo_param *bp) | |
822 | { | |
823 | memset(bp, 0, sizeof(*bp)); | |
824 | ||
825 | bp->size = amdgpu_vm_bo_size(adev, level); | |
826 | bp->byte_align = AMDGPU_GPU_PAGE_SIZE; | |
827 | bp->domain = AMDGPU_GEM_DOMAIN_VRAM; | |
284dec43 CK |
828 | bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain); |
829 | bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
830 | AMDGPU_GEM_CREATE_CPU_GTT_USWC; | |
e21eb261 CK |
831 | if (vm->use_cpu_for_update) |
832 | bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
03e9dee1 FK |
833 | else if (!vm->root.base.bo || vm->root.base.bo->shadow) |
834 | bp->flags |= AMDGPU_GEM_CREATE_SHADOW; | |
e21eb261 CK |
835 | bp->type = ttm_bo_type_kernel; |
836 | if (vm->root.base.bo) | |
837 | bp->resv = vm->root.base.bo->tbo.resv; | |
838 | } | |
839 | ||
663e4577 | 840 | /** |
98ae7f98 | 841 | * amdgpu_vm_alloc_pts - Allocate a specific page table |
663e4577 CK |
842 | * |
843 | * @adev: amdgpu_device pointer | |
844 | * @vm: VM to allocate page tables for | |
98ae7f98 | 845 | * @cursor: Which page table to allocate |
663e4577 | 846 | * |
98ae7f98 | 847 | * Make sure a specific page table or directory is allocated. |
7fc48e59 AG |
848 | * |
849 | * Returns: | |
98ae7f98 FK |
850 | * 1 if page table needed to be allocated, 0 if page table was already |
851 | * allocated, negative errno if an error occurred. | |
663e4577 | 852 | */ |
0ce15d6f CK |
853 | static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, |
854 | struct amdgpu_vm *vm, | |
855 | struct amdgpu_vm_pt_cursor *cursor) | |
663e4577 | 856 | { |
0ce15d6f CK |
857 | struct amdgpu_vm_pt *entry = cursor->entry; |
858 | struct amdgpu_bo_param bp; | |
d72a6887 | 859 | struct amdgpu_bo *pt; |
d72a6887 | 860 | int r; |
663e4577 | 861 | |
0ce15d6f CK |
862 | if (cursor->level < AMDGPU_VM_PTB && !entry->entries) { |
863 | unsigned num_entries; | |
663e4577 | 864 | |
0ce15d6f CK |
865 | num_entries = amdgpu_vm_num_entries(adev, cursor->level); |
866 | entry->entries = kvmalloc_array(num_entries, | |
867 | sizeof(*entry->entries), | |
868 | GFP_KERNEL | __GFP_ZERO); | |
869 | if (!entry->entries) | |
870 | return -ENOMEM; | |
4584312d CK |
871 | } |
872 | ||
0ce15d6f CK |
873 | if (entry->base.bo) |
874 | return 0; | |
d72a6887 | 875 | |
0ce15d6f | 876 | amdgpu_vm_bo_param(adev, vm, cursor->level, &bp); |
d72a6887 | 877 | |
0ce15d6f CK |
878 | r = amdgpu_bo_create(adev, &bp, &pt); |
879 | if (r) | |
880 | return r; | |
d72a6887 | 881 | |
0ce15d6f CK |
882 | /* Keep a reference to the root directory to avoid |
883 | * freeing them up in the wrong order. | |
884 | */ | |
885 | pt->parent = amdgpu_bo_ref(cursor->parent->base.bo); | |
886 | amdgpu_vm_bo_base_init(&entry->base, vm, pt); | |
1e293037 | 887 | |
0ce15d6f CK |
888 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
889 | if (r) | |
890 | goto error_free_pt; | |
d72a6887 CK |
891 | |
892 | return 0; | |
893 | ||
894 | error_free_pt: | |
895 | amdgpu_bo_unref(&pt->shadow); | |
896 | amdgpu_bo_unref(&pt); | |
897 | return r; | |
663e4577 CK |
898 | } |
899 | ||
e35fb064 CK |
900 | /** |
901 | * amdgpu_vm_free_table - fre one PD/PT | |
902 | * | |
903 | * @entry: PDE to free | |
904 | */ | |
905 | static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry) | |
906 | { | |
907 | if (entry->base.bo) { | |
908 | entry->base.bo->vm_bo = NULL; | |
909 | list_del(&entry->base.vm_status); | |
910 | amdgpu_bo_unref(&entry->base.bo->shadow); | |
911 | amdgpu_bo_unref(&entry->base.bo); | |
912 | } | |
913 | kvfree(entry->entries); | |
914 | entry->entries = NULL; | |
915 | } | |
916 | ||
229a37f8 CK |
917 | /** |
918 | * amdgpu_vm_free_pts - free PD/PT levels | |
919 | * | |
920 | * @adev: amdgpu device structure | |
769f846e | 921 | * @vm: amdgpu vm structure |
e35fb064 | 922 | * @start: optional cursor where to start freeing PDs/PTs |
229a37f8 CK |
923 | * |
924 | * Free the page directory or page table level and all sub levels. | |
925 | */ | |
926 | static void amdgpu_vm_free_pts(struct amdgpu_device *adev, | |
e35fb064 CK |
927 | struct amdgpu_vm *vm, |
928 | struct amdgpu_vm_pt_cursor *start) | |
229a37f8 CK |
929 | { |
930 | struct amdgpu_vm_pt_cursor cursor; | |
931 | struct amdgpu_vm_pt *entry; | |
932 | ||
e35fb064 | 933 | vm->bulk_moveable = false; |
229a37f8 | 934 | |
e35fb064 CK |
935 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) |
936 | amdgpu_vm_free_table(entry); | |
229a37f8 | 937 | |
e35fb064 CK |
938 | if (start) |
939 | amdgpu_vm_free_table(start->entry); | |
229a37f8 CK |
940 | } |
941 | ||
e59c0205 AX |
942 | /** |
943 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
944 | * | |
945 | * @adev: amdgpu_device pointer | |
946 | */ | |
947 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 948 | { |
a1255107 | 949 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
950 | bool has_compute_vm_bug; |
951 | struct amdgpu_ring *ring; | |
952 | int i; | |
93dcc37d | 953 | |
e59c0205 | 954 | has_compute_vm_bug = false; |
93dcc37d | 955 | |
2990a1fc | 956 | ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); |
e59c0205 AX |
957 | if (ip_block) { |
958 | /* Compute has a VM bug for GFX version < 7. | |
959 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
960 | if (ip_block->version->major <= 7) | |
961 | has_compute_vm_bug = true; | |
962 | else if (ip_block->version->major == 8) | |
963 | if (adev->gfx.mec_fw_version < 673) | |
964 | has_compute_vm_bug = true; | |
965 | } | |
93dcc37d | 966 | |
e59c0205 AX |
967 | for (i = 0; i < adev->num_rings; i++) { |
968 | ring = adev->rings[i]; | |
969 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
970 | /* only compute rings */ | |
971 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 972 | else |
e59c0205 | 973 | ring->has_compute_vm_bug = false; |
93dcc37d | 974 | } |
93dcc37d AD |
975 | } |
976 | ||
7fc48e59 AG |
977 | /** |
978 | * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job. | |
979 | * | |
980 | * @ring: ring on which the job will be submitted | |
981 | * @job: job to submit | |
982 | * | |
983 | * Returns: | |
984 | * True if sync is needed. | |
985 | */ | |
b9bf33d5 CZ |
986 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
987 | struct amdgpu_job *job) | |
e60f8db5 | 988 | { |
b9bf33d5 CZ |
989 | struct amdgpu_device *adev = ring->adev; |
990 | unsigned vmhub = ring->funcs->vmhub; | |
620f774f CK |
991 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
992 | struct amdgpu_vmid *id; | |
b9bf33d5 | 993 | bool gds_switch_needed; |
e59c0205 | 994 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 | 995 | |
c4f46f22 | 996 | if (job->vmid == 0) |
b9bf33d5 | 997 | return false; |
c4f46f22 | 998 | id = &id_mgr->ids[job->vmid]; |
b9bf33d5 CZ |
999 | gds_switch_needed = ring->funcs->emit_gds_switch && ( |
1000 | id->gds_base != job->gds_base || | |
1001 | id->gds_size != job->gds_size || | |
1002 | id->gws_base != job->gws_base || | |
1003 | id->gws_size != job->gws_size || | |
1004 | id->oa_base != job->oa_base || | |
1005 | id->oa_size != job->oa_size); | |
e60f8db5 | 1006 | |
620f774f | 1007 | if (amdgpu_vmid_had_gpu_reset(adev, id)) |
b9bf33d5 | 1008 | return true; |
e60f8db5 | 1009 | |
bb37b67d | 1010 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
1011 | } |
1012 | ||
d38ceaf9 AD |
1013 | /** |
1014 | * amdgpu_vm_flush - hardware flush the vm | |
1015 | * | |
1016 | * @ring: ring to use for flush | |
00553cf8 | 1017 | * @job: related job |
7fc48e59 | 1018 | * @need_pipe_sync: is pipe sync needed |
d38ceaf9 | 1019 | * |
4ff37a83 | 1020 | * Emit a VM flush when it is necessary. |
7fc48e59 AG |
1021 | * |
1022 | * Returns: | |
1023 | * 0 on success, errno otherwise. | |
d38ceaf9 | 1024 | */ |
8fdf074f | 1025 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 1026 | { |
971fe9a9 | 1027 | struct amdgpu_device *adev = ring->adev; |
7645670d | 1028 | unsigned vmhub = ring->funcs->vmhub; |
620f774f | 1029 | struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
c4f46f22 | 1030 | struct amdgpu_vmid *id = &id_mgr->ids[job->vmid]; |
d564a06e | 1031 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
1032 | id->gds_base != job->gds_base || |
1033 | id->gds_size != job->gds_size || | |
1034 | id->gws_base != job->gws_base || | |
1035 | id->gws_size != job->gws_size || | |
1036 | id->oa_base != job->oa_base || | |
1037 | id->oa_size != job->oa_size); | |
de37e68a | 1038 | bool vm_flush_needed = job->vm_needs_flush; |
b3cd285f CK |
1039 | bool pasid_mapping_needed = id->pasid != job->pasid || |
1040 | !id->pasid_mapping || | |
1041 | !dma_fence_is_signaled(id->pasid_mapping); | |
1042 | struct dma_fence *fence = NULL; | |
c0e51931 | 1043 | unsigned patch_offset = 0; |
41d9eb2c | 1044 | int r; |
d564a06e | 1045 | |
620f774f | 1046 | if (amdgpu_vmid_had_gpu_reset(adev, id)) { |
f7d015b9 CK |
1047 | gds_switch_needed = true; |
1048 | vm_flush_needed = true; | |
b3cd285f | 1049 | pasid_mapping_needed = true; |
f7d015b9 | 1050 | } |
971fe9a9 | 1051 | |
b3cd285f | 1052 | gds_switch_needed &= !!ring->funcs->emit_gds_switch; |
d8de8260 AG |
1053 | vm_flush_needed &= !!ring->funcs->emit_vm_flush && |
1054 | job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET; | |
b3cd285f CK |
1055 | pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping && |
1056 | ring->funcs->emit_wreg; | |
1057 | ||
8fdf074f | 1058 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 1059 | return 0; |
41d9eb2c | 1060 | |
c0e51931 CK |
1061 | if (ring->funcs->init_cond_exec) |
1062 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 1063 | |
8fdf074f ML |
1064 | if (need_pipe_sync) |
1065 | amdgpu_ring_emit_pipeline_sync(ring); | |
1066 | ||
b3cd285f | 1067 | if (vm_flush_needed) { |
c4f46f22 | 1068 | trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr); |
c633c00b | 1069 | amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr); |
b3cd285f CK |
1070 | } |
1071 | ||
1072 | if (pasid_mapping_needed) | |
1073 | amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); | |
e9d672b2 | 1074 | |
b3cd285f | 1075 | if (vm_flush_needed || pasid_mapping_needed) { |
d240cd9e | 1076 | r = amdgpu_fence_emit(ring, &fence, 0); |
c0e51931 CK |
1077 | if (r) |
1078 | return r; | |
b3cd285f | 1079 | } |
e9d672b2 | 1080 | |
b3cd285f | 1081 | if (vm_flush_needed) { |
7645670d | 1082 | mutex_lock(&id_mgr->lock); |
c0e51931 | 1083 | dma_fence_put(id->last_flush); |
b3cd285f CK |
1084 | id->last_flush = dma_fence_get(fence); |
1085 | id->current_gpu_reset_count = | |
1086 | atomic_read(&adev->gpu_reset_counter); | |
7645670d | 1087 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 1088 | } |
e9d672b2 | 1089 | |
b3cd285f CK |
1090 | if (pasid_mapping_needed) { |
1091 | id->pasid = job->pasid; | |
1092 | dma_fence_put(id->pasid_mapping); | |
1093 | id->pasid_mapping = dma_fence_get(fence); | |
1094 | } | |
1095 | dma_fence_put(fence); | |
1096 | ||
7c4378f4 | 1097 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
1098 | id->gds_base = job->gds_base; |
1099 | id->gds_size = job->gds_size; | |
1100 | id->gws_base = job->gws_base; | |
1101 | id->gws_size = job->gws_size; | |
1102 | id->oa_base = job->oa_base; | |
1103 | id->oa_size = job->oa_size; | |
c4f46f22 | 1104 | amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base, |
c0e51931 CK |
1105 | job->gds_size, job->gws_base, |
1106 | job->gws_size, job->oa_base, | |
1107 | job->oa_size); | |
1108 | } | |
1109 | ||
1110 | if (ring->funcs->patch_cond_exec) | |
1111 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
1112 | ||
1113 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
1114 | if (ring->funcs->emit_switch_buffer) { | |
1115 | amdgpu_ring_emit_switch_buffer(ring); | |
1116 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 1117 | } |
41d9eb2c | 1118 | return 0; |
971fe9a9 CK |
1119 | } |
1120 | ||
d38ceaf9 AD |
1121 | /** |
1122 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
1123 | * | |
1124 | * @vm: requested vm | |
1125 | * @bo: requested buffer object | |
1126 | * | |
8843dbbb | 1127 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
1128 | * Search inside the @bos vm list for the requested vm |
1129 | * Returns the found bo_va or NULL if none is found | |
1130 | * | |
1131 | * Object has to be reserved! | |
7fc48e59 AG |
1132 | * |
1133 | * Returns: | |
1134 | * Found bo_va or NULL. | |
d38ceaf9 AD |
1135 | */ |
1136 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
1137 | struct amdgpu_bo *bo) | |
1138 | { | |
646b9025 | 1139 | struct amdgpu_vm_bo_base *base; |
d38ceaf9 | 1140 | |
646b9025 CK |
1141 | for (base = bo->vm_bo; base; base = base->next) { |
1142 | if (base->vm != vm) | |
1143 | continue; | |
1144 | ||
1145 | return container_of(base, struct amdgpu_bo_va, base); | |
d38ceaf9 AD |
1146 | } |
1147 | return NULL; | |
1148 | } | |
1149 | ||
d38ceaf9 | 1150 | /** |
b07c9d2a | 1151 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 1152 | * |
b07c9d2a | 1153 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
1154 | * @addr: the unmapped addr |
1155 | * | |
1156 | * Look up the physical address of the page that the pte resolves | |
7fc48e59 AG |
1157 | * to. |
1158 | * | |
1159 | * Returns: | |
1160 | * The pointer for the page table entry. | |
d38ceaf9 | 1161 | */ |
6dd09027 | 1162 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
1163 | { |
1164 | uint64_t result; | |
1165 | ||
de9ea7bd CK |
1166 | /* page table offset */ |
1167 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 1168 | |
de9ea7bd CK |
1169 | /* in case cpu page size != gpu page size*/ |
1170 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 1171 | |
b07c9d2a | 1172 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
1173 | |
1174 | return result; | |
1175 | } | |
1176 | ||
f8991bab | 1177 | /* |
6989f246 | 1178 | * amdgpu_vm_update_pde - update a single level in the hierarchy |
f8991bab | 1179 | * |
6989f246 | 1180 | * @param: parameters for the update |
f8991bab | 1181 | * @vm: requested vm |
6989f246 | 1182 | * @entry: entry to update |
f8991bab | 1183 | * |
6989f246 | 1184 | * Makes sure the requested entry in parent is up to date. |
f8991bab | 1185 | */ |
e6899d55 CK |
1186 | static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params, |
1187 | struct amdgpu_vm *vm, | |
e6899d55 | 1188 | struct amdgpu_vm_pt *entry) |
d38ceaf9 | 1189 | { |
fda43ab6 | 1190 | struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry); |
373ac645 | 1191 | struct amdgpu_bo *bo = parent->base.bo, *pbo; |
3de676d8 CK |
1192 | uint64_t pde, pt, flags; |
1193 | unsigned level; | |
d5fc5e82 | 1194 | |
373ac645 | 1195 | for (level = 0, pbo = bo->parent; pbo; ++level) |
3de676d8 CK |
1196 | pbo = pbo->parent; |
1197 | ||
196f7489 | 1198 | level += params->adev->vm_manager.root_level; |
24a8d289 | 1199 | amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags); |
373ac645 | 1200 | pde = (entry - parent->entries) * 8; |
e6899d55 | 1201 | return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags); |
d38ceaf9 AD |
1202 | } |
1203 | ||
92456b93 | 1204 | /* |
d4085ea9 | 1205 | * amdgpu_vm_invalidate_pds - mark all PDs as invalid |
92456b93 | 1206 | * |
7fc48e59 AG |
1207 | * @adev: amdgpu_device pointer |
1208 | * @vm: related vm | |
92456b93 CK |
1209 | * |
1210 | * Mark all PD level as invalid after an error. | |
1211 | */ | |
d4085ea9 CK |
1212 | static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev, |
1213 | struct amdgpu_vm *vm) | |
92456b93 | 1214 | { |
d4085ea9 CK |
1215 | struct amdgpu_vm_pt_cursor cursor; |
1216 | struct amdgpu_vm_pt *entry; | |
92456b93 | 1217 | |
e35fb064 | 1218 | for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry) |
d4085ea9 | 1219 | if (entry->base.bo && !entry->base.moved) |
bcdc9fd6 | 1220 | amdgpu_vm_bo_relocated(&entry->base); |
92456b93 CK |
1221 | } |
1222 | ||
194d2161 CK |
1223 | /* |
1224 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1225 | * | |
1226 | * @adev: amdgpu_device pointer | |
1227 | * @vm: requested vm | |
1228 | * | |
1229 | * Makes sure all directories are up to date. | |
7fc48e59 AG |
1230 | * |
1231 | * Returns: | |
1232 | * 0 for success, error for failure. | |
194d2161 CK |
1233 | */ |
1234 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1235 | struct amdgpu_vm *vm) | |
1236 | { | |
d1e29462 | 1237 | struct amdgpu_vm_update_params params; |
e6899d55 | 1238 | int r; |
92456b93 | 1239 | |
6989f246 CK |
1240 | if (list_empty(&vm->relocated)) |
1241 | return 0; | |
1242 | ||
6989f246 CK |
1243 | memset(¶ms, 0, sizeof(params)); |
1244 | params.adev = adev; | |
e6899d55 | 1245 | params.vm = vm; |
6989f246 | 1246 | |
e6899d55 CK |
1247 | r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_VM, NULL); |
1248 | if (r) | |
1249 | return r; | |
6989f246 | 1250 | |
ea09729c | 1251 | while (!list_empty(&vm->relocated)) { |
fda43ab6 | 1252 | struct amdgpu_vm_pt *entry; |
ea09729c | 1253 | |
ba79fde4 CK |
1254 | entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt, |
1255 | base.vm_status); | |
1256 | amdgpu_vm_bo_idle(&entry->base); | |
ea09729c | 1257 | |
fda43ab6 | 1258 | r = amdgpu_vm_update_pde(¶ms, vm, entry); |
6989f246 CK |
1259 | if (r) |
1260 | goto error; | |
68c62306 CK |
1261 | } |
1262 | ||
e6899d55 CK |
1263 | r = vm->update_funcs->commit(¶ms, &vm->last_update); |
1264 | if (r) | |
1265 | goto error; | |
6989f246 CK |
1266 | return 0; |
1267 | ||
1268 | error: | |
d4085ea9 | 1269 | amdgpu_vm_invalidate_pds(adev, vm); |
92456b93 | 1270 | return r; |
194d2161 CK |
1271 | } |
1272 | ||
cf2f0a37 | 1273 | /** |
e95b93ce | 1274 | * amdgpu_vm_update_flags - figure out flags for PTE updates |
cf2f0a37 | 1275 | * |
dfcd99f6 | 1276 | * Make sure to set the right flags for the PTEs at the desired level. |
cf2f0a37 | 1277 | */ |
d1e29462 | 1278 | static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params, |
e95b93ce CK |
1279 | struct amdgpu_bo *bo, unsigned level, |
1280 | uint64_t pe, uint64_t addr, | |
1281 | unsigned count, uint32_t incr, | |
1282 | uint64_t flags) | |
cf2f0a37 | 1283 | |
dfcd99f6 CK |
1284 | { |
1285 | if (level != AMDGPU_VM_PTB) { | |
cf2f0a37 | 1286 | flags |= AMDGPU_PDE_PTE; |
dfcd99f6 | 1287 | amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags); |
e95b93ce CK |
1288 | |
1289 | } else if (params->adev->asic_type >= CHIP_VEGA10 && | |
1290 | !(flags & AMDGPU_PTE_VALID) && | |
1291 | !(flags & AMDGPU_PTE_PRT)) { | |
1292 | ||
1293 | /* Workaround for fault priority problem on GMC9 */ | |
1294 | flags |= AMDGPU_PTE_EXECUTABLE; | |
cf2f0a37 AD |
1295 | } |
1296 | ||
c3546695 CK |
1297 | params->vm->update_funcs->update(params, bo, pe, addr, count, incr, |
1298 | flags); | |
dfcd99f6 CK |
1299 | } |
1300 | ||
1301 | /** | |
1302 | * amdgpu_vm_fragment - get fragment for PTEs | |
1303 | * | |
d1e29462 | 1304 | * @params: see amdgpu_vm_update_params definition |
dfcd99f6 CK |
1305 | * @start: first PTE to handle |
1306 | * @end: last PTE to handle | |
1307 | * @flags: hw mapping flags | |
1308 | * @frag: resulting fragment size | |
1309 | * @frag_end: end of this fragment | |
1310 | * | |
1311 | * Returns the first possible fragment for the start and end address. | |
1312 | */ | |
d1e29462 | 1313 | static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params, |
dfcd99f6 CK |
1314 | uint64_t start, uint64_t end, uint64_t flags, |
1315 | unsigned int *frag, uint64_t *frag_end) | |
1316 | { | |
1317 | /** | |
1318 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1319 | * field in the PTE. When this field is set to a non-zero value, page | |
1320 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1321 | * flags are considered valid for all PTEs within the fragment range | |
1322 | * and corresponding mappings are assumed to be physically contiguous. | |
1323 | * | |
1324 | * The L1 TLB can store a single PTE for the whole fragment, | |
1325 | * significantly increasing the space available for translation | |
1326 | * caching. This leads to large improvements in throughput when the | |
1327 | * TLB is under pressure. | |
1328 | * | |
1329 | * The L2 TLB distributes small and large fragments into two | |
1330 | * asymmetric partitions. The large fragment cache is significantly | |
1331 | * larger. Thus, we try to use large fragments wherever possible. | |
1332 | * Userspace can support this by aligning virtual base address and | |
1333 | * allocation size to the fragment size. | |
1b1d5c43 CK |
1334 | * |
1335 | * Starting with Vega10 the fragment size only controls the L1. The L2 | |
1336 | * is now directly feed with small/huge/giant pages from the walker. | |
dfcd99f6 | 1337 | */ |
1b1d5c43 CK |
1338 | unsigned max_frag; |
1339 | ||
1340 | if (params->adev->asic_type < CHIP_VEGA10) | |
1341 | max_frag = params->adev->vm_manager.fragment_size; | |
1342 | else | |
1343 | max_frag = 31; | |
dfcd99f6 CK |
1344 | |
1345 | /* system pages are non continuously */ | |
072b7a0b | 1346 | if (params->pages_addr) { |
dfcd99f6 CK |
1347 | *frag = 0; |
1348 | *frag_end = end; | |
ec5207c9 | 1349 | return; |
3cc1d3ea | 1350 | } |
cf2f0a37 | 1351 | |
dfcd99f6 CK |
1352 | /* This intentionally wraps around if no bit is set */ |
1353 | *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1); | |
1354 | if (*frag >= max_frag) { | |
1355 | *frag = max_frag; | |
1356 | *frag_end = end & ~((1ULL << max_frag) - 1); | |
1357 | } else { | |
1358 | *frag_end = start + (1 << *frag); | |
1359 | } | |
4e2cb640 CK |
1360 | } |
1361 | ||
d38ceaf9 AD |
1362 | /** |
1363 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1364 | * | |
d1e29462 | 1365 | * @params: see amdgpu_vm_update_params definition |
d38ceaf9 AD |
1366 | * @start: start of GPU address range |
1367 | * @end: end of GPU address range | |
677131a1 | 1368 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1369 | * @flags: mapping flags |
1370 | * | |
8843dbbb | 1371 | * Update the page tables in the range @start - @end. |
7fc48e59 AG |
1372 | * |
1373 | * Returns: | |
1374 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 | 1375 | */ |
d1e29462 | 1376 | static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, |
dfcd99f6 CK |
1377 | uint64_t start, uint64_t end, |
1378 | uint64_t dst, uint64_t flags) | |
d38ceaf9 | 1379 | { |
36b32a68 | 1380 | struct amdgpu_device *adev = params->adev; |
dfa70550 | 1381 | struct amdgpu_vm_pt_cursor cursor; |
dfcd99f6 CK |
1382 | uint64_t frag_start = start, frag_end; |
1383 | unsigned int frag; | |
0ce15d6f | 1384 | int r; |
dfcd99f6 CK |
1385 | |
1386 | /* figure out the initial fragment */ | |
1387 | amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end); | |
d38ceaf9 | 1388 | |
dfcd99f6 CK |
1389 | /* walk over the address space and update the PTs */ |
1390 | amdgpu_vm_pt_start(adev, params->vm, start, &cursor); | |
1391 | while (cursor.pfn < end) { | |
cb90b97b | 1392 | unsigned shift, parent_shift, mask; |
dfcd99f6 | 1393 | uint64_t incr, entry_end, pe_start; |
0ce15d6f | 1394 | struct amdgpu_bo *pt; |
cf2f0a37 | 1395 | |
0ce15d6f | 1396 | r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor); |
adc7e863 | 1397 | if (r) |
0ce15d6f CK |
1398 | return r; |
1399 | ||
1400 | pt = cursor.entry->base.bo; | |
4e2cb640 | 1401 | |
dfcd99f6 CK |
1402 | /* The root level can't be a huge page */ |
1403 | if (cursor.level == adev->vm_manager.root_level) { | |
1404 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1405 | return -ENOENT; | |
cf2f0a37 | 1406 | continue; |
dfa70550 | 1407 | } |
cf2f0a37 | 1408 | |
dfcd99f6 CK |
1409 | shift = amdgpu_vm_level_shift(adev, cursor.level); |
1410 | parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1); | |
8ce1f7e7 CK |
1411 | if (adev->asic_type < CHIP_VEGA10 && |
1412 | (flags & AMDGPU_PTE_VALID)) { | |
dfcd99f6 CK |
1413 | /* No huge page support before GMC v9 */ |
1414 | if (cursor.level != AMDGPU_VM_PTB) { | |
1415 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1416 | return -ENOENT; | |
1417 | continue; | |
1418 | } | |
1419 | } else if (frag < shift) { | |
1420 | /* We can't use this level when the fragment size is | |
1421 | * smaller than the address shift. Go to the next | |
1422 | * child entry and try again. | |
1423 | */ | |
1424 | if (!amdgpu_vm_pt_descendant(adev, &cursor)) | |
1425 | return -ENOENT; | |
1426 | continue; | |
1954db15 FK |
1427 | } else if (frag >= parent_shift && |
1428 | cursor.level - 1 != adev->vm_manager.root_level) { | |
dfcd99f6 | 1429 | /* If the fragment size is even larger than the parent |
1954db15 FK |
1430 | * shift we should go up one level and check it again |
1431 | * unless one level up is the root level. | |
dfcd99f6 CK |
1432 | */ |
1433 | if (!amdgpu_vm_pt_ancestor(&cursor)) | |
1434 | return -ENOENT; | |
1435 | continue; | |
6849d47c RH |
1436 | } |
1437 | ||
dfcd99f6 | 1438 | /* Looks good so far, calculate parameters for the update */ |
9ce2b991 | 1439 | incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift; |
cb90b97b CK |
1440 | mask = amdgpu_vm_entries_mask(adev, cursor.level); |
1441 | pe_start = ((cursor.pfn >> shift) & mask) * 8; | |
9ce2b991 | 1442 | entry_end = (uint64_t)(mask + 1) << shift; |
dfcd99f6 CK |
1443 | entry_end += cursor.pfn & ~(entry_end - 1); |
1444 | entry_end = min(entry_end, end); | |
1445 | ||
1446 | do { | |
1447 | uint64_t upd_end = min(entry_end, frag_end); | |
1448 | unsigned nptes = (upd_end - frag_start) >> shift; | |
1449 | ||
e95b93ce CK |
1450 | amdgpu_vm_update_flags(params, pt, cursor.level, |
1451 | pe_start, dst, nptes, incr, | |
1452 | flags | AMDGPU_PTE_FRAG(frag)); | |
dfcd99f6 CK |
1453 | |
1454 | pe_start += nptes * 8; | |
9ce2b991 | 1455 | dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift; |
dfcd99f6 CK |
1456 | |
1457 | frag_start = upd_end; | |
1458 | if (frag_start >= frag_end) { | |
1459 | /* figure out the next fragment */ | |
1460 | amdgpu_vm_fragment(params, frag_start, end, | |
1461 | flags, &frag, &frag_end); | |
1462 | if (frag < shift) | |
1463 | break; | |
1464 | } | |
1465 | } while (frag_start < entry_end); | |
92696dd5 | 1466 | |
c1a17777 | 1467 | if (amdgpu_vm_pt_descendant(adev, &cursor)) { |
adc7bfe5 | 1468 | /* Free all child entries */ |
c1a17777 | 1469 | while (cursor.pfn < frag_start) { |
e35fb064 | 1470 | amdgpu_vm_free_pts(adev, params->vm, &cursor); |
c1a17777 CK |
1471 | amdgpu_vm_pt_next(adev, &cursor); |
1472 | } | |
1473 | ||
1474 | } else if (frag >= shift) { | |
1475 | /* or just move on to the next on the same level. */ | |
dfcd99f6 | 1476 | amdgpu_vm_pt_next(adev, &cursor); |
c1a17777 | 1477 | } |
92696dd5 | 1478 | } |
6849d47c RH |
1479 | |
1480 | return 0; | |
d38ceaf9 AD |
1481 | } |
1482 | ||
d38ceaf9 AD |
1483 | /** |
1484 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1485 | * | |
1486 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1487 | * @exclusive: fence we need to sync to |
fa3ab3c7 | 1488 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 | 1489 | * @vm: requested vm |
a14faa65 CK |
1490 | * @start: start of mapped range |
1491 | * @last: last mapped entry | |
1492 | * @flags: flags for the entries | |
d38ceaf9 | 1493 | * @addr: addr to set the area to |
d38ceaf9 AD |
1494 | * @fence: optional resulting fence |
1495 | * | |
a14faa65 | 1496 | * Fill in the page table entries between @start and @last. |
7fc48e59 AG |
1497 | * |
1498 | * Returns: | |
1499 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1500 | */ |
1501 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1502 | struct dma_fence *exclusive, |
fa3ab3c7 | 1503 | dma_addr_t *pages_addr, |
d38ceaf9 | 1504 | struct amdgpu_vm *vm, |
a14faa65 | 1505 | uint64_t start, uint64_t last, |
6b777607 | 1506 | uint64_t flags, uint64_t addr, |
f54d1867 | 1507 | struct dma_fence **fence) |
d38ceaf9 | 1508 | { |
d1e29462 | 1509 | struct amdgpu_vm_update_params params; |
a1e08d3b | 1510 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 AD |
1511 | int r; |
1512 | ||
afef8b8f CK |
1513 | memset(¶ms, 0, sizeof(params)); |
1514 | params.adev = adev; | |
49ac8a24 | 1515 | params.vm = vm; |
072b7a0b | 1516 | params.pages_addr = pages_addr; |
afef8b8f | 1517 | |
8db588d5 | 1518 | /* sync to everything except eviction fences on unmapping */ |
a33cab7a | 1519 | if (!(flags & AMDGPU_PTE_VALID)) |
8db588d5 | 1520 | owner = AMDGPU_FENCE_OWNER_KFD; |
a33cab7a | 1521 | |
c3546695 | 1522 | r = vm->update_funcs->prepare(¶ms, owner, exclusive); |
d71518b5 | 1523 | if (r) |
d38ceaf9 | 1524 | return r; |
d71518b5 | 1525 | |
dfcd99f6 | 1526 | r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags); |
cc28c4ed | 1527 | if (r) |
c3546695 | 1528 | return r; |
d5fc5e82 | 1529 | |
c3546695 | 1530 | return vm->update_funcs->commit(¶ms, fence); |
d38ceaf9 AD |
1531 | } |
1532 | ||
a14faa65 CK |
1533 | /** |
1534 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1535 | * | |
1536 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1537 | * @exclusive: fence we need to sync to |
8358dcee | 1538 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1539 | * @vm: requested vm |
1540 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1541 | * @flags: HW flags for the mapping |
a690aa0f | 1542 | * @bo_adev: amdgpu_device pointer that bo actually been allocated |
63e0ba40 | 1543 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1544 | * @fence: optional resulting fence |
1545 | * | |
1546 | * Split the mapping into smaller chunks so that each update fits | |
1547 | * into a SDMA IB. | |
7fc48e59 AG |
1548 | * |
1549 | * Returns: | |
1550 | * 0 for success, -EINVAL for failure. | |
a14faa65 CK |
1551 | */ |
1552 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1553 | struct dma_fence *exclusive, |
8358dcee | 1554 | dma_addr_t *pages_addr, |
a14faa65 CK |
1555 | struct amdgpu_vm *vm, |
1556 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1557 | uint64_t flags, |
a690aa0f | 1558 | struct amdgpu_device *bo_adev, |
63e0ba40 | 1559 | struct drm_mm_node *nodes, |
f54d1867 | 1560 | struct dma_fence **fence) |
a14faa65 | 1561 | { |
9fc8fc70 | 1562 | unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size; |
570144c6 | 1563 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1564 | int r; |
1565 | ||
1566 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1567 | * but in case of something, we filter the flags in first place | |
1568 | */ | |
1569 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1570 | flags &= ~AMDGPU_PTE_READABLE; | |
1571 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1572 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1573 | ||
15b31c59 AX |
1574 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1575 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1576 | ||
b0fd18b0 AX |
1577 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1578 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1579 | ||
d0766e98 ZJ |
1580 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1581 | (adev->asic_type >= CHIP_VEGA10)) { | |
1582 | flags |= AMDGPU_PTE_PRT; | |
1583 | flags &= ~AMDGPU_PTE_VALID; | |
1584 | } | |
1585 | ||
a14faa65 CK |
1586 | trace_amdgpu_vm_bo_update(mapping); |
1587 | ||
63e0ba40 CK |
1588 | pfn = mapping->offset >> PAGE_SHIFT; |
1589 | if (nodes) { | |
1590 | while (pfn >= nodes->size) { | |
1591 | pfn -= nodes->size; | |
1592 | ++nodes; | |
1593 | } | |
fa3ab3c7 | 1594 | } |
a14faa65 | 1595 | |
63e0ba40 | 1596 | do { |
9fc8fc70 | 1597 | dma_addr_t *dma_addr = NULL; |
63e0ba40 CK |
1598 | uint64_t max_entries; |
1599 | uint64_t addr, last; | |
a14faa65 | 1600 | |
63e0ba40 CK |
1601 | if (nodes) { |
1602 | addr = nodes->start << PAGE_SHIFT; | |
1603 | max_entries = (nodes->size - pfn) * | |
463d2fe8 | 1604 | AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1605 | } else { |
1606 | addr = 0; | |
1607 | max_entries = S64_MAX; | |
1608 | } | |
a14faa65 | 1609 | |
63e0ba40 | 1610 | if (pages_addr) { |
9fc8fc70 CK |
1611 | uint64_t count; |
1612 | ||
38e624a1 | 1613 | for (count = 1; |
463d2fe8 | 1614 | count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
38e624a1 | 1615 | ++count) { |
9fc8fc70 CK |
1616 | uint64_t idx = pfn + count; |
1617 | ||
1618 | if (pages_addr[idx] != | |
1619 | (pages_addr[idx - 1] + PAGE_SIZE)) | |
1620 | break; | |
1621 | } | |
1622 | ||
1623 | if (count < min_linear_pages) { | |
1624 | addr = pfn << PAGE_SHIFT; | |
1625 | dma_addr = pages_addr; | |
1626 | } else { | |
1627 | addr = pages_addr[pfn]; | |
463d2fe8 | 1628 | max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
9fc8fc70 CK |
1629 | } |
1630 | ||
63e0ba40 | 1631 | } else if (flags & AMDGPU_PTE_VALID) { |
a690aa0f | 1632 | addr += bo_adev->vm_manager.vram_base_offset; |
9fc8fc70 | 1633 | addr += pfn << PAGE_SHIFT; |
63e0ba40 | 1634 | } |
63e0ba40 | 1635 | |
a9f87f64 | 1636 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
9fc8fc70 | 1637 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm, |
a14faa65 CK |
1638 | start, last, flags, addr, |
1639 | fence); | |
1640 | if (r) | |
1641 | return r; | |
1642 | ||
463d2fe8 | 1643 | pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE; |
63e0ba40 CK |
1644 | if (nodes && nodes->size == pfn) { |
1645 | pfn = 0; | |
1646 | ++nodes; | |
1647 | } | |
a14faa65 | 1648 | start = last + 1; |
63e0ba40 | 1649 | |
a9f87f64 | 1650 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1651 | |
1652 | return 0; | |
1653 | } | |
1654 | ||
d38ceaf9 AD |
1655 | /** |
1656 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1657 | * | |
1658 | * @adev: amdgpu_device pointer | |
1659 | * @bo_va: requested BO and VM object | |
99e124f4 | 1660 | * @clear: if true clear the entries |
d38ceaf9 AD |
1661 | * |
1662 | * Fill in the page table entries for @bo_va. | |
7fc48e59 AG |
1663 | * |
1664 | * Returns: | |
1665 | * 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1666 | */ |
1667 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1668 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1669 | bool clear) |
d38ceaf9 | 1670 | { |
ec681545 CK |
1671 | struct amdgpu_bo *bo = bo_va->base.bo; |
1672 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1673 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1674 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 1675 | struct ttm_mem_reg *mem; |
63e0ba40 | 1676 | struct drm_mm_node *nodes; |
4e55eb38 | 1677 | struct dma_fence *exclusive, **last_update; |
457e0fee | 1678 | uint64_t flags; |
86f7bae5 | 1679 | struct amdgpu_device *bo_adev = adev; |
d38ceaf9 AD |
1680 | int r; |
1681 | ||
7eb80427 | 1682 | if (clear || !bo) { |
99e124f4 | 1683 | mem = NULL; |
63e0ba40 | 1684 | nodes = NULL; |
99e124f4 CK |
1685 | exclusive = NULL; |
1686 | } else { | |
8358dcee CK |
1687 | struct ttm_dma_tt *ttm; |
1688 | ||
7eb80427 | 1689 | mem = &bo->tbo.mem; |
63e0ba40 CK |
1690 | nodes = mem->mm_node; |
1691 | if (mem->mem_type == TTM_PL_TT) { | |
7eb80427 | 1692 | ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm); |
8358dcee | 1693 | pages_addr = ttm->dma_address; |
9ab21462 | 1694 | } |
ec681545 | 1695 | exclusive = reservation_object_get_excl(bo->tbo.resv); |
d38ceaf9 AD |
1696 | } |
1697 | ||
a690aa0f | 1698 | if (bo) { |
ec681545 | 1699 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
a690aa0f | 1700 | bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); |
1701 | } else { | |
a5f6b5b1 | 1702 | flags = 0x0; |
a690aa0f | 1703 | } |
d38ceaf9 | 1704 | |
4e55eb38 CK |
1705 | if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)) |
1706 | last_update = &vm->last_update; | |
1707 | else | |
1708 | last_update = &bo_va->last_pt_update; | |
1709 | ||
3d7d4d3a CK |
1710 | if (!clear && bo_va->base.moved) { |
1711 | bo_va->base.moved = false; | |
7fc11959 | 1712 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1713 | |
cb7b6ec2 CK |
1714 | } else if (bo_va->cleared != clear) { |
1715 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1716 | } |
7fc11959 CK |
1717 | |
1718 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
457e0fee | 1719 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
a690aa0f | 1720 | mapping, flags, bo_adev, nodes, |
4e55eb38 | 1721 | last_update); |
d38ceaf9 AD |
1722 | if (r) |
1723 | return r; | |
1724 | } | |
1725 | ||
cb7b6ec2 CK |
1726 | if (vm->use_cpu_for_update) { |
1727 | /* Flush HDP */ | |
1728 | mb(); | |
69882565 | 1729 | amdgpu_asic_flush_hdp(adev, NULL); |
d6c10f6b CK |
1730 | } |
1731 | ||
bb475839 JZ |
1732 | /* If the BO is not in its preferred location add it back to |
1733 | * the evicted list so that it gets validated again on the | |
1734 | * next command submission. | |
1735 | */ | |
806f043f CK |
1736 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
1737 | uint32_t mem_type = bo->tbo.mem.mem_type; | |
1738 | ||
1739 | if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type))) | |
bcdc9fd6 | 1740 | amdgpu_vm_bo_evicted(&bo_va->base); |
806f043f | 1741 | else |
bcdc9fd6 | 1742 | amdgpu_vm_bo_idle(&bo_va->base); |
c12a2ee5 | 1743 | } else { |
bcdc9fd6 | 1744 | amdgpu_vm_bo_done(&bo_va->base); |
806f043f | 1745 | } |
d38ceaf9 | 1746 | |
cb7b6ec2 CK |
1747 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1748 | bo_va->cleared = clear; | |
1749 | ||
1750 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1751 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1752 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1753 | } |
1754 | ||
d38ceaf9 AD |
1755 | return 0; |
1756 | } | |
1757 | ||
284710fa CK |
1758 | /** |
1759 | * amdgpu_vm_update_prt_state - update the global PRT state | |
7fc48e59 AG |
1760 | * |
1761 | * @adev: amdgpu_device pointer | |
284710fa CK |
1762 | */ |
1763 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1764 | { | |
1765 | unsigned long flags; | |
1766 | bool enable; | |
1767 | ||
1768 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1769 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
132f34e4 | 1770 | adev->gmc.gmc_funcs->set_prt(adev, enable); |
284710fa CK |
1771 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); |
1772 | } | |
1773 | ||
451bc8eb | 1774 | /** |
4388fc2a | 1775 | * amdgpu_vm_prt_get - add a PRT user |
7fc48e59 AG |
1776 | * |
1777 | * @adev: amdgpu_device pointer | |
451bc8eb CK |
1778 | */ |
1779 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1780 | { | |
132f34e4 | 1781 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1782 | return; |
1783 | ||
451bc8eb CK |
1784 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1785 | amdgpu_vm_update_prt_state(adev); | |
1786 | } | |
1787 | ||
0b15f2fc CK |
1788 | /** |
1789 | * amdgpu_vm_prt_put - drop a PRT user | |
7fc48e59 AG |
1790 | * |
1791 | * @adev: amdgpu_device pointer | |
0b15f2fc CK |
1792 | */ |
1793 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1794 | { | |
451bc8eb | 1795 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1796 | amdgpu_vm_update_prt_state(adev); |
1797 | } | |
1798 | ||
284710fa | 1799 | /** |
451bc8eb | 1800 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
7fc48e59 AG |
1801 | * |
1802 | * @fence: fence for the callback | |
00553cf8 | 1803 | * @_cb: the callback function |
284710fa CK |
1804 | */ |
1805 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1806 | { | |
1807 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1808 | ||
0b15f2fc | 1809 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1810 | kfree(cb); |
1811 | } | |
1812 | ||
451bc8eb CK |
1813 | /** |
1814 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
7fc48e59 AG |
1815 | * |
1816 | * @adev: amdgpu_device pointer | |
1817 | * @fence: fence for the callback | |
451bc8eb CK |
1818 | */ |
1819 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1820 | struct dma_fence *fence) | |
1821 | { | |
4388fc2a | 1822 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1823 | |
132f34e4 | 1824 | if (!adev->gmc.gmc_funcs->set_prt) |
4388fc2a CK |
1825 | return; |
1826 | ||
1827 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1828 | if (!cb) { |
1829 | /* Last resort when we are OOM */ | |
1830 | if (fence) | |
1831 | dma_fence_wait(fence, false); | |
1832 | ||
486a68f5 | 1833 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1834 | } else { |
1835 | cb->adev = adev; | |
1836 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1837 | amdgpu_vm_prt_cb)) | |
1838 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1839 | } | |
1840 | } | |
1841 | ||
284710fa CK |
1842 | /** |
1843 | * amdgpu_vm_free_mapping - free a mapping | |
1844 | * | |
1845 | * @adev: amdgpu_device pointer | |
1846 | * @vm: requested vm | |
1847 | * @mapping: mapping to be freed | |
1848 | * @fence: fence of the unmap operation | |
1849 | * | |
1850 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1851 | */ | |
1852 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1853 | struct amdgpu_vm *vm, | |
1854 | struct amdgpu_bo_va_mapping *mapping, | |
1855 | struct dma_fence *fence) | |
1856 | { | |
451bc8eb CK |
1857 | if (mapping->flags & AMDGPU_PTE_PRT) |
1858 | amdgpu_vm_add_prt_cb(adev, fence); | |
1859 | kfree(mapping); | |
1860 | } | |
284710fa | 1861 | |
451bc8eb CK |
1862 | /** |
1863 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1864 | * | |
1865 | * @adev: amdgpu_device pointer | |
1866 | * @vm: requested vm | |
1867 | * | |
1868 | * Register a cleanup callback to disable PRT support after VM dies. | |
1869 | */ | |
1870 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1871 | { | |
3f3333f8 | 1872 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
451bc8eb CK |
1873 | struct dma_fence *excl, **shared; |
1874 | unsigned i, shared_count; | |
1875 | int r; | |
0b15f2fc | 1876 | |
451bc8eb CK |
1877 | r = reservation_object_get_fences_rcu(resv, &excl, |
1878 | &shared_count, &shared); | |
1879 | if (r) { | |
1880 | /* Not enough memory to grab the fence list, as last resort | |
1881 | * block for all the fences to complete. | |
1882 | */ | |
1883 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1884 | MAX_SCHEDULE_TIMEOUT); | |
1885 | return; | |
284710fa | 1886 | } |
451bc8eb CK |
1887 | |
1888 | /* Add a callback for each fence in the reservation object */ | |
1889 | amdgpu_vm_prt_get(adev); | |
1890 | amdgpu_vm_add_prt_cb(adev, excl); | |
1891 | ||
1892 | for (i = 0; i < shared_count; ++i) { | |
1893 | amdgpu_vm_prt_get(adev); | |
1894 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1895 | } | |
1896 | ||
1897 | kfree(shared); | |
284710fa CK |
1898 | } |
1899 | ||
d38ceaf9 AD |
1900 | /** |
1901 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1902 | * | |
1903 | * @adev: amdgpu_device pointer | |
1904 | * @vm: requested vm | |
f3467818 NH |
1905 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1906 | * or if an error occurred) | |
d38ceaf9 AD |
1907 | * |
1908 | * Make sure all freed BOs are cleared in the PT. | |
d38ceaf9 | 1909 | * PTs have to be reserved and mutex must be locked! |
7fc48e59 AG |
1910 | * |
1911 | * Returns: | |
1912 | * 0 for success. | |
1913 | * | |
d38ceaf9 AD |
1914 | */ |
1915 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1916 | struct amdgpu_vm *vm, |
1917 | struct dma_fence **fence) | |
d38ceaf9 AD |
1918 | { |
1919 | struct amdgpu_bo_va_mapping *mapping; | |
4584312d | 1920 | uint64_t init_pte_value = 0; |
f3467818 | 1921 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1922 | int r; |
1923 | ||
1924 | while (!list_empty(&vm->freed)) { | |
1925 | mapping = list_first_entry(&vm->freed, | |
1926 | struct amdgpu_bo_va_mapping, list); | |
1927 | list_del(&mapping->list); | |
e17841b9 | 1928 | |
ad9a5b78 CK |
1929 | if (vm->pte_support_ats && |
1930 | mapping->start < AMDGPU_GMC_HOLE_START) | |
6d16dac8 | 1931 | init_pte_value = AMDGPU_PTE_DEFAULT_ATC; |
51ac7eec | 1932 | |
570144c6 | 1933 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, |
fc6aa33d | 1934 | mapping->start, mapping->last, |
51ac7eec | 1935 | init_pte_value, 0, &f); |
f3467818 | 1936 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1937 | if (r) { |
f3467818 | 1938 | dma_fence_put(f); |
d38ceaf9 | 1939 | return r; |
284710fa | 1940 | } |
f3467818 | 1941 | } |
d38ceaf9 | 1942 | |
f3467818 NH |
1943 | if (fence && f) { |
1944 | dma_fence_put(*fence); | |
1945 | *fence = f; | |
1946 | } else { | |
1947 | dma_fence_put(f); | |
d38ceaf9 | 1948 | } |
f3467818 | 1949 | |
d38ceaf9 AD |
1950 | return 0; |
1951 | ||
1952 | } | |
1953 | ||
1954 | /** | |
73fb16e7 | 1955 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
1956 | * |
1957 | * @adev: amdgpu_device pointer | |
1958 | * @vm: requested vm | |
1959 | * | |
73fb16e7 | 1960 | * Make sure all BOs which are moved are updated in the PTs. |
7fc48e59 AG |
1961 | * |
1962 | * Returns: | |
1963 | * 0 for success. | |
d38ceaf9 | 1964 | * |
73fb16e7 | 1965 | * PTs have to be reserved! |
d38ceaf9 | 1966 | */ |
73fb16e7 | 1967 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
4e55eb38 | 1968 | struct amdgpu_vm *vm) |
d38ceaf9 | 1969 | { |
789f3317 | 1970 | struct amdgpu_bo_va *bo_va, *tmp; |
c12a2ee5 | 1971 | struct reservation_object *resv; |
73fb16e7 | 1972 | bool clear; |
789f3317 | 1973 | int r; |
d38ceaf9 | 1974 | |
c12a2ee5 CK |
1975 | list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { |
1976 | /* Per VM BOs never need to bo cleared in the page tables */ | |
1977 | r = amdgpu_vm_bo_update(adev, bo_va, false); | |
1978 | if (r) | |
1979 | return r; | |
1980 | } | |
32b41ac2 | 1981 | |
c12a2ee5 CK |
1982 | spin_lock(&vm->invalidated_lock); |
1983 | while (!list_empty(&vm->invalidated)) { | |
1984 | bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, | |
1985 | base.vm_status); | |
1986 | resv = bo_va->base.bo->tbo.resv; | |
1987 | spin_unlock(&vm->invalidated_lock); | |
ec363e0d | 1988 | |
ec363e0d | 1989 | /* Try to reserve the BO to avoid clearing its ptes */ |
c12a2ee5 | 1990 | if (!amdgpu_vm_debug && reservation_object_trylock(resv)) |
ec363e0d CK |
1991 | clear = false; |
1992 | /* Somebody else is using the BO right now */ | |
1993 | else | |
1994 | clear = true; | |
73fb16e7 CK |
1995 | |
1996 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
c12a2ee5 | 1997 | if (r) |
d38ceaf9 AD |
1998 | return r; |
1999 | ||
c12a2ee5 | 2000 | if (!clear) |
ec363e0d | 2001 | reservation_object_unlock(resv); |
c12a2ee5 | 2002 | spin_lock(&vm->invalidated_lock); |
d38ceaf9 | 2003 | } |
c12a2ee5 | 2004 | spin_unlock(&vm->invalidated_lock); |
d38ceaf9 | 2005 | |
789f3317 | 2006 | return 0; |
d38ceaf9 AD |
2007 | } |
2008 | ||
2009 | /** | |
2010 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
2011 | * | |
2012 | * @adev: amdgpu_device pointer | |
2013 | * @vm: requested vm | |
2014 | * @bo: amdgpu buffer object | |
2015 | * | |
8843dbbb | 2016 | * Add @bo into the requested vm. |
d38ceaf9 | 2017 | * Add @bo to the list of bos associated with the vm |
7fc48e59 AG |
2018 | * |
2019 | * Returns: | |
2020 | * Newly added bo_va or NULL for failure | |
d38ceaf9 AD |
2021 | * |
2022 | * Object has to be reserved! | |
2023 | */ | |
2024 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
2025 | struct amdgpu_vm *vm, | |
2026 | struct amdgpu_bo *bo) | |
2027 | { | |
2028 | struct amdgpu_bo_va *bo_va; | |
2029 | ||
2030 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2031 | if (bo_va == NULL) { | |
2032 | return NULL; | |
2033 | } | |
3f4299be | 2034 | amdgpu_vm_bo_base_init(&bo_va->base, vm, bo); |
ec681545 | 2035 | |
d38ceaf9 | 2036 | bo_va->ref_count = 1; |
7fc11959 CK |
2037 | INIT_LIST_HEAD(&bo_va->valids); |
2038 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2039 | |
b4ae4fe6 | 2040 | if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) && |
2041 | (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)) { | |
df399b06 | 2042 | bo_va->is_xgmi = true; |
2043 | mutex_lock(&adev->vm_manager.lock_pstate); | |
2044 | /* Power up XGMI if it can be potentially used */ | |
2045 | if (++adev->vm_manager.xgmi_map_counter == 1) | |
2046 | amdgpu_xgmi_set_pstate(adev, 1); | |
2047 | mutex_unlock(&adev->vm_manager.lock_pstate); | |
2048 | } | |
2049 | ||
d38ceaf9 AD |
2050 | return bo_va; |
2051 | } | |
2052 | ||
73fb16e7 CK |
2053 | |
2054 | /** | |
2055 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
2056 | * | |
2057 | * @adev: amdgpu_device pointer | |
2058 | * @bo_va: bo_va to store the address | |
2059 | * @mapping: the mapping to insert | |
2060 | * | |
2061 | * Insert a new mapping into all structures. | |
2062 | */ | |
2063 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2064 | struct amdgpu_bo_va *bo_va, | |
2065 | struct amdgpu_bo_va_mapping *mapping) | |
2066 | { | |
2067 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2068 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2069 | ||
aebc5e6f | 2070 | mapping->bo_va = bo_va; |
73fb16e7 CK |
2071 | list_add(&mapping->list, &bo_va->invalids); |
2072 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2073 | ||
2074 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2075 | amdgpu_vm_prt_get(adev); | |
2076 | ||
862b8c57 CK |
2077 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv && |
2078 | !bo_va->base.moved) { | |
862b8c57 | 2079 | list_move(&bo_va->base.vm_status, &vm->moved); |
73fb16e7 CK |
2080 | } |
2081 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2082 | } | |
2083 | ||
d38ceaf9 AD |
2084 | /** |
2085 | * amdgpu_vm_bo_map - map bo inside a vm | |
2086 | * | |
2087 | * @adev: amdgpu_device pointer | |
2088 | * @bo_va: bo_va to store the address | |
2089 | * @saddr: where to map the BO | |
2090 | * @offset: requested offset in the BO | |
00553cf8 | 2091 | * @size: BO size in bytes |
d38ceaf9 AD |
2092 | * @flags: attributes of pages (read/write/valid/etc.) |
2093 | * | |
2094 | * Add a mapping of the BO at the specefied addr into the VM. | |
7fc48e59 AG |
2095 | * |
2096 | * Returns: | |
2097 | * 0 for success, error for failure. | |
d38ceaf9 | 2098 | * |
49b02b18 | 2099 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2100 | */ |
2101 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2102 | struct amdgpu_bo_va *bo_va, | |
2103 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2104 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2105 | { |
a9f87f64 | 2106 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2107 | struct amdgpu_bo *bo = bo_va->base.bo; |
2108 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2109 | uint64_t eaddr; |
d38ceaf9 | 2110 | |
0be52de9 CK |
2111 | /* validate the parameters */ |
2112 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2113 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2114 | return -EINVAL; |
0be52de9 | 2115 | |
d38ceaf9 | 2116 | /* make sure object fit at this offset */ |
005ae95e | 2117 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2118 | if (saddr >= eaddr || |
ec681545 | 2119 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 2120 | return -EINVAL; |
d38ceaf9 | 2121 | |
d38ceaf9 AD |
2122 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2123 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2124 | ||
a9f87f64 CK |
2125 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2126 | if (tmp) { | |
d38ceaf9 AD |
2127 | /* bo and tmp overlap, invalid addr */ |
2128 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2129 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2130 | tmp->start, tmp->last + 1); |
663e4577 | 2131 | return -EINVAL; |
d38ceaf9 AD |
2132 | } |
2133 | ||
2134 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2135 | if (!mapping) |
2136 | return -ENOMEM; | |
d38ceaf9 | 2137 | |
a9f87f64 CK |
2138 | mapping->start = saddr; |
2139 | mapping->last = eaddr; | |
d38ceaf9 AD |
2140 | mapping->offset = offset; |
2141 | mapping->flags = flags; | |
2142 | ||
73fb16e7 | 2143 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
2144 | |
2145 | return 0; | |
2146 | } | |
2147 | ||
2148 | /** | |
2149 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2150 | * | |
2151 | * @adev: amdgpu_device pointer | |
2152 | * @bo_va: bo_va to store the address | |
2153 | * @saddr: where to map the BO | |
2154 | * @offset: requested offset in the BO | |
00553cf8 | 2155 | * @size: BO size in bytes |
80f95c57 CK |
2156 | * @flags: attributes of pages (read/write/valid/etc.) |
2157 | * | |
2158 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2159 | * mappings as we do so. | |
7fc48e59 AG |
2160 | * |
2161 | * Returns: | |
2162 | * 0 for success, error for failure. | |
80f95c57 CK |
2163 | * |
2164 | * Object has to be reserved and unreserved outside! | |
2165 | */ | |
2166 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2167 | struct amdgpu_bo_va *bo_va, | |
2168 | uint64_t saddr, uint64_t offset, | |
2169 | uint64_t size, uint64_t flags) | |
2170 | { | |
2171 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2172 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
2173 | uint64_t eaddr; |
2174 | int r; | |
2175 | ||
2176 | /* validate the parameters */ | |
2177 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2178 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2179 | return -EINVAL; | |
2180 | ||
2181 | /* make sure object fit at this offset */ | |
2182 | eaddr = saddr + size - 1; | |
2183 | if (saddr >= eaddr || | |
ec681545 | 2184 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
2185 | return -EINVAL; |
2186 | ||
2187 | /* Allocate all the needed memory */ | |
2188 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2189 | if (!mapping) | |
2190 | return -ENOMEM; | |
2191 | ||
ec681545 | 2192 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2193 | if (r) { |
2194 | kfree(mapping); | |
2195 | return r; | |
2196 | } | |
2197 | ||
2198 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2199 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2200 | ||
a9f87f64 CK |
2201 | mapping->start = saddr; |
2202 | mapping->last = eaddr; | |
80f95c57 CK |
2203 | mapping->offset = offset; |
2204 | mapping->flags = flags; | |
2205 | ||
73fb16e7 | 2206 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 2207 | |
d38ceaf9 | 2208 | return 0; |
d38ceaf9 AD |
2209 | } |
2210 | ||
2211 | /** | |
2212 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2213 | * | |
2214 | * @adev: amdgpu_device pointer | |
2215 | * @bo_va: bo_va to remove the address from | |
2216 | * @saddr: where to the BO is mapped | |
2217 | * | |
2218 | * Remove a mapping of the BO at the specefied addr from the VM. | |
7fc48e59 AG |
2219 | * |
2220 | * Returns: | |
2221 | * 0 for success, error for failure. | |
d38ceaf9 | 2222 | * |
49b02b18 | 2223 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2224 | */ |
2225 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2226 | struct amdgpu_bo_va *bo_va, | |
2227 | uint64_t saddr) | |
2228 | { | |
2229 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2230 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2231 | bool valid = true; |
d38ceaf9 | 2232 | |
6c7fc503 | 2233 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2234 | |
7fc11959 | 2235 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2236 | if (mapping->start == saddr) |
d38ceaf9 AD |
2237 | break; |
2238 | } | |
2239 | ||
7fc11959 CK |
2240 | if (&mapping->list == &bo_va->valids) { |
2241 | valid = false; | |
2242 | ||
2243 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2244 | if (mapping->start == saddr) |
7fc11959 CK |
2245 | break; |
2246 | } | |
2247 | ||
32b41ac2 | 2248 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2249 | return -ENOENT; |
d38ceaf9 | 2250 | } |
32b41ac2 | 2251 | |
d38ceaf9 | 2252 | list_del(&mapping->list); |
a9f87f64 | 2253 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2254 | mapping->bo_va = NULL; |
93e3e438 | 2255 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2256 | |
e17841b9 | 2257 | if (valid) |
d38ceaf9 | 2258 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2259 | else |
284710fa CK |
2260 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2261 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2262 | |
2263 | return 0; | |
2264 | } | |
2265 | ||
dc54d3d1 CK |
2266 | /** |
2267 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2268 | * | |
2269 | * @adev: amdgpu_device pointer | |
2270 | * @vm: VM structure to use | |
2271 | * @saddr: start of the range | |
2272 | * @size: size of the range | |
2273 | * | |
2274 | * Remove all mappings in a range, split them as appropriate. | |
7fc48e59 AG |
2275 | * |
2276 | * Returns: | |
2277 | * 0 for success, error for failure. | |
dc54d3d1 CK |
2278 | */ |
2279 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2280 | struct amdgpu_vm *vm, | |
2281 | uint64_t saddr, uint64_t size) | |
2282 | { | |
2283 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2284 | LIST_HEAD(removed); |
2285 | uint64_t eaddr; | |
2286 | ||
2287 | eaddr = saddr + size - 1; | |
2288 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2289 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2290 | ||
2291 | /* Allocate all the needed memory */ | |
2292 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2293 | if (!before) | |
2294 | return -ENOMEM; | |
27f6d610 | 2295 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2296 | |
2297 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2298 | if (!after) { | |
2299 | kfree(before); | |
2300 | return -ENOMEM; | |
2301 | } | |
27f6d610 | 2302 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2303 | |
2304 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2305 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2306 | while (tmp) { | |
dc54d3d1 | 2307 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2308 | if (tmp->start < saddr) { |
2309 | before->start = tmp->start; | |
2310 | before->last = saddr - 1; | |
dc54d3d1 CK |
2311 | before->offset = tmp->offset; |
2312 | before->flags = tmp->flags; | |
387f49e5 JZ |
2313 | before->bo_va = tmp->bo_va; |
2314 | list_add(&before->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2315 | } |
2316 | ||
2317 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2318 | if (tmp->last > eaddr) { |
2319 | after->start = eaddr + 1; | |
2320 | after->last = tmp->last; | |
dc54d3d1 | 2321 | after->offset = tmp->offset; |
a9f87f64 | 2322 | after->offset += after->start - tmp->start; |
dc54d3d1 | 2323 | after->flags = tmp->flags; |
387f49e5 JZ |
2324 | after->bo_va = tmp->bo_va; |
2325 | list_add(&after->list, &tmp->bo_va->invalids); | |
dc54d3d1 CK |
2326 | } |
2327 | ||
2328 | list_del(&tmp->list); | |
2329 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2330 | |
2331 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2332 | } |
2333 | ||
2334 | /* And free them up */ | |
2335 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2336 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2337 | list_del(&tmp->list); |
2338 | ||
a9f87f64 CK |
2339 | if (tmp->start < saddr) |
2340 | tmp->start = saddr; | |
2341 | if (tmp->last > eaddr) | |
2342 | tmp->last = eaddr; | |
dc54d3d1 | 2343 | |
aebc5e6f | 2344 | tmp->bo_va = NULL; |
dc54d3d1 CK |
2345 | list_add(&tmp->list, &vm->freed); |
2346 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2347 | } | |
2348 | ||
27f6d610 JZ |
2349 | /* Insert partial mapping before the range */ |
2350 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2351 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2352 | if (before->flags & AMDGPU_PTE_PRT) |
2353 | amdgpu_vm_prt_get(adev); | |
2354 | } else { | |
2355 | kfree(before); | |
2356 | } | |
2357 | ||
2358 | /* Insert partial mapping after the range */ | |
27f6d610 | 2359 | if (!list_empty(&after->list)) { |
a9f87f64 | 2360 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2361 | if (after->flags & AMDGPU_PTE_PRT) |
2362 | amdgpu_vm_prt_get(adev); | |
2363 | } else { | |
2364 | kfree(after); | |
2365 | } | |
2366 | ||
2367 | return 0; | |
2368 | } | |
2369 | ||
aebc5e6f CK |
2370 | /** |
2371 | * amdgpu_vm_bo_lookup_mapping - find mapping by address | |
2372 | * | |
2373 | * @vm: the requested VM | |
00553cf8 | 2374 | * @addr: the address |
aebc5e6f CK |
2375 | * |
2376 | * Find a mapping by it's address. | |
7fc48e59 AG |
2377 | * |
2378 | * Returns: | |
2379 | * The amdgpu_bo_va_mapping matching for addr or NULL | |
2380 | * | |
aebc5e6f CK |
2381 | */ |
2382 | struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, | |
2383 | uint64_t addr) | |
2384 | { | |
2385 | return amdgpu_vm_it_iter_first(&vm->va, addr, addr); | |
2386 | } | |
2387 | ||
8ab19ea6 CK |
2388 | /** |
2389 | * amdgpu_vm_bo_trace_cs - trace all reserved mappings | |
2390 | * | |
2391 | * @vm: the requested vm | |
2392 | * @ticket: CS ticket | |
2393 | * | |
2394 | * Trace all mappings of BOs reserved during a command submission. | |
2395 | */ | |
2396 | void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) | |
2397 | { | |
2398 | struct amdgpu_bo_va_mapping *mapping; | |
2399 | ||
2400 | if (!trace_amdgpu_vm_bo_cs_enabled()) | |
2401 | return; | |
2402 | ||
2403 | for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping; | |
2404 | mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) { | |
2405 | if (mapping->bo_va && mapping->bo_va->base.bo) { | |
2406 | struct amdgpu_bo *bo; | |
2407 | ||
2408 | bo = mapping->bo_va->base.bo; | |
2409 | if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket) | |
2410 | continue; | |
2411 | } | |
2412 | ||
2413 | trace_amdgpu_vm_bo_cs(mapping); | |
2414 | } | |
2415 | } | |
2416 | ||
d38ceaf9 AD |
2417 | /** |
2418 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2419 | * | |
2420 | * @adev: amdgpu_device pointer | |
2421 | * @bo_va: requested bo_va | |
2422 | * | |
8843dbbb | 2423 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2424 | * |
2425 | * Object have to be reserved! | |
2426 | */ | |
2427 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2428 | struct amdgpu_bo_va *bo_va) | |
2429 | { | |
2430 | struct amdgpu_bo_va_mapping *mapping, *next; | |
fbbf794c | 2431 | struct amdgpu_bo *bo = bo_va->base.bo; |
ec681545 | 2432 | struct amdgpu_vm *vm = bo_va->base.vm; |
646b9025 | 2433 | struct amdgpu_vm_bo_base **base; |
d38ceaf9 | 2434 | |
646b9025 CK |
2435 | if (bo) { |
2436 | if (bo->tbo.resv == vm->root.base.bo->tbo.resv) | |
2437 | vm->bulk_moveable = false; | |
fbbf794c | 2438 | |
646b9025 CK |
2439 | for (base = &bo_va->base.bo->vm_bo; *base; |
2440 | base = &(*base)->next) { | |
2441 | if (*base != &bo_va->base) | |
2442 | continue; | |
2443 | ||
2444 | *base = bo_va->base.next; | |
2445 | break; | |
2446 | } | |
2447 | } | |
d38ceaf9 | 2448 | |
c12a2ee5 | 2449 | spin_lock(&vm->invalidated_lock); |
ec681545 | 2450 | list_del(&bo_va->base.vm_status); |
c12a2ee5 | 2451 | spin_unlock(&vm->invalidated_lock); |
d38ceaf9 | 2452 | |
7fc11959 | 2453 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2454 | list_del(&mapping->list); |
a9f87f64 | 2455 | amdgpu_vm_it_remove(mapping, &vm->va); |
aebc5e6f | 2456 | mapping->bo_va = NULL; |
93e3e438 | 2457 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2458 | list_add(&mapping->list, &vm->freed); |
2459 | } | |
2460 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2461 | list_del(&mapping->list); | |
a9f87f64 | 2462 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2463 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2464 | bo_va->last_pt_update); | |
d38ceaf9 | 2465 | } |
32b41ac2 | 2466 | |
f54d1867 | 2467 | dma_fence_put(bo_va->last_pt_update); |
df399b06 | 2468 | |
2469 | if (bo && bo_va->is_xgmi) { | |
2470 | mutex_lock(&adev->vm_manager.lock_pstate); | |
2471 | if (--adev->vm_manager.xgmi_map_counter == 0) | |
2472 | amdgpu_xgmi_set_pstate(adev, 0); | |
2473 | mutex_unlock(&adev->vm_manager.lock_pstate); | |
2474 | } | |
2475 | ||
d38ceaf9 | 2476 | kfree(bo_va); |
d38ceaf9 AD |
2477 | } |
2478 | ||
2479 | /** | |
2480 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2481 | * | |
2482 | * @adev: amdgpu_device pointer | |
d38ceaf9 | 2483 | * @bo: amdgpu buffer object |
00553cf8 | 2484 | * @evicted: is the BO evicted |
d38ceaf9 | 2485 | * |
8843dbbb | 2486 | * Mark @bo as invalid. |
d38ceaf9 AD |
2487 | */ |
2488 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2489 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2490 | { |
ec681545 CK |
2491 | struct amdgpu_vm_bo_base *bo_base; |
2492 | ||
4bebccee CZ |
2493 | /* shadow bo doesn't have bo base, its validation needs its parent */ |
2494 | if (bo->parent && bo->parent->shadow == bo) | |
2495 | bo = bo->parent; | |
2496 | ||
646b9025 | 2497 | for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { |
3f3333f8 CK |
2498 | struct amdgpu_vm *vm = bo_base->vm; |
2499 | ||
3f3333f8 | 2500 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
bcdc9fd6 | 2501 | amdgpu_vm_bo_evicted(bo_base); |
3f3333f8 CK |
2502 | continue; |
2503 | } | |
2504 | ||
bcdc9fd6 | 2505 | if (bo_base->moved) |
3f3333f8 | 2506 | continue; |
bcdc9fd6 | 2507 | bo_base->moved = true; |
3f3333f8 | 2508 | |
bcdc9fd6 CK |
2509 | if (bo->tbo.type == ttm_bo_type_kernel) |
2510 | amdgpu_vm_bo_relocated(bo_base); | |
2511 | else if (bo->tbo.resv == vm->root.base.bo->tbo.resv) | |
2512 | amdgpu_vm_bo_moved(bo_base); | |
2513 | else | |
2514 | amdgpu_vm_bo_invalidated(bo_base); | |
d38ceaf9 AD |
2515 | } |
2516 | } | |
2517 | ||
7fc48e59 AG |
2518 | /** |
2519 | * amdgpu_vm_get_block_size - calculate VM page table size as power of two | |
2520 | * | |
2521 | * @vm_size: VM size | |
2522 | * | |
2523 | * Returns: | |
2524 | * VM page table as power of two | |
2525 | */ | |
bab4fee7 JZ |
2526 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2527 | { | |
2528 | /* Total bits covered by PD + PTs */ | |
2529 | unsigned bits = ilog2(vm_size) + 18; | |
2530 | ||
2531 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2532 | Above that split equal between PD and PTs */ | |
2533 | if (vm_size <= 8) | |
2534 | return (bits - 9); | |
2535 | else | |
2536 | return ((bits + 3) / 2); | |
2537 | } | |
2538 | ||
d07f14be RH |
2539 | /** |
2540 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2541 | * |
2542 | * @adev: amdgpu_device pointer | |
43370c4c | 2543 | * @min_vm_size: the minimum vm size in GB if it's set auto |
00553cf8 AG |
2544 | * @fragment_size_default: Default PTE fragment size |
2545 | * @max_level: max VMPT level | |
2546 | * @max_bits: max address space size in bits | |
2547 | * | |
bab4fee7 | 2548 | */ |
43370c4c | 2549 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, |
f3368128 CK |
2550 | uint32_t fragment_size_default, unsigned max_level, |
2551 | unsigned max_bits) | |
bab4fee7 | 2552 | { |
43370c4c FK |
2553 | unsigned int max_size = 1 << (max_bits - 30); |
2554 | unsigned int vm_size; | |
36539dce CK |
2555 | uint64_t tmp; |
2556 | ||
2557 | /* adjust vm size first */ | |
f3368128 | 2558 | if (amdgpu_vm_size != -1) { |
fdd5faaa | 2559 | vm_size = amdgpu_vm_size; |
f3368128 CK |
2560 | if (vm_size > max_size) { |
2561 | dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", | |
2562 | amdgpu_vm_size, max_size); | |
2563 | vm_size = max_size; | |
2564 | } | |
43370c4c FK |
2565 | } else { |
2566 | struct sysinfo si; | |
2567 | unsigned int phys_ram_gb; | |
2568 | ||
2569 | /* Optimal VM size depends on the amount of physical | |
2570 | * RAM available. Underlying requirements and | |
2571 | * assumptions: | |
2572 | * | |
2573 | * - Need to map system memory and VRAM from all GPUs | |
2574 | * - VRAM from other GPUs not known here | |
2575 | * - Assume VRAM <= system memory | |
2576 | * - On GFX8 and older, VM space can be segmented for | |
2577 | * different MTYPEs | |
2578 | * - Need to allow room for fragmentation, guard pages etc. | |
2579 | * | |
2580 | * This adds up to a rough guess of system memory x3. | |
2581 | * Round up to power of two to maximize the available | |
2582 | * VM size with the given page table size. | |
2583 | */ | |
2584 | si_meminfo(&si); | |
2585 | phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit + | |
2586 | (1 << 30) - 1) >> 30; | |
2587 | vm_size = roundup_pow_of_two( | |
2588 | min(max(phys_ram_gb * 3, min_vm_size), max_size)); | |
f3368128 | 2589 | } |
fdd5faaa CK |
2590 | |
2591 | adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; | |
36539dce CK |
2592 | |
2593 | tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); | |
97489129 CK |
2594 | if (amdgpu_vm_block_size != -1) |
2595 | tmp >>= amdgpu_vm_block_size - 9; | |
36539dce CK |
2596 | tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; |
2597 | adev->vm_manager.num_level = min(max_level, (unsigned)tmp); | |
196f7489 CZ |
2598 | switch (adev->vm_manager.num_level) { |
2599 | case 3: | |
2600 | adev->vm_manager.root_level = AMDGPU_VM_PDB2; | |
2601 | break; | |
2602 | case 2: | |
2603 | adev->vm_manager.root_level = AMDGPU_VM_PDB1; | |
2604 | break; | |
2605 | case 1: | |
2606 | adev->vm_manager.root_level = AMDGPU_VM_PDB0; | |
2607 | break; | |
2608 | default: | |
2609 | dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n"); | |
2610 | } | |
b38f41eb | 2611 | /* block size depends on vm size and hw setup*/ |
97489129 | 2612 | if (amdgpu_vm_block_size != -1) |
bab4fee7 | 2613 | adev->vm_manager.block_size = |
97489129 CK |
2614 | min((unsigned)amdgpu_vm_block_size, max_bits |
2615 | - AMDGPU_GPU_PAGE_SHIFT | |
2616 | - 9 * adev->vm_manager.num_level); | |
2617 | else if (adev->vm_manager.num_level > 1) | |
2618 | adev->vm_manager.block_size = 9; | |
bab4fee7 | 2619 | else |
97489129 | 2620 | adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); |
bab4fee7 | 2621 | |
b38f41eb CK |
2622 | if (amdgpu_vm_fragment_size == -1) |
2623 | adev->vm_manager.fragment_size = fragment_size_default; | |
2624 | else | |
2625 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
d07f14be | 2626 | |
36539dce CK |
2627 | DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", |
2628 | vm_size, adev->vm_manager.num_level + 1, | |
2629 | adev->vm_manager.block_size, | |
fdd5faaa | 2630 | adev->vm_manager.fragment_size); |
bab4fee7 JZ |
2631 | } |
2632 | ||
56753e73 CK |
2633 | /** |
2634 | * amdgpu_vm_wait_idle - wait for the VM to become idle | |
2635 | * | |
2636 | * @vm: VM object to wait for | |
2637 | * @timeout: timeout to wait for VM to become idle | |
2638 | */ | |
2639 | long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout) | |
240cd9a6 | 2640 | { |
56753e73 CK |
2641 | return reservation_object_wait_timeout_rcu(vm->root.base.bo->tbo.resv, |
2642 | true, true, timeout); | |
240cd9a6 OZ |
2643 | } |
2644 | ||
d38ceaf9 AD |
2645 | /** |
2646 | * amdgpu_vm_init - initialize a vm instance | |
2647 | * | |
2648 | * @adev: amdgpu_device pointer | |
2649 | * @vm: requested vm | |
9a4b7d4c | 2650 | * @vm_context: Indicates if it GFX or Compute context |
00553cf8 | 2651 | * @pasid: Process address space identifier |
d38ceaf9 | 2652 | * |
8843dbbb | 2653 | * Init @vm fields. |
7fc48e59 AG |
2654 | * |
2655 | * Returns: | |
2656 | * 0 for success, error for failure. | |
d38ceaf9 | 2657 | */ |
9a4b7d4c | 2658 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
02208441 | 2659 | int vm_context, unsigned int pasid) |
d38ceaf9 | 2660 | { |
3216c6b7 | 2661 | struct amdgpu_bo_param bp; |
3f4299be | 2662 | struct amdgpu_bo *root; |
36bbf3bf | 2663 | int r, i; |
d38ceaf9 | 2664 | |
f808c13f | 2665 | vm->va = RB_ROOT_CACHED; |
36bbf3bf CZ |
2666 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2667 | vm->reserved_vmid[i] = NULL; | |
3f3333f8 | 2668 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2669 | INIT_LIST_HEAD(&vm->relocated); |
27c7b9ae | 2670 | INIT_LIST_HEAD(&vm->moved); |
806f043f | 2671 | INIT_LIST_HEAD(&vm->idle); |
c12a2ee5 CK |
2672 | INIT_LIST_HEAD(&vm->invalidated); |
2673 | spin_lock_init(&vm->invalidated_lock); | |
d38ceaf9 | 2674 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2675 | |
2bd9ccfa | 2676 | /* create scheduler entity for page table updates */ |
3798e9a6 CK |
2677 | r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs, |
2678 | adev->vm_manager.vm_pte_num_rqs, NULL); | |
2bd9ccfa | 2679 | if (r) |
f566ceb1 | 2680 | return r; |
2bd9ccfa | 2681 | |
51ac7eec YZ |
2682 | vm->pte_support_ats = false; |
2683 | ||
2684 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2685 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2686 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec | 2687 | |
741deade | 2688 | if (adev->asic_type == CHIP_RAVEN) |
51ac7eec | 2689 | vm->pte_support_ats = true; |
13307f7e | 2690 | } else { |
9a4b7d4c HK |
2691 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2692 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
13307f7e | 2693 | } |
9a4b7d4c HK |
2694 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2695 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
0855c9c9 | 2696 | WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)), |
9a4b7d4c | 2697 | "CPU update of VM recommended only for large BAR system\n"); |
6dd09027 CK |
2698 | |
2699 | if (vm->use_cpu_for_update) | |
2700 | vm->update_funcs = &amdgpu_vm_cpu_funcs; | |
2701 | else | |
2702 | vm->update_funcs = &amdgpu_vm_sdma_funcs; | |
d5884513 | 2703 | vm->last_update = NULL; |
05906dec | 2704 | |
e21eb261 | 2705 | amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp); |
03e9dee1 FK |
2706 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) |
2707 | bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW; | |
3f4299be | 2708 | r = amdgpu_bo_create(adev, &bp, &root); |
d38ceaf9 | 2709 | if (r) |
2bd9ccfa CK |
2710 | goto error_free_sched_entity; |
2711 | ||
3f4299be | 2712 | r = amdgpu_bo_reserve(root, true); |
d3aab672 CK |
2713 | if (r) |
2714 | goto error_free_root; | |
2715 | ||
0aa7aa24 CK |
2716 | r = reservation_object_reserve_shared(root->tbo.resv, 1); |
2717 | if (r) | |
2718 | goto error_unreserve; | |
2719 | ||
1e293037 CK |
2720 | amdgpu_vm_bo_base_init(&vm->root.base, vm, root); |
2721 | ||
780637cb | 2722 | r = amdgpu_vm_clear_bo(adev, vm, root); |
13307f7e CK |
2723 | if (r) |
2724 | goto error_unreserve; | |
2725 | ||
d3aab672 | 2726 | amdgpu_bo_unreserve(vm->root.base.bo); |
d38ceaf9 | 2727 | |
02208441 FK |
2728 | if (pasid) { |
2729 | unsigned long flags; | |
2730 | ||
2731 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2732 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2733 | GFP_ATOMIC); | |
2734 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2735 | if (r < 0) | |
2736 | goto error_free_root; | |
2737 | ||
2738 | vm->pasid = pasid; | |
0a096fb6 CK |
2739 | } |
2740 | ||
a2f14820 | 2741 | INIT_KFIFO(vm->faults); |
d38ceaf9 AD |
2742 | |
2743 | return 0; | |
2bd9ccfa | 2744 | |
13307f7e CK |
2745 | error_unreserve: |
2746 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2747 | ||
67003a15 | 2748 | error_free_root: |
3f3333f8 CK |
2749 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2750 | amdgpu_bo_unref(&vm->root.base.bo); | |
2751 | vm->root.base.bo = NULL; | |
2bd9ccfa CK |
2752 | |
2753 | error_free_sched_entity: | |
cdc50176 | 2754 | drm_sched_entity_destroy(&vm->entity); |
2bd9ccfa CK |
2755 | |
2756 | return r; | |
d38ceaf9 AD |
2757 | } |
2758 | ||
3680624e TH |
2759 | /** |
2760 | * amdgpu_vm_check_clean_reserved - check if a VM is clean | |
2761 | * | |
2762 | * @adev: amdgpu_device pointer | |
2763 | * @vm: the VM to check | |
2764 | * | |
2765 | * check all entries of the root PD, if any subsequent PDs are allocated, | |
2766 | * it means there are page table creating and filling, and is no a clean | |
2767 | * VM | |
2768 | * | |
2769 | * Returns: | |
2770 | * 0 if this VM is clean | |
2771 | */ | |
2772 | static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev, | |
2773 | struct amdgpu_vm *vm) | |
2774 | { | |
2775 | enum amdgpu_vm_level root = adev->vm_manager.root_level; | |
2776 | unsigned int entries = amdgpu_vm_num_entries(adev, root); | |
2777 | unsigned int i = 0; | |
2778 | ||
2779 | if (!(vm->root.entries)) | |
2780 | return 0; | |
2781 | ||
2782 | for (i = 0; i < entries; i++) { | |
2783 | if (vm->root.entries[i].base.bo) | |
2784 | return -EINVAL; | |
2785 | } | |
2786 | ||
2787 | return 0; | |
2788 | } | |
2789 | ||
b236fa1d FK |
2790 | /** |
2791 | * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM | |
2792 | * | |
7fc48e59 AG |
2793 | * @adev: amdgpu_device pointer |
2794 | * @vm: requested vm | |
2795 | * | |
b236fa1d FK |
2796 | * This only works on GFX VMs that don't have any BOs added and no |
2797 | * page tables allocated yet. | |
2798 | * | |
2799 | * Changes the following VM parameters: | |
2800 | * - use_cpu_for_update | |
2801 | * - pte_supports_ats | |
2802 | * - pasid (old PASID is released, because compute manages its own PASIDs) | |
2803 | * | |
2804 | * Reinitializes the page directory to reflect the changed ATS | |
b5d21aac | 2805 | * setting. |
b236fa1d | 2806 | * |
7fc48e59 AG |
2807 | * Returns: |
2808 | * 0 for success, -errno for errors. | |
b236fa1d | 2809 | */ |
1685b01a | 2810 | int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid) |
b236fa1d | 2811 | { |
741deade | 2812 | bool pte_support_ats = (adev->asic_type == CHIP_RAVEN); |
b236fa1d FK |
2813 | int r; |
2814 | ||
2815 | r = amdgpu_bo_reserve(vm->root.base.bo, true); | |
2816 | if (r) | |
2817 | return r; | |
2818 | ||
2819 | /* Sanity checks */ | |
3680624e TH |
2820 | r = amdgpu_vm_check_clean_reserved(adev, vm); |
2821 | if (r) | |
1685b01a | 2822 | goto unreserve_bo; |
1685b01a OZ |
2823 | |
2824 | if (pasid) { | |
2825 | unsigned long flags; | |
2826 | ||
2827 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2828 | r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, | |
2829 | GFP_ATOMIC); | |
2830 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2831 | ||
2832 | if (r == -ENOSPC) | |
2833 | goto unreserve_bo; | |
2834 | r = 0; | |
b236fa1d FK |
2835 | } |
2836 | ||
2837 | /* Check if PD needs to be reinitialized and do it before | |
2838 | * changing any other state, in case it fails. | |
2839 | */ | |
2840 | if (pte_support_ats != vm->pte_support_ats) { | |
780637cb CK |
2841 | vm->pte_support_ats = pte_support_ats; |
2842 | r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo); | |
b236fa1d | 2843 | if (r) |
1685b01a | 2844 | goto free_idr; |
b236fa1d FK |
2845 | } |
2846 | ||
2847 | /* Update VM state */ | |
2848 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & | |
2849 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
b236fa1d FK |
2850 | DRM_DEBUG_DRIVER("VM update mode is %s\n", |
2851 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
0855c9c9 | 2852 | WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)), |
b236fa1d FK |
2853 | "CPU update of VM recommended only for large BAR system\n"); |
2854 | ||
2855 | if (vm->pasid) { | |
2856 | unsigned long flags; | |
2857 | ||
2858 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2859 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2860 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2861 | ||
1685b01a OZ |
2862 | /* Free the original amdgpu allocated pasid |
2863 | * Will be replaced with kfd allocated pasid | |
2864 | */ | |
2865 | amdgpu_pasid_free(vm->pasid); | |
b236fa1d FK |
2866 | vm->pasid = 0; |
2867 | } | |
2868 | ||
b5d21aac SL |
2869 | /* Free the shadow bo for compute VM */ |
2870 | amdgpu_bo_unref(&vm->root.base.bo->shadow); | |
2871 | ||
1685b01a OZ |
2872 | if (pasid) |
2873 | vm->pasid = pasid; | |
2874 | ||
2875 | goto unreserve_bo; | |
2876 | ||
2877 | free_idr: | |
2878 | if (pasid) { | |
2879 | unsigned long flags; | |
2880 | ||
2881 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2882 | idr_remove(&adev->vm_manager.pasid_idr, pasid); | |
2883 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2884 | } | |
2885 | unreserve_bo: | |
b236fa1d FK |
2886 | amdgpu_bo_unreserve(vm->root.base.bo); |
2887 | return r; | |
2888 | } | |
2889 | ||
bf47afba OZ |
2890 | /** |
2891 | * amdgpu_vm_release_compute - release a compute vm | |
2892 | * @adev: amdgpu_device pointer | |
2893 | * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute | |
2894 | * | |
2895 | * This is a correspondant of amdgpu_vm_make_compute. It decouples compute | |
2896 | * pasid from vm. Compute should stop use of vm after this call. | |
2897 | */ | |
2898 | void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2899 | { | |
2900 | if (vm->pasid) { | |
2901 | unsigned long flags; | |
2902 | ||
2903 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2904 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2905 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2906 | } | |
2907 | vm->pasid = 0; | |
2908 | } | |
2909 | ||
d38ceaf9 AD |
2910 | /** |
2911 | * amdgpu_vm_fini - tear down a vm instance | |
2912 | * | |
2913 | * @adev: amdgpu_device pointer | |
2914 | * @vm: requested vm | |
2915 | * | |
8843dbbb | 2916 | * Tear down @vm. |
d38ceaf9 AD |
2917 | * Unbind the VM and remove all bos from the vm bo list |
2918 | */ | |
2919 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2920 | { | |
2921 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
132f34e4 | 2922 | bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt; |
2642cf11 | 2923 | struct amdgpu_bo *root; |
2642cf11 | 2924 | int i, r; |
d38ceaf9 | 2925 | |
ede0dd86 FK |
2926 | amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm); |
2927 | ||
02208441 FK |
2928 | if (vm->pasid) { |
2929 | unsigned long flags; | |
2930 | ||
2931 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); | |
2932 | idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); | |
2933 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); | |
2934 | } | |
2935 | ||
cdc50176 | 2936 | drm_sched_entity_destroy(&vm->entity); |
2bd9ccfa | 2937 | |
f808c13f | 2938 | if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { |
d38ceaf9 AD |
2939 | dev_err(adev->dev, "still active bo inside vm\n"); |
2940 | } | |
f808c13f DB |
2941 | rbtree_postorder_for_each_entry_safe(mapping, tmp, |
2942 | &vm->va.rb_root, rb) { | |
0af5c656 CK |
2943 | /* Don't remove the mapping here, we don't want to trigger a |
2944 | * rebalance and the tree is about to be destroyed anyway. | |
2945 | */ | |
d38ceaf9 | 2946 | list_del(&mapping->list); |
d38ceaf9 AD |
2947 | kfree(mapping); |
2948 | } | |
2949 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2950 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2951 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2952 | prt_fini_needed = false; |
451bc8eb | 2953 | } |
284710fa | 2954 | |
d38ceaf9 | 2955 | list_del(&mapping->list); |
451bc8eb | 2956 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2957 | } |
2958 | ||
2642cf11 CK |
2959 | root = amdgpu_bo_ref(vm->root.base.bo); |
2960 | r = amdgpu_bo_reserve(root, true); | |
2961 | if (r) { | |
2962 | dev_err(adev->dev, "Leaking page tables because BO reservation failed\n"); | |
2963 | } else { | |
e35fb064 | 2964 | amdgpu_vm_free_pts(adev, vm, NULL); |
2642cf11 CK |
2965 | amdgpu_bo_unreserve(root); |
2966 | } | |
2967 | amdgpu_bo_unref(&root); | |
e35fb064 | 2968 | WARN_ON(vm->root.base.bo); |
d5884513 | 2969 | dma_fence_put(vm->last_update); |
1e9ef26f | 2970 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
620f774f | 2971 | amdgpu_vmid_free_reserved(adev, vm, i); |
d38ceaf9 | 2972 | } |
ea89f8c9 | 2973 | |
a9a78b32 CK |
2974 | /** |
2975 | * amdgpu_vm_manager_init - init the VM manager | |
2976 | * | |
2977 | * @adev: amdgpu_device pointer | |
2978 | * | |
2979 | * Initialize the VM manager structures | |
2980 | */ | |
2981 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2982 | { | |
620f774f | 2983 | unsigned i; |
a9a78b32 | 2984 | |
620f774f | 2985 | amdgpu_vmid_mgr_init(adev); |
2d55e45a | 2986 | |
f54d1867 CW |
2987 | adev->vm_manager.fence_context = |
2988 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2989 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2990 | adev->vm_manager.seqno[i] = 0; | |
2991 | ||
284710fa | 2992 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2993 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
2994 | |
2995 | /* If not overridden by the user, by default, only in large BAR systems | |
2996 | * Compute VM tables will be updated by CPU | |
2997 | */ | |
2998 | #ifdef CONFIG_X86_64 | |
2999 | if (amdgpu_vm_update_mode == -1) { | |
c8c5e569 | 3000 | if (amdgpu_gmc_vram_full_visible(&adev->gmc)) |
9a4b7d4c HK |
3001 | adev->vm_manager.vm_update_mode = |
3002 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
3003 | else | |
3004 | adev->vm_manager.vm_update_mode = 0; | |
3005 | } else | |
3006 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
3007 | #else | |
3008 | adev->vm_manager.vm_update_mode = 0; | |
3009 | #endif | |
3010 | ||
02208441 FK |
3011 | idr_init(&adev->vm_manager.pasid_idr); |
3012 | spin_lock_init(&adev->vm_manager.pasid_lock); | |
df399b06 | 3013 | |
3014 | adev->vm_manager.xgmi_map_counter = 0; | |
3015 | mutex_init(&adev->vm_manager.lock_pstate); | |
a9a78b32 CK |
3016 | } |
3017 | ||
ea89f8c9 CK |
3018 | /** |
3019 | * amdgpu_vm_manager_fini - cleanup VM manager | |
3020 | * | |
3021 | * @adev: amdgpu_device pointer | |
3022 | * | |
3023 | * Cleanup the VM manager and free resources. | |
3024 | */ | |
3025 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
3026 | { | |
02208441 FK |
3027 | WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); |
3028 | idr_destroy(&adev->vm_manager.pasid_idr); | |
3029 | ||
620f774f | 3030 | amdgpu_vmid_mgr_fini(adev); |
ea89f8c9 | 3031 | } |
cfbcacf4 | 3032 | |
7fc48e59 AG |
3033 | /** |
3034 | * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs. | |
3035 | * | |
3036 | * @dev: drm device pointer | |
3037 | * @data: drm_amdgpu_vm | |
3038 | * @filp: drm file pointer | |
3039 | * | |
3040 | * Returns: | |
3041 | * 0 for success, -errno for errors. | |
3042 | */ | |
cfbcacf4 CZ |
3043 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
3044 | { | |
3045 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
3046 | struct amdgpu_device *adev = dev->dev_private; |
3047 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
3048 | int r; | |
cfbcacf4 CZ |
3049 | |
3050 | switch (args->in.op) { | |
3051 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f | 3052 | /* current, we only have requirement to reserve vmid from gfxhub */ |
620f774f | 3053 | r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
1e9ef26f CZ |
3054 | if (r) |
3055 | return r; | |
3056 | break; | |
cfbcacf4 | 3057 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
620f774f | 3058 | amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
3059 | break; |
3060 | default: | |
3061 | return -EINVAL; | |
3062 | } | |
3063 | ||
3064 | return 0; | |
3065 | } | |
2aa37bf5 AG |
3066 | |
3067 | /** | |
3068 | * amdgpu_vm_get_task_info - Extracts task info for a PASID. | |
3069 | * | |
989edc69 | 3070 | * @adev: drm device pointer |
2aa37bf5 AG |
3071 | * @pasid: PASID identifier for VM |
3072 | * @task_info: task_info to fill. | |
3073 | */ | |
3074 | void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid, | |
3075 | struct amdgpu_task_info *task_info) | |
3076 | { | |
3077 | struct amdgpu_vm *vm; | |
0a5f49cb | 3078 | unsigned long flags; |
2aa37bf5 | 3079 | |
0a5f49cb | 3080 | spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); |
2aa37bf5 AG |
3081 | |
3082 | vm = idr_find(&adev->vm_manager.pasid_idr, pasid); | |
3083 | if (vm) | |
3084 | *task_info = vm->task_info; | |
3085 | ||
0a5f49cb | 3086 | spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); |
2aa37bf5 AG |
3087 | } |
3088 | ||
3089 | /** | |
3090 | * amdgpu_vm_set_task_info - Sets VMs task info. | |
3091 | * | |
3092 | * @vm: vm for which to set the info | |
3093 | */ | |
3094 | void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) | |
3095 | { | |
3096 | if (!vm->task_info.pid) { | |
3097 | vm->task_info.pid = current->pid; | |
3098 | get_task_comm(vm->task_info.task_name, current); | |
3099 | ||
3100 | if (current->group_leader->mm == current->mm) { | |
3101 | vm->task_info.tgid = current->group_leader->pid; | |
3102 | get_task_comm(vm->task_info.process_name, current->group_leader); | |
3103 | } | |
3104 | } | |
3105 | } |