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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include <drm/amdgpu_drm.h> | |
30 | #include "amdgpu.h" | |
31 | #include "amdgpu_trace.h" | |
32 | ||
33 | /* | |
34 | * GPUVM | |
35 | * GPUVM is similar to the legacy gart on older asics, however | |
36 | * rather than there being a single global gart table | |
37 | * for the entire GPU, there are multiple VM page tables active | |
38 | * at any given time. The VM page tables can contain a mix | |
39 | * vram pages and system memory pages and system memory pages | |
40 | * can be mapped as snooped (cached system pages) or unsnooped | |
41 | * (uncached system pages). | |
42 | * Each VM has an ID associated with it and there is a page table | |
43 | * associated with each VMID. When execting a command buffer, | |
44 | * the kernel tells the the ring what VMID to use for that command | |
45 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
46 | * The userspace drivers maintain their own address space and the kernel | |
47 | * sets up their pages tables accordingly when they submit their | |
48 | * command buffers and a VMID is assigned. | |
49 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
50 | * SI supports 16. | |
51 | */ | |
52 | ||
4ff37a83 CK |
53 | /* Special value that no flush is necessary */ |
54 | #define AMDGPU_VM_NO_FLUSH (~0ll) | |
55 | ||
f4833c4f HK |
56 | /* Local structure. Encapsulate some VM table update parameters to reduce |
57 | * the number of function parameters | |
58 | */ | |
59 | struct amdgpu_vm_update_params { | |
60 | /* address where to copy page table entries from */ | |
61 | uint64_t src; | |
62 | /* DMA addresses to use for mapping */ | |
63 | dma_addr_t *pages_addr; | |
64 | /* indirect buffer to fill with commands */ | |
65 | struct amdgpu_ib *ib; | |
66 | }; | |
67 | ||
d38ceaf9 AD |
68 | /** |
69 | * amdgpu_vm_num_pde - return the number of page directory entries | |
70 | * | |
71 | * @adev: amdgpu_device pointer | |
72 | * | |
8843dbbb | 73 | * Calculate the number of page directory entries. |
d38ceaf9 AD |
74 | */ |
75 | static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) | |
76 | { | |
77 | return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; | |
78 | } | |
79 | ||
80 | /** | |
81 | * amdgpu_vm_directory_size - returns the size of the page directory in bytes | |
82 | * | |
83 | * @adev: amdgpu_device pointer | |
84 | * | |
8843dbbb | 85 | * Calculate the size of the page directory in bytes. |
d38ceaf9 AD |
86 | */ |
87 | static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) | |
88 | { | |
89 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); | |
90 | } | |
91 | ||
92 | /** | |
56467ebf | 93 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
94 | * |
95 | * @vm: vm providing the BOs | |
3c0eea6c | 96 | * @validated: head of validation list |
56467ebf | 97 | * @entry: entry to add |
d38ceaf9 AD |
98 | * |
99 | * Add the page directory to the list of BOs to | |
56467ebf | 100 | * validate for command submission. |
d38ceaf9 | 101 | */ |
56467ebf CK |
102 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
103 | struct list_head *validated, | |
104 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 105 | { |
56467ebf | 106 | entry->robj = vm->page_directory; |
56467ebf CK |
107 | entry->priority = 0; |
108 | entry->tv.bo = &vm->page_directory->tbo; | |
109 | entry->tv.shared = true; | |
2f568dbd | 110 | entry->user_pages = NULL; |
56467ebf CK |
111 | list_add(&entry->tv.head, validated); |
112 | } | |
d38ceaf9 | 113 | |
56467ebf | 114 | /** |
ee1782c3 | 115 | * amdgpu_vm_get_bos - add the vm BOs to a duplicates list |
56467ebf CK |
116 | * |
117 | * @vm: vm providing the BOs | |
3c0eea6c | 118 | * @duplicates: head of duplicates list |
d38ceaf9 | 119 | * |
ee1782c3 CK |
120 | * Add the page directory to the BO duplicates list |
121 | * for command submission. | |
d38ceaf9 | 122 | */ |
ee1782c3 | 123 | void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates) |
d38ceaf9 | 124 | { |
ee1782c3 | 125 | unsigned i; |
d38ceaf9 AD |
126 | |
127 | /* add the vm page table to the list */ | |
ee1782c3 CK |
128 | for (i = 0; i <= vm->max_pde_used; ++i) { |
129 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
130 | ||
131 | if (!entry->robj) | |
d38ceaf9 AD |
132 | continue; |
133 | ||
ee1782c3 | 134 | list_add(&entry->tv.head, duplicates); |
d38ceaf9 | 135 | } |
eceb8a15 CK |
136 | |
137 | } | |
138 | ||
139 | /** | |
140 | * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail | |
141 | * | |
142 | * @adev: amdgpu device instance | |
143 | * @vm: vm providing the BOs | |
144 | * | |
145 | * Move the PT BOs to the tail of the LRU. | |
146 | */ | |
147 | void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, | |
148 | struct amdgpu_vm *vm) | |
149 | { | |
150 | struct ttm_bo_global *glob = adev->mman.bdev.glob; | |
151 | unsigned i; | |
152 | ||
153 | spin_lock(&glob->lru_lock); | |
154 | for (i = 0; i <= vm->max_pde_used; ++i) { | |
155 | struct amdgpu_bo_list_entry *entry = &vm->page_tables[i].entry; | |
156 | ||
157 | if (!entry->robj) | |
158 | continue; | |
159 | ||
160 | ttm_bo_move_to_lru_tail(&entry->robj->tbo); | |
161 | } | |
162 | spin_unlock(&glob->lru_lock); | |
d38ceaf9 AD |
163 | } |
164 | ||
165 | /** | |
166 | * amdgpu_vm_grab_id - allocate the next free VMID | |
167 | * | |
d38ceaf9 | 168 | * @vm: vm to allocate id for |
7f8a5290 CK |
169 | * @ring: ring we want to submit job to |
170 | * @sync: sync object where we add dependencies | |
94dd0a4a | 171 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 172 | * |
7f8a5290 | 173 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 174 | */ |
7f8a5290 | 175 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
4ff37a83 CK |
176 | struct amdgpu_sync *sync, struct fence *fence, |
177 | unsigned *vm_id, uint64_t *vm_pd_addr) | |
d38ceaf9 | 178 | { |
4ff37a83 | 179 | uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); |
d38ceaf9 | 180 | struct amdgpu_device *adev = ring->adev; |
4ff37a83 | 181 | struct fence *updates = sync->last_vm_update; |
794f50b9 CK |
182 | struct amdgpu_vm_id *id; |
183 | unsigned i = ring->idx; | |
a9a78b32 | 184 | int r; |
d38ceaf9 | 185 | |
94dd0a4a CK |
186 | mutex_lock(&adev->vm_manager.lock); |
187 | ||
794f50b9 CK |
188 | /* Check if we can use a VMID already assigned to this VM */ |
189 | do { | |
190 | struct fence *flushed; | |
4ff37a83 | 191 | |
794f50b9 CK |
192 | id = vm->ids[i++]; |
193 | if (i == AMDGPU_MAX_RINGS) | |
194 | i = 0; | |
4ff37a83 | 195 | |
794f50b9 CK |
196 | /* Check all the prerequisites to using this VMID */ |
197 | if (!id) | |
198 | continue; | |
199 | ||
0ea54b9b | 200 | if (atomic64_read(&id->owner) != vm->client_id) |
794f50b9 CK |
201 | continue; |
202 | ||
203 | if (pd_addr != id->pd_gpu_addr) | |
204 | continue; | |
205 | ||
178d7cb8 | 206 | if (id->last_user != ring && |
794f50b9 CK |
207 | (!id->last_flush || !fence_is_signaled(id->last_flush))) |
208 | continue; | |
209 | ||
210 | flushed = id->flushed_updates; | |
211 | if (updates && (!flushed || fence_is_later(updates, flushed))) | |
212 | continue; | |
a8bd1bec | 213 | |
794f50b9 | 214 | /* Good we can use this VMID */ |
178d7cb8 | 215 | if (id->last_user == ring) { |
794f50b9 CK |
216 | r = amdgpu_sync_fence(ring->adev, sync, |
217 | id->first); | |
832a902f CK |
218 | if (r) |
219 | goto error; | |
794f50b9 CK |
220 | } |
221 | ||
222 | /* And remember this submission as user of the VMID */ | |
223 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
224 | if (r) | |
225 | goto error; | |
4ff37a83 | 226 | |
794f50b9 CK |
227 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
228 | vm->ids[ring->idx] = id; | |
d38ceaf9 | 229 | |
794f50b9 CK |
230 | *vm_id = id - adev->vm_manager.ids; |
231 | *vm_pd_addr = AMDGPU_VM_NO_FLUSH; | |
232 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); | |
d38ceaf9 | 233 | |
794f50b9 CK |
234 | mutex_unlock(&adev->vm_manager.lock); |
235 | return 0; | |
236 | ||
237 | } while (i != ring->idx); | |
d38ceaf9 | 238 | |
36fd7c5c CK |
239 | /* Check if we have an idle VMID */ |
240 | list_for_each_entry(id, &adev->vm_manager.ids_lru, list) { | |
241 | if (amdgpu_sync_is_idle(&id->active, ring)) | |
242 | break; | |
243 | ||
244 | } | |
245 | ||
246 | /* If we can't find a idle VMID to use, just wait for the oldest */ | |
247 | if (&id->list == &adev->vm_manager.ids_lru) { | |
bcb1ba35 CK |
248 | id = list_first_entry(&adev->vm_manager.ids_lru, |
249 | struct amdgpu_vm_id, | |
250 | list); | |
8e9fbeb5 CZ |
251 | } |
252 | ||
832a902f CK |
253 | r = amdgpu_sync_cycle_fences(sync, &id->active, fence); |
254 | if (r) | |
255 | goto error; | |
94dd0a4a | 256 | |
832a902f CK |
257 | fence_put(id->first); |
258 | id->first = fence_get(fence); | |
94dd0a4a | 259 | |
41d9eb2c CK |
260 | fence_put(id->last_flush); |
261 | id->last_flush = NULL; | |
262 | ||
832a902f CK |
263 | fence_put(id->flushed_updates); |
264 | id->flushed_updates = fence_get(updates); | |
94dd0a4a | 265 | |
832a902f | 266 | id->pd_gpu_addr = pd_addr; |
4ff37a83 | 267 | |
832a902f | 268 | list_move_tail(&id->list, &adev->vm_manager.ids_lru); |
68befebe | 269 | id->last_user = ring; |
0ea54b9b | 270 | atomic64_set(&id->owner, vm->client_id); |
832a902f | 271 | vm->ids[ring->idx] = id; |
d38ceaf9 | 272 | |
832a902f CK |
273 | *vm_id = id - adev->vm_manager.ids; |
274 | *vm_pd_addr = pd_addr; | |
275 | trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr); | |
276 | ||
277 | error: | |
94dd0a4a | 278 | mutex_unlock(&adev->vm_manager.lock); |
a9a78b32 | 279 | return r; |
d38ceaf9 AD |
280 | } |
281 | ||
282 | /** | |
283 | * amdgpu_vm_flush - hardware flush the vm | |
284 | * | |
285 | * @ring: ring to use for flush | |
cffadc83 | 286 | * @vm_id: vmid number to use |
4ff37a83 | 287 | * @pd_addr: address of the page directory |
d38ceaf9 | 288 | * |
4ff37a83 | 289 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 290 | */ |
41d9eb2c CK |
291 | int amdgpu_vm_flush(struct amdgpu_ring *ring, |
292 | unsigned vm_id, uint64_t pd_addr, | |
293 | uint32_t gds_base, uint32_t gds_size, | |
294 | uint32_t gws_base, uint32_t gws_size, | |
295 | uint32_t oa_base, uint32_t oa_size) | |
d38ceaf9 | 296 | { |
971fe9a9 | 297 | struct amdgpu_device *adev = ring->adev; |
bcb1ba35 | 298 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
d564a06e | 299 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
bcb1ba35 CK |
300 | id->gds_base != gds_base || |
301 | id->gds_size != gds_size || | |
302 | id->gws_base != gws_base || | |
303 | id->gws_size != gws_size || | |
304 | id->oa_base != oa_base || | |
305 | id->oa_size != oa_size); | |
41d9eb2c | 306 | int r; |
d564a06e CK |
307 | |
308 | if (ring->funcs->emit_pipeline_sync && ( | |
fe707664 CZ |
309 | pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed || |
310 | ring->type == AMDGPU_RING_TYPE_COMPUTE)) | |
d564a06e | 311 | amdgpu_ring_emit_pipeline_sync(ring); |
971fe9a9 | 312 | |
c5637837 ML |
313 | if (ring->funcs->emit_vm_flush && |
314 | pd_addr != AMDGPU_VM_NO_FLUSH) { | |
41d9eb2c CK |
315 | struct fence *fence; |
316 | ||
cffadc83 CK |
317 | trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id); |
318 | amdgpu_ring_emit_vm_flush(ring, vm_id, pd_addr); | |
41d9eb2c CK |
319 | |
320 | mutex_lock(&adev->vm_manager.lock); | |
68befebe CZ |
321 | if ((id->pd_gpu_addr == pd_addr) && (id->last_user == ring)) { |
322 | r = amdgpu_fence_emit(ring, &fence); | |
323 | if (r) { | |
324 | mutex_unlock(&adev->vm_manager.lock); | |
325 | return r; | |
326 | } | |
327 | fence_put(id->last_flush); | |
328 | id->last_flush = fence; | |
329 | } | |
41d9eb2c | 330 | mutex_unlock(&adev->vm_manager.lock); |
d38ceaf9 | 331 | } |
cffadc83 | 332 | |
d564a06e | 333 | if (gds_switch_needed) { |
bcb1ba35 CK |
334 | id->gds_base = gds_base; |
335 | id->gds_size = gds_size; | |
336 | id->gws_base = gws_base; | |
337 | id->gws_size = gws_size; | |
338 | id->oa_base = oa_base; | |
339 | id->oa_size = oa_size; | |
cffadc83 CK |
340 | amdgpu_ring_emit_gds_switch(ring, vm_id, |
341 | gds_base, gds_size, | |
342 | gws_base, gws_size, | |
343 | oa_base, oa_size); | |
971fe9a9 | 344 | } |
41d9eb2c CK |
345 | |
346 | return 0; | |
971fe9a9 CK |
347 | } |
348 | ||
349 | /** | |
350 | * amdgpu_vm_reset_id - reset VMID to zero | |
351 | * | |
352 | * @adev: amdgpu device structure | |
353 | * @vm_id: vmid number to use | |
354 | * | |
355 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
356 | */ | |
357 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id) | |
358 | { | |
bcb1ba35 CK |
359 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[vm_id]; |
360 | ||
361 | id->gds_base = 0; | |
362 | id->gds_size = 0; | |
363 | id->gws_base = 0; | |
364 | id->gws_size = 0; | |
365 | id->oa_base = 0; | |
366 | id->oa_size = 0; | |
d38ceaf9 AD |
367 | } |
368 | ||
d38ceaf9 AD |
369 | /** |
370 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
371 | * | |
372 | * @vm: requested vm | |
373 | * @bo: requested buffer object | |
374 | * | |
8843dbbb | 375 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
376 | * Search inside the @bos vm list for the requested vm |
377 | * Returns the found bo_va or NULL if none is found | |
378 | * | |
379 | * Object has to be reserved! | |
380 | */ | |
381 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
382 | struct amdgpu_bo *bo) | |
383 | { | |
384 | struct amdgpu_bo_va *bo_va; | |
385 | ||
386 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
387 | if (bo_va->vm == vm) { | |
388 | return bo_va; | |
389 | } | |
390 | } | |
391 | return NULL; | |
392 | } | |
393 | ||
394 | /** | |
395 | * amdgpu_vm_update_pages - helper to call the right asic function | |
396 | * | |
397 | * @adev: amdgpu_device pointer | |
f4833c4f | 398 | * @vm_update_params: see amdgpu_vm_update_params definition |
d38ceaf9 AD |
399 | * @pe: addr of the page entry |
400 | * @addr: dst addr to write into pe | |
401 | * @count: number of page entries to update | |
402 | * @incr: increase next addr by incr bytes | |
403 | * @flags: hw access flags | |
d38ceaf9 AD |
404 | * |
405 | * Traces the parameters and calls the right asic functions | |
406 | * to setup the page table using the DMA. | |
407 | */ | |
408 | static void amdgpu_vm_update_pages(struct amdgpu_device *adev, | |
f4833c4f HK |
409 | struct amdgpu_vm_update_params |
410 | *vm_update_params, | |
d38ceaf9 AD |
411 | uint64_t pe, uint64_t addr, |
412 | unsigned count, uint32_t incr, | |
9ab21462 | 413 | uint32_t flags) |
d38ceaf9 AD |
414 | { |
415 | trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); | |
416 | ||
f4833c4f HK |
417 | if (vm_update_params->src) { |
418 | amdgpu_vm_copy_pte(adev, vm_update_params->ib, | |
419 | pe, (vm_update_params->src + (addr >> 12) * 8), count); | |
d38ceaf9 | 420 | |
f4833c4f HK |
421 | } else if (vm_update_params->pages_addr) { |
422 | amdgpu_vm_write_pte(adev, vm_update_params->ib, | |
423 | vm_update_params->pages_addr, | |
424 | pe, addr, count, incr, flags); | |
b07c9d2a CK |
425 | |
426 | } else if (count < 3) { | |
f4833c4f | 427 | amdgpu_vm_write_pte(adev, vm_update_params->ib, NULL, pe, addr, |
b07c9d2a | 428 | count, incr, flags); |
d38ceaf9 AD |
429 | |
430 | } else { | |
f4833c4f | 431 | amdgpu_vm_set_pte_pde(adev, vm_update_params->ib, pe, addr, |
d38ceaf9 AD |
432 | count, incr, flags); |
433 | } | |
434 | } | |
435 | ||
436 | /** | |
437 | * amdgpu_vm_clear_bo - initially clear the page dir/table | |
438 | * | |
439 | * @adev: amdgpu_device pointer | |
440 | * @bo: bo to clear | |
ef9f0a83 CZ |
441 | * |
442 | * need to reserve bo first before calling it. | |
d38ceaf9 AD |
443 | */ |
444 | static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, | |
2bd9ccfa | 445 | struct amdgpu_vm *vm, |
d38ceaf9 AD |
446 | struct amdgpu_bo *bo) |
447 | { | |
2d55e45a | 448 | struct amdgpu_ring *ring; |
4af9f07c | 449 | struct fence *fence = NULL; |
d71518b5 | 450 | struct amdgpu_job *job; |
f4833c4f | 451 | struct amdgpu_vm_update_params vm_update_params; |
d38ceaf9 AD |
452 | unsigned entries; |
453 | uint64_t addr; | |
454 | int r; | |
455 | ||
f4833c4f | 456 | memset(&vm_update_params, 0, sizeof(vm_update_params)); |
2d55e45a CK |
457 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
458 | ||
ca952613 | 459 | r = reservation_object_reserve_shared(bo->tbo.resv); |
460 | if (r) | |
461 | return r; | |
462 | ||
d38ceaf9 AD |
463 | r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); |
464 | if (r) | |
ef9f0a83 | 465 | goto error; |
d38ceaf9 AD |
466 | |
467 | addr = amdgpu_bo_gpu_offset(bo); | |
468 | entries = amdgpu_bo_size(bo) / 8; | |
469 | ||
d71518b5 CK |
470 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
471 | if (r) | |
ef9f0a83 | 472 | goto error; |
d38ceaf9 | 473 | |
f4833c4f HK |
474 | vm_update_params.ib = &job->ibs[0]; |
475 | amdgpu_vm_update_pages(adev, &vm_update_params, addr, 0, entries, | |
d71518b5 CK |
476 | 0, 0); |
477 | amdgpu_ring_pad_ib(ring, &job->ibs[0]); | |
478 | ||
479 | WARN_ON(job->ibs[0].length_dw > 64); | |
2bd9ccfa CK |
480 | r = amdgpu_job_submit(job, ring, &vm->entity, |
481 | AMDGPU_FENCE_OWNER_VM, &fence); | |
d38ceaf9 AD |
482 | if (r) |
483 | goto error_free; | |
484 | ||
d71518b5 | 485 | amdgpu_bo_fence(bo, fence, true); |
281b4223 | 486 | fence_put(fence); |
cadf97b1 | 487 | return 0; |
ef9f0a83 | 488 | |
d38ceaf9 | 489 | error_free: |
d71518b5 | 490 | amdgpu_job_free(job); |
d38ceaf9 | 491 | |
ef9f0a83 | 492 | error: |
d38ceaf9 AD |
493 | return r; |
494 | } | |
495 | ||
496 | /** | |
b07c9d2a | 497 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 498 | * |
b07c9d2a | 499 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
500 | * @addr: the unmapped addr |
501 | * | |
502 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 503 | * to and return the pointer for the page table entry. |
d38ceaf9 | 504 | */ |
b07c9d2a | 505 | uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
506 | { |
507 | uint64_t result; | |
508 | ||
b07c9d2a CK |
509 | if (pages_addr) { |
510 | /* page table offset */ | |
511 | result = pages_addr[addr >> PAGE_SHIFT]; | |
512 | ||
513 | /* in case cpu page size != gpu page size*/ | |
514 | result |= addr & (~PAGE_MASK); | |
515 | ||
516 | } else { | |
517 | /* No mapping required */ | |
518 | result = addr; | |
519 | } | |
d38ceaf9 | 520 | |
b07c9d2a | 521 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
522 | |
523 | return result; | |
524 | } | |
525 | ||
526 | /** | |
527 | * amdgpu_vm_update_pdes - make sure that page directory is valid | |
528 | * | |
529 | * @adev: amdgpu_device pointer | |
530 | * @vm: requested vm | |
531 | * @start: start of GPU address range | |
532 | * @end: end of GPU address range | |
533 | * | |
534 | * Allocates new page tables if necessary | |
8843dbbb | 535 | * and updates the page directory. |
d38ceaf9 | 536 | * Returns 0 for success, error for failure. |
d38ceaf9 AD |
537 | */ |
538 | int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, | |
539 | struct amdgpu_vm *vm) | |
540 | { | |
2d55e45a | 541 | struct amdgpu_ring *ring; |
d38ceaf9 AD |
542 | struct amdgpu_bo *pd = vm->page_directory; |
543 | uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); | |
544 | uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; | |
545 | uint64_t last_pde = ~0, last_pt = ~0; | |
546 | unsigned count = 0, pt_idx, ndw; | |
d71518b5 | 547 | struct amdgpu_job *job; |
f4833c4f | 548 | struct amdgpu_vm_update_params vm_update_params; |
4af9f07c | 549 | struct fence *fence = NULL; |
d5fc5e82 | 550 | |
d38ceaf9 AD |
551 | int r; |
552 | ||
f4833c4f | 553 | memset(&vm_update_params, 0, sizeof(vm_update_params)); |
2d55e45a CK |
554 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
555 | ||
d38ceaf9 AD |
556 | /* padding, etc. */ |
557 | ndw = 64; | |
558 | ||
559 | /* assume the worst case */ | |
560 | ndw += vm->max_pde_used * 6; | |
561 | ||
d71518b5 CK |
562 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
563 | if (r) | |
d38ceaf9 | 564 | return r; |
d71518b5 | 565 | |
f4833c4f | 566 | vm_update_params.ib = &job->ibs[0]; |
d38ceaf9 AD |
567 | |
568 | /* walk over the address space and update the page directory */ | |
569 | for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { | |
ee1782c3 | 570 | struct amdgpu_bo *bo = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 AD |
571 | uint64_t pde, pt; |
572 | ||
573 | if (bo == NULL) | |
574 | continue; | |
575 | ||
576 | pt = amdgpu_bo_gpu_offset(bo); | |
577 | if (vm->page_tables[pt_idx].addr == pt) | |
578 | continue; | |
579 | vm->page_tables[pt_idx].addr = pt; | |
580 | ||
581 | pde = pd_addr + pt_idx * 8; | |
582 | if (((last_pde + 8 * count) != pde) || | |
583 | ((last_pt + incr * count) != pt)) { | |
584 | ||
585 | if (count) { | |
f4833c4f | 586 | amdgpu_vm_update_pages(adev, &vm_update_params, |
9ab21462 CK |
587 | last_pde, last_pt, |
588 | count, incr, | |
589 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
590 | } |
591 | ||
592 | count = 1; | |
593 | last_pde = pde; | |
594 | last_pt = pt; | |
595 | } else { | |
596 | ++count; | |
597 | } | |
598 | } | |
599 | ||
600 | if (count) | |
f4833c4f HK |
601 | amdgpu_vm_update_pages(adev, &vm_update_params, |
602 | last_pde, last_pt, | |
603 | count, incr, AMDGPU_PTE_VALID); | |
d38ceaf9 | 604 | |
f4833c4f HK |
605 | if (vm_update_params.ib->length_dw != 0) { |
606 | amdgpu_ring_pad_ib(ring, vm_update_params.ib); | |
e86f9cee CK |
607 | amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv, |
608 | AMDGPU_FENCE_OWNER_VM); | |
f4833c4f | 609 | WARN_ON(vm_update_params.ib->length_dw > ndw); |
2bd9ccfa CK |
610 | r = amdgpu_job_submit(job, ring, &vm->entity, |
611 | AMDGPU_FENCE_OWNER_VM, &fence); | |
4af9f07c CZ |
612 | if (r) |
613 | goto error_free; | |
05906dec | 614 | |
4af9f07c | 615 | amdgpu_bo_fence(pd, fence, true); |
05906dec BN |
616 | fence_put(vm->page_directory_fence); |
617 | vm->page_directory_fence = fence_get(fence); | |
281b4223 | 618 | fence_put(fence); |
d5fc5e82 | 619 | |
d71518b5 CK |
620 | } else { |
621 | amdgpu_job_free(job); | |
d5fc5e82 | 622 | } |
d38ceaf9 AD |
623 | |
624 | return 0; | |
d5fc5e82 CZ |
625 | |
626 | error_free: | |
d71518b5 | 627 | amdgpu_job_free(job); |
4af9f07c | 628 | return r; |
d38ceaf9 AD |
629 | } |
630 | ||
631 | /** | |
632 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
633 | * | |
634 | * @adev: amdgpu_device pointer | |
f4833c4f | 635 | * @vm_update_params: see amdgpu_vm_update_params definition |
d38ceaf9 AD |
636 | * @pe_start: first PTE to handle |
637 | * @pe_end: last PTE to handle | |
638 | * @addr: addr those PTEs should point to | |
639 | * @flags: hw mapping flags | |
d38ceaf9 AD |
640 | */ |
641 | static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev, | |
f4833c4f HK |
642 | struct amdgpu_vm_update_params |
643 | *vm_update_params, | |
d38ceaf9 | 644 | uint64_t pe_start, uint64_t pe_end, |
9ab21462 | 645 | uint64_t addr, uint32_t flags) |
d38ceaf9 AD |
646 | { |
647 | /** | |
648 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
649 | * field in the PTE. When this field is set to a non-zero value, page | |
650 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
651 | * flags are considered valid for all PTEs within the fragment range | |
652 | * and corresponding mappings are assumed to be physically contiguous. | |
653 | * | |
654 | * The L1 TLB can store a single PTE for the whole fragment, | |
655 | * significantly increasing the space available for translation | |
656 | * caching. This leads to large improvements in throughput when the | |
657 | * TLB is under pressure. | |
658 | * | |
659 | * The L2 TLB distributes small and large fragments into two | |
660 | * asymmetric partitions. The large fragment cache is significantly | |
661 | * larger. Thus, we try to use large fragments wherever possible. | |
662 | * Userspace can support this by aligning virtual base address and | |
663 | * allocation size to the fragment size. | |
664 | */ | |
665 | ||
666 | /* SI and newer are optimized for 64KB */ | |
667 | uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB; | |
668 | uint64_t frag_align = 0x80; | |
669 | ||
670 | uint64_t frag_start = ALIGN(pe_start, frag_align); | |
671 | uint64_t frag_end = pe_end & ~(frag_align - 1); | |
672 | ||
673 | unsigned count; | |
674 | ||
31f6c1fe CK |
675 | /* Abort early if there isn't anything to do */ |
676 | if (pe_start == pe_end) | |
677 | return; | |
678 | ||
d38ceaf9 | 679 | /* system pages are non continuously */ |
f4833c4f HK |
680 | if (vm_update_params->src || vm_update_params->pages_addr || |
681 | !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) { | |
d38ceaf9 AD |
682 | |
683 | count = (pe_end - pe_start) / 8; | |
f4833c4f | 684 | amdgpu_vm_update_pages(adev, vm_update_params, pe_start, |
9ab21462 CK |
685 | addr, count, AMDGPU_GPU_PAGE_SIZE, |
686 | flags); | |
d38ceaf9 AD |
687 | return; |
688 | } | |
689 | ||
690 | /* handle the 4K area at the beginning */ | |
691 | if (pe_start != frag_start) { | |
692 | count = (frag_start - pe_start) / 8; | |
f4833c4f | 693 | amdgpu_vm_update_pages(adev, vm_update_params, pe_start, addr, |
9ab21462 | 694 | count, AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
695 | addr += AMDGPU_GPU_PAGE_SIZE * count; |
696 | } | |
697 | ||
698 | /* handle the area in the middle */ | |
699 | count = (frag_end - frag_start) / 8; | |
f4833c4f | 700 | amdgpu_vm_update_pages(adev, vm_update_params, frag_start, addr, count, |
9ab21462 | 701 | AMDGPU_GPU_PAGE_SIZE, flags | frag_flags); |
d38ceaf9 AD |
702 | |
703 | /* handle the 4K area at the end */ | |
704 | if (frag_end != pe_end) { | |
705 | addr += AMDGPU_GPU_PAGE_SIZE * count; | |
706 | count = (pe_end - frag_end) / 8; | |
f4833c4f | 707 | amdgpu_vm_update_pages(adev, vm_update_params, frag_end, addr, |
9ab21462 | 708 | count, AMDGPU_GPU_PAGE_SIZE, flags); |
d38ceaf9 AD |
709 | } |
710 | } | |
711 | ||
712 | /** | |
713 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
714 | * | |
715 | * @adev: amdgpu_device pointer | |
f4833c4f | 716 | * @vm_update_params: see amdgpu_vm_update_params definition |
d38ceaf9 AD |
717 | * @vm: requested vm |
718 | * @start: start of GPU address range | |
719 | * @end: end of GPU address range | |
720 | * @dst: destination address to map to | |
721 | * @flags: mapping flags | |
722 | * | |
8843dbbb | 723 | * Update the page tables in the range @start - @end. |
d38ceaf9 | 724 | */ |
a1e08d3b | 725 | static void amdgpu_vm_update_ptes(struct amdgpu_device *adev, |
f4833c4f HK |
726 | struct amdgpu_vm_update_params |
727 | *vm_update_params, | |
a1e08d3b | 728 | struct amdgpu_vm *vm, |
a1e08d3b CK |
729 | uint64_t start, uint64_t end, |
730 | uint64_t dst, uint32_t flags) | |
d38ceaf9 | 731 | { |
31f6c1fe CK |
732 | const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1; |
733 | ||
734 | uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0; | |
d38ceaf9 AD |
735 | uint64_t addr; |
736 | ||
737 | /* walk over the address space and update the page tables */ | |
738 | for (addr = start; addr < end; ) { | |
739 | uint64_t pt_idx = addr >> amdgpu_vm_block_size; | |
ee1782c3 | 740 | struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj; |
d38ceaf9 | 741 | unsigned nptes; |
31f6c1fe | 742 | uint64_t pe_start; |
d38ceaf9 AD |
743 | |
744 | if ((addr & ~mask) == (end & ~mask)) | |
745 | nptes = end - addr; | |
746 | else | |
747 | nptes = AMDGPU_VM_PTE_COUNT - (addr & mask); | |
748 | ||
31f6c1fe CK |
749 | pe_start = amdgpu_bo_gpu_offset(pt); |
750 | pe_start += (addr & mask) * 8; | |
d38ceaf9 | 751 | |
31f6c1fe | 752 | if (last_pe_end != pe_start) { |
d38ceaf9 | 753 | |
f4833c4f | 754 | amdgpu_vm_frag_ptes(adev, vm_update_params, |
31f6c1fe CK |
755 | last_pe_start, last_pe_end, |
756 | last_dst, flags); | |
d38ceaf9 | 757 | |
31f6c1fe CK |
758 | last_pe_start = pe_start; |
759 | last_pe_end = pe_start + 8 * nptes; | |
d38ceaf9 AD |
760 | last_dst = dst; |
761 | } else { | |
31f6c1fe | 762 | last_pe_end += 8 * nptes; |
d38ceaf9 AD |
763 | } |
764 | ||
765 | addr += nptes; | |
766 | dst += nptes * AMDGPU_GPU_PAGE_SIZE; | |
767 | } | |
768 | ||
f4833c4f | 769 | amdgpu_vm_frag_ptes(adev, vm_update_params, last_pe_start, |
fa3ab3c7 | 770 | last_pe_end, last_dst, flags); |
d38ceaf9 AD |
771 | } |
772 | ||
d38ceaf9 AD |
773 | /** |
774 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
775 | * | |
776 | * @adev: amdgpu_device pointer | |
fa3ab3c7 CK |
777 | * @src: address where to copy page table entries from |
778 | * @pages_addr: DMA addresses to use for mapping | |
d38ceaf9 | 779 | * @vm: requested vm |
a14faa65 CK |
780 | * @start: start of mapped range |
781 | * @last: last mapped entry | |
782 | * @flags: flags for the entries | |
d38ceaf9 | 783 | * @addr: addr to set the area to |
d38ceaf9 AD |
784 | * @fence: optional resulting fence |
785 | * | |
a14faa65 | 786 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 787 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
788 | */ |
789 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
fa3ab3c7 CK |
790 | uint64_t src, |
791 | dma_addr_t *pages_addr, | |
d38ceaf9 | 792 | struct amdgpu_vm *vm, |
a14faa65 CK |
793 | uint64_t start, uint64_t last, |
794 | uint32_t flags, uint64_t addr, | |
795 | struct fence **fence) | |
d38ceaf9 | 796 | { |
2d55e45a | 797 | struct amdgpu_ring *ring; |
a1e08d3b | 798 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 799 | unsigned nptes, ncmds, ndw; |
d71518b5 | 800 | struct amdgpu_job *job; |
f4833c4f | 801 | struct amdgpu_vm_update_params vm_update_params; |
4af9f07c | 802 | struct fence *f = NULL; |
d38ceaf9 AD |
803 | int r; |
804 | ||
2d55e45a | 805 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
f4833c4f HK |
806 | memset(&vm_update_params, 0, sizeof(vm_update_params)); |
807 | vm_update_params.src = src; | |
808 | vm_update_params.pages_addr = pages_addr; | |
2d55e45a | 809 | |
a1e08d3b CK |
810 | /* sync to everything on unmapping */ |
811 | if (!(flags & AMDGPU_PTE_VALID)) | |
812 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
813 | ||
a14faa65 | 814 | nptes = last - start + 1; |
d38ceaf9 AD |
815 | |
816 | /* | |
817 | * reserve space for one command every (1 << BLOCK_SIZE) | |
818 | * entries or 2k dwords (whatever is smaller) | |
819 | */ | |
820 | ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1; | |
821 | ||
822 | /* padding, etc. */ | |
823 | ndw = 64; | |
824 | ||
f4833c4f | 825 | if (vm_update_params.src) { |
d38ceaf9 AD |
826 | /* only copy commands needed */ |
827 | ndw += ncmds * 7; | |
828 | ||
f4833c4f | 829 | } else if (vm_update_params.pages_addr) { |
d38ceaf9 AD |
830 | /* header for write data commands */ |
831 | ndw += ncmds * 4; | |
832 | ||
833 | /* body of write data command */ | |
834 | ndw += nptes * 2; | |
835 | ||
836 | } else { | |
837 | /* set page commands needed */ | |
838 | ndw += ncmds * 10; | |
839 | ||
840 | /* two extra commands for begin/end of fragment */ | |
841 | ndw += 2 * 10; | |
842 | } | |
843 | ||
d71518b5 CK |
844 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
845 | if (r) | |
d38ceaf9 | 846 | return r; |
d71518b5 | 847 | |
f4833c4f | 848 | vm_update_params.ib = &job->ibs[0]; |
d5fc5e82 | 849 | |
e86f9cee | 850 | r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv, |
a1e08d3b CK |
851 | owner); |
852 | if (r) | |
853 | goto error_free; | |
d38ceaf9 | 854 | |
a1e08d3b CK |
855 | r = reservation_object_reserve_shared(vm->page_directory->tbo.resv); |
856 | if (r) | |
857 | goto error_free; | |
858 | ||
f4833c4f | 859 | amdgpu_vm_update_ptes(adev, &vm_update_params, vm, start, |
fa3ab3c7 | 860 | last + 1, addr, flags); |
d38ceaf9 | 861 | |
f4833c4f HK |
862 | amdgpu_ring_pad_ib(ring, vm_update_params.ib); |
863 | WARN_ON(vm_update_params.ib->length_dw > ndw); | |
2bd9ccfa CK |
864 | r = amdgpu_job_submit(job, ring, &vm->entity, |
865 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
866 | if (r) |
867 | goto error_free; | |
d38ceaf9 | 868 | |
bf60efd3 | 869 | amdgpu_bo_fence(vm->page_directory, f, true); |
4af9f07c CZ |
870 | if (fence) { |
871 | fence_put(*fence); | |
872 | *fence = fence_get(f); | |
873 | } | |
281b4223 | 874 | fence_put(f); |
d38ceaf9 | 875 | return 0; |
d5fc5e82 CZ |
876 | |
877 | error_free: | |
d71518b5 | 878 | amdgpu_job_free(job); |
4af9f07c | 879 | return r; |
d38ceaf9 AD |
880 | } |
881 | ||
a14faa65 CK |
882 | /** |
883 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
884 | * | |
885 | * @adev: amdgpu_device pointer | |
8358dcee CK |
886 | * @gtt_flags: flags as they are used for GTT |
887 | * @pages_addr: DMA addresses to use for mapping | |
a14faa65 CK |
888 | * @vm: requested vm |
889 | * @mapping: mapped range and flags to use for the update | |
890 | * @addr: addr to set the area to | |
8358dcee | 891 | * @flags: HW flags for the mapping |
a14faa65 CK |
892 | * @fence: optional resulting fence |
893 | * | |
894 | * Split the mapping into smaller chunks so that each update fits | |
895 | * into a SDMA IB. | |
896 | * Returns 0 for success, -EINVAL for failure. | |
897 | */ | |
898 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
a14faa65 | 899 | uint32_t gtt_flags, |
8358dcee | 900 | dma_addr_t *pages_addr, |
a14faa65 CK |
901 | struct amdgpu_vm *vm, |
902 | struct amdgpu_bo_va_mapping *mapping, | |
fa3ab3c7 CK |
903 | uint32_t flags, uint64_t addr, |
904 | struct fence **fence) | |
a14faa65 CK |
905 | { |
906 | const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE; | |
907 | ||
fa3ab3c7 | 908 | uint64_t src = 0, start = mapping->it.start; |
a14faa65 CK |
909 | int r; |
910 | ||
911 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
912 | * but in case of something, we filter the flags in first place | |
913 | */ | |
914 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
915 | flags &= ~AMDGPU_PTE_READABLE; | |
916 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
917 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
918 | ||
919 | trace_amdgpu_vm_bo_update(mapping); | |
920 | ||
8358dcee | 921 | if (pages_addr) { |
fa3ab3c7 CK |
922 | if (flags == gtt_flags) |
923 | src = adev->gart.table_addr + (addr >> 12) * 8; | |
fa3ab3c7 CK |
924 | addr = 0; |
925 | } | |
a14faa65 CK |
926 | addr += mapping->offset; |
927 | ||
8358dcee | 928 | if (!pages_addr || src) |
fa3ab3c7 | 929 | return amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm, |
a14faa65 CK |
930 | start, mapping->it.last, |
931 | flags, addr, fence); | |
932 | ||
933 | while (start != mapping->it.last + 1) { | |
934 | uint64_t last; | |
935 | ||
fb29b57c | 936 | last = min((uint64_t)mapping->it.last, start + max_size - 1); |
fa3ab3c7 | 937 | r = amdgpu_vm_bo_update_mapping(adev, src, pages_addr, vm, |
a14faa65 CK |
938 | start, last, flags, addr, |
939 | fence); | |
940 | if (r) | |
941 | return r; | |
942 | ||
943 | start = last + 1; | |
fb29b57c | 944 | addr += max_size * AMDGPU_GPU_PAGE_SIZE; |
a14faa65 CK |
945 | } |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
d38ceaf9 AD |
950 | /** |
951 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
952 | * | |
953 | * @adev: amdgpu_device pointer | |
954 | * @bo_va: requested BO and VM object | |
955 | * @mem: ttm mem | |
956 | * | |
957 | * Fill in the page table entries for @bo_va. | |
958 | * Returns 0 for success, -EINVAL for failure. | |
959 | * | |
960 | * Object have to be reserved and mutex must be locked! | |
961 | */ | |
962 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
963 | struct amdgpu_bo_va *bo_va, | |
964 | struct ttm_mem_reg *mem) | |
965 | { | |
966 | struct amdgpu_vm *vm = bo_va->vm; | |
967 | struct amdgpu_bo_va_mapping *mapping; | |
8358dcee | 968 | dma_addr_t *pages_addr = NULL; |
fa3ab3c7 | 969 | uint32_t gtt_flags, flags; |
d38ceaf9 AD |
970 | uint64_t addr; |
971 | int r; | |
972 | ||
973 | if (mem) { | |
8358dcee CK |
974 | struct ttm_dma_tt *ttm; |
975 | ||
b7d698d7 | 976 | addr = (u64)mem->start << PAGE_SHIFT; |
9ab21462 CK |
977 | switch (mem->mem_type) { |
978 | case TTM_PL_TT: | |
8358dcee CK |
979 | ttm = container_of(bo_va->bo->tbo.ttm, struct |
980 | ttm_dma_tt, ttm); | |
981 | pages_addr = ttm->dma_address; | |
9ab21462 CK |
982 | break; |
983 | ||
984 | case TTM_PL_VRAM: | |
d38ceaf9 | 985 | addr += adev->vm_manager.vram_base_offset; |
9ab21462 CK |
986 | break; |
987 | ||
988 | default: | |
989 | break; | |
990 | } | |
d38ceaf9 AD |
991 | } else { |
992 | addr = 0; | |
993 | } | |
994 | ||
d38ceaf9 | 995 | flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem); |
fa3ab3c7 | 996 | gtt_flags = (adev == bo_va->bo->adev) ? flags : 0; |
d38ceaf9 | 997 | |
7fc11959 CK |
998 | spin_lock(&vm->status_lock); |
999 | if (!list_empty(&bo_va->vm_status)) | |
1000 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
1001 | spin_unlock(&vm->status_lock); | |
1002 | ||
1003 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
8358dcee CK |
1004 | r = amdgpu_vm_bo_split_mapping(adev, gtt_flags, pages_addr, vm, |
1005 | mapping, flags, addr, | |
1006 | &bo_va->last_pt_update); | |
d38ceaf9 AD |
1007 | if (r) |
1008 | return r; | |
1009 | } | |
1010 | ||
d6c10f6b CK |
1011 | if (trace_amdgpu_vm_bo_mapping_enabled()) { |
1012 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1013 | trace_amdgpu_vm_bo_mapping(mapping); | |
1014 | ||
1015 | list_for_each_entry(mapping, &bo_va->invalids, list) | |
1016 | trace_amdgpu_vm_bo_mapping(mapping); | |
1017 | } | |
1018 | ||
d38ceaf9 | 1019 | spin_lock(&vm->status_lock); |
6d1d0ef7 | 1020 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
d38ceaf9 | 1021 | list_del_init(&bo_va->vm_status); |
7fc11959 CK |
1022 | if (!mem) |
1023 | list_add(&bo_va->vm_status, &vm->cleared); | |
d38ceaf9 AD |
1024 | spin_unlock(&vm->status_lock); |
1025 | ||
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | /** | |
1030 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1031 | * | |
1032 | * @adev: amdgpu_device pointer | |
1033 | * @vm: requested vm | |
1034 | * | |
1035 | * Make sure all freed BOs are cleared in the PT. | |
1036 | * Returns 0 for success. | |
1037 | * | |
1038 | * PTs have to be reserved and mutex must be locked! | |
1039 | */ | |
1040 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
1041 | struct amdgpu_vm *vm) | |
1042 | { | |
1043 | struct amdgpu_bo_va_mapping *mapping; | |
1044 | int r; | |
1045 | ||
1046 | while (!list_empty(&vm->freed)) { | |
1047 | mapping = list_first_entry(&vm->freed, | |
1048 | struct amdgpu_bo_va_mapping, list); | |
1049 | list_del(&mapping->list); | |
e17841b9 | 1050 | |
8358dcee | 1051 | r = amdgpu_vm_bo_split_mapping(adev, 0, NULL, vm, mapping, |
fa3ab3c7 | 1052 | 0, 0, NULL); |
d38ceaf9 AD |
1053 | kfree(mapping); |
1054 | if (r) | |
1055 | return r; | |
1056 | ||
1057 | } | |
1058 | return 0; | |
1059 | ||
1060 | } | |
1061 | ||
1062 | /** | |
1063 | * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT | |
1064 | * | |
1065 | * @adev: amdgpu_device pointer | |
1066 | * @vm: requested vm | |
1067 | * | |
1068 | * Make sure all invalidated BOs are cleared in the PT. | |
1069 | * Returns 0 for success. | |
1070 | * | |
1071 | * PTs have to be reserved and mutex must be locked! | |
1072 | */ | |
1073 | int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, | |
cfe2c978 | 1074 | struct amdgpu_vm *vm, struct amdgpu_sync *sync) |
d38ceaf9 | 1075 | { |
cfe2c978 | 1076 | struct amdgpu_bo_va *bo_va = NULL; |
91e1a520 | 1077 | int r = 0; |
d38ceaf9 AD |
1078 | |
1079 | spin_lock(&vm->status_lock); | |
1080 | while (!list_empty(&vm->invalidated)) { | |
1081 | bo_va = list_first_entry(&vm->invalidated, | |
1082 | struct amdgpu_bo_va, vm_status); | |
1083 | spin_unlock(&vm->status_lock); | |
32b41ac2 | 1084 | |
d38ceaf9 AD |
1085 | r = amdgpu_vm_bo_update(adev, bo_va, NULL); |
1086 | if (r) | |
1087 | return r; | |
1088 | ||
1089 | spin_lock(&vm->status_lock); | |
1090 | } | |
1091 | spin_unlock(&vm->status_lock); | |
1092 | ||
cfe2c978 | 1093 | if (bo_va) |
bb1e38a4 | 1094 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
1095 | |
1096 | return r; | |
d38ceaf9 AD |
1097 | } |
1098 | ||
1099 | /** | |
1100 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
1101 | * | |
1102 | * @adev: amdgpu_device pointer | |
1103 | * @vm: requested vm | |
1104 | * @bo: amdgpu buffer object | |
1105 | * | |
8843dbbb | 1106 | * Add @bo into the requested vm. |
d38ceaf9 AD |
1107 | * Add @bo to the list of bos associated with the vm |
1108 | * Returns newly added bo_va or NULL for failure | |
1109 | * | |
1110 | * Object has to be reserved! | |
1111 | */ | |
1112 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
1113 | struct amdgpu_vm *vm, | |
1114 | struct amdgpu_bo *bo) | |
1115 | { | |
1116 | struct amdgpu_bo_va *bo_va; | |
1117 | ||
1118 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
1119 | if (bo_va == NULL) { | |
1120 | return NULL; | |
1121 | } | |
1122 | bo_va->vm = vm; | |
1123 | bo_va->bo = bo; | |
d38ceaf9 AD |
1124 | bo_va->ref_count = 1; |
1125 | INIT_LIST_HEAD(&bo_va->bo_list); | |
7fc11959 CK |
1126 | INIT_LIST_HEAD(&bo_va->valids); |
1127 | INIT_LIST_HEAD(&bo_va->invalids); | |
d38ceaf9 | 1128 | INIT_LIST_HEAD(&bo_va->vm_status); |
32b41ac2 | 1129 | |
d38ceaf9 | 1130 | list_add_tail(&bo_va->bo_list, &bo->va); |
d38ceaf9 AD |
1131 | |
1132 | return bo_va; | |
1133 | } | |
1134 | ||
1135 | /** | |
1136 | * amdgpu_vm_bo_map - map bo inside a vm | |
1137 | * | |
1138 | * @adev: amdgpu_device pointer | |
1139 | * @bo_va: bo_va to store the address | |
1140 | * @saddr: where to map the BO | |
1141 | * @offset: requested offset in the BO | |
1142 | * @flags: attributes of pages (read/write/valid/etc.) | |
1143 | * | |
1144 | * Add a mapping of the BO at the specefied addr into the VM. | |
1145 | * Returns 0 for success, error for failure. | |
1146 | * | |
49b02b18 | 1147 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1148 | */ |
1149 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
1150 | struct amdgpu_bo_va *bo_va, | |
1151 | uint64_t saddr, uint64_t offset, | |
1152 | uint64_t size, uint32_t flags) | |
1153 | { | |
1154 | struct amdgpu_bo_va_mapping *mapping; | |
1155 | struct amdgpu_vm *vm = bo_va->vm; | |
1156 | struct interval_tree_node *it; | |
1157 | unsigned last_pfn, pt_idx; | |
1158 | uint64_t eaddr; | |
1159 | int r; | |
1160 | ||
0be52de9 CK |
1161 | /* validate the parameters */ |
1162 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 1163 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 1164 | return -EINVAL; |
0be52de9 | 1165 | |
d38ceaf9 | 1166 | /* make sure object fit at this offset */ |
005ae95e | 1167 | eaddr = saddr + size - 1; |
49b02b18 | 1168 | if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) |
d38ceaf9 | 1169 | return -EINVAL; |
d38ceaf9 AD |
1170 | |
1171 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
005ae95e FK |
1172 | if (last_pfn >= adev->vm_manager.max_pfn) { |
1173 | dev_err(adev->dev, "va above limit (0x%08X >= 0x%08X)\n", | |
d38ceaf9 | 1174 | last_pfn, adev->vm_manager.max_pfn); |
d38ceaf9 AD |
1175 | return -EINVAL; |
1176 | } | |
1177 | ||
d38ceaf9 AD |
1178 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
1179 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
1180 | ||
005ae95e | 1181 | it = interval_tree_iter_first(&vm->va, saddr, eaddr); |
d38ceaf9 AD |
1182 | if (it) { |
1183 | struct amdgpu_bo_va_mapping *tmp; | |
1184 | tmp = container_of(it, struct amdgpu_bo_va_mapping, it); | |
1185 | /* bo and tmp overlap, invalid addr */ | |
1186 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
1187 | "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, | |
1188 | tmp->it.start, tmp->it.last + 1); | |
d38ceaf9 | 1189 | r = -EINVAL; |
f48b2659 | 1190 | goto error; |
d38ceaf9 AD |
1191 | } |
1192 | ||
1193 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
1194 | if (!mapping) { | |
d38ceaf9 | 1195 | r = -ENOMEM; |
f48b2659 | 1196 | goto error; |
d38ceaf9 AD |
1197 | } |
1198 | ||
1199 | INIT_LIST_HEAD(&mapping->list); | |
1200 | mapping->it.start = saddr; | |
005ae95e | 1201 | mapping->it.last = eaddr; |
d38ceaf9 AD |
1202 | mapping->offset = offset; |
1203 | mapping->flags = flags; | |
1204 | ||
7fc11959 | 1205 | list_add(&mapping->list, &bo_va->invalids); |
d38ceaf9 AD |
1206 | interval_tree_insert(&mapping->it, &vm->va); |
1207 | ||
1208 | /* Make sure the page tables are allocated */ | |
1209 | saddr >>= amdgpu_vm_block_size; | |
1210 | eaddr >>= amdgpu_vm_block_size; | |
1211 | ||
1212 | BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev)); | |
1213 | ||
1214 | if (eaddr > vm->max_pde_used) | |
1215 | vm->max_pde_used = eaddr; | |
1216 | ||
d38ceaf9 AD |
1217 | /* walk over the address space and allocate the page tables */ |
1218 | for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { | |
bf60efd3 | 1219 | struct reservation_object *resv = vm->page_directory->tbo.resv; |
ee1782c3 | 1220 | struct amdgpu_bo_list_entry *entry; |
d38ceaf9 AD |
1221 | struct amdgpu_bo *pt; |
1222 | ||
ee1782c3 CK |
1223 | entry = &vm->page_tables[pt_idx].entry; |
1224 | if (entry->robj) | |
d38ceaf9 AD |
1225 | continue; |
1226 | ||
d38ceaf9 AD |
1227 | r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, |
1228 | AMDGPU_GPU_PAGE_SIZE, true, | |
857d913d AD |
1229 | AMDGPU_GEM_DOMAIN_VRAM, |
1230 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
bf60efd3 | 1231 | NULL, resv, &pt); |
49b02b18 | 1232 | if (r) |
d38ceaf9 | 1233 | goto error_free; |
49b02b18 | 1234 | |
82b9c55b CK |
1235 | /* Keep a reference to the page table to avoid freeing |
1236 | * them up in the wrong order. | |
1237 | */ | |
1238 | pt->parent = amdgpu_bo_ref(vm->page_directory); | |
1239 | ||
2bd9ccfa | 1240 | r = amdgpu_vm_clear_bo(adev, vm, pt); |
d38ceaf9 AD |
1241 | if (r) { |
1242 | amdgpu_bo_unref(&pt); | |
1243 | goto error_free; | |
1244 | } | |
1245 | ||
ee1782c3 | 1246 | entry->robj = pt; |
ee1782c3 CK |
1247 | entry->priority = 0; |
1248 | entry->tv.bo = &entry->robj->tbo; | |
1249 | entry->tv.shared = true; | |
2f568dbd | 1250 | entry->user_pages = NULL; |
d38ceaf9 | 1251 | vm->page_tables[pt_idx].addr = 0; |
d38ceaf9 AD |
1252 | } |
1253 | ||
d38ceaf9 AD |
1254 | return 0; |
1255 | ||
1256 | error_free: | |
d38ceaf9 AD |
1257 | list_del(&mapping->list); |
1258 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1259 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 AD |
1260 | kfree(mapping); |
1261 | ||
f48b2659 | 1262 | error: |
d38ceaf9 AD |
1263 | return r; |
1264 | } | |
1265 | ||
1266 | /** | |
1267 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
1268 | * | |
1269 | * @adev: amdgpu_device pointer | |
1270 | * @bo_va: bo_va to remove the address from | |
1271 | * @saddr: where to the BO is mapped | |
1272 | * | |
1273 | * Remove a mapping of the BO at the specefied addr from the VM. | |
1274 | * Returns 0 for success, error for failure. | |
1275 | * | |
49b02b18 | 1276 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
1277 | */ |
1278 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
1279 | struct amdgpu_bo_va *bo_va, | |
1280 | uint64_t saddr) | |
1281 | { | |
1282 | struct amdgpu_bo_va_mapping *mapping; | |
1283 | struct amdgpu_vm *vm = bo_va->vm; | |
7fc11959 | 1284 | bool valid = true; |
d38ceaf9 | 1285 | |
6c7fc503 | 1286 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 1287 | |
7fc11959 | 1288 | list_for_each_entry(mapping, &bo_va->valids, list) { |
d38ceaf9 AD |
1289 | if (mapping->it.start == saddr) |
1290 | break; | |
1291 | } | |
1292 | ||
7fc11959 CK |
1293 | if (&mapping->list == &bo_va->valids) { |
1294 | valid = false; | |
1295 | ||
1296 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
1297 | if (mapping->it.start == saddr) | |
1298 | break; | |
1299 | } | |
1300 | ||
32b41ac2 | 1301 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 1302 | return -ENOENT; |
d38ceaf9 | 1303 | } |
32b41ac2 | 1304 | |
d38ceaf9 AD |
1305 | list_del(&mapping->list); |
1306 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1307 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 1308 | |
e17841b9 | 1309 | if (valid) |
d38ceaf9 | 1310 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 1311 | else |
d38ceaf9 | 1312 | kfree(mapping); |
d38ceaf9 AD |
1313 | |
1314 | return 0; | |
1315 | } | |
1316 | ||
1317 | /** | |
1318 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
1319 | * | |
1320 | * @adev: amdgpu_device pointer | |
1321 | * @bo_va: requested bo_va | |
1322 | * | |
8843dbbb | 1323 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
1324 | * |
1325 | * Object have to be reserved! | |
1326 | */ | |
1327 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
1328 | struct amdgpu_bo_va *bo_va) | |
1329 | { | |
1330 | struct amdgpu_bo_va_mapping *mapping, *next; | |
1331 | struct amdgpu_vm *vm = bo_va->vm; | |
1332 | ||
1333 | list_del(&bo_va->bo_list); | |
1334 | ||
d38ceaf9 AD |
1335 | spin_lock(&vm->status_lock); |
1336 | list_del(&bo_va->vm_status); | |
1337 | spin_unlock(&vm->status_lock); | |
1338 | ||
7fc11959 | 1339 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 AD |
1340 | list_del(&mapping->list); |
1341 | interval_tree_remove(&mapping->it, &vm->va); | |
93e3e438 | 1342 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
1343 | list_add(&mapping->list, &vm->freed); |
1344 | } | |
1345 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
1346 | list_del(&mapping->list); | |
1347 | interval_tree_remove(&mapping->it, &vm->va); | |
1348 | kfree(mapping); | |
d38ceaf9 | 1349 | } |
32b41ac2 | 1350 | |
bb1e38a4 | 1351 | fence_put(bo_va->last_pt_update); |
d38ceaf9 | 1352 | kfree(bo_va); |
d38ceaf9 AD |
1353 | } |
1354 | ||
1355 | /** | |
1356 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
1357 | * | |
1358 | * @adev: amdgpu_device pointer | |
1359 | * @vm: requested vm | |
1360 | * @bo: amdgpu buffer object | |
1361 | * | |
8843dbbb | 1362 | * Mark @bo as invalid. |
d38ceaf9 AD |
1363 | */ |
1364 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
1365 | struct amdgpu_bo *bo) | |
1366 | { | |
1367 | struct amdgpu_bo_va *bo_va; | |
1368 | ||
1369 | list_for_each_entry(bo_va, &bo->va, bo_list) { | |
7fc11959 CK |
1370 | spin_lock(&bo_va->vm->status_lock); |
1371 | if (list_empty(&bo_va->vm_status)) | |
d38ceaf9 | 1372 | list_add(&bo_va->vm_status, &bo_va->vm->invalidated); |
7fc11959 | 1373 | spin_unlock(&bo_va->vm->status_lock); |
d38ceaf9 AD |
1374 | } |
1375 | } | |
1376 | ||
1377 | /** | |
1378 | * amdgpu_vm_init - initialize a vm instance | |
1379 | * | |
1380 | * @adev: amdgpu_device pointer | |
1381 | * @vm: requested vm | |
1382 | * | |
8843dbbb | 1383 | * Init @vm fields. |
d38ceaf9 AD |
1384 | */ |
1385 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1386 | { | |
1387 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
1388 | AMDGPU_VM_PTE_COUNT * 8); | |
9571e1d8 | 1389 | unsigned pd_size, pd_entries; |
2d55e45a CK |
1390 | unsigned ring_instance; |
1391 | struct amdgpu_ring *ring; | |
2bd9ccfa | 1392 | struct amd_sched_rq *rq; |
d38ceaf9 AD |
1393 | int i, r; |
1394 | ||
bcb1ba35 CK |
1395 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
1396 | vm->ids[i] = NULL; | |
d38ceaf9 | 1397 | vm->va = RB_ROOT; |
031e2983 | 1398 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
d38ceaf9 AD |
1399 | spin_lock_init(&vm->status_lock); |
1400 | INIT_LIST_HEAD(&vm->invalidated); | |
7fc11959 | 1401 | INIT_LIST_HEAD(&vm->cleared); |
d38ceaf9 | 1402 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 1403 | |
d38ceaf9 AD |
1404 | pd_size = amdgpu_vm_directory_size(adev); |
1405 | pd_entries = amdgpu_vm_num_pdes(adev); | |
1406 | ||
1407 | /* allocate page table array */ | |
9571e1d8 | 1408 | vm->page_tables = drm_calloc_large(pd_entries, sizeof(struct amdgpu_vm_pt)); |
d38ceaf9 AD |
1409 | if (vm->page_tables == NULL) { |
1410 | DRM_ERROR("Cannot allocate memory for page table array\n"); | |
1411 | return -ENOMEM; | |
1412 | } | |
1413 | ||
2bd9ccfa | 1414 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
1415 | |
1416 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
1417 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
1418 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
1419 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
1420 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
1421 | rq, amdgpu_sched_jobs); | |
1422 | if (r) | |
1423 | return r; | |
1424 | ||
05906dec BN |
1425 | vm->page_directory_fence = NULL; |
1426 | ||
d38ceaf9 | 1427 | r = amdgpu_bo_create(adev, pd_size, align, true, |
857d913d AD |
1428 | AMDGPU_GEM_DOMAIN_VRAM, |
1429 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS, | |
72d7668b | 1430 | NULL, NULL, &vm->page_directory); |
d38ceaf9 | 1431 | if (r) |
2bd9ccfa CK |
1432 | goto error_free_sched_entity; |
1433 | ||
ef9f0a83 | 1434 | r = amdgpu_bo_reserve(vm->page_directory, false); |
2bd9ccfa CK |
1435 | if (r) |
1436 | goto error_free_page_directory; | |
1437 | ||
1438 | r = amdgpu_vm_clear_bo(adev, vm, vm->page_directory); | |
ef9f0a83 | 1439 | amdgpu_bo_unreserve(vm->page_directory); |
2bd9ccfa CK |
1440 | if (r) |
1441 | goto error_free_page_directory; | |
d38ceaf9 AD |
1442 | |
1443 | return 0; | |
2bd9ccfa CK |
1444 | |
1445 | error_free_page_directory: | |
1446 | amdgpu_bo_unref(&vm->page_directory); | |
1447 | vm->page_directory = NULL; | |
1448 | ||
1449 | error_free_sched_entity: | |
1450 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
1451 | ||
1452 | return r; | |
d38ceaf9 AD |
1453 | } |
1454 | ||
1455 | /** | |
1456 | * amdgpu_vm_fini - tear down a vm instance | |
1457 | * | |
1458 | * @adev: amdgpu_device pointer | |
1459 | * @vm: requested vm | |
1460 | * | |
8843dbbb | 1461 | * Tear down @vm. |
d38ceaf9 AD |
1462 | * Unbind the VM and remove all bos from the vm bo list |
1463 | */ | |
1464 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1465 | { | |
1466 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
1467 | int i; | |
1468 | ||
2d55e45a | 1469 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 1470 | |
d38ceaf9 AD |
1471 | if (!RB_EMPTY_ROOT(&vm->va)) { |
1472 | dev_err(adev->dev, "still active bo inside vm\n"); | |
1473 | } | |
1474 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) { | |
1475 | list_del(&mapping->list); | |
1476 | interval_tree_remove(&mapping->it, &vm->va); | |
1477 | kfree(mapping); | |
1478 | } | |
1479 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
1480 | list_del(&mapping->list); | |
1481 | kfree(mapping); | |
1482 | } | |
1483 | ||
1484 | for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) | |
ee1782c3 | 1485 | amdgpu_bo_unref(&vm->page_tables[i].entry.robj); |
9571e1d8 | 1486 | drm_free_large(vm->page_tables); |
d38ceaf9 AD |
1487 | |
1488 | amdgpu_bo_unref(&vm->page_directory); | |
05906dec | 1489 | fence_put(vm->page_directory_fence); |
d38ceaf9 | 1490 | } |
ea89f8c9 | 1491 | |
a9a78b32 CK |
1492 | /** |
1493 | * amdgpu_vm_manager_init - init the VM manager | |
1494 | * | |
1495 | * @adev: amdgpu_device pointer | |
1496 | * | |
1497 | * Initialize the VM manager structures | |
1498 | */ | |
1499 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
1500 | { | |
1501 | unsigned i; | |
1502 | ||
1503 | INIT_LIST_HEAD(&adev->vm_manager.ids_lru); | |
1504 | ||
1505 | /* skip over VMID 0, since it is the system VM */ | |
971fe9a9 CK |
1506 | for (i = 1; i < adev->vm_manager.num_ids; ++i) { |
1507 | amdgpu_vm_reset_id(adev, i); | |
832a902f | 1508 | amdgpu_sync_create(&adev->vm_manager.ids[i].active); |
a9a78b32 CK |
1509 | list_add_tail(&adev->vm_manager.ids[i].list, |
1510 | &adev->vm_manager.ids_lru); | |
971fe9a9 | 1511 | } |
2d55e45a CK |
1512 | |
1513 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); | |
b1c8a81f | 1514 | atomic64_set(&adev->vm_manager.client_counter, 0); |
a9a78b32 CK |
1515 | } |
1516 | ||
ea89f8c9 CK |
1517 | /** |
1518 | * amdgpu_vm_manager_fini - cleanup VM manager | |
1519 | * | |
1520 | * @adev: amdgpu_device pointer | |
1521 | * | |
1522 | * Cleanup the VM manager and free resources. | |
1523 | */ | |
1524 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
1525 | { | |
1526 | unsigned i; | |
1527 | ||
bcb1ba35 CK |
1528 | for (i = 0; i < AMDGPU_NUM_VM; ++i) { |
1529 | struct amdgpu_vm_id *id = &adev->vm_manager.ids[i]; | |
1530 | ||
832a902f CK |
1531 | fence_put(adev->vm_manager.ids[i].first); |
1532 | amdgpu_sync_free(&adev->vm_manager.ids[i].active); | |
bcb1ba35 CK |
1533 | fence_put(id->flushed_updates); |
1534 | } | |
ea89f8c9 | 1535 | } |