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Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
f54d1867 | 28 | #include <linux/dma-fence-array.h> |
a9f87f64 | 29 | #include <linux/interval_tree_generic.h> |
d38ceaf9 AD |
30 | #include <drm/drmP.h> |
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
33 | #include "amdgpu_trace.h" | |
34 | ||
35 | /* | |
36 | * GPUVM | |
37 | * GPUVM is similar to the legacy gart on older asics, however | |
38 | * rather than there being a single global gart table | |
39 | * for the entire GPU, there are multiple VM page tables active | |
40 | * at any given time. The VM page tables can contain a mix | |
41 | * vram pages and system memory pages and system memory pages | |
42 | * can be mapped as snooped (cached system pages) or unsnooped | |
43 | * (uncached system pages). | |
44 | * Each VM has an ID associated with it and there is a page table | |
45 | * associated with each VMID. When execting a command buffer, | |
46 | * the kernel tells the the ring what VMID to use for that command | |
47 | * buffer. VMIDs are allocated dynamically as commands are submitted. | |
48 | * The userspace drivers maintain their own address space and the kernel | |
49 | * sets up their pages tables accordingly when they submit their | |
50 | * command buffers and a VMID is assigned. | |
51 | * Cayman/Trinity support up to 8 active VMs at any given time; | |
52 | * SI supports 16. | |
53 | */ | |
54 | ||
a9f87f64 CK |
55 | #define START(node) ((node)->start) |
56 | #define LAST(node) ((node)->last) | |
57 | ||
58 | INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last, | |
59 | START, LAST, static, amdgpu_vm_it) | |
60 | ||
61 | #undef START | |
62 | #undef LAST | |
63 | ||
f4833c4f HK |
64 | /* Local structure. Encapsulate some VM table update parameters to reduce |
65 | * the number of function parameters | |
66 | */ | |
29efc4f5 | 67 | struct amdgpu_pte_update_params { |
27c5f36f CK |
68 | /* amdgpu device we do this update for */ |
69 | struct amdgpu_device *adev; | |
49ac8a24 CK |
70 | /* optional amdgpu_vm we do this update for */ |
71 | struct amdgpu_vm *vm; | |
f4833c4f HK |
72 | /* address where to copy page table entries from */ |
73 | uint64_t src; | |
f4833c4f HK |
74 | /* indirect buffer to fill with commands */ |
75 | struct amdgpu_ib *ib; | |
afef8b8f CK |
76 | /* Function which actually does the update */ |
77 | void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe, | |
78 | uint64_t addr, unsigned count, uint32_t incr, | |
6b777607 | 79 | uint64_t flags); |
b4d42511 HK |
80 | /* The next two are used during VM update by CPU |
81 | * DMA addresses to use for mapping | |
82 | * Kernel pointer of PD/PT BO that needs to be updated | |
83 | */ | |
84 | dma_addr_t *pages_addr; | |
85 | void *kptr; | |
f4833c4f HK |
86 | }; |
87 | ||
284710fa CK |
88 | /* Helper to disable partial resident texture feature from a fence callback */ |
89 | struct amdgpu_prt_cb { | |
90 | struct amdgpu_device *adev; | |
91 | struct dma_fence_cb cb; | |
92 | }; | |
93 | ||
d38ceaf9 | 94 | /** |
72a7ec5c | 95 | * amdgpu_vm_num_entries - return the number of entries in a PD/PT |
d38ceaf9 AD |
96 | * |
97 | * @adev: amdgpu_device pointer | |
98 | * | |
72a7ec5c | 99 | * Calculate the number of entries in a page directory or page table. |
d38ceaf9 | 100 | */ |
72a7ec5c CK |
101 | static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, |
102 | unsigned level) | |
d38ceaf9 | 103 | { |
72a7ec5c CK |
104 | if (level == 0) |
105 | /* For the root directory */ | |
106 | return adev->vm_manager.max_pfn >> | |
36b32a68 ZJ |
107 | (adev->vm_manager.block_size * |
108 | adev->vm_manager.num_level); | |
72a7ec5c CK |
109 | else if (level == adev->vm_manager.num_level) |
110 | /* For the page tables on the leaves */ | |
36b32a68 | 111 | return AMDGPU_VM_PTE_COUNT(adev); |
72a7ec5c CK |
112 | else |
113 | /* Everything in between */ | |
36b32a68 | 114 | return 1 << adev->vm_manager.block_size; |
d38ceaf9 AD |
115 | } |
116 | ||
117 | /** | |
72a7ec5c | 118 | * amdgpu_vm_bo_size - returns the size of the BOs in bytes |
d38ceaf9 AD |
119 | * |
120 | * @adev: amdgpu_device pointer | |
121 | * | |
72a7ec5c | 122 | * Calculate the size of the BO for a page directory or page table in bytes. |
d38ceaf9 | 123 | */ |
72a7ec5c | 124 | static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level) |
d38ceaf9 | 125 | { |
72a7ec5c | 126 | return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8); |
d38ceaf9 AD |
127 | } |
128 | ||
129 | /** | |
56467ebf | 130 | * amdgpu_vm_get_pd_bo - add the VM PD to a validation list |
d38ceaf9 AD |
131 | * |
132 | * @vm: vm providing the BOs | |
3c0eea6c | 133 | * @validated: head of validation list |
56467ebf | 134 | * @entry: entry to add |
d38ceaf9 AD |
135 | * |
136 | * Add the page directory to the list of BOs to | |
56467ebf | 137 | * validate for command submission. |
d38ceaf9 | 138 | */ |
56467ebf CK |
139 | void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, |
140 | struct list_head *validated, | |
141 | struct amdgpu_bo_list_entry *entry) | |
d38ceaf9 | 142 | { |
3f3333f8 | 143 | entry->robj = vm->root.base.bo; |
56467ebf | 144 | entry->priority = 0; |
67003a15 | 145 | entry->tv.bo = &entry->robj->tbo; |
56467ebf | 146 | entry->tv.shared = true; |
2f568dbd | 147 | entry->user_pages = NULL; |
56467ebf CK |
148 | list_add(&entry->tv.head, validated); |
149 | } | |
d38ceaf9 | 150 | |
56467ebf | 151 | /** |
f7da30d9 | 152 | * amdgpu_vm_validate_pt_bos - validate the page table BOs |
56467ebf | 153 | * |
5a712a87 | 154 | * @adev: amdgpu device pointer |
56467ebf | 155 | * @vm: vm providing the BOs |
f7da30d9 CK |
156 | * @validate: callback to do the validation |
157 | * @param: parameter for the validation callback | |
d38ceaf9 | 158 | * |
f7da30d9 | 159 | * Validate the page table BOs on command submission if neccessary. |
d38ceaf9 | 160 | */ |
f7da30d9 CK |
161 | int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
162 | int (*validate)(void *p, struct amdgpu_bo *bo), | |
163 | void *param) | |
d38ceaf9 | 164 | { |
3f3333f8 CK |
165 | struct ttm_bo_global *glob = adev->mman.bdev.glob; |
166 | int r; | |
d38ceaf9 | 167 | |
3f3333f8 CK |
168 | spin_lock(&vm->status_lock); |
169 | while (!list_empty(&vm->evicted)) { | |
170 | struct amdgpu_vm_bo_base *bo_base; | |
171 | struct amdgpu_bo *bo; | |
5a712a87 | 172 | |
3f3333f8 CK |
173 | bo_base = list_first_entry(&vm->evicted, |
174 | struct amdgpu_vm_bo_base, | |
175 | vm_status); | |
176 | spin_unlock(&vm->status_lock); | |
d711e139 | 177 | |
3f3333f8 CK |
178 | bo = bo_base->bo; |
179 | BUG_ON(!bo); | |
180 | if (bo->parent) { | |
181 | r = validate(param, bo); | |
182 | if (r) | |
183 | return r; | |
34d7be5d | 184 | |
3f3333f8 CK |
185 | spin_lock(&glob->lru_lock); |
186 | ttm_bo_move_to_lru_tail(&bo->tbo); | |
187 | if (bo->shadow) | |
188 | ttm_bo_move_to_lru_tail(&bo->shadow->tbo); | |
189 | spin_unlock(&glob->lru_lock); | |
190 | } | |
191 | ||
73fb16e7 CK |
192 | if (bo->tbo.type == ttm_bo_type_kernel && |
193 | vm->use_cpu_for_update) { | |
3f3333f8 CK |
194 | r = amdgpu_bo_kmap(bo, NULL); |
195 | if (r) | |
196 | return r; | |
197 | } | |
198 | ||
199 | spin_lock(&vm->status_lock); | |
73fb16e7 CK |
200 | if (bo->tbo.type != ttm_bo_type_kernel) |
201 | list_move(&bo_base->vm_status, &vm->moved); | |
202 | else | |
203 | list_move(&bo_base->vm_status, &vm->relocated); | |
3f3333f8 CK |
204 | } |
205 | spin_unlock(&vm->status_lock); | |
34d7be5d CK |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
210 | /** | |
211 | * amdgpu_vm_ready - check VM is ready for updates | |
212 | * | |
34d7be5d CK |
213 | * @vm: VM to check |
214 | * | |
215 | * Check if all VM PDs/PTs are ready for updates | |
216 | */ | |
3f3333f8 | 217 | bool amdgpu_vm_ready(struct amdgpu_vm *vm) |
34d7be5d | 218 | { |
3f3333f8 CK |
219 | bool ready; |
220 | ||
221 | spin_lock(&vm->status_lock); | |
222 | ready = list_empty(&vm->evicted); | |
223 | spin_unlock(&vm->status_lock); | |
34d7be5d | 224 | |
3f3333f8 | 225 | return ready; |
34d7be5d CK |
226 | } |
227 | ||
d711e139 | 228 | /** |
f566ceb1 CK |
229 | * amdgpu_vm_alloc_levels - allocate the PD/PT levels |
230 | * | |
231 | * @adev: amdgpu_device pointer | |
232 | * @vm: requested vm | |
233 | * @saddr: start of the address range | |
234 | * @eaddr: end of the address range | |
235 | * | |
236 | * Make sure the page directories and page tables are allocated | |
237 | */ | |
238 | static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, | |
239 | struct amdgpu_vm *vm, | |
240 | struct amdgpu_vm_pt *parent, | |
241 | uint64_t saddr, uint64_t eaddr, | |
242 | unsigned level) | |
243 | { | |
244 | unsigned shift = (adev->vm_manager.num_level - level) * | |
36b32a68 | 245 | adev->vm_manager.block_size; |
f566ceb1 CK |
246 | unsigned pt_idx, from, to; |
247 | int r; | |
3c824172 | 248 | u64 flags; |
51ac7eec | 249 | uint64_t init_value = 0; |
f566ceb1 CK |
250 | |
251 | if (!parent->entries) { | |
252 | unsigned num_entries = amdgpu_vm_num_entries(adev, level); | |
253 | ||
2098105e MH |
254 | parent->entries = kvmalloc_array(num_entries, |
255 | sizeof(struct amdgpu_vm_pt), | |
256 | GFP_KERNEL | __GFP_ZERO); | |
f566ceb1 CK |
257 | if (!parent->entries) |
258 | return -ENOMEM; | |
259 | memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt)); | |
260 | } | |
261 | ||
1866bac8 FK |
262 | from = saddr >> shift; |
263 | to = eaddr >> shift; | |
264 | if (from >= amdgpu_vm_num_entries(adev, level) || | |
265 | to >= amdgpu_vm_num_entries(adev, level)) | |
266 | return -EINVAL; | |
f566ceb1 CK |
267 | |
268 | if (to > parent->last_entry_used) | |
269 | parent->last_entry_used = to; | |
270 | ||
271 | ++level; | |
1866bac8 FK |
272 | saddr = saddr & ((1 << shift) - 1); |
273 | eaddr = eaddr & ((1 << shift) - 1); | |
f566ceb1 | 274 | |
3c824172 HK |
275 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
276 | AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
277 | if (vm->use_cpu_for_update) | |
278 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
279 | else | |
280 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
281 | AMDGPU_GEM_CREATE_SHADOW); | |
282 | ||
51ac7eec YZ |
283 | if (vm->pte_support_ats) { |
284 | init_value = AMDGPU_PTE_SYSTEM; | |
285 | if (level != adev->vm_manager.num_level - 1) | |
286 | init_value |= AMDGPU_PDE_PTE; | |
287 | } | |
288 | ||
f566ceb1 CK |
289 | /* walk over the address space and allocate the page tables */ |
290 | for (pt_idx = from; pt_idx <= to; ++pt_idx) { | |
3f3333f8 | 291 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
f566ceb1 CK |
292 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
293 | struct amdgpu_bo *pt; | |
294 | ||
3f3333f8 | 295 | if (!entry->base.bo) { |
f566ceb1 CK |
296 | r = amdgpu_bo_create(adev, |
297 | amdgpu_vm_bo_size(adev, level), | |
298 | AMDGPU_GPU_PAGE_SIZE, true, | |
299 | AMDGPU_GEM_DOMAIN_VRAM, | |
3c824172 | 300 | flags, |
51ac7eec | 301 | NULL, resv, init_value, &pt); |
f566ceb1 CK |
302 | if (r) |
303 | return r; | |
304 | ||
0a096fb6 CK |
305 | if (vm->use_cpu_for_update) { |
306 | r = amdgpu_bo_kmap(pt, NULL); | |
307 | if (r) { | |
308 | amdgpu_bo_unref(&pt); | |
309 | return r; | |
310 | } | |
311 | } | |
312 | ||
f566ceb1 CK |
313 | /* Keep a reference to the root directory to avoid |
314 | * freeing them up in the wrong order. | |
315 | */ | |
0f2fc435 | 316 | pt->parent = amdgpu_bo_ref(parent->base.bo); |
f566ceb1 | 317 | |
3f3333f8 CK |
318 | entry->base.vm = vm; |
319 | entry->base.bo = pt; | |
320 | list_add_tail(&entry->base.bo_list, &pt->va); | |
ea09729c CK |
321 | spin_lock(&vm->status_lock); |
322 | list_add(&entry->base.vm_status, &vm->relocated); | |
323 | spin_unlock(&vm->status_lock); | |
0f2fc435 | 324 | entry->addr = 0; |
f566ceb1 CK |
325 | } |
326 | ||
327 | if (level < adev->vm_manager.num_level) { | |
1866bac8 FK |
328 | uint64_t sub_saddr = (pt_idx == from) ? saddr : 0; |
329 | uint64_t sub_eaddr = (pt_idx == to) ? eaddr : | |
330 | ((1 << shift) - 1); | |
331 | r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr, | |
332 | sub_eaddr, level); | |
f566ceb1 CK |
333 | if (r) |
334 | return r; | |
335 | } | |
336 | } | |
337 | ||
338 | return 0; | |
339 | } | |
340 | ||
663e4577 CK |
341 | /** |
342 | * amdgpu_vm_alloc_pts - Allocate page tables. | |
343 | * | |
344 | * @adev: amdgpu_device pointer | |
345 | * @vm: VM to allocate page tables for | |
346 | * @saddr: Start address which needs to be allocated | |
347 | * @size: Size from start address we need. | |
348 | * | |
349 | * Make sure the page tables are allocated. | |
350 | */ | |
351 | int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, | |
352 | struct amdgpu_vm *vm, | |
353 | uint64_t saddr, uint64_t size) | |
354 | { | |
22770e5a | 355 | uint64_t last_pfn; |
663e4577 | 356 | uint64_t eaddr; |
663e4577 CK |
357 | |
358 | /* validate the parameters */ | |
359 | if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK) | |
360 | return -EINVAL; | |
361 | ||
362 | eaddr = saddr + size - 1; | |
363 | last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; | |
364 | if (last_pfn >= adev->vm_manager.max_pfn) { | |
22770e5a | 365 | dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n", |
663e4577 CK |
366 | last_pfn, adev->vm_manager.max_pfn); |
367 | return -EINVAL; | |
368 | } | |
369 | ||
370 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
371 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
372 | ||
f566ceb1 | 373 | return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr, 0); |
663e4577 CK |
374 | } |
375 | ||
641e9400 CK |
376 | /** |
377 | * amdgpu_vm_had_gpu_reset - check if reset occured since last use | |
378 | * | |
379 | * @adev: amdgpu_device pointer | |
380 | * @id: VMID structure | |
381 | * | |
382 | * Check if GPU reset occured since last use of the VMID. | |
383 | */ | |
384 | static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev, | |
385 | struct amdgpu_vm_id *id) | |
192b7dcb CZ |
386 | { |
387 | return id->current_gpu_reset_count != | |
641e9400 | 388 | atomic_read(&adev->gpu_reset_counter); |
192b7dcb CZ |
389 | } |
390 | ||
7a63eb23 CZ |
391 | static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub) |
392 | { | |
393 | return !!vm->reserved_vmid[vmhub]; | |
394 | } | |
395 | ||
396 | /* idr_mgr->lock must be held */ | |
397 | static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, | |
398 | struct amdgpu_ring *ring, | |
399 | struct amdgpu_sync *sync, | |
400 | struct dma_fence *fence, | |
401 | struct amdgpu_job *job) | |
402 | { | |
403 | struct amdgpu_device *adev = ring->adev; | |
404 | unsigned vmhub = ring->funcs->vmhub; | |
405 | uint64_t fence_context = adev->fence_context + ring->idx; | |
406 | struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub]; | |
407 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
408 | struct dma_fence *updates = sync->last_vm_update; | |
409 | int r = 0; | |
410 | struct dma_fence *flushed, *tmp; | |
6f1ceabb | 411 | bool needs_flush = vm->use_cpu_for_update; |
7a63eb23 CZ |
412 | |
413 | flushed = id->flushed_updates; | |
414 | if ((amdgpu_vm_had_gpu_reset(adev, id)) || | |
415 | (atomic64_read(&id->owner) != vm->client_id) || | |
416 | (job->vm_pd_addr != id->pd_gpu_addr) || | |
417 | (updates && (!flushed || updates->context != flushed->context || | |
418 | dma_fence_is_later(updates, flushed))) || | |
419 | (!id->last_flush || (id->last_flush->context != fence_context && | |
420 | !dma_fence_is_signaled(id->last_flush)))) { | |
421 | needs_flush = true; | |
422 | /* to prevent one context starved by another context */ | |
423 | id->pd_gpu_addr = 0; | |
424 | tmp = amdgpu_sync_peek_fence(&id->active, ring); | |
425 | if (tmp) { | |
426 | r = amdgpu_sync_fence(adev, sync, tmp); | |
427 | return r; | |
428 | } | |
429 | } | |
430 | ||
431 | /* Good we can use this VMID. Remember this submission as | |
432 | * user of the VMID. | |
433 | */ | |
434 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
435 | if (r) | |
436 | goto out; | |
437 | ||
438 | if (updates && (!flushed || updates->context != flushed->context || | |
439 | dma_fence_is_later(updates, flushed))) { | |
440 | dma_fence_put(id->flushed_updates); | |
441 | id->flushed_updates = dma_fence_get(updates); | |
442 | } | |
443 | id->pd_gpu_addr = job->vm_pd_addr; | |
7a63eb23 CZ |
444 | atomic64_set(&id->owner, vm->client_id); |
445 | job->vm_needs_flush = needs_flush; | |
446 | if (needs_flush) { | |
447 | dma_fence_put(id->last_flush); | |
448 | id->last_flush = NULL; | |
449 | } | |
450 | job->vm_id = id - id_mgr->ids; | |
451 | trace_amdgpu_vm_grab_id(vm, ring, job); | |
452 | out: | |
453 | return r; | |
454 | } | |
455 | ||
d38ceaf9 AD |
456 | /** |
457 | * amdgpu_vm_grab_id - allocate the next free VMID | |
458 | * | |
d38ceaf9 | 459 | * @vm: vm to allocate id for |
7f8a5290 CK |
460 | * @ring: ring we want to submit job to |
461 | * @sync: sync object where we add dependencies | |
94dd0a4a | 462 | * @fence: fence protecting ID from reuse |
d38ceaf9 | 463 | * |
7f8a5290 | 464 | * Allocate an id for the vm, adding fences to the sync obj as necessary. |
d38ceaf9 | 465 | */ |
7f8a5290 | 466 | int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, |
f54d1867 | 467 | struct amdgpu_sync *sync, struct dma_fence *fence, |
fd53be30 | 468 | struct amdgpu_job *job) |
d38ceaf9 | 469 | { |
d38ceaf9 | 470 | struct amdgpu_device *adev = ring->adev; |
2e819849 | 471 | unsigned vmhub = ring->funcs->vmhub; |
7645670d | 472 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
090b767e | 473 | uint64_t fence_context = adev->fence_context + ring->idx; |
f54d1867 | 474 | struct dma_fence *updates = sync->last_vm_update; |
8d76001e | 475 | struct amdgpu_vm_id *id, *idle; |
f54d1867 | 476 | struct dma_fence **fences; |
1fbb2e92 CK |
477 | unsigned i; |
478 | int r = 0; | |
479 | ||
7a63eb23 CZ |
480 | mutex_lock(&id_mgr->lock); |
481 | if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) { | |
482 | r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job); | |
483 | mutex_unlock(&id_mgr->lock); | |
484 | return r; | |
485 | } | |
7645670d | 486 | fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); |
7a63eb23 CZ |
487 | if (!fences) { |
488 | mutex_unlock(&id_mgr->lock); | |
1fbb2e92 | 489 | return -ENOMEM; |
7a63eb23 | 490 | } |
36fd7c5c | 491 | /* Check if we have an idle VMID */ |
1fbb2e92 | 492 | i = 0; |
7645670d | 493 | list_for_each_entry(idle, &id_mgr->ids_lru, list) { |
1fbb2e92 CK |
494 | fences[i] = amdgpu_sync_peek_fence(&idle->active, ring); |
495 | if (!fences[i]) | |
36fd7c5c | 496 | break; |
1fbb2e92 | 497 | ++i; |
36fd7c5c CK |
498 | } |
499 | ||
1fbb2e92 | 500 | /* If we can't find a idle VMID to use, wait till one becomes available */ |
7645670d | 501 | if (&idle->list == &id_mgr->ids_lru) { |
1fbb2e92 CK |
502 | u64 fence_context = adev->vm_manager.fence_context + ring->idx; |
503 | unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; | |
f54d1867 | 504 | struct dma_fence_array *array; |
1fbb2e92 CK |
505 | unsigned j; |
506 | ||
507 | for (j = 0; j < i; ++j) | |
f54d1867 | 508 | dma_fence_get(fences[j]); |
1fbb2e92 | 509 | |
f54d1867 | 510 | array = dma_fence_array_create(i, fences, fence_context, |
1fbb2e92 CK |
511 | seqno, true); |
512 | if (!array) { | |
513 | for (j = 0; j < i; ++j) | |
f54d1867 | 514 | dma_fence_put(fences[j]); |
1fbb2e92 CK |
515 | kfree(fences); |
516 | r = -ENOMEM; | |
517 | goto error; | |
518 | } | |
519 | ||
520 | ||
521 | r = amdgpu_sync_fence(ring->adev, sync, &array->base); | |
f54d1867 | 522 | dma_fence_put(&array->base); |
1fbb2e92 CK |
523 | if (r) |
524 | goto error; | |
525 | ||
7645670d | 526 | mutex_unlock(&id_mgr->lock); |
1fbb2e92 CK |
527 | return 0; |
528 | ||
529 | } | |
530 | kfree(fences); | |
531 | ||
6f1ceabb | 532 | job->vm_needs_flush = vm->use_cpu_for_update; |
1fbb2e92 | 533 | /* Check if we can use a VMID already assigned to this VM */ |
7645670d | 534 | list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) { |
f54d1867 | 535 | struct dma_fence *flushed; |
6f1ceabb | 536 | bool needs_flush = vm->use_cpu_for_update; |
1fbb2e92 | 537 | |
1fbb2e92 | 538 | /* Check all the prerequisites to using this VMID */ |
641e9400 | 539 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
6adb0513 | 540 | continue; |
1fbb2e92 CK |
541 | |
542 | if (atomic64_read(&id->owner) != vm->client_id) | |
543 | continue; | |
544 | ||
fd53be30 | 545 | if (job->vm_pd_addr != id->pd_gpu_addr) |
1fbb2e92 CK |
546 | continue; |
547 | ||
87c910d8 CK |
548 | if (!id->last_flush || |
549 | (id->last_flush->context != fence_context && | |
550 | !dma_fence_is_signaled(id->last_flush))) | |
551 | needs_flush = true; | |
1fbb2e92 CK |
552 | |
553 | flushed = id->flushed_updates; | |
87c910d8 CK |
554 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) |
555 | needs_flush = true; | |
556 | ||
557 | /* Concurrent flushes are only possible starting with Vega10 */ | |
558 | if (adev->asic_type < CHIP_VEGA10 && needs_flush) | |
1fbb2e92 CK |
559 | continue; |
560 | ||
3dab83be CK |
561 | /* Good we can use this VMID. Remember this submission as |
562 | * user of the VMID. | |
563 | */ | |
1fbb2e92 CK |
564 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); |
565 | if (r) | |
566 | goto error; | |
8d76001e | 567 | |
87c910d8 CK |
568 | if (updates && (!flushed || dma_fence_is_later(updates, flushed))) { |
569 | dma_fence_put(id->flushed_updates); | |
570 | id->flushed_updates = dma_fence_get(updates); | |
571 | } | |
8d76001e | 572 | |
87c910d8 CK |
573 | if (needs_flush) |
574 | goto needs_flush; | |
575 | else | |
576 | goto no_flush_needed; | |
8d76001e | 577 | |
4f618e73 | 578 | }; |
8d76001e | 579 | |
1fbb2e92 CK |
580 | /* Still no ID to use? Then use the idle one found earlier */ |
581 | id = idle; | |
8e9fbeb5 | 582 | |
1fbb2e92 CK |
583 | /* Remember this submission as user of the VMID */ |
584 | r = amdgpu_sync_fence(ring->adev, &id->active, fence); | |
832a902f CK |
585 | if (r) |
586 | goto error; | |
94dd0a4a | 587 | |
87c910d8 | 588 | id->pd_gpu_addr = job->vm_pd_addr; |
f54d1867 CW |
589 | dma_fence_put(id->flushed_updates); |
590 | id->flushed_updates = dma_fence_get(updates); | |
0ea54b9b | 591 | atomic64_set(&id->owner, vm->client_id); |
d38ceaf9 | 592 | |
87c910d8 CK |
593 | needs_flush: |
594 | job->vm_needs_flush = true; | |
595 | dma_fence_put(id->last_flush); | |
596 | id->last_flush = NULL; | |
597 | ||
598 | no_flush_needed: | |
599 | list_move_tail(&id->list, &id_mgr->ids_lru); | |
600 | ||
7645670d | 601 | job->vm_id = id - id_mgr->ids; |
c5296d14 | 602 | trace_amdgpu_vm_grab_id(vm, ring, job); |
832a902f CK |
603 | |
604 | error: | |
7645670d | 605 | mutex_unlock(&id_mgr->lock); |
a9a78b32 | 606 | return r; |
d38ceaf9 AD |
607 | } |
608 | ||
1e9ef26f CZ |
609 | static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev, |
610 | struct amdgpu_vm *vm, | |
611 | unsigned vmhub) | |
612 | { | |
613 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
614 | ||
615 | mutex_lock(&id_mgr->lock); | |
616 | if (vm->reserved_vmid[vmhub]) { | |
617 | list_add(&vm->reserved_vmid[vmhub]->list, | |
618 | &id_mgr->ids_lru); | |
619 | vm->reserved_vmid[vmhub] = NULL; | |
c3505770 | 620 | atomic_dec(&id_mgr->reserved_vmid_num); |
1e9ef26f CZ |
621 | } |
622 | mutex_unlock(&id_mgr->lock); | |
623 | } | |
624 | ||
625 | static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev, | |
626 | struct amdgpu_vm *vm, | |
627 | unsigned vmhub) | |
628 | { | |
629 | struct amdgpu_vm_id_manager *id_mgr; | |
630 | struct amdgpu_vm_id *idle; | |
631 | int r = 0; | |
632 | ||
633 | id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
634 | mutex_lock(&id_mgr->lock); | |
635 | if (vm->reserved_vmid[vmhub]) | |
636 | goto unlock; | |
c3505770 CZ |
637 | if (atomic_inc_return(&id_mgr->reserved_vmid_num) > |
638 | AMDGPU_VM_MAX_RESERVED_VMID) { | |
639 | DRM_ERROR("Over limitation of reserved vmid\n"); | |
640 | atomic_dec(&id_mgr->reserved_vmid_num); | |
641 | r = -EINVAL; | |
642 | goto unlock; | |
643 | } | |
1e9ef26f CZ |
644 | /* Select the first entry VMID */ |
645 | idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list); | |
646 | list_del_init(&idle->list); | |
647 | vm->reserved_vmid[vmhub] = idle; | |
648 | mutex_unlock(&id_mgr->lock); | |
649 | ||
650 | return 0; | |
651 | unlock: | |
652 | mutex_unlock(&id_mgr->lock); | |
653 | return r; | |
654 | } | |
655 | ||
e59c0205 AX |
656 | /** |
657 | * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug | |
658 | * | |
659 | * @adev: amdgpu_device pointer | |
660 | */ | |
661 | void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) | |
93dcc37d | 662 | { |
a1255107 | 663 | const struct amdgpu_ip_block *ip_block; |
e59c0205 AX |
664 | bool has_compute_vm_bug; |
665 | struct amdgpu_ring *ring; | |
666 | int i; | |
93dcc37d | 667 | |
e59c0205 | 668 | has_compute_vm_bug = false; |
93dcc37d AD |
669 | |
670 | ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); | |
e59c0205 AX |
671 | if (ip_block) { |
672 | /* Compute has a VM bug for GFX version < 7. | |
673 | Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ | |
674 | if (ip_block->version->major <= 7) | |
675 | has_compute_vm_bug = true; | |
676 | else if (ip_block->version->major == 8) | |
677 | if (adev->gfx.mec_fw_version < 673) | |
678 | has_compute_vm_bug = true; | |
679 | } | |
93dcc37d | 680 | |
e59c0205 AX |
681 | for (i = 0; i < adev->num_rings; i++) { |
682 | ring = adev->rings[i]; | |
683 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) | |
684 | /* only compute rings */ | |
685 | ring->has_compute_vm_bug = has_compute_vm_bug; | |
93dcc37d | 686 | else |
e59c0205 | 687 | ring->has_compute_vm_bug = false; |
93dcc37d | 688 | } |
93dcc37d AD |
689 | } |
690 | ||
b9bf33d5 CZ |
691 | bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, |
692 | struct amdgpu_job *job) | |
e60f8db5 | 693 | { |
b9bf33d5 CZ |
694 | struct amdgpu_device *adev = ring->adev; |
695 | unsigned vmhub = ring->funcs->vmhub; | |
696 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
697 | struct amdgpu_vm_id *id; | |
698 | bool gds_switch_needed; | |
e59c0205 | 699 | bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug; |
b9bf33d5 CZ |
700 | |
701 | if (job->vm_id == 0) | |
702 | return false; | |
703 | id = &id_mgr->ids[job->vm_id]; | |
704 | gds_switch_needed = ring->funcs->emit_gds_switch && ( | |
705 | id->gds_base != job->gds_base || | |
706 | id->gds_size != job->gds_size || | |
707 | id->gws_base != job->gws_base || | |
708 | id->gws_size != job->gws_size || | |
709 | id->oa_base != job->oa_base || | |
710 | id->oa_size != job->oa_size); | |
e60f8db5 | 711 | |
b9bf33d5 CZ |
712 | if (amdgpu_vm_had_gpu_reset(adev, id)) |
713 | return true; | |
e60f8db5 | 714 | |
bb37b67d | 715 | return vm_flush_needed || gds_switch_needed; |
b9bf33d5 CZ |
716 | } |
717 | ||
9a4b7d4c HK |
718 | static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) |
719 | { | |
720 | return (adev->mc.real_vram_size == adev->mc.visible_vram_size); | |
e60f8db5 AX |
721 | } |
722 | ||
d38ceaf9 AD |
723 | /** |
724 | * amdgpu_vm_flush - hardware flush the vm | |
725 | * | |
726 | * @ring: ring to use for flush | |
cffadc83 | 727 | * @vm_id: vmid number to use |
4ff37a83 | 728 | * @pd_addr: address of the page directory |
d38ceaf9 | 729 | * |
4ff37a83 | 730 | * Emit a VM flush when it is necessary. |
d38ceaf9 | 731 | */ |
8fdf074f | 732 | int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync) |
d38ceaf9 | 733 | { |
971fe9a9 | 734 | struct amdgpu_device *adev = ring->adev; |
7645670d CK |
735 | unsigned vmhub = ring->funcs->vmhub; |
736 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; | |
737 | struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id]; | |
d564a06e | 738 | bool gds_switch_needed = ring->funcs->emit_gds_switch && ( |
fd53be30 CZ |
739 | id->gds_base != job->gds_base || |
740 | id->gds_size != job->gds_size || | |
741 | id->gws_base != job->gws_base || | |
742 | id->gws_size != job->gws_size || | |
743 | id->oa_base != job->oa_base || | |
744 | id->oa_size != job->oa_size); | |
de37e68a | 745 | bool vm_flush_needed = job->vm_needs_flush; |
c0e51931 | 746 | unsigned patch_offset = 0; |
41d9eb2c | 747 | int r; |
d564a06e | 748 | |
f7d015b9 CK |
749 | if (amdgpu_vm_had_gpu_reset(adev, id)) { |
750 | gds_switch_needed = true; | |
751 | vm_flush_needed = true; | |
752 | } | |
971fe9a9 | 753 | |
8fdf074f | 754 | if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) |
f7d015b9 | 755 | return 0; |
41d9eb2c | 756 | |
c0e51931 CK |
757 | if (ring->funcs->init_cond_exec) |
758 | patch_offset = amdgpu_ring_init_cond_exec(ring); | |
41d9eb2c | 759 | |
8fdf074f ML |
760 | if (need_pipe_sync) |
761 | amdgpu_ring_emit_pipeline_sync(ring); | |
762 | ||
f7d015b9 | 763 | if (ring->funcs->emit_vm_flush && vm_flush_needed) { |
c0e51931 | 764 | struct dma_fence *fence; |
41d9eb2c | 765 | |
9a94f5a5 CK |
766 | trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr); |
767 | amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr); | |
e9d672b2 | 768 | |
c0e51931 CK |
769 | r = amdgpu_fence_emit(ring, &fence); |
770 | if (r) | |
771 | return r; | |
e9d672b2 | 772 | |
7645670d | 773 | mutex_lock(&id_mgr->lock); |
c0e51931 CK |
774 | dma_fence_put(id->last_flush); |
775 | id->last_flush = fence; | |
bea39672 | 776 | id->current_gpu_reset_count = atomic_read(&adev->gpu_reset_counter); |
7645670d | 777 | mutex_unlock(&id_mgr->lock); |
c0e51931 | 778 | } |
e9d672b2 | 779 | |
7c4378f4 | 780 | if (ring->funcs->emit_gds_switch && gds_switch_needed) { |
c0e51931 CK |
781 | id->gds_base = job->gds_base; |
782 | id->gds_size = job->gds_size; | |
783 | id->gws_base = job->gws_base; | |
784 | id->gws_size = job->gws_size; | |
785 | id->oa_base = job->oa_base; | |
786 | id->oa_size = job->oa_size; | |
787 | amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base, | |
788 | job->gds_size, job->gws_base, | |
789 | job->gws_size, job->oa_base, | |
790 | job->oa_size); | |
791 | } | |
792 | ||
793 | if (ring->funcs->patch_cond_exec) | |
794 | amdgpu_ring_patch_cond_exec(ring, patch_offset); | |
795 | ||
796 | /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */ | |
797 | if (ring->funcs->emit_switch_buffer) { | |
798 | amdgpu_ring_emit_switch_buffer(ring); | |
799 | amdgpu_ring_emit_switch_buffer(ring); | |
e9d672b2 | 800 | } |
41d9eb2c | 801 | return 0; |
971fe9a9 CK |
802 | } |
803 | ||
804 | /** | |
805 | * amdgpu_vm_reset_id - reset VMID to zero | |
806 | * | |
807 | * @adev: amdgpu device structure | |
808 | * @vm_id: vmid number to use | |
809 | * | |
810 | * Reset saved GDW, GWS and OA to force switch on next flush. | |
811 | */ | |
7645670d CK |
812 | void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, |
813 | unsigned vmid) | |
971fe9a9 | 814 | { |
7645670d CK |
815 | struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub]; |
816 | struct amdgpu_vm_id *id = &id_mgr->ids[vmid]; | |
bcb1ba35 | 817 | |
b3c85a0f | 818 | atomic64_set(&id->owner, 0); |
bcb1ba35 CK |
819 | id->gds_base = 0; |
820 | id->gds_size = 0; | |
821 | id->gws_base = 0; | |
822 | id->gws_size = 0; | |
823 | id->oa_base = 0; | |
824 | id->oa_size = 0; | |
d38ceaf9 AD |
825 | } |
826 | ||
b3c85a0f CK |
827 | /** |
828 | * amdgpu_vm_reset_all_id - reset VMID to zero | |
829 | * | |
830 | * @adev: amdgpu device structure | |
831 | * | |
832 | * Reset VMID to force flush on next use | |
833 | */ | |
834 | void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev) | |
835 | { | |
836 | unsigned i, j; | |
837 | ||
838 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
839 | struct amdgpu_vm_id_manager *id_mgr = | |
840 | &adev->vm_manager.id_mgr[i]; | |
841 | ||
842 | for (j = 1; j < id_mgr->num_ids; ++j) | |
843 | amdgpu_vm_reset_id(adev, i, j); | |
844 | } | |
845 | } | |
846 | ||
d38ceaf9 AD |
847 | /** |
848 | * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo | |
849 | * | |
850 | * @vm: requested vm | |
851 | * @bo: requested buffer object | |
852 | * | |
8843dbbb | 853 | * Find @bo inside the requested vm. |
d38ceaf9 AD |
854 | * Search inside the @bos vm list for the requested vm |
855 | * Returns the found bo_va or NULL if none is found | |
856 | * | |
857 | * Object has to be reserved! | |
858 | */ | |
859 | struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, | |
860 | struct amdgpu_bo *bo) | |
861 | { | |
862 | struct amdgpu_bo_va *bo_va; | |
863 | ||
ec681545 CK |
864 | list_for_each_entry(bo_va, &bo->va, base.bo_list) { |
865 | if (bo_va->base.vm == vm) { | |
d38ceaf9 AD |
866 | return bo_va; |
867 | } | |
868 | } | |
869 | return NULL; | |
870 | } | |
871 | ||
872 | /** | |
afef8b8f | 873 | * amdgpu_vm_do_set_ptes - helper to call the right asic function |
d38ceaf9 | 874 | * |
29efc4f5 | 875 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
876 | * @pe: addr of the page entry |
877 | * @addr: dst addr to write into pe | |
878 | * @count: number of page entries to update | |
879 | * @incr: increase next addr by incr bytes | |
880 | * @flags: hw access flags | |
d38ceaf9 AD |
881 | * |
882 | * Traces the parameters and calls the right asic functions | |
883 | * to setup the page table using the DMA. | |
884 | */ | |
afef8b8f CK |
885 | static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params, |
886 | uint64_t pe, uint64_t addr, | |
887 | unsigned count, uint32_t incr, | |
6b777607 | 888 | uint64_t flags) |
d38ceaf9 | 889 | { |
ec2f05f0 | 890 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
d38ceaf9 | 891 | |
afef8b8f | 892 | if (count < 3) { |
de9ea7bd CK |
893 | amdgpu_vm_write_pte(params->adev, params->ib, pe, |
894 | addr | flags, count, incr); | |
d38ceaf9 AD |
895 | |
896 | } else { | |
27c5f36f | 897 | amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr, |
d38ceaf9 AD |
898 | count, incr, flags); |
899 | } | |
900 | } | |
901 | ||
afef8b8f CK |
902 | /** |
903 | * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART | |
904 | * | |
905 | * @params: see amdgpu_pte_update_params definition | |
906 | * @pe: addr of the page entry | |
907 | * @addr: dst addr to write into pe | |
908 | * @count: number of page entries to update | |
909 | * @incr: increase next addr by incr bytes | |
910 | * @flags: hw access flags | |
911 | * | |
912 | * Traces the parameters and calls the DMA function to copy the PTEs. | |
913 | */ | |
914 | static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params, | |
915 | uint64_t pe, uint64_t addr, | |
916 | unsigned count, uint32_t incr, | |
6b777607 | 917 | uint64_t flags) |
afef8b8f | 918 | { |
ec2f05f0 | 919 | uint64_t src = (params->src + (addr >> 12) * 8); |
afef8b8f | 920 | |
ec2f05f0 CK |
921 | |
922 | trace_amdgpu_vm_copy_ptes(pe, src, count); | |
923 | ||
924 | amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count); | |
afef8b8f CK |
925 | } |
926 | ||
d38ceaf9 | 927 | /** |
b07c9d2a | 928 | * amdgpu_vm_map_gart - Resolve gart mapping of addr |
d38ceaf9 | 929 | * |
b07c9d2a | 930 | * @pages_addr: optional DMA address to use for lookup |
d38ceaf9 AD |
931 | * @addr: the unmapped addr |
932 | * | |
933 | * Look up the physical address of the page that the pte resolves | |
b07c9d2a | 934 | * to and return the pointer for the page table entry. |
d38ceaf9 | 935 | */ |
de9ea7bd | 936 | static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr) |
d38ceaf9 AD |
937 | { |
938 | uint64_t result; | |
939 | ||
de9ea7bd CK |
940 | /* page table offset */ |
941 | result = pages_addr[addr >> PAGE_SHIFT]; | |
b07c9d2a | 942 | |
de9ea7bd CK |
943 | /* in case cpu page size != gpu page size*/ |
944 | result |= addr & (~PAGE_MASK); | |
d38ceaf9 | 945 | |
b07c9d2a | 946 | result &= 0xFFFFFFFFFFFFF000ULL; |
d38ceaf9 AD |
947 | |
948 | return result; | |
949 | } | |
950 | ||
3c824172 HK |
951 | /** |
952 | * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU | |
953 | * | |
954 | * @params: see amdgpu_pte_update_params definition | |
955 | * @pe: kmap addr of the page entry | |
956 | * @addr: dst addr to write into pe | |
957 | * @count: number of page entries to update | |
958 | * @incr: increase next addr by incr bytes | |
959 | * @flags: hw access flags | |
960 | * | |
961 | * Write count number of PT/PD entries directly. | |
962 | */ | |
963 | static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, | |
964 | uint64_t pe, uint64_t addr, | |
965 | unsigned count, uint32_t incr, | |
966 | uint64_t flags) | |
967 | { | |
968 | unsigned int i; | |
b4d42511 | 969 | uint64_t value; |
3c824172 | 970 | |
03918b36 CK |
971 | trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags); |
972 | ||
3c824172 | 973 | for (i = 0; i < count; i++) { |
b4d42511 HK |
974 | value = params->pages_addr ? |
975 | amdgpu_vm_map_gart(params->pages_addr, addr) : | |
976 | addr; | |
a1924005 | 977 | amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe, |
b4d42511 | 978 | i, value, flags); |
3c824172 HK |
979 | addr += incr; |
980 | } | |
3c824172 HK |
981 | } |
982 | ||
a33cab7a CK |
983 | static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
984 | void *owner) | |
3c824172 HK |
985 | { |
986 | struct amdgpu_sync sync; | |
987 | int r; | |
988 | ||
989 | amdgpu_sync_create(&sync); | |
3f3333f8 | 990 | amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner); |
3c824172 HK |
991 | r = amdgpu_sync_wait(&sync, true); |
992 | amdgpu_sync_free(&sync); | |
993 | ||
994 | return r; | |
995 | } | |
996 | ||
f8991bab | 997 | /* |
194d2161 | 998 | * amdgpu_vm_update_level - update a single level in the hierarchy |
f8991bab CK |
999 | * |
1000 | * @adev: amdgpu_device pointer | |
1001 | * @vm: requested vm | |
194d2161 | 1002 | * @parent: parent directory |
f8991bab | 1003 | * |
194d2161 | 1004 | * Makes sure all entries in @parent are up to date. |
f8991bab CK |
1005 | * Returns 0 for success, error for failure. |
1006 | */ | |
194d2161 CK |
1007 | static int amdgpu_vm_update_level(struct amdgpu_device *adev, |
1008 | struct amdgpu_vm *vm, | |
ea09729c | 1009 | struct amdgpu_vm_pt *parent) |
d38ceaf9 | 1010 | { |
f8991bab | 1011 | struct amdgpu_bo *shadow; |
a1924005 HK |
1012 | struct amdgpu_ring *ring = NULL; |
1013 | uint64_t pd_addr, shadow_addr = 0; | |
f8991bab | 1014 | uint64_t last_pde = ~0, last_pt = ~0, last_shadow = ~0; |
a1924005 | 1015 | unsigned count = 0, pt_idx, ndw = 0; |
d71518b5 | 1016 | struct amdgpu_job *job; |
29efc4f5 | 1017 | struct amdgpu_pte_update_params params; |
f54d1867 | 1018 | struct dma_fence *fence = NULL; |
ea09729c | 1019 | uint32_t incr; |
d5fc5e82 | 1020 | |
d38ceaf9 AD |
1021 | int r; |
1022 | ||
194d2161 CK |
1023 | if (!parent->entries) |
1024 | return 0; | |
2d55e45a | 1025 | |
3c824172 HK |
1026 | memset(¶ms, 0, sizeof(params)); |
1027 | params.adev = adev; | |
3f3333f8 | 1028 | shadow = parent->base.bo->shadow; |
d38ceaf9 | 1029 | |
69277985 | 1030 | if (vm->use_cpu_for_update) { |
3f3333f8 | 1031 | pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); |
a33cab7a | 1032 | r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM); |
0a096fb6 | 1033 | if (unlikely(r)) |
3c824172 | 1034 | return r; |
0a096fb6 | 1035 | |
3c824172 HK |
1036 | params.func = amdgpu_vm_cpu_set_ptes; |
1037 | } else { | |
3c824172 HK |
1038 | ring = container_of(vm->entity.sched, struct amdgpu_ring, |
1039 | sched); | |
d38ceaf9 | 1040 | |
3c824172 HK |
1041 | /* padding, etc. */ |
1042 | ndw = 64; | |
194d2161 | 1043 | |
3c824172 HK |
1044 | /* assume the worst case */ |
1045 | ndw += parent->last_entry_used * 6; | |
1046 | ||
3f3333f8 | 1047 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); |
3c824172 HK |
1048 | |
1049 | if (shadow) { | |
1050 | shadow_addr = amdgpu_bo_gpu_offset(shadow); | |
1051 | ndw *= 2; | |
1052 | } else { | |
1053 | shadow_addr = 0; | |
1054 | } | |
1055 | ||
1056 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); | |
f8991bab CK |
1057 | if (r) |
1058 | return r; | |
f8991bab | 1059 | |
3c824172 HK |
1060 | params.ib = &job->ibs[0]; |
1061 | params.func = amdgpu_vm_do_set_ptes; | |
1062 | } | |
d71518b5 | 1063 | |
d38ceaf9 | 1064 | |
194d2161 CK |
1065 | /* walk over the address space and update the directory */ |
1066 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
ea09729c CK |
1067 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; |
1068 | struct amdgpu_bo *bo = entry->base.bo; | |
d38ceaf9 AD |
1069 | uint64_t pde, pt; |
1070 | ||
1071 | if (bo == NULL) | |
1072 | continue; | |
1073 | ||
ea09729c CK |
1074 | spin_lock(&vm->status_lock); |
1075 | list_del_init(&entry->base.vm_status); | |
1076 | spin_unlock(&vm->status_lock); | |
1077 | ||
d38ceaf9 | 1078 | pt = amdgpu_bo_gpu_offset(bo); |
53e2e91d | 1079 | pt = amdgpu_gart_get_vm_pde(adev, pt); |
4ab4016a CK |
1080 | /* Don't update huge pages here */ |
1081 | if ((parent->entries[pt_idx].addr & AMDGPU_PDE_PTE) || | |
1082 | parent->entries[pt_idx].addr == (pt | AMDGPU_PTE_VALID)) | |
f8991bab CK |
1083 | continue; |
1084 | ||
4ab4016a | 1085 | parent->entries[pt_idx].addr = pt | AMDGPU_PTE_VALID; |
d38ceaf9 AD |
1086 | |
1087 | pde = pd_addr + pt_idx * 8; | |
ea09729c | 1088 | incr = amdgpu_bo_size(bo); |
d38ceaf9 | 1089 | if (((last_pde + 8 * count) != pde) || |
96105e53 CK |
1090 | ((last_pt + incr * count) != pt) || |
1091 | (count == AMDGPU_VM_MAX_UPDATE_SIZE)) { | |
d38ceaf9 AD |
1092 | |
1093 | if (count) { | |
f8991bab | 1094 | if (shadow) |
3c824172 HK |
1095 | params.func(¶ms, |
1096 | last_shadow, | |
1097 | last_pt, count, | |
1098 | incr, | |
1099 | AMDGPU_PTE_VALID); | |
1100 | ||
1101 | params.func(¶ms, last_pde, | |
1102 | last_pt, count, incr, | |
1103 | AMDGPU_PTE_VALID); | |
d38ceaf9 AD |
1104 | } |
1105 | ||
1106 | count = 1; | |
1107 | last_pde = pde; | |
f8991bab | 1108 | last_shadow = shadow_addr + pt_idx * 8; |
d38ceaf9 AD |
1109 | last_pt = pt; |
1110 | } else { | |
1111 | ++count; | |
1112 | } | |
1113 | } | |
1114 | ||
f8991bab | 1115 | if (count) { |
3f3333f8 | 1116 | if (vm->root.base.bo->shadow) |
3c824172 HK |
1117 | params.func(¶ms, last_shadow, last_pt, |
1118 | count, incr, AMDGPU_PTE_VALID); | |
f8991bab | 1119 | |
3c824172 HK |
1120 | params.func(¶ms, last_pde, last_pt, |
1121 | count, incr, AMDGPU_PTE_VALID); | |
f8991bab | 1122 | } |
d38ceaf9 | 1123 | |
0a096fb6 CK |
1124 | if (!vm->use_cpu_for_update) { |
1125 | if (params.ib->length_dw == 0) { | |
1126 | amdgpu_job_free(job); | |
1127 | } else { | |
1128 | amdgpu_ring_pad_ib(ring, params.ib); | |
3f3333f8 CK |
1129 | amdgpu_sync_resv(adev, &job->sync, |
1130 | parent->base.bo->tbo.resv, | |
194d2161 | 1131 | AMDGPU_FENCE_OWNER_VM); |
0a096fb6 CK |
1132 | if (shadow) |
1133 | amdgpu_sync_resv(adev, &job->sync, | |
1134 | shadow->tbo.resv, | |
1135 | AMDGPU_FENCE_OWNER_VM); | |
1136 | ||
1137 | WARN_ON(params.ib->length_dw > ndw); | |
1138 | r = amdgpu_job_submit(job, ring, &vm->entity, | |
1139 | AMDGPU_FENCE_OWNER_VM, &fence); | |
1140 | if (r) | |
1141 | goto error_free; | |
05906dec | 1142 | |
3f3333f8 | 1143 | amdgpu_bo_fence(parent->base.bo, fence, true); |
0a096fb6 CK |
1144 | dma_fence_put(vm->last_dir_update); |
1145 | vm->last_dir_update = dma_fence_get(fence); | |
1146 | dma_fence_put(fence); | |
1147 | } | |
194d2161 | 1148 | } |
d38ceaf9 AD |
1149 | |
1150 | return 0; | |
d5fc5e82 CZ |
1151 | |
1152 | error_free: | |
d71518b5 | 1153 | amdgpu_job_free(job); |
4af9f07c | 1154 | return r; |
d38ceaf9 AD |
1155 | } |
1156 | ||
92456b93 CK |
1157 | /* |
1158 | * amdgpu_vm_invalidate_level - mark all PD levels as invalid | |
1159 | * | |
1160 | * @parent: parent PD | |
1161 | * | |
1162 | * Mark all PD level as invalid after an error. | |
1163 | */ | |
ea09729c CK |
1164 | static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm, |
1165 | struct amdgpu_vm_pt *parent) | |
92456b93 CK |
1166 | { |
1167 | unsigned pt_idx; | |
1168 | ||
1169 | /* | |
1170 | * Recurse into the subdirectories. This recursion is harmless because | |
1171 | * we only have a maximum of 5 layers. | |
1172 | */ | |
1173 | for (pt_idx = 0; pt_idx <= parent->last_entry_used; ++pt_idx) { | |
1174 | struct amdgpu_vm_pt *entry = &parent->entries[pt_idx]; | |
1175 | ||
3f3333f8 | 1176 | if (!entry->base.bo) |
92456b93 CK |
1177 | continue; |
1178 | ||
1179 | entry->addr = ~0ULL; | |
ea09729c | 1180 | spin_lock(&vm->status_lock); |
481c2e94 CK |
1181 | if (list_empty(&entry->base.vm_status)) |
1182 | list_add(&entry->base.vm_status, &vm->relocated); | |
ea09729c CK |
1183 | spin_unlock(&vm->status_lock); |
1184 | amdgpu_vm_invalidate_level(vm, entry); | |
92456b93 CK |
1185 | } |
1186 | } | |
1187 | ||
194d2161 CK |
1188 | /* |
1189 | * amdgpu_vm_update_directories - make sure that all directories are valid | |
1190 | * | |
1191 | * @adev: amdgpu_device pointer | |
1192 | * @vm: requested vm | |
1193 | * | |
1194 | * Makes sure all directories are up to date. | |
1195 | * Returns 0 for success, error for failure. | |
1196 | */ | |
1197 | int amdgpu_vm_update_directories(struct amdgpu_device *adev, | |
1198 | struct amdgpu_vm *vm) | |
1199 | { | |
92456b93 CK |
1200 | int r; |
1201 | ||
ea09729c CK |
1202 | spin_lock(&vm->status_lock); |
1203 | while (!list_empty(&vm->relocated)) { | |
1204 | struct amdgpu_vm_bo_base *bo_base; | |
1205 | struct amdgpu_bo *bo; | |
1206 | ||
1207 | bo_base = list_first_entry(&vm->relocated, | |
1208 | struct amdgpu_vm_bo_base, | |
1209 | vm_status); | |
1210 | spin_unlock(&vm->status_lock); | |
1211 | ||
1212 | bo = bo_base->bo->parent; | |
1213 | if (bo) { | |
1214 | struct amdgpu_vm_bo_base *parent; | |
1215 | struct amdgpu_vm_pt *pt; | |
1216 | ||
1217 | parent = list_first_entry(&bo->va, | |
1218 | struct amdgpu_vm_bo_base, | |
1219 | bo_list); | |
1220 | pt = container_of(parent, struct amdgpu_vm_pt, base); | |
1221 | ||
1222 | r = amdgpu_vm_update_level(adev, vm, pt); | |
1223 | if (r) { | |
1224 | amdgpu_vm_invalidate_level(vm, &vm->root); | |
1225 | return r; | |
1226 | } | |
1227 | spin_lock(&vm->status_lock); | |
1228 | } else { | |
1229 | spin_lock(&vm->status_lock); | |
1230 | list_del_init(&bo_base->vm_status); | |
1231 | } | |
1232 | } | |
1233 | spin_unlock(&vm->status_lock); | |
92456b93 | 1234 | |
68c62306 CK |
1235 | if (vm->use_cpu_for_update) { |
1236 | /* Flush HDP */ | |
1237 | mb(); | |
1238 | amdgpu_gart_flush_gpu_tlb(adev, 0); | |
1239 | } | |
1240 | ||
92456b93 | 1241 | return r; |
194d2161 CK |
1242 | } |
1243 | ||
4e2cb640 | 1244 | /** |
cf2f0a37 | 1245 | * amdgpu_vm_find_entry - find the entry for an address |
4e2cb640 CK |
1246 | * |
1247 | * @p: see amdgpu_pte_update_params definition | |
1248 | * @addr: virtual address in question | |
cf2f0a37 AD |
1249 | * @entry: resulting entry or NULL |
1250 | * @parent: parent entry | |
4e2cb640 | 1251 | * |
cf2f0a37 | 1252 | * Find the vm_pt entry and it's parent for the given address. |
4e2cb640 | 1253 | */ |
cf2f0a37 AD |
1254 | void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, |
1255 | struct amdgpu_vm_pt **entry, | |
1256 | struct amdgpu_vm_pt **parent) | |
4e2cb640 | 1257 | { |
4e2cb640 CK |
1258 | unsigned idx, level = p->adev->vm_manager.num_level; |
1259 | ||
cf2f0a37 AD |
1260 | *parent = NULL; |
1261 | *entry = &p->vm->root; | |
1262 | while ((*entry)->entries) { | |
36b32a68 | 1263 | idx = addr >> (p->adev->vm_manager.block_size * level--); |
3f3333f8 | 1264 | idx %= amdgpu_bo_size((*entry)->base.bo) / 8; |
cf2f0a37 AD |
1265 | *parent = *entry; |
1266 | *entry = &(*entry)->entries[idx]; | |
4e2cb640 CK |
1267 | } |
1268 | ||
1269 | if (level) | |
cf2f0a37 AD |
1270 | *entry = NULL; |
1271 | } | |
1272 | ||
1273 | /** | |
1274 | * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages | |
1275 | * | |
1276 | * @p: see amdgpu_pte_update_params definition | |
1277 | * @entry: vm_pt entry to check | |
1278 | * @parent: parent entry | |
1279 | * @nptes: number of PTEs updated with this operation | |
1280 | * @dst: destination address where the PTEs should point to | |
1281 | * @flags: access flags fro the PTEs | |
1282 | * | |
1283 | * Check if we can update the PD with a huge page. | |
1284 | */ | |
ec5207c9 CK |
1285 | static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, |
1286 | struct amdgpu_vm_pt *entry, | |
1287 | struct amdgpu_vm_pt *parent, | |
1288 | unsigned nptes, uint64_t dst, | |
1289 | uint64_t flags) | |
cf2f0a37 AD |
1290 | { |
1291 | bool use_cpu_update = (p->func == amdgpu_vm_cpu_set_ptes); | |
1292 | uint64_t pd_addr, pde; | |
cf2f0a37 AD |
1293 | |
1294 | /* In the case of a mixed PT the PDE must point to it*/ | |
1295 | if (p->adev->asic_type < CHIP_VEGA10 || | |
1296 | nptes != AMDGPU_VM_PTE_COUNT(p->adev) || | |
38a8791a | 1297 | p->src || |
cf2f0a37 AD |
1298 | !(flags & AMDGPU_PTE_VALID)) { |
1299 | ||
3f3333f8 | 1300 | dst = amdgpu_bo_gpu_offset(entry->base.bo); |
cf2f0a37 AD |
1301 | dst = amdgpu_gart_get_vm_pde(p->adev, dst); |
1302 | flags = AMDGPU_PTE_VALID; | |
1303 | } else { | |
4ab4016a | 1304 | /* Set the huge page flag to stop scanning at this PDE */ |
cf2f0a37 AD |
1305 | flags |= AMDGPU_PDE_PTE; |
1306 | } | |
1307 | ||
4ab4016a | 1308 | if (entry->addr == (dst | flags)) |
ec5207c9 | 1309 | return; |
cf2f0a37 | 1310 | |
4ab4016a | 1311 | entry->addr = (dst | flags); |
cf2f0a37 AD |
1312 | |
1313 | if (use_cpu_update) { | |
38a8791a FK |
1314 | /* In case a huge page is replaced with a system |
1315 | * memory mapping, p->pages_addr != NULL and | |
1316 | * amdgpu_vm_cpu_set_ptes would try to translate dst | |
1317 | * through amdgpu_vm_map_gart. But dst is already a | |
1318 | * GPU address (of the page table). Disable | |
1319 | * amdgpu_vm_map_gart temporarily. | |
1320 | */ | |
1321 | dma_addr_t *tmp; | |
1322 | ||
1323 | tmp = p->pages_addr; | |
1324 | p->pages_addr = NULL; | |
1325 | ||
3f3333f8 | 1326 | pd_addr = (unsigned long)amdgpu_bo_kptr(parent->base.bo); |
cf2f0a37 AD |
1327 | pde = pd_addr + (entry - parent->entries) * 8; |
1328 | amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags); | |
38a8791a FK |
1329 | |
1330 | p->pages_addr = tmp; | |
cf2f0a37 | 1331 | } else { |
3f3333f8 CK |
1332 | if (parent->base.bo->shadow) { |
1333 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow); | |
cf2f0a37 AD |
1334 | pde = pd_addr + (entry - parent->entries) * 8; |
1335 | amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); | |
1336 | } | |
3f3333f8 | 1337 | pd_addr = amdgpu_bo_gpu_offset(parent->base.bo); |
cf2f0a37 AD |
1338 | pde = pd_addr + (entry - parent->entries) * 8; |
1339 | amdgpu_vm_do_set_ptes(p, pde, dst, 1, 0, flags); | |
1340 | } | |
4e2cb640 CK |
1341 | } |
1342 | ||
d38ceaf9 AD |
1343 | /** |
1344 | * amdgpu_vm_update_ptes - make sure that page tables are valid | |
1345 | * | |
29efc4f5 | 1346 | * @params: see amdgpu_pte_update_params definition |
d38ceaf9 AD |
1347 | * @vm: requested vm |
1348 | * @start: start of GPU address range | |
1349 | * @end: end of GPU address range | |
677131a1 | 1350 | * @dst: destination address to map to, the next dst inside the function |
d38ceaf9 AD |
1351 | * @flags: mapping flags |
1352 | * | |
8843dbbb | 1353 | * Update the page tables in the range @start - @end. |
cc28c4ed | 1354 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 | 1355 | */ |
cc28c4ed | 1356 | static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, |
a1e08d3b | 1357 | uint64_t start, uint64_t end, |
6b777607 | 1358 | uint64_t dst, uint64_t flags) |
d38ceaf9 | 1359 | { |
36b32a68 ZJ |
1360 | struct amdgpu_device *adev = params->adev; |
1361 | const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1; | |
31f6c1fe | 1362 | |
301654a4 | 1363 | uint64_t addr, pe_start; |
21718497 | 1364 | struct amdgpu_bo *pt; |
301654a4 | 1365 | unsigned nptes; |
370f092f | 1366 | bool use_cpu_update = (params->func == amdgpu_vm_cpu_set_ptes); |
d38ceaf9 AD |
1367 | |
1368 | /* walk over the address space and update the page tables */ | |
cf2f0a37 AD |
1369 | for (addr = start; addr < end; addr += nptes, |
1370 | dst += nptes * AMDGPU_GPU_PAGE_SIZE) { | |
1371 | struct amdgpu_vm_pt *entry, *parent; | |
1372 | ||
1373 | amdgpu_vm_get_entry(params, addr, &entry, &parent); | |
1374 | if (!entry) | |
1375 | return -ENOENT; | |
4e2cb640 | 1376 | |
d38ceaf9 AD |
1377 | if ((addr & ~mask) == (end & ~mask)) |
1378 | nptes = end - addr; | |
1379 | else | |
36b32a68 | 1380 | nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask); |
d38ceaf9 | 1381 | |
ec5207c9 CK |
1382 | amdgpu_vm_handle_huge_pages(params, entry, parent, |
1383 | nptes, dst, flags); | |
4ab4016a CK |
1384 | /* We don't need to update PTEs for huge pages */ |
1385 | if (entry->addr & AMDGPU_PDE_PTE) | |
cf2f0a37 AD |
1386 | continue; |
1387 | ||
3f3333f8 | 1388 | pt = entry->base.bo; |
370f092f | 1389 | if (use_cpu_update) { |
f5e1c740 | 1390 | pe_start = (unsigned long)amdgpu_bo_kptr(pt); |
dd0792c1 CK |
1391 | } else { |
1392 | if (pt->shadow) { | |
1393 | pe_start = amdgpu_bo_gpu_offset(pt->shadow); | |
1394 | pe_start += (addr & mask) * 8; | |
1395 | params->func(params, pe_start, dst, nptes, | |
1396 | AMDGPU_GPU_PAGE_SIZE, flags); | |
1397 | } | |
370f092f | 1398 | pe_start = amdgpu_bo_gpu_offset(pt); |
dd0792c1 | 1399 | } |
d38ceaf9 | 1400 | |
301654a4 | 1401 | pe_start += (addr & mask) * 8; |
301654a4 CK |
1402 | params->func(params, pe_start, dst, nptes, |
1403 | AMDGPU_GPU_PAGE_SIZE, flags); | |
d38ceaf9 AD |
1404 | } |
1405 | ||
cc28c4ed | 1406 | return 0; |
92696dd5 CK |
1407 | } |
1408 | ||
1409 | /* | |
1410 | * amdgpu_vm_frag_ptes - add fragment information to PTEs | |
1411 | * | |
1412 | * @params: see amdgpu_pte_update_params definition | |
1413 | * @vm: requested vm | |
1414 | * @start: first PTE to handle | |
1415 | * @end: last PTE to handle | |
1416 | * @dst: addr those PTEs should point to | |
1417 | * @flags: hw mapping flags | |
cc28c4ed | 1418 | * Returns 0 for success, -EINVAL for failure. |
92696dd5 | 1419 | */ |
cc28c4ed | 1420 | static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, |
92696dd5 | 1421 | uint64_t start, uint64_t end, |
6b777607 | 1422 | uint64_t dst, uint64_t flags) |
92696dd5 CK |
1423 | { |
1424 | /** | |
1425 | * The MC L1 TLB supports variable sized pages, based on a fragment | |
1426 | * field in the PTE. When this field is set to a non-zero value, page | |
1427 | * granularity is increased from 4KB to (1 << (12 + frag)). The PTE | |
1428 | * flags are considered valid for all PTEs within the fragment range | |
1429 | * and corresponding mappings are assumed to be physically contiguous. | |
1430 | * | |
1431 | * The L1 TLB can store a single PTE for the whole fragment, | |
1432 | * significantly increasing the space available for translation | |
1433 | * caching. This leads to large improvements in throughput when the | |
1434 | * TLB is under pressure. | |
1435 | * | |
1436 | * The L2 TLB distributes small and large fragments into two | |
1437 | * asymmetric partitions. The large fragment cache is significantly | |
1438 | * larger. Thus, we try to use large fragments wherever possible. | |
1439 | * Userspace can support this by aligning virtual base address and | |
1440 | * allocation size to the fragment size. | |
1441 | */ | |
6849d47c RH |
1442 | unsigned max_frag = params->adev->vm_manager.fragment_size; |
1443 | int r; | |
92696dd5 CK |
1444 | |
1445 | /* system pages are non continuously */ | |
6849d47c | 1446 | if (params->src || !(flags & AMDGPU_PTE_VALID)) |
cc28c4ed | 1447 | return amdgpu_vm_update_ptes(params, start, end, dst, flags); |
92696dd5 | 1448 | |
6849d47c RH |
1449 | while (start != end) { |
1450 | uint64_t frag_flags, frag_end; | |
1451 | unsigned frag; | |
1452 | ||
1453 | /* This intentionally wraps around if no bit is set */ | |
1454 | frag = min((unsigned)ffs(start) - 1, | |
1455 | (unsigned)fls64(end - start) - 1); | |
1456 | if (frag >= max_frag) { | |
1457 | frag_flags = AMDGPU_PTE_FRAG(max_frag); | |
1458 | frag_end = end & ~((1ULL << max_frag) - 1); | |
1459 | } else { | |
1460 | frag_flags = AMDGPU_PTE_FRAG(frag); | |
1461 | frag_end = start + (1 << frag); | |
1462 | } | |
1463 | ||
1464 | r = amdgpu_vm_update_ptes(params, start, frag_end, dst, | |
1465 | flags | frag_flags); | |
cc28c4ed HK |
1466 | if (r) |
1467 | return r; | |
92696dd5 | 1468 | |
6849d47c RH |
1469 | dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE; |
1470 | start = frag_end; | |
92696dd5 | 1471 | } |
6849d47c RH |
1472 | |
1473 | return 0; | |
d38ceaf9 AD |
1474 | } |
1475 | ||
d38ceaf9 AD |
1476 | /** |
1477 | * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table | |
1478 | * | |
1479 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1480 | * @exclusive: fence we need to sync to |
fa3ab3c7 | 1481 | * @pages_addr: DMA addresses to use for mapping |
d38ceaf9 | 1482 | * @vm: requested vm |
a14faa65 CK |
1483 | * @start: start of mapped range |
1484 | * @last: last mapped entry | |
1485 | * @flags: flags for the entries | |
d38ceaf9 | 1486 | * @addr: addr to set the area to |
d38ceaf9 AD |
1487 | * @fence: optional resulting fence |
1488 | * | |
a14faa65 | 1489 | * Fill in the page table entries between @start and @last. |
d38ceaf9 | 1490 | * Returns 0 for success, -EINVAL for failure. |
d38ceaf9 AD |
1491 | */ |
1492 | static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1493 | struct dma_fence *exclusive, |
fa3ab3c7 | 1494 | dma_addr_t *pages_addr, |
d38ceaf9 | 1495 | struct amdgpu_vm *vm, |
a14faa65 | 1496 | uint64_t start, uint64_t last, |
6b777607 | 1497 | uint64_t flags, uint64_t addr, |
f54d1867 | 1498 | struct dma_fence **fence) |
d38ceaf9 | 1499 | { |
2d55e45a | 1500 | struct amdgpu_ring *ring; |
a1e08d3b | 1501 | void *owner = AMDGPU_FENCE_OWNER_VM; |
d38ceaf9 | 1502 | unsigned nptes, ncmds, ndw; |
d71518b5 | 1503 | struct amdgpu_job *job; |
29efc4f5 | 1504 | struct amdgpu_pte_update_params params; |
f54d1867 | 1505 | struct dma_fence *f = NULL; |
d38ceaf9 AD |
1506 | int r; |
1507 | ||
afef8b8f CK |
1508 | memset(¶ms, 0, sizeof(params)); |
1509 | params.adev = adev; | |
49ac8a24 | 1510 | params.vm = vm; |
afef8b8f | 1511 | |
a33cab7a CK |
1512 | /* sync to everything on unmapping */ |
1513 | if (!(flags & AMDGPU_PTE_VALID)) | |
1514 | owner = AMDGPU_FENCE_OWNER_UNDEFINED; | |
1515 | ||
b4d42511 HK |
1516 | if (vm->use_cpu_for_update) { |
1517 | /* params.src is used as flag to indicate system Memory */ | |
1518 | if (pages_addr) | |
1519 | params.src = ~0; | |
1520 | ||
1521 | /* Wait for PT BOs to be free. PTs share the same resv. object | |
1522 | * as the root PD BO | |
1523 | */ | |
a33cab7a | 1524 | r = amdgpu_vm_wait_pd(adev, vm, owner); |
b4d42511 HK |
1525 | if (unlikely(r)) |
1526 | return r; | |
1527 | ||
1528 | params.func = amdgpu_vm_cpu_set_ptes; | |
1529 | params.pages_addr = pages_addr; | |
b4d42511 HK |
1530 | return amdgpu_vm_frag_ptes(¶ms, start, last + 1, |
1531 | addr, flags); | |
1532 | } | |
1533 | ||
2d55e45a | 1534 | ring = container_of(vm->entity.sched, struct amdgpu_ring, sched); |
27c5f36f | 1535 | |
a14faa65 | 1536 | nptes = last - start + 1; |
d38ceaf9 AD |
1537 | |
1538 | /* | |
1539 | * reserve space for one command every (1 << BLOCK_SIZE) | |
1540 | * entries or 2k dwords (whatever is smaller) | |
1541 | */ | |
36b32a68 | 1542 | ncmds = (nptes >> min(adev->vm_manager.block_size, 11u)) + 1; |
d38ceaf9 AD |
1543 | |
1544 | /* padding, etc. */ | |
1545 | ndw = 64; | |
1546 | ||
cf2f0a37 AD |
1547 | /* one PDE write for each huge page */ |
1548 | ndw += ((nptes >> adev->vm_manager.block_size) + 1) * 6; | |
1549 | ||
570144c6 | 1550 | if (pages_addr) { |
b0456f93 CK |
1551 | /* copy commands needed */ |
1552 | ndw += ncmds * 7; | |
d38ceaf9 | 1553 | |
b0456f93 | 1554 | /* and also PTEs */ |
d38ceaf9 AD |
1555 | ndw += nptes * 2; |
1556 | ||
afef8b8f CK |
1557 | params.func = amdgpu_vm_do_copy_ptes; |
1558 | ||
d38ceaf9 AD |
1559 | } else { |
1560 | /* set page commands needed */ | |
1561 | ndw += ncmds * 10; | |
1562 | ||
6849d47c RH |
1563 | /* extra commands for begin/end fragments */ |
1564 | ndw += 2 * 10 * adev->vm_manager.fragment_size; | |
afef8b8f CK |
1565 | |
1566 | params.func = amdgpu_vm_do_set_ptes; | |
d38ceaf9 AD |
1567 | } |
1568 | ||
d71518b5 CK |
1569 | r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job); |
1570 | if (r) | |
d38ceaf9 | 1571 | return r; |
d71518b5 | 1572 | |
29efc4f5 | 1573 | params.ib = &job->ibs[0]; |
d5fc5e82 | 1574 | |
570144c6 | 1575 | if (pages_addr) { |
b0456f93 CK |
1576 | uint64_t *pte; |
1577 | unsigned i; | |
1578 | ||
1579 | /* Put the PTEs at the end of the IB. */ | |
1580 | i = ndw - nptes * 2; | |
1581 | pte= (uint64_t *)&(job->ibs->ptr[i]); | |
1582 | params.src = job->ibs->gpu_addr + i * 4; | |
1583 | ||
1584 | for (i = 0; i < nptes; ++i) { | |
1585 | pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i * | |
1586 | AMDGPU_GPU_PAGE_SIZE); | |
1587 | pte[i] |= flags; | |
1588 | } | |
d7a4ac66 | 1589 | addr = 0; |
b0456f93 CK |
1590 | } |
1591 | ||
3cabaa54 CK |
1592 | r = amdgpu_sync_fence(adev, &job->sync, exclusive); |
1593 | if (r) | |
1594 | goto error_free; | |
1595 | ||
3f3333f8 | 1596 | r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv, |
a1e08d3b CK |
1597 | owner); |
1598 | if (r) | |
1599 | goto error_free; | |
d38ceaf9 | 1600 | |
3f3333f8 | 1601 | r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv); |
a1e08d3b CK |
1602 | if (r) |
1603 | goto error_free; | |
1604 | ||
cc28c4ed HK |
1605 | r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags); |
1606 | if (r) | |
1607 | goto error_free; | |
d38ceaf9 | 1608 | |
29efc4f5 CK |
1609 | amdgpu_ring_pad_ib(ring, params.ib); |
1610 | WARN_ON(params.ib->length_dw > ndw); | |
2bd9ccfa CK |
1611 | r = amdgpu_job_submit(job, ring, &vm->entity, |
1612 | AMDGPU_FENCE_OWNER_VM, &f); | |
4af9f07c CZ |
1613 | if (r) |
1614 | goto error_free; | |
d38ceaf9 | 1615 | |
3f3333f8 | 1616 | amdgpu_bo_fence(vm->root.base.bo, f, true); |
284710fa CK |
1617 | dma_fence_put(*fence); |
1618 | *fence = f; | |
d38ceaf9 | 1619 | return 0; |
d5fc5e82 CZ |
1620 | |
1621 | error_free: | |
d71518b5 | 1622 | amdgpu_job_free(job); |
ea09729c | 1623 | amdgpu_vm_invalidate_level(vm, &vm->root); |
4af9f07c | 1624 | return r; |
d38ceaf9 AD |
1625 | } |
1626 | ||
a14faa65 CK |
1627 | /** |
1628 | * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks | |
1629 | * | |
1630 | * @adev: amdgpu_device pointer | |
3cabaa54 | 1631 | * @exclusive: fence we need to sync to |
8358dcee | 1632 | * @pages_addr: DMA addresses to use for mapping |
a14faa65 CK |
1633 | * @vm: requested vm |
1634 | * @mapping: mapped range and flags to use for the update | |
8358dcee | 1635 | * @flags: HW flags for the mapping |
63e0ba40 | 1636 | * @nodes: array of drm_mm_nodes with the MC addresses |
a14faa65 CK |
1637 | * @fence: optional resulting fence |
1638 | * | |
1639 | * Split the mapping into smaller chunks so that each update fits | |
1640 | * into a SDMA IB. | |
1641 | * Returns 0 for success, -EINVAL for failure. | |
1642 | */ | |
1643 | static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, | |
f54d1867 | 1644 | struct dma_fence *exclusive, |
8358dcee | 1645 | dma_addr_t *pages_addr, |
a14faa65 CK |
1646 | struct amdgpu_vm *vm, |
1647 | struct amdgpu_bo_va_mapping *mapping, | |
6b777607 | 1648 | uint64_t flags, |
63e0ba40 | 1649 | struct drm_mm_node *nodes, |
f54d1867 | 1650 | struct dma_fence **fence) |
a14faa65 | 1651 | { |
570144c6 | 1652 | uint64_t pfn, start = mapping->start; |
a14faa65 CK |
1653 | int r; |
1654 | ||
1655 | /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here | |
1656 | * but in case of something, we filter the flags in first place | |
1657 | */ | |
1658 | if (!(mapping->flags & AMDGPU_PTE_READABLE)) | |
1659 | flags &= ~AMDGPU_PTE_READABLE; | |
1660 | if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) | |
1661 | flags &= ~AMDGPU_PTE_WRITEABLE; | |
1662 | ||
15b31c59 AX |
1663 | flags &= ~AMDGPU_PTE_EXECUTABLE; |
1664 | flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; | |
1665 | ||
b0fd18b0 AX |
1666 | flags &= ~AMDGPU_PTE_MTYPE_MASK; |
1667 | flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK); | |
1668 | ||
d0766e98 ZJ |
1669 | if ((mapping->flags & AMDGPU_PTE_PRT) && |
1670 | (adev->asic_type >= CHIP_VEGA10)) { | |
1671 | flags |= AMDGPU_PTE_PRT; | |
1672 | flags &= ~AMDGPU_PTE_VALID; | |
1673 | } | |
1674 | ||
a14faa65 CK |
1675 | trace_amdgpu_vm_bo_update(mapping); |
1676 | ||
63e0ba40 CK |
1677 | pfn = mapping->offset >> PAGE_SHIFT; |
1678 | if (nodes) { | |
1679 | while (pfn >= nodes->size) { | |
1680 | pfn -= nodes->size; | |
1681 | ++nodes; | |
1682 | } | |
fa3ab3c7 | 1683 | } |
a14faa65 | 1684 | |
63e0ba40 CK |
1685 | do { |
1686 | uint64_t max_entries; | |
1687 | uint64_t addr, last; | |
a14faa65 | 1688 | |
63e0ba40 CK |
1689 | if (nodes) { |
1690 | addr = nodes->start << PAGE_SHIFT; | |
1691 | max_entries = (nodes->size - pfn) * | |
1692 | (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); | |
1693 | } else { | |
1694 | addr = 0; | |
1695 | max_entries = S64_MAX; | |
1696 | } | |
a14faa65 | 1697 | |
63e0ba40 | 1698 | if (pages_addr) { |
febb84a6 | 1699 | max_entries = min(max_entries, 16ull * 1024ull); |
63e0ba40 CK |
1700 | addr = 0; |
1701 | } else if (flags & AMDGPU_PTE_VALID) { | |
1702 | addr += adev->vm_manager.vram_base_offset; | |
1703 | } | |
1704 | addr += pfn << PAGE_SHIFT; | |
1705 | ||
a9f87f64 | 1706 | last = min((uint64_t)mapping->last, start + max_entries - 1); |
570144c6 | 1707 | r = amdgpu_vm_bo_update_mapping(adev, exclusive, pages_addr, vm, |
a14faa65 CK |
1708 | start, last, flags, addr, |
1709 | fence); | |
1710 | if (r) | |
1711 | return r; | |
1712 | ||
63e0ba40 CK |
1713 | pfn += last - start + 1; |
1714 | if (nodes && nodes->size == pfn) { | |
1715 | pfn = 0; | |
1716 | ++nodes; | |
1717 | } | |
a14faa65 | 1718 | start = last + 1; |
63e0ba40 | 1719 | |
a9f87f64 | 1720 | } while (unlikely(start != mapping->last + 1)); |
a14faa65 CK |
1721 | |
1722 | return 0; | |
1723 | } | |
1724 | ||
d38ceaf9 AD |
1725 | /** |
1726 | * amdgpu_vm_bo_update - update all BO mappings in the vm page table | |
1727 | * | |
1728 | * @adev: amdgpu_device pointer | |
1729 | * @bo_va: requested BO and VM object | |
99e124f4 | 1730 | * @clear: if true clear the entries |
d38ceaf9 AD |
1731 | * |
1732 | * Fill in the page table entries for @bo_va. | |
1733 | * Returns 0 for success, -EINVAL for failure. | |
d38ceaf9 AD |
1734 | */ |
1735 | int amdgpu_vm_bo_update(struct amdgpu_device *adev, | |
1736 | struct amdgpu_bo_va *bo_va, | |
99e124f4 | 1737 | bool clear) |
d38ceaf9 | 1738 | { |
ec681545 CK |
1739 | struct amdgpu_bo *bo = bo_va->base.bo; |
1740 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 1741 | struct amdgpu_bo_va_mapping *mapping; |
8358dcee | 1742 | dma_addr_t *pages_addr = NULL; |
99e124f4 | 1743 | struct ttm_mem_reg *mem; |
63e0ba40 | 1744 | struct drm_mm_node *nodes; |
f54d1867 | 1745 | struct dma_fence *exclusive; |
febb84a6 | 1746 | uint64_t flags; |
d38ceaf9 AD |
1747 | int r; |
1748 | ||
ec681545 | 1749 | if (clear || !bo_va->base.bo) { |
99e124f4 | 1750 | mem = NULL; |
63e0ba40 | 1751 | nodes = NULL; |
99e124f4 CK |
1752 | exclusive = NULL; |
1753 | } else { | |
8358dcee CK |
1754 | struct ttm_dma_tt *ttm; |
1755 | ||
ec681545 | 1756 | mem = &bo_va->base.bo->tbo.mem; |
63e0ba40 CK |
1757 | nodes = mem->mm_node; |
1758 | if (mem->mem_type == TTM_PL_TT) { | |
ec681545 CK |
1759 | ttm = container_of(bo_va->base.bo->tbo.ttm, |
1760 | struct ttm_dma_tt, ttm); | |
8358dcee | 1761 | pages_addr = ttm->dma_address; |
9ab21462 | 1762 | } |
ec681545 | 1763 | exclusive = reservation_object_get_excl(bo->tbo.resv); |
d38ceaf9 AD |
1764 | } |
1765 | ||
febb84a6 | 1766 | if (bo) |
ec681545 | 1767 | flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); |
febb84a6 | 1768 | else |
a5f6b5b1 | 1769 | flags = 0x0; |
d38ceaf9 | 1770 | |
3d7d4d3a CK |
1771 | if (!clear && bo_va->base.moved) { |
1772 | bo_va->base.moved = false; | |
7fc11959 | 1773 | list_splice_init(&bo_va->valids, &bo_va->invalids); |
3d7d4d3a | 1774 | |
cb7b6ec2 CK |
1775 | } else if (bo_va->cleared != clear) { |
1776 | list_splice_init(&bo_va->valids, &bo_va->invalids); | |
3d7d4d3a | 1777 | } |
7fc11959 CK |
1778 | |
1779 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
febb84a6 | 1780 | r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm, |
63e0ba40 | 1781 | mapping, flags, nodes, |
8358dcee | 1782 | &bo_va->last_pt_update); |
d38ceaf9 AD |
1783 | if (r) |
1784 | return r; | |
1785 | } | |
1786 | ||
cb7b6ec2 CK |
1787 | if (vm->use_cpu_for_update) { |
1788 | /* Flush HDP */ | |
1789 | mb(); | |
1790 | amdgpu_gart_flush_gpu_tlb(adev, 0); | |
d6c10f6b CK |
1791 | } |
1792 | ||
d38ceaf9 | 1793 | spin_lock(&vm->status_lock); |
ec681545 | 1794 | list_del_init(&bo_va->base.vm_status); |
d38ceaf9 AD |
1795 | spin_unlock(&vm->status_lock); |
1796 | ||
cb7b6ec2 CK |
1797 | list_splice_init(&bo_va->invalids, &bo_va->valids); |
1798 | bo_va->cleared = clear; | |
1799 | ||
1800 | if (trace_amdgpu_vm_bo_mapping_enabled()) { | |
1801 | list_for_each_entry(mapping, &bo_va->valids, list) | |
1802 | trace_amdgpu_vm_bo_mapping(mapping); | |
68c62306 CK |
1803 | } |
1804 | ||
d38ceaf9 AD |
1805 | return 0; |
1806 | } | |
1807 | ||
284710fa CK |
1808 | /** |
1809 | * amdgpu_vm_update_prt_state - update the global PRT state | |
1810 | */ | |
1811 | static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) | |
1812 | { | |
1813 | unsigned long flags; | |
1814 | bool enable; | |
1815 | ||
1816 | spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); | |
451bc8eb | 1817 | enable = !!atomic_read(&adev->vm_manager.num_prt_users); |
284710fa CK |
1818 | adev->gart.gart_funcs->set_prt(adev, enable); |
1819 | spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); | |
1820 | } | |
1821 | ||
451bc8eb | 1822 | /** |
4388fc2a | 1823 | * amdgpu_vm_prt_get - add a PRT user |
451bc8eb CK |
1824 | */ |
1825 | static void amdgpu_vm_prt_get(struct amdgpu_device *adev) | |
1826 | { | |
4388fc2a CK |
1827 | if (!adev->gart.gart_funcs->set_prt) |
1828 | return; | |
1829 | ||
451bc8eb CK |
1830 | if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) |
1831 | amdgpu_vm_update_prt_state(adev); | |
1832 | } | |
1833 | ||
0b15f2fc CK |
1834 | /** |
1835 | * amdgpu_vm_prt_put - drop a PRT user | |
1836 | */ | |
1837 | static void amdgpu_vm_prt_put(struct amdgpu_device *adev) | |
1838 | { | |
451bc8eb | 1839 | if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0) |
0b15f2fc CK |
1840 | amdgpu_vm_update_prt_state(adev); |
1841 | } | |
1842 | ||
284710fa | 1843 | /** |
451bc8eb | 1844 | * amdgpu_vm_prt_cb - callback for updating the PRT status |
284710fa CK |
1845 | */ |
1846 | static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb) | |
1847 | { | |
1848 | struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb); | |
1849 | ||
0b15f2fc | 1850 | amdgpu_vm_prt_put(cb->adev); |
284710fa CK |
1851 | kfree(cb); |
1852 | } | |
1853 | ||
451bc8eb CK |
1854 | /** |
1855 | * amdgpu_vm_add_prt_cb - add callback for updating the PRT status | |
1856 | */ | |
1857 | static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, | |
1858 | struct dma_fence *fence) | |
1859 | { | |
4388fc2a | 1860 | struct amdgpu_prt_cb *cb; |
451bc8eb | 1861 | |
4388fc2a CK |
1862 | if (!adev->gart.gart_funcs->set_prt) |
1863 | return; | |
1864 | ||
1865 | cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); | |
451bc8eb CK |
1866 | if (!cb) { |
1867 | /* Last resort when we are OOM */ | |
1868 | if (fence) | |
1869 | dma_fence_wait(fence, false); | |
1870 | ||
486a68f5 | 1871 | amdgpu_vm_prt_put(adev); |
451bc8eb CK |
1872 | } else { |
1873 | cb->adev = adev; | |
1874 | if (!fence || dma_fence_add_callback(fence, &cb->cb, | |
1875 | amdgpu_vm_prt_cb)) | |
1876 | amdgpu_vm_prt_cb(fence, &cb->cb); | |
1877 | } | |
1878 | } | |
1879 | ||
284710fa CK |
1880 | /** |
1881 | * amdgpu_vm_free_mapping - free a mapping | |
1882 | * | |
1883 | * @adev: amdgpu_device pointer | |
1884 | * @vm: requested vm | |
1885 | * @mapping: mapping to be freed | |
1886 | * @fence: fence of the unmap operation | |
1887 | * | |
1888 | * Free a mapping and make sure we decrease the PRT usage count if applicable. | |
1889 | */ | |
1890 | static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, | |
1891 | struct amdgpu_vm *vm, | |
1892 | struct amdgpu_bo_va_mapping *mapping, | |
1893 | struct dma_fence *fence) | |
1894 | { | |
451bc8eb CK |
1895 | if (mapping->flags & AMDGPU_PTE_PRT) |
1896 | amdgpu_vm_add_prt_cb(adev, fence); | |
1897 | kfree(mapping); | |
1898 | } | |
284710fa | 1899 | |
451bc8eb CK |
1900 | /** |
1901 | * amdgpu_vm_prt_fini - finish all prt mappings | |
1902 | * | |
1903 | * @adev: amdgpu_device pointer | |
1904 | * @vm: requested vm | |
1905 | * | |
1906 | * Register a cleanup callback to disable PRT support after VM dies. | |
1907 | */ | |
1908 | static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
1909 | { | |
3f3333f8 | 1910 | struct reservation_object *resv = vm->root.base.bo->tbo.resv; |
451bc8eb CK |
1911 | struct dma_fence *excl, **shared; |
1912 | unsigned i, shared_count; | |
1913 | int r; | |
0b15f2fc | 1914 | |
451bc8eb CK |
1915 | r = reservation_object_get_fences_rcu(resv, &excl, |
1916 | &shared_count, &shared); | |
1917 | if (r) { | |
1918 | /* Not enough memory to grab the fence list, as last resort | |
1919 | * block for all the fences to complete. | |
1920 | */ | |
1921 | reservation_object_wait_timeout_rcu(resv, true, false, | |
1922 | MAX_SCHEDULE_TIMEOUT); | |
1923 | return; | |
284710fa | 1924 | } |
451bc8eb CK |
1925 | |
1926 | /* Add a callback for each fence in the reservation object */ | |
1927 | amdgpu_vm_prt_get(adev); | |
1928 | amdgpu_vm_add_prt_cb(adev, excl); | |
1929 | ||
1930 | for (i = 0; i < shared_count; ++i) { | |
1931 | amdgpu_vm_prt_get(adev); | |
1932 | amdgpu_vm_add_prt_cb(adev, shared[i]); | |
1933 | } | |
1934 | ||
1935 | kfree(shared); | |
284710fa CK |
1936 | } |
1937 | ||
d38ceaf9 AD |
1938 | /** |
1939 | * amdgpu_vm_clear_freed - clear freed BOs in the PT | |
1940 | * | |
1941 | * @adev: amdgpu_device pointer | |
1942 | * @vm: requested vm | |
f3467818 NH |
1943 | * @fence: optional resulting fence (unchanged if no work needed to be done |
1944 | * or if an error occurred) | |
d38ceaf9 AD |
1945 | * |
1946 | * Make sure all freed BOs are cleared in the PT. | |
1947 | * Returns 0 for success. | |
1948 | * | |
1949 | * PTs have to be reserved and mutex must be locked! | |
1950 | */ | |
1951 | int amdgpu_vm_clear_freed(struct amdgpu_device *adev, | |
f3467818 NH |
1952 | struct amdgpu_vm *vm, |
1953 | struct dma_fence **fence) | |
d38ceaf9 AD |
1954 | { |
1955 | struct amdgpu_bo_va_mapping *mapping; | |
f3467818 | 1956 | struct dma_fence *f = NULL; |
d38ceaf9 | 1957 | int r; |
51ac7eec | 1958 | uint64_t init_pte_value = 0; |
d38ceaf9 AD |
1959 | |
1960 | while (!list_empty(&vm->freed)) { | |
1961 | mapping = list_first_entry(&vm->freed, | |
1962 | struct amdgpu_bo_va_mapping, list); | |
1963 | list_del(&mapping->list); | |
e17841b9 | 1964 | |
51ac7eec YZ |
1965 | if (vm->pte_support_ats) |
1966 | init_pte_value = AMDGPU_PTE_SYSTEM; | |
1967 | ||
570144c6 | 1968 | r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm, |
fc6aa33d | 1969 | mapping->start, mapping->last, |
51ac7eec | 1970 | init_pte_value, 0, &f); |
f3467818 | 1971 | amdgpu_vm_free_mapping(adev, vm, mapping, f); |
284710fa | 1972 | if (r) { |
f3467818 | 1973 | dma_fence_put(f); |
d38ceaf9 | 1974 | return r; |
284710fa | 1975 | } |
f3467818 | 1976 | } |
d38ceaf9 | 1977 | |
f3467818 NH |
1978 | if (fence && f) { |
1979 | dma_fence_put(*fence); | |
1980 | *fence = f; | |
1981 | } else { | |
1982 | dma_fence_put(f); | |
d38ceaf9 | 1983 | } |
f3467818 | 1984 | |
d38ceaf9 AD |
1985 | return 0; |
1986 | ||
1987 | } | |
1988 | ||
1989 | /** | |
73fb16e7 | 1990 | * amdgpu_vm_handle_moved - handle moved BOs in the PT |
d38ceaf9 AD |
1991 | * |
1992 | * @adev: amdgpu_device pointer | |
1993 | * @vm: requested vm | |
73fb16e7 | 1994 | * @sync: sync object to add fences to |
d38ceaf9 | 1995 | * |
73fb16e7 | 1996 | * Make sure all BOs which are moved are updated in the PTs. |
d38ceaf9 AD |
1997 | * Returns 0 for success. |
1998 | * | |
73fb16e7 | 1999 | * PTs have to be reserved! |
d38ceaf9 | 2000 | */ |
73fb16e7 CK |
2001 | int amdgpu_vm_handle_moved(struct amdgpu_device *adev, |
2002 | struct amdgpu_vm *vm, | |
2003 | struct amdgpu_sync *sync) | |
d38ceaf9 | 2004 | { |
cfe2c978 | 2005 | struct amdgpu_bo_va *bo_va = NULL; |
73fb16e7 | 2006 | bool clear; |
91e1a520 | 2007 | int r = 0; |
d38ceaf9 AD |
2008 | |
2009 | spin_lock(&vm->status_lock); | |
27c7b9ae CK |
2010 | while (!list_empty(&vm->moved)) { |
2011 | bo_va = list_first_entry(&vm->moved, | |
ec681545 | 2012 | struct amdgpu_bo_va, base.vm_status); |
d38ceaf9 | 2013 | spin_unlock(&vm->status_lock); |
32b41ac2 | 2014 | |
73fb16e7 CK |
2015 | /* Per VM BOs never need to bo cleared in the page tables */ |
2016 | clear = bo_va->base.bo->tbo.resv != vm->root.base.bo->tbo.resv; | |
2017 | ||
2018 | r = amdgpu_vm_bo_update(adev, bo_va, clear); | |
d38ceaf9 AD |
2019 | if (r) |
2020 | return r; | |
2021 | ||
2022 | spin_lock(&vm->status_lock); | |
2023 | } | |
2024 | spin_unlock(&vm->status_lock); | |
2025 | ||
cfe2c978 | 2026 | if (bo_va) |
bb1e38a4 | 2027 | r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update); |
91e1a520 CK |
2028 | |
2029 | return r; | |
d38ceaf9 AD |
2030 | } |
2031 | ||
2032 | /** | |
2033 | * amdgpu_vm_bo_add - add a bo to a specific vm | |
2034 | * | |
2035 | * @adev: amdgpu_device pointer | |
2036 | * @vm: requested vm | |
2037 | * @bo: amdgpu buffer object | |
2038 | * | |
8843dbbb | 2039 | * Add @bo into the requested vm. |
d38ceaf9 AD |
2040 | * Add @bo to the list of bos associated with the vm |
2041 | * Returns newly added bo_va or NULL for failure | |
2042 | * | |
2043 | * Object has to be reserved! | |
2044 | */ | |
2045 | struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, | |
2046 | struct amdgpu_vm *vm, | |
2047 | struct amdgpu_bo *bo) | |
2048 | { | |
2049 | struct amdgpu_bo_va *bo_va; | |
2050 | ||
2051 | bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); | |
2052 | if (bo_va == NULL) { | |
2053 | return NULL; | |
2054 | } | |
ec681545 CK |
2055 | bo_va->base.vm = vm; |
2056 | bo_va->base.bo = bo; | |
2057 | INIT_LIST_HEAD(&bo_va->base.bo_list); | |
2058 | INIT_LIST_HEAD(&bo_va->base.vm_status); | |
2059 | ||
d38ceaf9 | 2060 | bo_va->ref_count = 1; |
7fc11959 CK |
2061 | INIT_LIST_HEAD(&bo_va->valids); |
2062 | INIT_LIST_HEAD(&bo_va->invalids); | |
32b41ac2 | 2063 | |
a5f6b5b1 | 2064 | if (bo) |
ec681545 | 2065 | list_add_tail(&bo_va->base.bo_list, &bo->va); |
d38ceaf9 AD |
2066 | |
2067 | return bo_va; | |
2068 | } | |
2069 | ||
73fb16e7 CK |
2070 | |
2071 | /** | |
2072 | * amdgpu_vm_bo_insert_mapping - insert a new mapping | |
2073 | * | |
2074 | * @adev: amdgpu_device pointer | |
2075 | * @bo_va: bo_va to store the address | |
2076 | * @mapping: the mapping to insert | |
2077 | * | |
2078 | * Insert a new mapping into all structures. | |
2079 | */ | |
2080 | static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, | |
2081 | struct amdgpu_bo_va *bo_va, | |
2082 | struct amdgpu_bo_va_mapping *mapping) | |
2083 | { | |
2084 | struct amdgpu_vm *vm = bo_va->base.vm; | |
2085 | struct amdgpu_bo *bo = bo_va->base.bo; | |
2086 | ||
2087 | list_add(&mapping->list, &bo_va->invalids); | |
2088 | amdgpu_vm_it_insert(mapping, &vm->va); | |
2089 | ||
2090 | if (mapping->flags & AMDGPU_PTE_PRT) | |
2091 | amdgpu_vm_prt_get(adev); | |
2092 | ||
2093 | if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) { | |
2094 | spin_lock(&vm->status_lock); | |
481c2e94 CK |
2095 | if (list_empty(&bo_va->base.vm_status)) |
2096 | list_add(&bo_va->base.vm_status, &vm->moved); | |
73fb16e7 CK |
2097 | spin_unlock(&vm->status_lock); |
2098 | } | |
2099 | trace_amdgpu_vm_bo_map(bo_va, mapping); | |
2100 | } | |
2101 | ||
d38ceaf9 AD |
2102 | /** |
2103 | * amdgpu_vm_bo_map - map bo inside a vm | |
2104 | * | |
2105 | * @adev: amdgpu_device pointer | |
2106 | * @bo_va: bo_va to store the address | |
2107 | * @saddr: where to map the BO | |
2108 | * @offset: requested offset in the BO | |
2109 | * @flags: attributes of pages (read/write/valid/etc.) | |
2110 | * | |
2111 | * Add a mapping of the BO at the specefied addr into the VM. | |
2112 | * Returns 0 for success, error for failure. | |
2113 | * | |
49b02b18 | 2114 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2115 | */ |
2116 | int amdgpu_vm_bo_map(struct amdgpu_device *adev, | |
2117 | struct amdgpu_bo_va *bo_va, | |
2118 | uint64_t saddr, uint64_t offset, | |
268c3001 | 2119 | uint64_t size, uint64_t flags) |
d38ceaf9 | 2120 | { |
a9f87f64 | 2121 | struct amdgpu_bo_va_mapping *mapping, *tmp; |
ec681545 CK |
2122 | struct amdgpu_bo *bo = bo_va->base.bo; |
2123 | struct amdgpu_vm *vm = bo_va->base.vm; | |
d38ceaf9 | 2124 | uint64_t eaddr; |
d38ceaf9 | 2125 | |
0be52de9 CK |
2126 | /* validate the parameters */ |
2127 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
49b02b18 | 2128 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) |
0be52de9 | 2129 | return -EINVAL; |
0be52de9 | 2130 | |
d38ceaf9 | 2131 | /* make sure object fit at this offset */ |
005ae95e | 2132 | eaddr = saddr + size - 1; |
a5f6b5b1 | 2133 | if (saddr >= eaddr || |
ec681545 | 2134 | (bo && offset + size > amdgpu_bo_size(bo))) |
d38ceaf9 | 2135 | return -EINVAL; |
d38ceaf9 | 2136 | |
d38ceaf9 AD |
2137 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
2138 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2139 | ||
a9f87f64 CK |
2140 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2141 | if (tmp) { | |
d38ceaf9 AD |
2142 | /* bo and tmp overlap, invalid addr */ |
2143 | dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " | |
ec681545 | 2144 | "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr, |
a9f87f64 | 2145 | tmp->start, tmp->last + 1); |
663e4577 | 2146 | return -EINVAL; |
d38ceaf9 AD |
2147 | } |
2148 | ||
2149 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
663e4577 CK |
2150 | if (!mapping) |
2151 | return -ENOMEM; | |
d38ceaf9 | 2152 | |
a9f87f64 CK |
2153 | mapping->start = saddr; |
2154 | mapping->last = eaddr; | |
d38ceaf9 AD |
2155 | mapping->offset = offset; |
2156 | mapping->flags = flags; | |
2157 | ||
73fb16e7 | 2158 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
80f95c57 CK |
2159 | |
2160 | return 0; | |
2161 | } | |
2162 | ||
2163 | /** | |
2164 | * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings | |
2165 | * | |
2166 | * @adev: amdgpu_device pointer | |
2167 | * @bo_va: bo_va to store the address | |
2168 | * @saddr: where to map the BO | |
2169 | * @offset: requested offset in the BO | |
2170 | * @flags: attributes of pages (read/write/valid/etc.) | |
2171 | * | |
2172 | * Add a mapping of the BO at the specefied addr into the VM. Replace existing | |
2173 | * mappings as we do so. | |
2174 | * Returns 0 for success, error for failure. | |
2175 | * | |
2176 | * Object has to be reserved and unreserved outside! | |
2177 | */ | |
2178 | int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, | |
2179 | struct amdgpu_bo_va *bo_va, | |
2180 | uint64_t saddr, uint64_t offset, | |
2181 | uint64_t size, uint64_t flags) | |
2182 | { | |
2183 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2184 | struct amdgpu_bo *bo = bo_va->base.bo; |
80f95c57 CK |
2185 | uint64_t eaddr; |
2186 | int r; | |
2187 | ||
2188 | /* validate the parameters */ | |
2189 | if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || | |
2190 | size == 0 || size & AMDGPU_GPU_PAGE_MASK) | |
2191 | return -EINVAL; | |
2192 | ||
2193 | /* make sure object fit at this offset */ | |
2194 | eaddr = saddr + size - 1; | |
2195 | if (saddr >= eaddr || | |
ec681545 | 2196 | (bo && offset + size > amdgpu_bo_size(bo))) |
80f95c57 CK |
2197 | return -EINVAL; |
2198 | ||
2199 | /* Allocate all the needed memory */ | |
2200 | mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); | |
2201 | if (!mapping) | |
2202 | return -ENOMEM; | |
2203 | ||
ec681545 | 2204 | r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size); |
80f95c57 CK |
2205 | if (r) { |
2206 | kfree(mapping); | |
2207 | return r; | |
2208 | } | |
2209 | ||
2210 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2211 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2212 | ||
a9f87f64 CK |
2213 | mapping->start = saddr; |
2214 | mapping->last = eaddr; | |
80f95c57 CK |
2215 | mapping->offset = offset; |
2216 | mapping->flags = flags; | |
2217 | ||
73fb16e7 | 2218 | amdgpu_vm_bo_insert_map(adev, bo_va, mapping); |
4388fc2a | 2219 | |
d38ceaf9 | 2220 | return 0; |
d38ceaf9 AD |
2221 | } |
2222 | ||
2223 | /** | |
2224 | * amdgpu_vm_bo_unmap - remove bo mapping from vm | |
2225 | * | |
2226 | * @adev: amdgpu_device pointer | |
2227 | * @bo_va: bo_va to remove the address from | |
2228 | * @saddr: where to the BO is mapped | |
2229 | * | |
2230 | * Remove a mapping of the BO at the specefied addr from the VM. | |
2231 | * Returns 0 for success, error for failure. | |
2232 | * | |
49b02b18 | 2233 | * Object has to be reserved and unreserved outside! |
d38ceaf9 AD |
2234 | */ |
2235 | int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, | |
2236 | struct amdgpu_bo_va *bo_va, | |
2237 | uint64_t saddr) | |
2238 | { | |
2239 | struct amdgpu_bo_va_mapping *mapping; | |
ec681545 | 2240 | struct amdgpu_vm *vm = bo_va->base.vm; |
7fc11959 | 2241 | bool valid = true; |
d38ceaf9 | 2242 | |
6c7fc503 | 2243 | saddr /= AMDGPU_GPU_PAGE_SIZE; |
32b41ac2 | 2244 | |
7fc11959 | 2245 | list_for_each_entry(mapping, &bo_va->valids, list) { |
a9f87f64 | 2246 | if (mapping->start == saddr) |
d38ceaf9 AD |
2247 | break; |
2248 | } | |
2249 | ||
7fc11959 CK |
2250 | if (&mapping->list == &bo_va->valids) { |
2251 | valid = false; | |
2252 | ||
2253 | list_for_each_entry(mapping, &bo_va->invalids, list) { | |
a9f87f64 | 2254 | if (mapping->start == saddr) |
7fc11959 CK |
2255 | break; |
2256 | } | |
2257 | ||
32b41ac2 | 2258 | if (&mapping->list == &bo_va->invalids) |
7fc11959 | 2259 | return -ENOENT; |
d38ceaf9 | 2260 | } |
32b41ac2 | 2261 | |
d38ceaf9 | 2262 | list_del(&mapping->list); |
a9f87f64 | 2263 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2264 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
d38ceaf9 | 2265 | |
e17841b9 | 2266 | if (valid) |
d38ceaf9 | 2267 | list_add(&mapping->list, &vm->freed); |
e17841b9 | 2268 | else |
284710fa CK |
2269 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2270 | bo_va->last_pt_update); | |
d38ceaf9 AD |
2271 | |
2272 | return 0; | |
2273 | } | |
2274 | ||
dc54d3d1 CK |
2275 | /** |
2276 | * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range | |
2277 | * | |
2278 | * @adev: amdgpu_device pointer | |
2279 | * @vm: VM structure to use | |
2280 | * @saddr: start of the range | |
2281 | * @size: size of the range | |
2282 | * | |
2283 | * Remove all mappings in a range, split them as appropriate. | |
2284 | * Returns 0 for success, error for failure. | |
2285 | */ | |
2286 | int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, | |
2287 | struct amdgpu_vm *vm, | |
2288 | uint64_t saddr, uint64_t size) | |
2289 | { | |
2290 | struct amdgpu_bo_va_mapping *before, *after, *tmp, *next; | |
dc54d3d1 CK |
2291 | LIST_HEAD(removed); |
2292 | uint64_t eaddr; | |
2293 | ||
2294 | eaddr = saddr + size - 1; | |
2295 | saddr /= AMDGPU_GPU_PAGE_SIZE; | |
2296 | eaddr /= AMDGPU_GPU_PAGE_SIZE; | |
2297 | ||
2298 | /* Allocate all the needed memory */ | |
2299 | before = kzalloc(sizeof(*before), GFP_KERNEL); | |
2300 | if (!before) | |
2301 | return -ENOMEM; | |
27f6d610 | 2302 | INIT_LIST_HEAD(&before->list); |
dc54d3d1 CK |
2303 | |
2304 | after = kzalloc(sizeof(*after), GFP_KERNEL); | |
2305 | if (!after) { | |
2306 | kfree(before); | |
2307 | return -ENOMEM; | |
2308 | } | |
27f6d610 | 2309 | INIT_LIST_HEAD(&after->list); |
dc54d3d1 CK |
2310 | |
2311 | /* Now gather all removed mappings */ | |
a9f87f64 CK |
2312 | tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr); |
2313 | while (tmp) { | |
dc54d3d1 | 2314 | /* Remember mapping split at the start */ |
a9f87f64 CK |
2315 | if (tmp->start < saddr) { |
2316 | before->start = tmp->start; | |
2317 | before->last = saddr - 1; | |
dc54d3d1 CK |
2318 | before->offset = tmp->offset; |
2319 | before->flags = tmp->flags; | |
2320 | list_add(&before->list, &tmp->list); | |
2321 | } | |
2322 | ||
2323 | /* Remember mapping split at the end */ | |
a9f87f64 CK |
2324 | if (tmp->last > eaddr) { |
2325 | after->start = eaddr + 1; | |
2326 | after->last = tmp->last; | |
dc54d3d1 | 2327 | after->offset = tmp->offset; |
a9f87f64 | 2328 | after->offset += after->start - tmp->start; |
dc54d3d1 CK |
2329 | after->flags = tmp->flags; |
2330 | list_add(&after->list, &tmp->list); | |
2331 | } | |
2332 | ||
2333 | list_del(&tmp->list); | |
2334 | list_add(&tmp->list, &removed); | |
a9f87f64 CK |
2335 | |
2336 | tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr); | |
dc54d3d1 CK |
2337 | } |
2338 | ||
2339 | /* And free them up */ | |
2340 | list_for_each_entry_safe(tmp, next, &removed, list) { | |
a9f87f64 | 2341 | amdgpu_vm_it_remove(tmp, &vm->va); |
dc54d3d1 CK |
2342 | list_del(&tmp->list); |
2343 | ||
a9f87f64 CK |
2344 | if (tmp->start < saddr) |
2345 | tmp->start = saddr; | |
2346 | if (tmp->last > eaddr) | |
2347 | tmp->last = eaddr; | |
dc54d3d1 CK |
2348 | |
2349 | list_add(&tmp->list, &vm->freed); | |
2350 | trace_amdgpu_vm_bo_unmap(NULL, tmp); | |
2351 | } | |
2352 | ||
27f6d610 JZ |
2353 | /* Insert partial mapping before the range */ |
2354 | if (!list_empty(&before->list)) { | |
a9f87f64 | 2355 | amdgpu_vm_it_insert(before, &vm->va); |
dc54d3d1 CK |
2356 | if (before->flags & AMDGPU_PTE_PRT) |
2357 | amdgpu_vm_prt_get(adev); | |
2358 | } else { | |
2359 | kfree(before); | |
2360 | } | |
2361 | ||
2362 | /* Insert partial mapping after the range */ | |
27f6d610 | 2363 | if (!list_empty(&after->list)) { |
a9f87f64 | 2364 | amdgpu_vm_it_insert(after, &vm->va); |
dc54d3d1 CK |
2365 | if (after->flags & AMDGPU_PTE_PRT) |
2366 | amdgpu_vm_prt_get(adev); | |
2367 | } else { | |
2368 | kfree(after); | |
2369 | } | |
2370 | ||
2371 | return 0; | |
2372 | } | |
2373 | ||
d38ceaf9 AD |
2374 | /** |
2375 | * amdgpu_vm_bo_rmv - remove a bo to a specific vm | |
2376 | * | |
2377 | * @adev: amdgpu_device pointer | |
2378 | * @bo_va: requested bo_va | |
2379 | * | |
8843dbbb | 2380 | * Remove @bo_va->bo from the requested vm. |
d38ceaf9 AD |
2381 | * |
2382 | * Object have to be reserved! | |
2383 | */ | |
2384 | void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, | |
2385 | struct amdgpu_bo_va *bo_va) | |
2386 | { | |
2387 | struct amdgpu_bo_va_mapping *mapping, *next; | |
ec681545 | 2388 | struct amdgpu_vm *vm = bo_va->base.vm; |
d38ceaf9 | 2389 | |
ec681545 | 2390 | list_del(&bo_va->base.bo_list); |
d38ceaf9 | 2391 | |
d38ceaf9 | 2392 | spin_lock(&vm->status_lock); |
ec681545 | 2393 | list_del(&bo_va->base.vm_status); |
d38ceaf9 AD |
2394 | spin_unlock(&vm->status_lock); |
2395 | ||
7fc11959 | 2396 | list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { |
d38ceaf9 | 2397 | list_del(&mapping->list); |
a9f87f64 | 2398 | amdgpu_vm_it_remove(mapping, &vm->va); |
93e3e438 | 2399 | trace_amdgpu_vm_bo_unmap(bo_va, mapping); |
7fc11959 CK |
2400 | list_add(&mapping->list, &vm->freed); |
2401 | } | |
2402 | list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { | |
2403 | list_del(&mapping->list); | |
a9f87f64 | 2404 | amdgpu_vm_it_remove(mapping, &vm->va); |
284710fa CK |
2405 | amdgpu_vm_free_mapping(adev, vm, mapping, |
2406 | bo_va->last_pt_update); | |
d38ceaf9 | 2407 | } |
32b41ac2 | 2408 | |
f54d1867 | 2409 | dma_fence_put(bo_va->last_pt_update); |
d38ceaf9 | 2410 | kfree(bo_va); |
d38ceaf9 AD |
2411 | } |
2412 | ||
2413 | /** | |
2414 | * amdgpu_vm_bo_invalidate - mark the bo as invalid | |
2415 | * | |
2416 | * @adev: amdgpu_device pointer | |
2417 | * @vm: requested vm | |
2418 | * @bo: amdgpu buffer object | |
2419 | * | |
8843dbbb | 2420 | * Mark @bo as invalid. |
d38ceaf9 AD |
2421 | */ |
2422 | void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, | |
3f3333f8 | 2423 | struct amdgpu_bo *bo, bool evicted) |
d38ceaf9 | 2424 | { |
ec681545 CK |
2425 | struct amdgpu_vm_bo_base *bo_base; |
2426 | ||
2427 | list_for_each_entry(bo_base, &bo->va, bo_list) { | |
3f3333f8 CK |
2428 | struct amdgpu_vm *vm = bo_base->vm; |
2429 | ||
3d7d4d3a | 2430 | bo_base->moved = true; |
3f3333f8 CK |
2431 | if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) { |
2432 | spin_lock(&bo_base->vm->status_lock); | |
73fb16e7 CK |
2433 | if (bo->tbo.type == ttm_bo_type_kernel) |
2434 | list_move(&bo_base->vm_status, &vm->evicted); | |
2435 | else | |
2436 | list_move_tail(&bo_base->vm_status, | |
2437 | &vm->evicted); | |
3f3333f8 CK |
2438 | spin_unlock(&bo_base->vm->status_lock); |
2439 | continue; | |
2440 | } | |
2441 | ||
ea09729c CK |
2442 | if (bo->tbo.type == ttm_bo_type_kernel) { |
2443 | spin_lock(&bo_base->vm->status_lock); | |
2444 | if (list_empty(&bo_base->vm_status)) | |
2445 | list_add(&bo_base->vm_status, &vm->relocated); | |
2446 | spin_unlock(&bo_base->vm->status_lock); | |
3f3333f8 | 2447 | continue; |
ea09729c | 2448 | } |
3f3333f8 | 2449 | |
ec681545 | 2450 | spin_lock(&bo_base->vm->status_lock); |
481c2e94 CK |
2451 | if (list_empty(&bo_base->vm_status)) |
2452 | list_add(&bo_base->vm_status, &vm->moved); | |
ec681545 | 2453 | spin_unlock(&bo_base->vm->status_lock); |
d38ceaf9 AD |
2454 | } |
2455 | } | |
2456 | ||
bab4fee7 JZ |
2457 | static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) |
2458 | { | |
2459 | /* Total bits covered by PD + PTs */ | |
2460 | unsigned bits = ilog2(vm_size) + 18; | |
2461 | ||
2462 | /* Make sure the PD is 4K in size up to 8GB address space. | |
2463 | Above that split equal between PD and PTs */ | |
2464 | if (vm_size <= 8) | |
2465 | return (bits - 9); | |
2466 | else | |
2467 | return ((bits + 3) / 2); | |
2468 | } | |
2469 | ||
2470 | /** | |
d07f14be RH |
2471 | * amdgpu_vm_set_fragment_size - adjust fragment size in PTE |
2472 | * | |
2473 | * @adev: amdgpu_device pointer | |
2474 | * @fragment_size_default: the default fragment size if it's set auto | |
2475 | */ | |
2476 | void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, uint32_t fragment_size_default) | |
2477 | { | |
2478 | if (amdgpu_vm_fragment_size == -1) | |
2479 | adev->vm_manager.fragment_size = fragment_size_default; | |
2480 | else | |
2481 | adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; | |
2482 | } | |
2483 | ||
2484 | /** | |
2485 | * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size | |
bab4fee7 JZ |
2486 | * |
2487 | * @adev: amdgpu_device pointer | |
2488 | * @vm_size: the default vm size if it's set auto | |
2489 | */ | |
d07f14be | 2490 | void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, uint32_t fragment_size_default) |
bab4fee7 JZ |
2491 | { |
2492 | /* adjust vm size firstly */ | |
2493 | if (amdgpu_vm_size == -1) | |
2494 | adev->vm_manager.vm_size = vm_size; | |
2495 | else | |
2496 | adev->vm_manager.vm_size = amdgpu_vm_size; | |
2497 | ||
2498 | /* block size depends on vm size */ | |
2499 | if (amdgpu_vm_block_size == -1) | |
2500 | adev->vm_manager.block_size = | |
2501 | amdgpu_vm_get_block_size(adev->vm_manager.vm_size); | |
2502 | else | |
2503 | adev->vm_manager.block_size = amdgpu_vm_block_size; | |
2504 | ||
d07f14be RH |
2505 | amdgpu_vm_set_fragment_size(adev, fragment_size_default); |
2506 | ||
2507 | DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n", | |
2508 | adev->vm_manager.vm_size, adev->vm_manager.block_size, | |
2509 | adev->vm_manager.fragment_size); | |
bab4fee7 JZ |
2510 | } |
2511 | ||
d38ceaf9 AD |
2512 | /** |
2513 | * amdgpu_vm_init - initialize a vm instance | |
2514 | * | |
2515 | * @adev: amdgpu_device pointer | |
2516 | * @vm: requested vm | |
9a4b7d4c | 2517 | * @vm_context: Indicates if it GFX or Compute context |
d38ceaf9 | 2518 | * |
8843dbbb | 2519 | * Init @vm fields. |
d38ceaf9 | 2520 | */ |
9a4b7d4c HK |
2521 | int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
2522 | int vm_context) | |
d38ceaf9 AD |
2523 | { |
2524 | const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, | |
36b32a68 | 2525 | AMDGPU_VM_PTE_COUNT(adev) * 8); |
2d55e45a CK |
2526 | unsigned ring_instance; |
2527 | struct amdgpu_ring *ring; | |
2bd9ccfa | 2528 | struct amd_sched_rq *rq; |
36bbf3bf | 2529 | int r, i; |
3c824172 | 2530 | u64 flags; |
51ac7eec | 2531 | uint64_t init_pde_value = 0; |
d38ceaf9 | 2532 | |
d38ceaf9 | 2533 | vm->va = RB_ROOT; |
031e2983 | 2534 | vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter); |
36bbf3bf CZ |
2535 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2536 | vm->reserved_vmid[i] = NULL; | |
d38ceaf9 | 2537 | spin_lock_init(&vm->status_lock); |
3f3333f8 | 2538 | INIT_LIST_HEAD(&vm->evicted); |
ea09729c | 2539 | INIT_LIST_HEAD(&vm->relocated); |
27c7b9ae | 2540 | INIT_LIST_HEAD(&vm->moved); |
d38ceaf9 | 2541 | INIT_LIST_HEAD(&vm->freed); |
20250215 | 2542 | |
2bd9ccfa | 2543 | /* create scheduler entity for page table updates */ |
2d55e45a CK |
2544 | |
2545 | ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring); | |
2546 | ring_instance %= adev->vm_manager.vm_pte_num_rings; | |
2547 | ring = adev->vm_manager.vm_pte_rings[ring_instance]; | |
2bd9ccfa CK |
2548 | rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; |
2549 | r = amd_sched_entity_init(&ring->sched, &vm->entity, | |
2550 | rq, amdgpu_sched_jobs); | |
2551 | if (r) | |
f566ceb1 | 2552 | return r; |
2bd9ccfa | 2553 | |
51ac7eec YZ |
2554 | vm->pte_support_ats = false; |
2555 | ||
2556 | if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) { | |
9a4b7d4c HK |
2557 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2558 | AMDGPU_VM_USE_CPU_FOR_COMPUTE); | |
51ac7eec YZ |
2559 | |
2560 | if (adev->asic_type == CHIP_RAVEN) { | |
2561 | vm->pte_support_ats = true; | |
2562 | init_pde_value = AMDGPU_PTE_SYSTEM | AMDGPU_PDE_PTE; | |
2563 | } | |
2564 | } else | |
9a4b7d4c HK |
2565 | vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & |
2566 | AMDGPU_VM_USE_CPU_FOR_GFX); | |
2567 | DRM_DEBUG_DRIVER("VM update mode is %s\n", | |
2568 | vm->use_cpu_for_update ? "CPU" : "SDMA"); | |
2569 | WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), | |
2570 | "CPU update of VM recommended only for large BAR system\n"); | |
a24960f3 | 2571 | vm->last_dir_update = NULL; |
05906dec | 2572 | |
3c824172 HK |
2573 | flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | |
2574 | AMDGPU_GEM_CREATE_VRAM_CLEARED; | |
2575 | if (vm->use_cpu_for_update) | |
2576 | flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
2577 | else | |
2578 | flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
2579 | AMDGPU_GEM_CREATE_SHADOW); | |
2580 | ||
f566ceb1 | 2581 | r = amdgpu_bo_create(adev, amdgpu_vm_bo_size(adev, 0), align, true, |
857d913d | 2582 | AMDGPU_GEM_DOMAIN_VRAM, |
3c824172 | 2583 | flags, |
3f3333f8 | 2584 | NULL, NULL, init_pde_value, &vm->root.base.bo); |
d38ceaf9 | 2585 | if (r) |
2bd9ccfa CK |
2586 | goto error_free_sched_entity; |
2587 | ||
3f3333f8 CK |
2588 | vm->root.base.vm = vm; |
2589 | list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va); | |
2590 | INIT_LIST_HEAD(&vm->root.base.vm_status); | |
0a096fb6 CK |
2591 | |
2592 | if (vm->use_cpu_for_update) { | |
3f3333f8 | 2593 | r = amdgpu_bo_reserve(vm->root.base.bo, false); |
0a096fb6 CK |
2594 | if (r) |
2595 | goto error_free_root; | |
0a096fb6 | 2596 | |
3f3333f8 CK |
2597 | r = amdgpu_bo_kmap(vm->root.base.bo, NULL); |
2598 | if (r) | |
2599 | goto error_free_root; | |
2600 | amdgpu_bo_unreserve(vm->root.base.bo); | |
2601 | } | |
d38ceaf9 AD |
2602 | |
2603 | return 0; | |
2bd9ccfa | 2604 | |
67003a15 | 2605 | error_free_root: |
3f3333f8 CK |
2606 | amdgpu_bo_unref(&vm->root.base.bo->shadow); |
2607 | amdgpu_bo_unref(&vm->root.base.bo); | |
2608 | vm->root.base.bo = NULL; | |
2bd9ccfa CK |
2609 | |
2610 | error_free_sched_entity: | |
2611 | amd_sched_entity_fini(&ring->sched, &vm->entity); | |
2612 | ||
2613 | return r; | |
d38ceaf9 AD |
2614 | } |
2615 | ||
f566ceb1 CK |
2616 | /** |
2617 | * amdgpu_vm_free_levels - free PD/PT levels | |
2618 | * | |
2619 | * @level: PD/PT starting level to free | |
2620 | * | |
2621 | * Free the page directory or page table level and all sub levels. | |
2622 | */ | |
2623 | static void amdgpu_vm_free_levels(struct amdgpu_vm_pt *level) | |
2624 | { | |
2625 | unsigned i; | |
2626 | ||
3f3333f8 CK |
2627 | if (level->base.bo) { |
2628 | list_del(&level->base.bo_list); | |
2629 | list_del(&level->base.vm_status); | |
2630 | amdgpu_bo_unref(&level->base.bo->shadow); | |
2631 | amdgpu_bo_unref(&level->base.bo); | |
f566ceb1 CK |
2632 | } |
2633 | ||
2634 | if (level->entries) | |
2635 | for (i = 0; i <= level->last_entry_used; i++) | |
2636 | amdgpu_vm_free_levels(&level->entries[i]); | |
2637 | ||
2098105e | 2638 | kvfree(level->entries); |
f566ceb1 CK |
2639 | } |
2640 | ||
d38ceaf9 AD |
2641 | /** |
2642 | * amdgpu_vm_fini - tear down a vm instance | |
2643 | * | |
2644 | * @adev: amdgpu_device pointer | |
2645 | * @vm: requested vm | |
2646 | * | |
8843dbbb | 2647 | * Tear down @vm. |
d38ceaf9 AD |
2648 | * Unbind the VM and remove all bos from the vm bo list |
2649 | */ | |
2650 | void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) | |
2651 | { | |
2652 | struct amdgpu_bo_va_mapping *mapping, *tmp; | |
4388fc2a | 2653 | bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; |
36bbf3bf | 2654 | int i; |
d38ceaf9 | 2655 | |
2d55e45a | 2656 | amd_sched_entity_fini(vm->entity.sched, &vm->entity); |
2bd9ccfa | 2657 | |
d38ceaf9 AD |
2658 | if (!RB_EMPTY_ROOT(&vm->va)) { |
2659 | dev_err(adev->dev, "still active bo inside vm\n"); | |
2660 | } | |
a9f87f64 | 2661 | rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, rb) { |
d38ceaf9 | 2662 | list_del(&mapping->list); |
a9f87f64 | 2663 | amdgpu_vm_it_remove(mapping, &vm->va); |
d38ceaf9 AD |
2664 | kfree(mapping); |
2665 | } | |
2666 | list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { | |
4388fc2a | 2667 | if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) { |
451bc8eb | 2668 | amdgpu_vm_prt_fini(adev, vm); |
4388fc2a | 2669 | prt_fini_needed = false; |
451bc8eb | 2670 | } |
284710fa | 2671 | |
d38ceaf9 | 2672 | list_del(&mapping->list); |
451bc8eb | 2673 | amdgpu_vm_free_mapping(adev, vm, mapping, NULL); |
d38ceaf9 AD |
2674 | } |
2675 | ||
f566ceb1 | 2676 | amdgpu_vm_free_levels(&vm->root); |
a24960f3 | 2677 | dma_fence_put(vm->last_dir_update); |
1e9ef26f CZ |
2678 | for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) |
2679 | amdgpu_vm_free_reserved_vmid(adev, vm, i); | |
d38ceaf9 | 2680 | } |
ea89f8c9 | 2681 | |
a9a78b32 CK |
2682 | /** |
2683 | * amdgpu_vm_manager_init - init the VM manager | |
2684 | * | |
2685 | * @adev: amdgpu_device pointer | |
2686 | * | |
2687 | * Initialize the VM manager structures | |
2688 | */ | |
2689 | void amdgpu_vm_manager_init(struct amdgpu_device *adev) | |
2690 | { | |
7645670d CK |
2691 | unsigned i, j; |
2692 | ||
2693 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { | |
2694 | struct amdgpu_vm_id_manager *id_mgr = | |
2695 | &adev->vm_manager.id_mgr[i]; | |
a9a78b32 | 2696 | |
7645670d CK |
2697 | mutex_init(&id_mgr->lock); |
2698 | INIT_LIST_HEAD(&id_mgr->ids_lru); | |
c3505770 | 2699 | atomic_set(&id_mgr->reserved_vmid_num, 0); |
a9a78b32 | 2700 | |
7645670d CK |
2701 | /* skip over VMID 0, since it is the system VM */ |
2702 | for (j = 1; j < id_mgr->num_ids; ++j) { | |
2703 | amdgpu_vm_reset_id(adev, i, j); | |
2704 | amdgpu_sync_create(&id_mgr->ids[i].active); | |
2705 | list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); | |
2706 | } | |
971fe9a9 | 2707 | } |
2d55e45a | 2708 | |
f54d1867 CW |
2709 | adev->vm_manager.fence_context = |
2710 | dma_fence_context_alloc(AMDGPU_MAX_RINGS); | |
1fbb2e92 CK |
2711 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
2712 | adev->vm_manager.seqno[i] = 0; | |
2713 | ||
2d55e45a | 2714 | atomic_set(&adev->vm_manager.vm_pte_next_ring, 0); |
b1c8a81f | 2715 | atomic64_set(&adev->vm_manager.client_counter, 0); |
284710fa | 2716 | spin_lock_init(&adev->vm_manager.prt_lock); |
451bc8eb | 2717 | atomic_set(&adev->vm_manager.num_prt_users, 0); |
9a4b7d4c HK |
2718 | |
2719 | /* If not overridden by the user, by default, only in large BAR systems | |
2720 | * Compute VM tables will be updated by CPU | |
2721 | */ | |
2722 | #ifdef CONFIG_X86_64 | |
2723 | if (amdgpu_vm_update_mode == -1) { | |
2724 | if (amdgpu_vm_is_large_bar(adev)) | |
2725 | adev->vm_manager.vm_update_mode = | |
2726 | AMDGPU_VM_USE_CPU_FOR_COMPUTE; | |
2727 | else | |
2728 | adev->vm_manager.vm_update_mode = 0; | |
2729 | } else | |
2730 | adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode; | |
2731 | #else | |
2732 | adev->vm_manager.vm_update_mode = 0; | |
2733 | #endif | |
2734 | ||
a9a78b32 CK |
2735 | } |
2736 | ||
ea89f8c9 CK |
2737 | /** |
2738 | * amdgpu_vm_manager_fini - cleanup VM manager | |
2739 | * | |
2740 | * @adev: amdgpu_device pointer | |
2741 | * | |
2742 | * Cleanup the VM manager and free resources. | |
2743 | */ | |
2744 | void amdgpu_vm_manager_fini(struct amdgpu_device *adev) | |
2745 | { | |
7645670d | 2746 | unsigned i, j; |
ea89f8c9 | 2747 | |
7645670d CK |
2748 | for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { |
2749 | struct amdgpu_vm_id_manager *id_mgr = | |
2750 | &adev->vm_manager.id_mgr[i]; | |
bcb1ba35 | 2751 | |
7645670d CK |
2752 | mutex_destroy(&id_mgr->lock); |
2753 | for (j = 0; j < AMDGPU_NUM_VM; ++j) { | |
2754 | struct amdgpu_vm_id *id = &id_mgr->ids[j]; | |
2755 | ||
2756 | amdgpu_sync_free(&id->active); | |
2757 | dma_fence_put(id->flushed_updates); | |
2758 | dma_fence_put(id->last_flush); | |
2759 | } | |
bcb1ba35 | 2760 | } |
ea89f8c9 | 2761 | } |
cfbcacf4 CZ |
2762 | |
2763 | int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
2764 | { | |
2765 | union drm_amdgpu_vm *args = data; | |
1e9ef26f CZ |
2766 | struct amdgpu_device *adev = dev->dev_private; |
2767 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
2768 | int r; | |
cfbcacf4 CZ |
2769 | |
2770 | switch (args->in.op) { | |
2771 | case AMDGPU_VM_OP_RESERVE_VMID: | |
1e9ef26f CZ |
2772 | /* current, we only have requirement to reserve vmid from gfxhub */ |
2773 | r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm, | |
2774 | AMDGPU_GFXHUB); | |
2775 | if (r) | |
2776 | return r; | |
2777 | break; | |
cfbcacf4 | 2778 | case AMDGPU_VM_OP_UNRESERVE_VMID: |
1e9ef26f | 2779 | amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB); |
cfbcacf4 CZ |
2780 | break; |
2781 | default: | |
2782 | return -EINVAL; | |
2783 | } | |
2784 | ||
2785 | return 0; | |
2786 | } |